1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2015 Broadcom Corporation
7 #include <linux/kernel.h>
10 #include <linux/clk.h>
11 #include <linux/module.h>
12 #include <linux/mbus.h>
13 #include <linux/slab.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/irqchip/arm-gic-v3.h>
17 #include <linux/platform_device.h>
18 #include <linux/of_address.h>
19 #include <linux/of_pci.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/phy/phy.h>
24 #include "pcie-iproc.h"
26 #define EP_PERST_SOURCE_SELECT_SHIFT 2
27 #define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT)
28 #define EP_MODE_SURVIVE_PERST_SHIFT 1
29 #define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
30 #define RC_PCIE_RST_OUTPUT_SHIFT 0
31 #define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
32 #define PAXC_RESET_MASK 0x7f
34 #define GIC_V3_CFG_SHIFT 0
35 #define GIC_V3_CFG BIT(GIC_V3_CFG_SHIFT)
37 #define MSI_ENABLE_CFG_SHIFT 0
38 #define MSI_ENABLE_CFG BIT(MSI_ENABLE_CFG_SHIFT)
40 #define CFG_IND_ADDR_MASK 0x00001ffc
42 #define CFG_ADDR_BUS_NUM_SHIFT 20
43 #define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
44 #define CFG_ADDR_DEV_NUM_SHIFT 15
45 #define CFG_ADDR_DEV_NUM_MASK 0x000f8000
46 #define CFG_ADDR_FUNC_NUM_SHIFT 12
47 #define CFG_ADDR_FUNC_NUM_MASK 0x00007000
48 #define CFG_ADDR_REG_NUM_SHIFT 2
49 #define CFG_ADDR_REG_NUM_MASK 0x00000ffc
50 #define CFG_ADDR_CFG_TYPE_SHIFT 0
51 #define CFG_ADDR_CFG_TYPE_MASK 0x00000003
53 #define SYS_RC_INTX_MASK 0xf
55 #define PCIE_PHYLINKUP_SHIFT 3
56 #define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT)
57 #define PCIE_DL_ACTIVE_SHIFT 2
58 #define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT)
60 #define APB_ERR_EN_SHIFT 0
61 #define APB_ERR_EN BIT(APB_ERR_EN_SHIFT)
63 #define CFG_RETRY_STATUS 0xffff0001
64 #define CFG_RETRY_STATUS_TIMEOUT_US 500000 /* 500 milliseconds */
66 /* derive the enum index of the outbound/inbound mapping registers */
67 #define MAP_REG(base_reg, index) ((base_reg) + (index) * 2)
70 * Maximum number of outbound mapping window sizes that can be supported by any
71 * OARR/OMAP mapping pair
73 #define MAX_NUM_OB_WINDOW_SIZES 4
75 #define OARR_VALID_SHIFT 0
76 #define OARR_VALID BIT(OARR_VALID_SHIFT)
77 #define OARR_SIZE_CFG_SHIFT 1
80 * Maximum number of inbound mapping region sizes that can be supported by an
83 #define MAX_NUM_IB_REGION_SIZES 9
85 #define IMAP_VALID_SHIFT 0
86 #define IMAP_VALID BIT(IMAP_VALID_SHIFT)
88 #define IPROC_PCI_EXP_CAP 0xac
90 #define IPROC_PCIE_REG_INVALID 0xffff
93 * iProc PCIe outbound mapping controller specific parameters
95 * @window_sizes: list of supported outbound mapping window sizes in MB
96 * @nr_sizes: number of supported outbound mapping window sizes
98 struct iproc_pcie_ob_map {
99 resource_size_t window_sizes[MAX_NUM_OB_WINDOW_SIZES];
100 unsigned int nr_sizes;
103 static const struct iproc_pcie_ob_map paxb_ob_map[] = {
106 .window_sizes = { 128, 256 },
111 .window_sizes = { 128, 256 },
116 static const struct iproc_pcie_ob_map paxb_v2_ob_map[] = {
119 .window_sizes = { 128, 256 },
124 .window_sizes = { 128, 256 },
129 .window_sizes = { 128, 256, 512, 1024 },
134 .window_sizes = { 128, 256, 512, 1024 },
140 * iProc PCIe inbound mapping type
142 enum iproc_pcie_ib_map_type {
144 IPROC_PCIE_IB_MAP_MEM = 0,
146 /* for device I/O memory */
147 IPROC_PCIE_IB_MAP_IO,
149 /* invalid or unused */
150 IPROC_PCIE_IB_MAP_INVALID
154 * iProc PCIe inbound mapping controller specific parameters
156 * @type: inbound mapping region type
157 * @size_unit: inbound mapping region size unit, could be SZ_1K, SZ_1M, or
159 * @region_sizes: list of supported inbound mapping region sizes in KB, MB, or
160 * GB, depedning on the size unit
161 * @nr_sizes: number of supported inbound mapping region sizes
162 * @nr_windows: number of supported inbound mapping windows for the region
163 * @imap_addr_offset: register offset between the upper and lower 32-bit
164 * IMAP address registers
165 * @imap_window_offset: register offset between each IMAP window
167 struct iproc_pcie_ib_map {
168 enum iproc_pcie_ib_map_type type;
169 unsigned int size_unit;
170 resource_size_t region_sizes[MAX_NUM_IB_REGION_SIZES];
171 unsigned int nr_sizes;
172 unsigned int nr_windows;
173 u16 imap_addr_offset;
174 u16 imap_window_offset;
177 static const struct iproc_pcie_ib_map paxb_v2_ib_map[] = {
180 .type = IPROC_PCIE_IB_MAP_IO,
182 .region_sizes = { 32 },
185 .imap_addr_offset = 0x40,
186 .imap_window_offset = 0x4,
189 /* IARR1/IMAP1 (currently unused) */
190 .type = IPROC_PCIE_IB_MAP_INVALID,
194 .type = IPROC_PCIE_IB_MAP_MEM,
196 .region_sizes = { 64, 128, 256, 512, 1024, 2048, 4096, 8192,
200 .imap_addr_offset = 0x4,
201 .imap_window_offset = 0x8,
205 .type = IPROC_PCIE_IB_MAP_MEM,
207 .region_sizes = { 1, 2, 4, 8, 16, 32 },
210 .imap_addr_offset = 0x4,
211 .imap_window_offset = 0x8,
215 .type = IPROC_PCIE_IB_MAP_MEM,
217 .region_sizes = { 32, 64, 128, 256, 512 },
220 .imap_addr_offset = 0x4,
221 .imap_window_offset = 0x8,
226 * iProc PCIe host registers
228 enum iproc_pcie_reg {
229 /* clock/reset signal control */
230 IPROC_PCIE_CLK_CTRL = 0,
233 * To allow MSI to be steered to an external MSI controller (e.g., ARM
236 IPROC_PCIE_MSI_GIC_MODE,
239 * IPROC_PCIE_MSI_BASE_ADDR and IPROC_PCIE_MSI_WINDOW_SIZE define the
240 * window where the MSI posted writes are written, for the writes to be
241 * interpreted as MSI writes.
243 IPROC_PCIE_MSI_BASE_ADDR,
244 IPROC_PCIE_MSI_WINDOW_SIZE,
247 * To hold the address of the register where the MSI writes are
248 * programed. When ARM GICv3 ITS is used, this should be programmed
249 * with the address of the GITS_TRANSLATER register.
251 IPROC_PCIE_MSI_ADDR_LO,
252 IPROC_PCIE_MSI_ADDR_HI,
255 IPROC_PCIE_MSI_EN_CFG,
257 /* allow access to root complex configuration space */
258 IPROC_PCIE_CFG_IND_ADDR,
259 IPROC_PCIE_CFG_IND_DATA,
261 /* allow access to device configuration space */
268 /* outbound address mapping */
278 /* inbound address mapping */
291 IPROC_PCIE_LINK_STATUS,
293 /* enable APB error for unsupported requests */
294 IPROC_PCIE_APB_ERR_EN,
296 /* total number of core registers */
297 IPROC_PCIE_MAX_NUM_REG,
300 /* iProc PCIe PAXB BCMA registers */
301 static const u16 iproc_pcie_reg_paxb_bcma[] = {
302 [IPROC_PCIE_CLK_CTRL] = 0x000,
303 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
304 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
305 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
306 [IPROC_PCIE_CFG_DATA] = 0x1fc,
307 [IPROC_PCIE_INTX_EN] = 0x330,
308 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
311 /* iProc PCIe PAXB registers */
312 static const u16 iproc_pcie_reg_paxb[] = {
313 [IPROC_PCIE_CLK_CTRL] = 0x000,
314 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
315 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
316 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
317 [IPROC_PCIE_CFG_DATA] = 0x1fc,
318 [IPROC_PCIE_INTX_EN] = 0x330,
319 [IPROC_PCIE_OARR0] = 0xd20,
320 [IPROC_PCIE_OMAP0] = 0xd40,
321 [IPROC_PCIE_OARR1] = 0xd28,
322 [IPROC_PCIE_OMAP1] = 0xd48,
323 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
324 [IPROC_PCIE_APB_ERR_EN] = 0xf40,
327 /* iProc PCIe PAXB v2 registers */
328 static const u16 iproc_pcie_reg_paxb_v2[] = {
329 [IPROC_PCIE_CLK_CTRL] = 0x000,
330 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
331 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
332 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
333 [IPROC_PCIE_CFG_DATA] = 0x1fc,
334 [IPROC_PCIE_INTX_EN] = 0x330,
335 [IPROC_PCIE_OARR0] = 0xd20,
336 [IPROC_PCIE_OMAP0] = 0xd40,
337 [IPROC_PCIE_OARR1] = 0xd28,
338 [IPROC_PCIE_OMAP1] = 0xd48,
339 [IPROC_PCIE_OARR2] = 0xd60,
340 [IPROC_PCIE_OMAP2] = 0xd68,
341 [IPROC_PCIE_OARR3] = 0xdf0,
342 [IPROC_PCIE_OMAP3] = 0xdf8,
343 [IPROC_PCIE_IARR0] = 0xd00,
344 [IPROC_PCIE_IMAP0] = 0xc00,
345 [IPROC_PCIE_IARR2] = 0xd10,
346 [IPROC_PCIE_IMAP2] = 0xcc0,
347 [IPROC_PCIE_IARR3] = 0xe00,
348 [IPROC_PCIE_IMAP3] = 0xe08,
349 [IPROC_PCIE_IARR4] = 0xe68,
350 [IPROC_PCIE_IMAP4] = 0xe70,
351 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
352 [IPROC_PCIE_APB_ERR_EN] = 0xf40,
355 /* iProc PCIe PAXC v1 registers */
356 static const u16 iproc_pcie_reg_paxc[] = {
357 [IPROC_PCIE_CLK_CTRL] = 0x000,
358 [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
359 [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
360 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
361 [IPROC_PCIE_CFG_DATA] = 0x1fc,
364 /* iProc PCIe PAXC v2 registers */
365 static const u16 iproc_pcie_reg_paxc_v2[] = {
366 [IPROC_PCIE_MSI_GIC_MODE] = 0x050,
367 [IPROC_PCIE_MSI_BASE_ADDR] = 0x074,
368 [IPROC_PCIE_MSI_WINDOW_SIZE] = 0x078,
369 [IPROC_PCIE_MSI_ADDR_LO] = 0x07c,
370 [IPROC_PCIE_MSI_ADDR_HI] = 0x080,
371 [IPROC_PCIE_MSI_EN_CFG] = 0x09c,
372 [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
373 [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
374 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
375 [IPROC_PCIE_CFG_DATA] = 0x1fc,
378 static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
380 struct iproc_pcie *pcie;
382 struct pci_sys_data *sys = bus->sysdata;
384 pcie = sys->private_data;
391 static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset)
393 return !!(reg_offset == IPROC_PCIE_REG_INVALID);
396 static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie,
397 enum iproc_pcie_reg reg)
399 return pcie->reg_offsets[reg];
402 static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie,
403 enum iproc_pcie_reg reg)
405 u16 offset = iproc_pcie_reg_offset(pcie, reg);
407 if (iproc_pcie_reg_is_invalid(offset))
410 return readl(pcie->base + offset);
413 static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie,
414 enum iproc_pcie_reg reg, u32 val)
416 u16 offset = iproc_pcie_reg_offset(pcie, reg);
418 if (iproc_pcie_reg_is_invalid(offset))
421 writel(val, pcie->base + offset);
425 * APB error forwarding can be disabled during access of configuration
426 * registers of the endpoint device, to prevent unsupported requests
427 * (typically seen during enumeration with multi-function devices) from
428 * triggering a system exception.
430 static inline void iproc_pcie_apb_err_disable(struct pci_bus *bus,
433 struct iproc_pcie *pcie = iproc_data(bus);
436 if (bus->number && pcie->has_apb_err_disable) {
437 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_APB_ERR_EN);
442 iproc_pcie_write_reg(pcie, IPROC_PCIE_APB_ERR_EN, val);
446 static void __iomem *iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *pcie,
455 /* EP device access */
456 val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
457 (slot << CFG_ADDR_DEV_NUM_SHIFT) |
458 (fn << CFG_ADDR_FUNC_NUM_SHIFT) |
459 (where & CFG_ADDR_REG_NUM_MASK) |
460 (1 & CFG_ADDR_CFG_TYPE_MASK);
462 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
463 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
465 if (iproc_pcie_reg_is_invalid(offset))
468 return (pcie->base + offset);
471 static unsigned int iproc_pcie_cfg_retry(void __iomem *cfg_data_p)
473 int timeout = CFG_RETRY_STATUS_TIMEOUT_US;
477 * As per PCIe spec r3.1, sec 2.3.2, CRS Software Visibility only
478 * affects config reads of the Vendor ID. For config writes or any
479 * other config reads, the Root may automatically reissue the
480 * configuration request again as a new request.
482 * For config reads, this hardware returns CFG_RETRY_STATUS data
483 * when it receives a CRS completion, regardless of the address of
484 * the read or the CRS Software Visibility Enable bit. As a
485 * partial workaround for this, we retry in software any read that
486 * returns CFG_RETRY_STATUS.
488 * Note that a non-Vendor ID config register may have a value of
489 * CFG_RETRY_STATUS. If we read that, we can't distinguish it from
490 * a CRS completion, so we will incorrectly retry the read and
491 * eventually return the wrong data (0xffffffff).
493 data = readl(cfg_data_p);
494 while (data == CFG_RETRY_STATUS && timeout--) {
496 data = readl(cfg_data_p);
499 if (data == CFG_RETRY_STATUS)
505 static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
506 int where, int size, u32 *val)
508 struct iproc_pcie *pcie = iproc_data(bus);
509 unsigned int slot = PCI_SLOT(devfn);
510 unsigned int fn = PCI_FUNC(devfn);
511 unsigned int busno = bus->number;
512 void __iomem *cfg_data_p;
516 /* root complex access */
518 ret = pci_generic_config_read32(bus, devfn, where, size, val);
519 if (ret != PCIBIOS_SUCCESSFUL)
522 /* Don't advertise CRS SV support */
523 if ((where & ~0x3) == IPROC_PCI_EXP_CAP + PCI_EXP_RTCTL)
524 *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
525 return PCIBIOS_SUCCESSFUL;
528 cfg_data_p = iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where);
531 return PCIBIOS_DEVICE_NOT_FOUND;
533 data = iproc_pcie_cfg_retry(cfg_data_p);
537 *val = (data >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
539 return PCIBIOS_SUCCESSFUL;
543 * Note access to the configuration registers are protected at the higher layer
544 * by 'pci_lock' in drivers/pci/access.c
546 static void __iomem *iproc_pcie_map_cfg_bus(struct iproc_pcie *pcie,
547 int busno, unsigned int devfn,
550 unsigned slot = PCI_SLOT(devfn);
551 unsigned fn = PCI_FUNC(devfn);
554 /* root complex access */
556 if (slot > 0 || fn > 0)
559 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR,
560 where & CFG_IND_ADDR_MASK);
561 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA);
562 if (iproc_pcie_reg_is_invalid(offset))
565 return (pcie->base + offset);
569 * PAXC is connected to an internally emulated EP within the SoC. It
570 * allows only one device.
572 if (pcie->ep_is_internal)
576 return iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where);
579 static void __iomem *iproc_pcie_bus_map_cfg_bus(struct pci_bus *bus,
583 return iproc_pcie_map_cfg_bus(iproc_data(bus), bus->number, devfn,
587 static int iproc_pci_raw_config_read32(struct iproc_pcie *pcie,
588 unsigned int devfn, int where,
593 addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3);
596 return PCIBIOS_DEVICE_NOT_FOUND;
602 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
604 return PCIBIOS_SUCCESSFUL;
607 static int iproc_pci_raw_config_write32(struct iproc_pcie *pcie,
608 unsigned int devfn, int where,
614 addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3);
616 return PCIBIOS_DEVICE_NOT_FOUND;
620 return PCIBIOS_SUCCESSFUL;
623 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
624 tmp = readl(addr) & mask;
625 tmp |= val << ((where & 0x3) * 8);
628 return PCIBIOS_SUCCESSFUL;
631 static int iproc_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
632 int where, int size, u32 *val)
635 struct iproc_pcie *pcie = iproc_data(bus);
637 iproc_pcie_apb_err_disable(bus, true);
638 if (pcie->type == IPROC_PCIE_PAXB_V2)
639 ret = iproc_pcie_config_read(bus, devfn, where, size, val);
641 ret = pci_generic_config_read32(bus, devfn, where, size, val);
642 iproc_pcie_apb_err_disable(bus, false);
647 static int iproc_pcie_config_write32(struct pci_bus *bus, unsigned int devfn,
648 int where, int size, u32 val)
652 iproc_pcie_apb_err_disable(bus, true);
653 ret = pci_generic_config_write32(bus, devfn, where, size, val);
654 iproc_pcie_apb_err_disable(bus, false);
659 static struct pci_ops iproc_pcie_ops = {
660 .map_bus = iproc_pcie_bus_map_cfg_bus,
661 .read = iproc_pcie_config_read32,
662 .write = iproc_pcie_config_write32,
665 static void iproc_pcie_perst_ctrl(struct iproc_pcie *pcie, bool assert)
670 * PAXC and the internal emulated endpoint device downstream should not
671 * be reset. If firmware has been loaded on the endpoint device at an
672 * earlier boot stage, reset here causes issues.
674 if (pcie->ep_is_internal)
678 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
679 val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
681 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
684 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
685 val |= RC_PCIE_RST_OUTPUT;
686 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
691 int iproc_pcie_shutdown(struct iproc_pcie *pcie)
693 iproc_pcie_perst_ctrl(pcie, true);
698 EXPORT_SYMBOL_GPL(iproc_pcie_shutdown);
700 static int iproc_pcie_check_link(struct iproc_pcie *pcie)
702 struct device *dev = pcie->dev;
703 u32 hdr_type, link_ctrl, link_status, class, val;
704 bool link_is_active = false;
707 * PAXC connects to emulated endpoint devices directly and does not
708 * have a Serdes. Therefore skip the link detection logic here.
710 if (pcie->ep_is_internal)
713 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS);
714 if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) {
715 dev_err(dev, "PHY or data link is INACTIVE!\n");
719 /* make sure we are not in EP mode */
720 iproc_pci_raw_config_read32(pcie, 0, PCI_HEADER_TYPE, 1, &hdr_type);
721 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
722 dev_err(dev, "in EP mode, hdr=%#02x\n", hdr_type);
726 /* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
727 #define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c
728 #define PCI_CLASS_BRIDGE_MASK 0xffff00
729 #define PCI_CLASS_BRIDGE_SHIFT 8
730 iproc_pci_raw_config_read32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET,
732 class &= ~PCI_CLASS_BRIDGE_MASK;
733 class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
734 iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET,
737 /* check link status to see if link is active */
738 iproc_pci_raw_config_read32(pcie, 0, IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA,
740 if (link_status & PCI_EXP_LNKSTA_NLW)
741 link_is_active = true;
743 if (!link_is_active) {
744 /* try GEN 1 link speed */
745 #define PCI_TARGET_LINK_SPEED_MASK 0xf
746 #define PCI_TARGET_LINK_SPEED_GEN2 0x2
747 #define PCI_TARGET_LINK_SPEED_GEN1 0x1
748 iproc_pci_raw_config_read32(pcie, 0,
749 IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2,
751 if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
752 PCI_TARGET_LINK_SPEED_GEN2) {
753 link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
754 link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1;
755 iproc_pci_raw_config_write32(pcie, 0,
756 IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2,
760 iproc_pci_raw_config_read32(pcie, 0,
761 IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA,
763 if (link_status & PCI_EXP_LNKSTA_NLW)
764 link_is_active = true;
768 dev_info(dev, "link: %s\n", link_is_active ? "UP" : "DOWN");
770 return link_is_active ? 0 : -ENODEV;
773 static void iproc_pcie_enable(struct iproc_pcie *pcie)
775 iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK);
778 static inline bool iproc_pcie_ob_is_valid(struct iproc_pcie *pcie,
783 val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_OARR0, window_idx));
785 return !!(val & OARR_VALID);
788 static inline int iproc_pcie_ob_write(struct iproc_pcie *pcie, int window_idx,
789 int size_idx, u64 axi_addr, u64 pci_addr)
791 struct device *dev = pcie->dev;
792 u16 oarr_offset, omap_offset;
795 * Derive the OARR/OMAP offset from the first pair (OARR0/OMAP0) based
798 oarr_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OARR0,
800 omap_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OMAP0,
802 if (iproc_pcie_reg_is_invalid(oarr_offset) ||
803 iproc_pcie_reg_is_invalid(omap_offset))
807 * Program the OARR registers. The upper 32-bit OARR register is
808 * always right after the lower 32-bit OARR register.
810 writel(lower_32_bits(axi_addr) | (size_idx << OARR_SIZE_CFG_SHIFT) |
811 OARR_VALID, pcie->base + oarr_offset);
812 writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4);
814 /* now program the OMAP registers */
815 writel(lower_32_bits(pci_addr), pcie->base + omap_offset);
816 writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4);
818 dev_info(dev, "ob window [%d]: offset 0x%x axi %pap pci %pap\n",
819 window_idx, oarr_offset, &axi_addr, &pci_addr);
820 dev_info(dev, "oarr lo 0x%x oarr hi 0x%x\n",
821 readl(pcie->base + oarr_offset),
822 readl(pcie->base + oarr_offset + 4));
823 dev_info(dev, "omap lo 0x%x omap hi 0x%x\n",
824 readl(pcie->base + omap_offset),
825 readl(pcie->base + omap_offset + 4));
831 * Some iProc SoCs require the SW to configure the outbound address mapping
833 * Outbound address translation:
835 * iproc_pcie_address = axi_address - axi_offset
836 * OARR = iproc_pcie_address
839 * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address
841 static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
842 u64 pci_addr, resource_size_t size)
844 struct iproc_pcie_ob *ob = &pcie->ob;
845 struct device *dev = pcie->dev;
846 int ret = -EINVAL, window_idx, size_idx;
848 if (axi_addr < ob->axi_offset) {
849 dev_err(dev, "axi address %pap less than offset %pap\n",
850 &axi_addr, &ob->axi_offset);
855 * Translate the AXI address to the internal address used by the iProc
856 * PCIe core before programming the OARR
858 axi_addr -= ob->axi_offset;
860 /* iterate through all OARR/OMAP mapping windows */
861 for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) {
862 const struct iproc_pcie_ob_map *ob_map =
863 &pcie->ob_map[window_idx];
866 * If current outbound window is already in use, move on to the
869 if (iproc_pcie_ob_is_valid(pcie, window_idx))
873 * Iterate through all supported window sizes within the
874 * OARR/OMAP pair to find a match. Go through the window sizes
875 * in a descending order.
877 for (size_idx = ob_map->nr_sizes - 1; size_idx >= 0;
879 resource_size_t window_size =
880 ob_map->window_sizes[size_idx] * SZ_1M;
882 if (size < window_size)
885 if (!IS_ALIGNED(axi_addr, window_size) ||
886 !IS_ALIGNED(pci_addr, window_size)) {
888 "axi %pap or pci %pap not aligned\n",
889 &axi_addr, &pci_addr);
894 * Match found! Program both OARR and OMAP and mark
895 * them as a valid entry.
897 ret = iproc_pcie_ob_write(pcie, window_idx, size_idx,
907 * If we are here, we are done with the current window,
908 * but not yet finished all mappings. Need to move on
909 * to the next window.
911 axi_addr += window_size;
912 pci_addr += window_size;
918 dev_err(dev, "unable to configure outbound mapping\n");
920 "axi %pap, axi offset %pap, pci %pap, res size %pap\n",
921 &axi_addr, &ob->axi_offset, &pci_addr, &size);
926 static int iproc_pcie_map_ranges(struct iproc_pcie *pcie,
927 struct list_head *resources)
929 struct device *dev = pcie->dev;
930 struct resource_entry *window;
933 resource_list_for_each_entry(window, resources) {
934 struct resource *res = window->res;
935 u64 res_type = resource_type(res);
942 ret = iproc_pcie_setup_ob(pcie, res->start,
943 res->start - window->offset,
949 dev_err(dev, "invalid resource %pR\n", res);
957 static inline bool iproc_pcie_ib_is_in_use(struct iproc_pcie *pcie,
960 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx];
963 val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_IARR0, region_idx));
965 return !!(val & (BIT(ib_map->nr_sizes) - 1));
968 static inline bool iproc_pcie_ib_check_type(const struct iproc_pcie_ib_map *ib_map,
969 enum iproc_pcie_ib_map_type type)
971 return !!(ib_map->type == type);
974 static int iproc_pcie_ib_write(struct iproc_pcie *pcie, int region_idx,
975 int size_idx, int nr_windows, u64 axi_addr,
976 u64 pci_addr, resource_size_t size)
978 struct device *dev = pcie->dev;
979 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx];
980 u16 iarr_offset, imap_offset;
984 iarr_offset = iproc_pcie_reg_offset(pcie,
985 MAP_REG(IPROC_PCIE_IARR0, region_idx));
986 imap_offset = iproc_pcie_reg_offset(pcie,
987 MAP_REG(IPROC_PCIE_IMAP0, region_idx));
988 if (iproc_pcie_reg_is_invalid(iarr_offset) ||
989 iproc_pcie_reg_is_invalid(imap_offset))
992 dev_info(dev, "ib region [%d]: offset 0x%x axi %pap pci %pap\n",
993 region_idx, iarr_offset, &axi_addr, &pci_addr);
996 * Program the IARR registers. The upper 32-bit IARR register is
997 * always right after the lower 32-bit IARR register.
999 writel(lower_32_bits(pci_addr) | BIT(size_idx),
1000 pcie->base + iarr_offset);
1001 writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4);
1003 dev_info(dev, "iarr lo 0x%x iarr hi 0x%x\n",
1004 readl(pcie->base + iarr_offset),
1005 readl(pcie->base + iarr_offset + 4));
1008 * Now program the IMAP registers. Each IARR region may have one or
1009 * more IMAP windows.
1011 size >>= ilog2(nr_windows);
1012 for (window_idx = 0; window_idx < nr_windows; window_idx++) {
1013 val = readl(pcie->base + imap_offset);
1014 val |= lower_32_bits(axi_addr) | IMAP_VALID;
1015 writel(val, pcie->base + imap_offset);
1016 writel(upper_32_bits(axi_addr),
1017 pcie->base + imap_offset + ib_map->imap_addr_offset);
1019 dev_info(dev, "imap window [%d] lo 0x%x hi 0x%x\n",
1020 window_idx, readl(pcie->base + imap_offset),
1021 readl(pcie->base + imap_offset +
1022 ib_map->imap_addr_offset));
1024 imap_offset += ib_map->imap_window_offset;
1031 static int iproc_pcie_setup_ib(struct iproc_pcie *pcie,
1032 struct of_pci_range *range,
1033 enum iproc_pcie_ib_map_type type)
1035 struct device *dev = pcie->dev;
1036 struct iproc_pcie_ib *ib = &pcie->ib;
1038 unsigned int region_idx, size_idx;
1039 u64 axi_addr = range->cpu_addr, pci_addr = range->pci_addr;
1040 resource_size_t size = range->size;
1042 /* iterate through all IARR mapping regions */
1043 for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) {
1044 const struct iproc_pcie_ib_map *ib_map =
1045 &pcie->ib_map[region_idx];
1048 * If current inbound region is already in use or not a
1049 * compatible type, move on to the next.
1051 if (iproc_pcie_ib_is_in_use(pcie, region_idx) ||
1052 !iproc_pcie_ib_check_type(ib_map, type))
1055 /* iterate through all supported region sizes to find a match */
1056 for (size_idx = 0; size_idx < ib_map->nr_sizes; size_idx++) {
1057 resource_size_t region_size =
1058 ib_map->region_sizes[size_idx] * ib_map->size_unit;
1060 if (size != region_size)
1063 if (!IS_ALIGNED(axi_addr, region_size) ||
1064 !IS_ALIGNED(pci_addr, region_size)) {
1066 "axi %pap or pci %pap not aligned\n",
1067 &axi_addr, &pci_addr);
1071 /* Match found! Program IARR and all IMAP windows. */
1072 ret = iproc_pcie_ib_write(pcie, region_idx, size_idx,
1073 ib_map->nr_windows, axi_addr,
1085 dev_err(dev, "unable to configure inbound mapping\n");
1086 dev_err(dev, "axi %pap, pci %pap, res size %pap\n",
1087 &axi_addr, &pci_addr, &size);
1092 static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie)
1094 struct of_pci_range range;
1095 struct of_pci_range_parser parser;
1098 /* Get the dma-ranges from DT */
1099 ret = of_pci_dma_range_parser_init(&parser, pcie->dev->of_node);
1103 for_each_of_pci_range(&parser, &range) {
1104 /* Each range entry corresponds to an inbound mapping region */
1105 ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_MEM);
1113 static int iproce_pcie_get_msi(struct iproc_pcie *pcie,
1114 struct device_node *msi_node,
1117 struct device *dev = pcie->dev;
1119 struct resource res;
1122 * Check if 'msi-map' points to ARM GICv3 ITS, which is the only
1123 * supported external MSI controller that requires steering.
1125 if (!of_device_is_compatible(msi_node, "arm,gic-v3-its")) {
1126 dev_err(dev, "unable to find compatible MSI controller\n");
1130 /* derive GITS_TRANSLATER address from GICv3 */
1131 ret = of_address_to_resource(msi_node, 0, &res);
1133 dev_err(dev, "unable to obtain MSI controller resources\n");
1137 *msi_addr = res.start + GITS_TRANSLATER;
1141 static int iproc_pcie_paxb_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr)
1144 struct of_pci_range range;
1146 memset(&range, 0, sizeof(range));
1147 range.size = SZ_32K;
1148 range.pci_addr = range.cpu_addr = msi_addr & ~(range.size - 1);
1150 ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_IO);
1154 static void iproc_pcie_paxc_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr)
1159 * Program bits [43:13] of address of GITS_TRANSLATER register into
1160 * bits [30:0] of the MSI base address register. In fact, in all iProc
1161 * based SoCs, all I/O register bases are well below the 32-bit
1162 * boundary, so we can safely assume bits [43:32] are always zeros.
1164 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_BASE_ADDR,
1165 (u32)(msi_addr >> 13));
1167 /* use a default 8K window size */
1168 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_WINDOW_SIZE, 0);
1170 /* steering MSI to GICv3 ITS */
1171 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_GIC_MODE);
1173 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_GIC_MODE, val);
1176 * Program bits [43:2] of address of GITS_TRANSLATER register into the
1177 * iProc MSI address registers.
1180 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_HI,
1181 upper_32_bits(msi_addr));
1182 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_LO,
1183 lower_32_bits(msi_addr));
1186 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_EN_CFG);
1187 val |= MSI_ENABLE_CFG;
1188 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_EN_CFG, val);
1191 static int iproc_pcie_msi_steer(struct iproc_pcie *pcie,
1192 struct device_node *msi_node)
1194 struct device *dev = pcie->dev;
1198 ret = iproce_pcie_get_msi(pcie, msi_node, &msi_addr);
1200 dev_err(dev, "msi steering failed\n");
1204 switch (pcie->type) {
1205 case IPROC_PCIE_PAXB_V2:
1206 ret = iproc_pcie_paxb_v2_msi_steer(pcie, msi_addr);
1210 case IPROC_PCIE_PAXC_V2:
1211 iproc_pcie_paxc_v2_msi_steer(pcie, msi_addr);
1220 static int iproc_pcie_msi_enable(struct iproc_pcie *pcie)
1222 struct device_node *msi_node;
1226 * Either the "msi-parent" or the "msi-map" phandle needs to exist
1227 * for us to obtain the MSI node.
1230 msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0);
1232 const __be32 *msi_map = NULL;
1236 msi_map = of_get_property(pcie->dev->of_node, "msi-map", &len);
1240 phandle = be32_to_cpup(msi_map + 1);
1241 msi_node = of_find_node_by_phandle(phandle);
1247 * Certain revisions of the iProc PCIe controller require additional
1248 * configurations to steer the MSI writes towards an external MSI
1251 if (pcie->need_msi_steer) {
1252 ret = iproc_pcie_msi_steer(pcie, msi_node);
1258 * If another MSI controller is being used, the call below should fail
1261 return iproc_msi_init(pcie, msi_node);
1264 static void iproc_pcie_msi_disable(struct iproc_pcie *pcie)
1266 iproc_msi_exit(pcie);
1269 static int iproc_pcie_rev_init(struct iproc_pcie *pcie)
1271 struct device *dev = pcie->dev;
1272 unsigned int reg_idx;
1275 switch (pcie->type) {
1276 case IPROC_PCIE_PAXB_BCMA:
1277 regs = iproc_pcie_reg_paxb_bcma;
1279 case IPROC_PCIE_PAXB:
1280 regs = iproc_pcie_reg_paxb;
1281 pcie->has_apb_err_disable = true;
1282 if (pcie->need_ob_cfg) {
1283 pcie->ob_map = paxb_ob_map;
1284 pcie->ob.nr_windows = ARRAY_SIZE(paxb_ob_map);
1287 case IPROC_PCIE_PAXB_V2:
1288 regs = iproc_pcie_reg_paxb_v2;
1289 pcie->has_apb_err_disable = true;
1290 if (pcie->need_ob_cfg) {
1291 pcie->ob_map = paxb_v2_ob_map;
1292 pcie->ob.nr_windows = ARRAY_SIZE(paxb_v2_ob_map);
1294 pcie->ib.nr_regions = ARRAY_SIZE(paxb_v2_ib_map);
1295 pcie->ib_map = paxb_v2_ib_map;
1296 pcie->need_msi_steer = true;
1297 dev_warn(dev, "reads of config registers that contain %#x return incorrect data\n",
1300 case IPROC_PCIE_PAXC:
1301 regs = iproc_pcie_reg_paxc;
1302 pcie->ep_is_internal = true;
1304 case IPROC_PCIE_PAXC_V2:
1305 regs = iproc_pcie_reg_paxc_v2;
1306 pcie->ep_is_internal = true;
1307 pcie->need_msi_steer = true;
1310 dev_err(dev, "incompatible iProc PCIe interface\n");
1314 pcie->reg_offsets = devm_kcalloc(dev, IPROC_PCIE_MAX_NUM_REG,
1315 sizeof(*pcie->reg_offsets),
1317 if (!pcie->reg_offsets)
1320 /* go through the register table and populate all valid registers */
1321 pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ?
1322 IPROC_PCIE_REG_INVALID : regs[0];
1323 for (reg_idx = 1; reg_idx < IPROC_PCIE_MAX_NUM_REG; reg_idx++)
1324 pcie->reg_offsets[reg_idx] = regs[reg_idx] ?
1325 regs[reg_idx] : IPROC_PCIE_REG_INVALID;
1330 int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
1335 struct pci_bus *child;
1336 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1340 ret = iproc_pcie_rev_init(pcie);
1342 dev_err(dev, "unable to initialize controller parameters\n");
1346 ret = devm_request_pci_bus_resources(dev, res);
1350 ret = phy_init(pcie->phy);
1352 dev_err(dev, "unable to initialize PCIe PHY\n");
1356 ret = phy_power_on(pcie->phy);
1358 dev_err(dev, "unable to power on PCIe PHY\n");
1362 iproc_pcie_perst_ctrl(pcie, true);
1363 iproc_pcie_perst_ctrl(pcie, false);
1365 if (pcie->need_ob_cfg) {
1366 ret = iproc_pcie_map_ranges(pcie, res);
1368 dev_err(dev, "map failed\n");
1369 goto err_power_off_phy;
1373 if (pcie->need_ib_cfg) {
1374 ret = iproc_pcie_map_dma_ranges(pcie);
1375 if (ret && ret != -ENOENT)
1376 goto err_power_off_phy;
1380 pcie->sysdata.private_data = pcie;
1381 sysdata = &pcie->sysdata;
1386 ret = iproc_pcie_check_link(pcie);
1388 dev_err(dev, "no PCIe EP device detected\n");
1389 goto err_power_off_phy;
1392 iproc_pcie_enable(pcie);
1394 if (IS_ENABLED(CONFIG_PCI_MSI))
1395 if (iproc_pcie_msi_enable(pcie))
1396 dev_info(dev, "not using iProc MSI\n");
1398 list_splice_init(res, &host->windows);
1400 host->dev.parent = dev;
1401 host->ops = &iproc_pcie_ops;
1402 host->sysdata = sysdata;
1403 host->map_irq = pcie->map_irq;
1404 host->swizzle_irq = pci_common_swizzle;
1406 ret = pci_scan_root_bus_bridge(host);
1408 dev_err(dev, "failed to scan host: %d\n", ret);
1409 goto err_power_off_phy;
1412 pci_assign_unassigned_bus_resources(host->bus);
1414 pcie->root_bus = host->bus;
1416 list_for_each_entry(child, &host->bus->children, node)
1417 pcie_bus_configure_settings(child);
1419 pci_bus_add_devices(host->bus);
1424 phy_power_off(pcie->phy);
1426 phy_exit(pcie->phy);
1429 EXPORT_SYMBOL(iproc_pcie_setup);
1431 int iproc_pcie_remove(struct iproc_pcie *pcie)
1433 pci_stop_root_bus(pcie->root_bus);
1434 pci_remove_root_bus(pcie->root_bus);
1436 iproc_pcie_msi_disable(pcie);
1438 phy_power_off(pcie->phy);
1439 phy_exit(pcie->phy);
1443 EXPORT_SYMBOL(iproc_pcie_remove);
1446 MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
1447 MODULE_LICENSE("GPL v2");