drivers/usb/dwc2/hcd.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * hcd.c - DesignWare HS OTG Controller host-mode routines
   4  *
   5  * Copyright (C) 2004-2013 Synopsys, Inc.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. The names of the above-listed copyright holders may not be used
  17  *    to endorse or promote products derived from this software without
  18  *    specific prior written permission.
  19  *
  20  * ALTERNATIVELY, this software may be distributed under the terms of the
  21  * GNU General Public License ("GPL") as published by the Free Software
  22  * Foundation; either version 2 of the License, or (at your option) any
  23  * later version.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  26  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  32  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  33  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  34  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /*
  39  * This file contains the core HCD code, and implements the Linux hc_driver
  40  * API
  41  */
  42 #include <linux/kernel.h>
  43 #include <linux/module.h>
  44 #include <linux/spinlock.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/platform_device.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/delay.h>
  49 #include <linux/io.h>
  50 #include <linux/slab.h>
  51 #include <linux/usb.h>
  52
  53 #include <linux/usb/hcd.h>
  54 #include <linux/usb/ch11.h>
  55
  56 #include "core.h"
  57 #include "hcd.h"
  58
  59 static void dwc2_port_resume(struct dwc2_hsotg *hsotg);
  60
  61 /*
  62  * =========================================================================
  63  *  Host Core Layer Functions
  64  * =========================================================================
  65  */
  66
  67 /**
  68  * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
  69  * used in both device and host modes
  70  *
  71  * @hsotg: Programming view of the DWC_otg controller
  72  */
  73 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
  74 {
  75         u32 intmsk;
  76
  77         /* Clear any pending OTG Interrupts */
  78         dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
  79
  80         /* Clear any pending interrupts */
  81         dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
  82
  83         /* Enable the interrupts in the GINTMSK */
  84         intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
  85
  86         if (!hsotg->params.host_dma)
  87                 intmsk |= GINTSTS_RXFLVL;
  88         if (!hsotg->params.external_id_pin_ctl)
  89                 intmsk |= GINTSTS_CONIDSTSCHNG;
  90
  91         intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
  92                   GINTSTS_SESSREQINT;
  93
  94         dwc2_writel(intmsk, hsotg->regs + GINTMSK);
  95 }
  96
  97 /*
  98  * Initializes the FSLSPClkSel field of the HCFG register depending on the
  99  * PHY type
 100  */
 101 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
 102 {
 103         u32 hcfg, val;
 104
 105         if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
 106              hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
 107              hsotg->params.ulpi_fs_ls) ||
 108             hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
 109                 /* Full speed PHY */
 110                 val = HCFG_FSLSPCLKSEL_48_MHZ;
 111         } else {
 112                 /* High speed PHY running at full speed or high speed */
 113                 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
 114         }
 115
 116         dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
 117         hcfg = dwc2_readl(hsotg->regs + HCFG);
 118         hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 119         hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
 120         dwc2_writel(hcfg, hsotg->regs + HCFG);
 121 }
 122
 123 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 124 {
 125         u32 usbcfg, ggpio, i2cctl;
 126         int retval = 0;
 127
 128         /*
 129          * core_init() is now called on every switch so only call the
 130          * following for the first time through
 131          */
 132         if (select_phy) {
 133                 dev_dbg(hsotg->dev, "FS PHY selected\n");
 134
 135                 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 136                 if (!(usbcfg & GUSBCFG_PHYSEL)) {
 137                         usbcfg |= GUSBCFG_PHYSEL;
 138                         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 139
 140                         /* Reset after a PHY select */
 141                         retval = dwc2_core_reset_and_force_dr_mode(hsotg);
 142
 143                         if (retval) {
 144                                 dev_err(hsotg->dev,
 145                                         "%s: Reset failed, aborting", __func__);
 146                                 return retval;
 147                         }
 148                 }
 149
 150                 if (hsotg->params.activate_stm_fs_transceiver) {
 151                         ggpio = dwc2_readl(hsotg->regs + GGPIO);
 152                         if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
 153                                 dev_dbg(hsotg->dev, "Activating transceiver\n");
 154                                 /*
 155                                  * STM32F4x9 uses the GGPIO register as general
 156                                  * core configuration register.
 157                                  */
 158                                 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
 159                                 dwc2_writel(ggpio, hsotg->regs + GGPIO);
 160                         }
 161                 }
 162         }
 163
 164         /*
 165          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
 166          * do this on HNP Dev/Host mode switches (done in dev_init and
 167          * host_init).
 168          */
 169         if (dwc2_is_host_mode(hsotg))
 170                 dwc2_init_fs_ls_pclk_sel(hsotg);
 171
 172         if (hsotg->params.i2c_enable) {
 173                 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
 174
 175                 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
 176                 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 177                 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
 178                 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 179
 180                 /* Program GI2CCTL.I2CEn */
 181                 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
 182                 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
 183                 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
 184                 i2cctl &= ~GI2CCTL_I2CEN;
 185                 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
 186                 i2cctl |= GI2CCTL_I2CEN;
 187                 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
 188         }
 189
 190         return retval;
 191 }
 192
 193 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 194 {
 195         u32 usbcfg, usbcfg_old;
 196         int retval = 0;
 197
 198         if (!select_phy)
 199                 return 0;
 200
 201         usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 202         usbcfg_old = usbcfg;
 203
 204         /*
 205          * HS PHY parameters. These parameters are preserved during soft reset
 206          * so only program the first time. Do a soft reset immediately after
 207          * setting phyif.
 208          */
 209         switch (hsotg->params.phy_type) {
 210         case DWC2_PHY_TYPE_PARAM_ULPI:
 211                 /* ULPI interface */
 212                 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
 213                 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
 214                 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
 215                 if (hsotg->params.phy_ulpi_ddr)
 216                         usbcfg |= GUSBCFG_DDRSEL;
 217
 218                 /* Set external VBUS indicator as needed. */
 219                 if (hsotg->params.oc_disable)
 220                         usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
 221                                    GUSBCFG_INDICATORPASSTHROUGH);
 222                 break;
 223         case DWC2_PHY_TYPE_PARAM_UTMI:
 224                 /* UTMI+ interface */
 225                 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
 226                 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
 227                 if (hsotg->params.phy_utmi_width == 16)
 228                         usbcfg |= GUSBCFG_PHYIF16;
 229                 break;
 230         default:
 231                 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
 232                 break;
 233         }
 234
 235         if (usbcfg != usbcfg_old) {
 236                 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 237
 238                 /* Reset after setting the PHY parameters */
 239                 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
 240                 if (retval) {
 241                         dev_err(hsotg->dev,
 242                                 "%s: Reset failed, aborting", __func__);
 243                         return retval;
 244                 }
 245         }
 246
 247         return retval;
 248 }
 249
 250 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 251 {
 252         u32 usbcfg;
 253         int retval = 0;
 254
 255         if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
 256              hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
 257             hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
 258                 /* If FS/LS mode with FS/LS PHY */
 259                 retval = dwc2_fs_phy_init(hsotg, select_phy);
 260                 if (retval)
 261                         return retval;
 262         } else {
 263                 /* High speed PHY */
 264                 retval = dwc2_hs_phy_init(hsotg, select_phy);
 265                 if (retval)
 266                         return retval;
 267         }
 268
 269         if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
 270             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
 271             hsotg->params.ulpi_fs_ls) {
 272                 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
 273                 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 274                 usbcfg |= GUSBCFG_ULPI_FS_LS;
 275                 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
 276                 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 277         } else {
 278                 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 279                 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
 280                 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
 281                 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 282         }
 283
 284         return retval;
 285 }
 286
 287 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
 288 {
 289         u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
 290
 291         switch (hsotg->hw_params.arch) {
 292         case GHWCFG2_EXT_DMA_ARCH:
 293                 dev_err(hsotg->dev, "External DMA Mode not supported\n");
 294                 return -EINVAL;
 295
 296         case GHWCFG2_INT_DMA_ARCH:
 297                 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
 298                 if (hsotg->params.ahbcfg != -1) {
 299                         ahbcfg &= GAHBCFG_CTRL_MASK;
 300                         ahbcfg |= hsotg->params.ahbcfg &
 301                                   ~GAHBCFG_CTRL_MASK;
 302                 }
 303                 break;
 304
 305         case GHWCFG2_SLAVE_ONLY_ARCH:
 306         default:
 307                 dev_dbg(hsotg->dev, "Slave Only Mode\n");
 308                 break;
 309         }
 310
 311         dev_dbg(hsotg->dev, "host_dma:%d dma_desc_enable:%d\n",
 312                 hsotg->params.host_dma,
 313                 hsotg->params.dma_desc_enable);
 314
 315         if (hsotg->params.host_dma) {
 316                 if (hsotg->params.dma_desc_enable)
 317                         dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n");
 318                 else
 319                         dev_dbg(hsotg->dev, "Using Buffer DMA mode\n");
 320         } else {
 321                 dev_dbg(hsotg->dev, "Using Slave mode\n");
 322                 hsotg->params.dma_desc_enable = false;
 323         }
 324
 325         if (hsotg->params.host_dma)
 326                 ahbcfg |= GAHBCFG_DMA_EN;
 327
 328         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
 329
 330         return 0;
 331 }
 332
 333 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
 334 {
 335         u32 usbcfg;
 336
 337         usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 338         usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
 339
 340         switch (hsotg->hw_params.op_mode) {
 341         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 342                 if (hsotg->params.otg_cap ==
 343                                 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
 344                         usbcfg |= GUSBCFG_HNPCAP;
 345                 if (hsotg->params.otg_cap !=
 346                                 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
 347                         usbcfg |= GUSBCFG_SRPCAP;
 348                 break;
 349
 350         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 351         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 352         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 353                 if (hsotg->params.otg_cap !=
 354                                 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
 355                         usbcfg |= GUSBCFG_SRPCAP;
 356                 break;
 357
 358         case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
 359         case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
 360         case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
 361         default:
 362                 break;
 363         }
 364
 365         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 366 }
 367
 368 /**
 369  * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
 370  *
 371  * @hsotg: Programming view of DWC_otg controller
 372  */
 373 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
 374 {
 375         u32 intmsk;
 376
 377         dev_dbg(hsotg->dev, "%s()\n", __func__);
 378
 379         /* Disable all interrupts */
 380         dwc2_writel(0, hsotg->regs + GINTMSK);
 381         dwc2_writel(0, hsotg->regs + HAINTMSK);
 382
 383         /* Enable the common interrupts */
 384         dwc2_enable_common_interrupts(hsotg);
 385
 386         /* Enable host mode interrupts without disturbing common interrupts */
 387         intmsk = dwc2_readl(hsotg->regs + GINTMSK);
 388         intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
 389         dwc2_writel(intmsk, hsotg->regs + GINTMSK);
 390 }
 391
 392 /**
 393  * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
 394  *
 395  * @hsotg: Programming view of DWC_otg controller
 396  */
 397 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
 398 {
 399         u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
 400
 401         /* Disable host mode interrupts without disturbing common interrupts */
 402         intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
 403                     GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
 404         dwc2_writel(intmsk, hsotg->regs + GINTMSK);
 405 }
 406
 407 /*
 408  * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
 409  * For system that have a total fifo depth that is smaller than the default
 410  * RX + TX fifo size.
 411  *
 412  * @hsotg: Programming view of DWC_otg controller
 413  */
 414 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
 415 {
 416         struct dwc2_core_params *params = &hsotg->params;
 417         struct dwc2_hw_params *hw = &hsotg->hw_params;
 418         u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
 419
 420         total_fifo_size = hw->total_fifo_size;
 421         rxfsiz = params->host_rx_fifo_size;
 422         nptxfsiz = params->host_nperio_tx_fifo_size;
 423         ptxfsiz = params->host_perio_tx_fifo_size;
 424
 425         /*
 426          * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
 427          * allocation with support for high bandwidth endpoints. Synopsys
 428          * defines MPS(Max Packet size) for a periodic EP=1024, and for
 429          * non-periodic as 512.
 430          */
 431         if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
 432                 /*
 433                  * For Buffer DMA mode/Scatter Gather DMA mode
 434                  * 2 * ((Largest Packet size / 4) + 1 + 1) + n
 435                  * with n = number of host channel.
 436                  * 2 * ((1024/4) + 2) = 516
 437                  */
 438                 rxfsiz = 516 + hw->host_channels;
 439
 440                 /*
 441                  * min non-periodic tx fifo depth
 442                  * 2 * (largest non-periodic USB packet used / 4)
 443                  * 2 * (512/4) = 256
 444                  */
 445                 nptxfsiz = 256;
 446
 447                 /*
 448                  * min periodic tx fifo depth
 449                  * (largest packet size*MC)/4
 450                  * (1024 * 3)/4 = 768
 451                  */
 452                 ptxfsiz = 768;
 453
 454                 params->host_rx_fifo_size = rxfsiz;
 455                 params->host_nperio_tx_fifo_size = nptxfsiz;
 456                 params->host_perio_tx_fifo_size = ptxfsiz;
 457         }
 458
 459         /*
 460          * If the summation of RX, NPTX and PTX fifo sizes is still
 461          * bigger than the total_fifo_size, then we have a problem.
 462          *
 463          * We won't be able to allocate as many endpoints. Right now,
 464          * we're just printing an error message, but ideally this FIFO
 465          * allocation algorithm would be improved in the future.
 466          *
 467          * FIXME improve this FIFO allocation algorithm.
 468          */
 469         if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
 470                 dev_err(hsotg->dev, "invalid fifo sizes\n");
 471 }
 472
 473 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
 474 {
 475         struct dwc2_core_params *params = &hsotg->params;
 476         u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
 477
 478         if (!params->enable_dynamic_fifo)
 479                 return;
 480
 481         dwc2_calculate_dynamic_fifo(hsotg);
 482
 483         /* Rx FIFO */
 484         grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
 485         dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
 486         grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
 487         grxfsiz |= params->host_rx_fifo_size <<
 488                    GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
 489         dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ);
 490         dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
 491                 dwc2_readl(hsotg->regs + GRXFSIZ));
 492
 493         /* Non-periodic Tx FIFO */
 494         dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
 495                 dwc2_readl(hsotg->regs + GNPTXFSIZ));
 496         nptxfsiz = params->host_nperio_tx_fifo_size <<
 497                    FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
 498         nptxfsiz |= params->host_rx_fifo_size <<
 499                     FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
 500         dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
 501         dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
 502                 dwc2_readl(hsotg->regs + GNPTXFSIZ));
 503
 504         /* Periodic Tx FIFO */
 505         dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
 506                 dwc2_readl(hsotg->regs + HPTXFSIZ));
 507         hptxfsiz = params->host_perio_tx_fifo_size <<
 508                    FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
 509         hptxfsiz |= (params->host_rx_fifo_size +
 510                      params->host_nperio_tx_fifo_size) <<
 511                     FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
 512         dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
 513         dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
 514                 dwc2_readl(hsotg->regs + HPTXFSIZ));
 515
 516         if (hsotg->params.en_multiple_tx_fifo &&
 517             hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
 518                 /*
 519                  * This feature was implemented in 2.91a version
 520                  * Global DFIFOCFG calculation for Host mode -
 521                  * include RxFIFO, NPTXFIFO and HPTXFIFO
 522                  */
 523                 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
 524                 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
 525                 dfifocfg |= (params->host_rx_fifo_size +
 526                              params->host_nperio_tx_fifo_size +
 527                              params->host_perio_tx_fifo_size) <<
 528                             GDFIFOCFG_EPINFOBASE_SHIFT &
 529                             GDFIFOCFG_EPINFOBASE_MASK;
 530                 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG);
 531         }
 532 }
 533
 534 /**
 535  * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
 536  * the HFIR register according to PHY type and speed
 537  *
 538  * @hsotg: Programming view of DWC_otg controller
 539  *
 540  * NOTE: The caller can modify the value of the HFIR register only after the
 541  * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
 542  * has been set
 543  */
 544 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
 545 {
 546         u32 usbcfg;
 547         u32 hprt0;
 548         int clock = 60; /* default value */
 549
 550         usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 551         hprt0 = dwc2_readl(hsotg->regs + HPRT0);
 552
 553         if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
 554             !(usbcfg & GUSBCFG_PHYIF16))
 555                 clock = 60;
 556         if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
 557             GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
 558                 clock = 48;
 559         if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
 560             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
 561                 clock = 30;
 562         if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
 563             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
 564                 clock = 60;
 565         if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
 566             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
 567                 clock = 48;
 568         if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
 569             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
 570                 clock = 48;
 571         if ((usbcfg & GUSBCFG_PHYSEL) &&
 572             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
 573                 clock = 48;
 574
 575         if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
 576                 /* High speed case */
 577                 return 125 * clock - 1;
 578
 579         /* FS/LS case */
 580         return 1000 * clock - 1;
 581 }
 582
 583 /**
 584  * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
 585  * buffer
 586  *
 587  * @core_if: Programming view of DWC_otg controller
 588  * @dest:    Destination buffer for the packet
 589  * @bytes:   Number of bytes to copy to the destination
 590  */
 591 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
 592 {
 593         u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
 594         u32 *data_buf = (u32 *)dest;
 595         int word_count = (bytes + 3) / 4;
 596         int i;
 597
 598         /*
 599          * Todo: Account for the case where dest is not dword aligned. This
 600          * requires reading data from the FIFO into a u32 temp buffer, then
 601          * moving it into the data buffer.
 602          */
 603
 604         dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
 605
 606         for (i = 0; i < word_count; i++, data_buf++)
 607                 *data_buf = dwc2_readl(fifo);
 608 }
 609
 610 /**
 611  * dwc2_dump_channel_info() - Prints the state of a host channel
 612  *
 613  * @hsotg: Programming view of DWC_otg controller
 614  * @chan:  Pointer to the channel to dump
 615  *
 616  * Must be called with interrupt disabled and spinlock held
 617  *
 618  * NOTE: This function will be removed once the peripheral controller code
 619  * is integrated and the driver is stable
 620  */
 621 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
 622                                    struct dwc2_host_chan *chan)
 623 {
 624 #ifdef VERBOSE_DEBUG
 625         int num_channels = hsotg->params.host_channels;
 626         struct dwc2_qh *qh;
 627         u32 hcchar;
 628         u32 hcsplt;
 629         u32 hctsiz;
 630         u32 hc_dma;
 631         int i;
 632
 633         if (!chan)
 634                 return;
 635
 636         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
 637         hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
 638         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
 639         hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
 640
 641         dev_dbg(hsotg->dev, "  Assigned to channel %p:\n", chan);
 642         dev_dbg(hsotg->dev, "    hcchar 0x%08x, hcsplt 0x%08x\n",
 643                 hcchar, hcsplt);
 644         dev_dbg(hsotg->dev, "    hctsiz 0x%08x, hc_dma 0x%08x\n",
 645                 hctsiz, hc_dma);
 646         dev_dbg(hsotg->dev, "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
 647                 chan->dev_addr, chan->ep_num, chan->ep_is_in);
 648         dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
 649         dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
 650         dev_dbg(hsotg->dev, "    data_pid_start: %d\n", chan->data_pid_start);
 651         dev_dbg(hsotg->dev, "    xfer_started: %d\n", chan->xfer_started);
 652         dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
 653         dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
 654         dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
 655                 (unsigned long)chan->xfer_dma);
 656         dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
 657         dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
 658         dev_dbg(hsotg->dev, "  NP inactive sched:\n");
 659         list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
 660                             qh_list_entry)
 661                 dev_dbg(hsotg->dev, "    %p\n", qh);
 662         dev_dbg(hsotg->dev, "  NP waiting sched:\n");
 663         list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting,
 664                             qh_list_entry)
 665                 dev_dbg(hsotg->dev, "    %p\n", qh);
 666         dev_dbg(hsotg->dev, "  NP active sched:\n");
 667         list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
 668                             qh_list_entry)
 669                 dev_dbg(hsotg->dev, "    %p\n", qh);
 670         dev_dbg(hsotg->dev, "  Channels:\n");
 671         for (i = 0; i < num_channels; i++) {
 672                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
 673
 674                 dev_dbg(hsotg->dev, "    %2d: %p\n", i, chan);
 675         }
 676 #endif /* VERBOSE_DEBUG */
 677 }
 678
 679 static int _dwc2_hcd_start(struct usb_hcd *hcd);
 680
 681 static void dwc2_host_start(struct dwc2_hsotg *hsotg)
 682 {
 683         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
 684
 685         hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
 686         _dwc2_hcd_start(hcd);
 687 }
 688
 689 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
 690 {
 691         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
 692
 693         hcd->self.is_b_host = 0;
 694 }
 695
 696 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
 697                                int *hub_addr, int *hub_port)
 698 {
 699         struct urb *urb = context;
 700
 701         if (urb->dev->tt)
 702                 *hub_addr = urb->dev->tt->hub->devnum;
 703         else
 704                 *hub_addr = 0;
 705         *hub_port = urb->dev->ttport;
 706 }
 707
 708 /*
 709  * =========================================================================
 710  *  Low Level Host Channel Access Functions
 711  * =========================================================================
 712  */
 713
 714 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
 715                                       struct dwc2_host_chan *chan)
 716 {
 717         u32 hcintmsk = HCINTMSK_CHHLTD;
 718
 719         switch (chan->ep_type) {
 720         case USB_ENDPOINT_XFER_CONTROL:
 721         case USB_ENDPOINT_XFER_BULK:
 722                 dev_vdbg(hsotg->dev, "control/bulk\n");
 723                 hcintmsk |= HCINTMSK_XFERCOMPL;
 724                 hcintmsk |= HCINTMSK_STALL;
 725                 hcintmsk |= HCINTMSK_XACTERR;
 726                 hcintmsk |= HCINTMSK_DATATGLERR;
 727                 if (chan->ep_is_in) {
 728                         hcintmsk |= HCINTMSK_BBLERR;
 729                 } else {
 730                         hcintmsk |= HCINTMSK_NAK;
 731                         hcintmsk |= HCINTMSK_NYET;
 732                         if (chan->do_ping)
 733                                 hcintmsk |= HCINTMSK_ACK;
 734                 }
 735
 736                 if (chan->do_split) {
 737                         hcintmsk |= HCINTMSK_NAK;
 738                         if (chan->complete_split)
 739                                 hcintmsk |= HCINTMSK_NYET;
 740                         else
 741                                 hcintmsk |= HCINTMSK_ACK;
 742                 }
 743
 744                 if (chan->error_state)
 745                         hcintmsk |= HCINTMSK_ACK;
 746                 break;
 747
 748         case USB_ENDPOINT_XFER_INT:
 749                 if (dbg_perio())
 750                         dev_vdbg(hsotg->dev, "intr\n");
 751                 hcintmsk |= HCINTMSK_XFERCOMPL;
 752                 hcintmsk |= HCINTMSK_NAK;
 753                 hcintmsk |= HCINTMSK_STALL;
 754                 hcintmsk |= HCINTMSK_XACTERR;
 755                 hcintmsk |= HCINTMSK_DATATGLERR;
 756                 hcintmsk |= HCINTMSK_FRMOVRUN;
 757
 758                 if (chan->ep_is_in)
 759                         hcintmsk |= HCINTMSK_BBLERR;
 760                 if (chan->error_state)
 761                         hcintmsk |= HCINTMSK_ACK;
 762                 if (chan->do_split) {
 763                         if (chan->complete_split)
 764                                 hcintmsk |= HCINTMSK_NYET;
 765                         else
 766                                 hcintmsk |= HCINTMSK_ACK;
 767                 }
 768                 break;
 769
 770         case USB_ENDPOINT_XFER_ISOC:
 771                 if (dbg_perio())
 772                         dev_vdbg(hsotg->dev, "isoc\n");
 773                 hcintmsk |= HCINTMSK_XFERCOMPL;
 774                 hcintmsk |= HCINTMSK_FRMOVRUN;
 775                 hcintmsk |= HCINTMSK_ACK;
 776
 777                 if (chan->ep_is_in) {
 778                         hcintmsk |= HCINTMSK_XACTERR;
 779                         hcintmsk |= HCINTMSK_BBLERR;
 780                 }
 781                 break;
 782         default:
 783                 dev_err(hsotg->dev, "## Unknown EP type ##\n");
 784                 break;
 785         }
 786
 787         dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
 788         if (dbg_hc(chan))
 789                 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
 790 }
 791
 792 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
 793                                     struct dwc2_host_chan *chan)
 794 {
 795         u32 hcintmsk = HCINTMSK_CHHLTD;
 796
 797         /*
 798          * For Descriptor DMA mode core halts the channel on AHB error.
 799          * Interrupt is not required.
 800          */
 801         if (!hsotg->params.dma_desc_enable) {
 802                 if (dbg_hc(chan))
 803                         dev_vdbg(hsotg->dev, "desc DMA disabled\n");
 804                 hcintmsk |= HCINTMSK_AHBERR;
 805         } else {
 806                 if (dbg_hc(chan))
 807                         dev_vdbg(hsotg->dev, "desc DMA enabled\n");
 808                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
 809                         hcintmsk |= HCINTMSK_XFERCOMPL;
 810         }
 811
 812         if (chan->error_state && !chan->do_split &&
 813             chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
 814                 if (dbg_hc(chan))
 815                         dev_vdbg(hsotg->dev, "setting ACK\n");
 816                 hcintmsk |= HCINTMSK_ACK;
 817                 if (chan->ep_is_in) {
 818                         hcintmsk |= HCINTMSK_DATATGLERR;
 819                         if (chan->ep_type != USB_ENDPOINT_XFER_INT)
 820                                 hcintmsk |= HCINTMSK_NAK;
 821                 }
 822         }
 823
 824         dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
 825         if (dbg_hc(chan))
 826                 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
 827 }
 828
 829 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
 830                                 struct dwc2_host_chan *chan)
 831 {
 832         u32 intmsk;
 833
 834         if (hsotg->params.host_dma) {
 835                 if (dbg_hc(chan))
 836                         dev_vdbg(hsotg->dev, "DMA enabled\n");
 837                 dwc2_hc_enable_dma_ints(hsotg, chan);
 838         } else {
 839                 if (dbg_hc(chan))
 840                         dev_vdbg(hsotg->dev, "DMA disabled\n");
 841                 dwc2_hc_enable_slave_ints(hsotg, chan);
 842         }
 843
 844         /* Enable the top level host channel interrupt */
 845         intmsk = dwc2_readl(hsotg->regs + HAINTMSK);
 846         intmsk |= 1 << chan->hc_num;
 847         dwc2_writel(intmsk, hsotg->regs + HAINTMSK);
 848         if (dbg_hc(chan))
 849                 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
 850
 851         /* Make sure host channel interrupts are enabled */
 852         intmsk = dwc2_readl(hsotg->regs + GINTMSK);
 853         intmsk |= GINTSTS_HCHINT;
 854         dwc2_writel(intmsk, hsotg->regs + GINTMSK);
 855         if (dbg_hc(chan))
 856                 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
 857 }
 858
 859 /**
 860  * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
 861  * a specific endpoint
 862  *
 863  * @hsotg: Programming view of DWC_otg controller
 864  * @chan:  Information needed to initialize the host channel
 865  *
 866  * The HCCHARn register is set up with the characteristics specified in chan.
 867  * Host channel interrupts that may need to be serviced while this transfer is
 868  * in progress are enabled.
 869  */
 870 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
 871 {
 872         u8 hc_num = chan->hc_num;
 873         u32 hcintmsk;
 874         u32 hcchar;
 875         u32 hcsplt = 0;
 876
 877         if (dbg_hc(chan))
 878                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
 879
 880         /* Clear old interrupt conditions for this host channel */
 881         hcintmsk = 0xffffffff;
 882         hcintmsk &= ~HCINTMSK_RESERVED14_31;
 883         dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num));
 884
 885         /* Enable channel interrupts required for this transfer */
 886         dwc2_hc_enable_ints(hsotg, chan);
 887
 888         /*
 889          * Program the HCCHARn register with the endpoint characteristics for
 890          * the current transfer
 891          */
 892         hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
 893         hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
 894         if (chan->ep_is_in)
 895                 hcchar |= HCCHAR_EPDIR;
 896         if (chan->speed == USB_SPEED_LOW)
 897                 hcchar |= HCCHAR_LSPDDEV;
 898         hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
 899         hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
 900         dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num));
 901         if (dbg_hc(chan)) {
 902                 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
 903                          hc_num, hcchar);
 904
 905                 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
 906                          __func__, hc_num);
 907                 dev_vdbg(hsotg->dev, "   Dev Addr: %d\n",
 908                          chan->dev_addr);
 909                 dev_vdbg(hsotg->dev, "   Ep Num: %d\n",
 910                          chan->ep_num);
 911                 dev_vdbg(hsotg->dev, "   Is In: %d\n",
 912                          chan->ep_is_in);
 913                 dev_vdbg(hsotg->dev, "   Is Low Speed: %d\n",
 914                          chan->speed == USB_SPEED_LOW);
 915                 dev_vdbg(hsotg->dev, "   Ep Type: %d\n",
 916                          chan->ep_type);
 917                 dev_vdbg(hsotg->dev, "   Max Pkt: %d\n",
 918                          chan->max_packet);
 919         }
 920
 921         /* Program the HCSPLT register for SPLITs */
 922         if (chan->do_split) {
 923                 if (dbg_hc(chan))
 924                         dev_vdbg(hsotg->dev,
 925                                  "Programming HC %d with split --> %s\n",
 926                                  hc_num,
 927                                  chan->complete_split ? "CSPLIT" : "SSPLIT");
 928                 if (chan->complete_split)
 929                         hcsplt |= HCSPLT_COMPSPLT;
 930                 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
 931                           HCSPLT_XACTPOS_MASK;
 932                 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
 933                           HCSPLT_HUBADDR_MASK;
 934                 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
 935                           HCSPLT_PRTADDR_MASK;
 936                 if (dbg_hc(chan)) {
 937                         dev_vdbg(hsotg->dev, "    comp split %d\n",
 938                                  chan->complete_split);
 939                         dev_vdbg(hsotg->dev, "    xact pos %d\n",
 940                                  chan->xact_pos);
 941                         dev_vdbg(hsotg->dev, "    hub addr %d\n",
 942                                  chan->hub_addr);
 943                         dev_vdbg(hsotg->dev, "    hub port %d\n",
 944                                  chan->hub_port);
 945                         dev_vdbg(hsotg->dev, "    is_in %d\n",
 946                                  chan->ep_is_in);
 947                         dev_vdbg(hsotg->dev, "    Max Pkt %d\n",
 948                                  chan->max_packet);
 949                         dev_vdbg(hsotg->dev, "    xferlen %d\n",
 950                                  chan->xfer_len);
 951                 }
 952         }
 953
 954         dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
 955 }
 956
 957 /**
 958  * dwc2_hc_halt() - Attempts to halt a host channel
 959  *
 960  * @hsotg:       Controller register interface
 961  * @chan:        Host channel to halt
 962  * @halt_status: Reason for halting the channel
 963  *
 964  * This function should only be called in Slave mode or to abort a transfer in
 965  * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
 966  * controller halts the channel when the transfer is complete or a condition
 967  * occurs that requires application intervention.
 968  *
 969  * In slave mode, checks for a free request queue entry, then sets the Channel
 970  * Enable and Channel Disable bits of the Host Channel Characteristics
 971  * register of the specified channel to intiate the halt. If there is no free
 972  * request queue entry, sets only the Channel Disable bit of the HCCHARn
 973  * register to flush requests for this channel. In the latter case, sets a
 974  * flag to indicate that the host channel needs to be halted when a request
 975  * queue slot is open.
 976  *
 977  * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
 978  * HCCHARn register. The controller ensures there is space in the request
 979  * queue before submitting the halt request.
 980  *
 981  * Some time may elapse before the core flushes any posted requests for this
 982  * host channel and halts. The Channel Halted interrupt handler completes the
 983  * deactivation of the host channel.
 984  */
 985 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
 986                   enum dwc2_halt_status halt_status)
 987 {
 988         u32 nptxsts, hptxsts, hcchar;
 989
 990         if (dbg_hc(chan))
 991                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
 992         if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
 993                 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
 994
 995         if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
 996             halt_status == DWC2_HC_XFER_AHB_ERR) {
 997                 /*
 998                  * Disable all channel interrupts except Ch Halted. The QTD
 999                  * and QH state associated with this transfer has been cleared
1000                  * (in the case of URB_DEQUEUE), so the channel needs to be
1001                  * shut down carefully to prevent crashes.
1002                  */
1003                 u32 hcintmsk = HCINTMSK_CHHLTD;
1004
1005                 dev_vdbg(hsotg->dev, "dequeue/error\n");
1006                 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1007
1008                 /*
1009                  * Make sure no other interrupts besides halt are currently
1010                  * pending. Handling another interrupt could cause a crash due
1011                  * to the QTD and QH state.
1012                  */
1013                 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1014
1015                 /*
1016                  * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
1017                  * even if the channel was already halted for some other
1018                  * reason
1019                  */
1020                 chan->halt_status = halt_status;
1021
1022                 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1023                 if (!(hcchar & HCCHAR_CHENA)) {
1024                         /*
1025                          * The channel is either already halted or it hasn't
1026                          * started yet. In DMA mode, the transfer may halt if
1027                          * it finishes normally or a condition occurs that
1028                          * requires driver intervention. Don't want to halt
1029                          * the channel again. In either Slave or DMA mode,
1030                          * it's possible that the transfer has been assigned
1031                          * to a channel, but not started yet when an URB is
1032                          * dequeued. Don't want to halt a channel that hasn't
1033                          * started yet.
1034                          */
1035                         return;
1036                 }
1037         }
1038         if (chan->halt_pending) {
1039                 /*
1040                  * A halt has already been issued for this channel. This might
1041                  * happen when a transfer is aborted by a higher level in
1042                  * the stack.
1043                  */
1044                 dev_vdbg(hsotg->dev,
1045                          "*** %s: Channel %d, chan->halt_pending already set ***\n",
1046                          __func__, chan->hc_num);
1047                 return;
1048         }
1049
1050         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1051
1052         /* No need to set the bit in DDMA for disabling the channel */
1053         /* TODO check it everywhere channel is disabled */
1054         if (!hsotg->params.dma_desc_enable) {
1055                 if (dbg_hc(chan))
1056                         dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1057                 hcchar |= HCCHAR_CHENA;
1058         } else {
1059                 if (dbg_hc(chan))
1060                         dev_dbg(hsotg->dev, "desc DMA enabled\n");
1061         }
1062         hcchar |= HCCHAR_CHDIS;
1063
1064         if (!hsotg->params.host_dma) {
1065                 if (dbg_hc(chan))
1066                         dev_vdbg(hsotg->dev, "DMA not enabled\n");
1067                 hcchar |= HCCHAR_CHENA;
1068
1069                 /* Check for space in the request queue to issue the halt */
1070                 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1071                     chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1072                         dev_vdbg(hsotg->dev, "control/bulk\n");
1073                         nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
1074                         if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1075                                 dev_vdbg(hsotg->dev, "Disabling channel\n");
1076                                 hcchar &= ~HCCHAR_CHENA;
1077                         }
1078                 } else {
1079                         if (dbg_perio())
1080                                 dev_vdbg(hsotg->dev, "isoc/intr\n");
1081                         hptxsts = dwc2_readl(hsotg->regs + HPTXSTS);
1082                         if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1083                             hsotg->queuing_high_bandwidth) {
1084                                 if (dbg_perio())
1085                                         dev_vdbg(hsotg->dev, "Disabling channel\n");
1086                                 hcchar &= ~HCCHAR_CHENA;
1087                         }
1088                 }
1089         } else {
1090                 if (dbg_hc(chan))
1091                         dev_vdbg(hsotg->dev, "DMA enabled\n");
1092         }
1093
1094         dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1095         chan->halt_status = halt_status;
1096
1097         if (hcchar & HCCHAR_CHENA) {
1098                 if (dbg_hc(chan))
1099                         dev_vdbg(hsotg->dev, "Channel enabled\n");
1100                 chan->halt_pending = 1;
1101                 chan->halt_on_queue = 0;
1102         } else {
1103                 if (dbg_hc(chan))
1104                         dev_vdbg(hsotg->dev, "Channel disabled\n");
1105                 chan->halt_on_queue = 1;
1106         }
1107
1108         if (dbg_hc(chan)) {
1109                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1110                          chan->hc_num);
1111                 dev_vdbg(hsotg->dev, "   hcchar: 0x%08x\n",
1112                          hcchar);
1113                 dev_vdbg(hsotg->dev, "   halt_pending: %d\n",
1114                          chan->halt_pending);
1115                 dev_vdbg(hsotg->dev, "   halt_on_queue: %d\n",
1116                          chan->halt_on_queue);
1117                 dev_vdbg(hsotg->dev, "   halt_status: %d\n",
1118                          chan->halt_status);
1119         }
1120 }
1121
1122 /**
1123  * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1124  *
1125  * @hsotg: Programming view of DWC_otg controller
1126  * @chan:  Identifies the host channel to clean up
1127  *
1128  * This function is normally called after a transfer is done and the host
1129  * channel is being released
1130  */
1131 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1132 {
1133         u32 hcintmsk;
1134
1135         chan->xfer_started = 0;
1136
1137         list_del_init(&chan->split_order_list_entry);
1138
1139         /*
1140          * Clear channel interrupt enables and any unhandled channel interrupt
1141          * conditions
1142          */
1143         dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
1144         hcintmsk = 0xffffffff;
1145         hcintmsk &= ~HCINTMSK_RESERVED14_31;
1146         dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1147 }
1148
1149 /**
1150  * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1151  * which frame a periodic transfer should occur
1152  *
1153  * @hsotg:  Programming view of DWC_otg controller
1154  * @chan:   Identifies the host channel to set up and its properties
1155  * @hcchar: Current value of the HCCHAR register for the specified host channel
1156  *
1157  * This function has no effect on non-periodic transfers
1158  */
1159 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1160                                        struct dwc2_host_chan *chan, u32 *hcchar)
1161 {
1162         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1163             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1164                 int host_speed;
1165                 int xfer_ns;
1166                 int xfer_us;
1167                 int bytes_in_fifo;
1168                 u16 fifo_space;
1169                 u16 frame_number;
1170                 u16 wire_frame;
1171
1172                 /*
1173                  * Try to figure out if we're an even or odd frame. If we set
1174                  * even and the current frame number is even the the transfer
1175                  * will happen immediately.  Similar if both are odd. If one is
1176                  * even and the other is odd then the transfer will happen when
1177                  * the frame number ticks.
1178                  *
1179                  * There's a bit of a balancing act to get this right.
1180                  * Sometimes we may want to send data in the current frame (AK
1181                  * right away).  We might want to do this if the frame number
1182                  * _just_ ticked, but we might also want to do this in order
1183                  * to continue a split transaction that happened late in a
1184                  * microframe (so we didn't know to queue the next transfer
1185                  * until the frame number had ticked).  The problem is that we
1186                  * need a lot of knowledge to know if there's actually still
1187                  * time to send things or if it would be better to wait until
1188                  * the next frame.
1189                  *
1190                  * We can look at how much time is left in the current frame
1191                  * and make a guess about whether we'll have time to transfer.
1192                  * We'll do that.
1193                  */
1194
1195                 /* Get speed host is running at */
1196                 host_speed = (chan->speed != USB_SPEED_HIGH &&
1197                               !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1198
1199                 /* See how many bytes are in the periodic FIFO right now */
1200                 fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) &
1201                               TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1202                 bytes_in_fifo = sizeof(u32) *
1203                                 (hsotg->params.host_perio_tx_fifo_size -
1204                                  fifo_space);
1205
1206                 /*
1207                  * Roughly estimate bus time for everything in the periodic
1208                  * queue + our new transfer.  This is "rough" because we're
1209                  * using a function that makes takes into account IN/OUT
1210                  * and INT/ISO and we're just slamming in one value for all
1211                  * transfers.  This should be an over-estimate and that should
1212                  * be OK, but we can probably tighten it.
1213                  */
1214                 xfer_ns = usb_calc_bus_time(host_speed, false, false,
1215                                             chan->xfer_len + bytes_in_fifo);
1216                 xfer_us = NS_TO_US(xfer_ns);
1217
1218                 /* See what frame number we'll be at by the time we finish */
1219                 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1220
1221                 /* This is when we were scheduled to be on the wire */
1222                 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
1223
1224                 /*
1225                  * If we'd finish _after_ the frame we're scheduled in then
1226                  * it's hopeless.  Just schedule right away and hope for the
1227                  * best.  Note that it _might_ be wise to call back into the
1228                  * scheduler to pick a better frame, but this is better than
1229                  * nothing.
1230                  */
1231                 if (dwc2_frame_num_gt(frame_number, wire_frame)) {
1232                         dwc2_sch_vdbg(hsotg,
1233                                       "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
1234                                       chan->qh, wire_frame, frame_number,
1235                                       dwc2_frame_num_dec(frame_number,
1236                                                          wire_frame));
1237                         wire_frame = frame_number;
1238
1239                         /*
1240                          * We picked a different frame number; communicate this
1241                          * back to the scheduler so it doesn't try to schedule
1242                          * another in the same frame.
1243                          *
1244                          * Remember that next_active_frame is 1 before the wire
1245                          * frame.
1246                          */
1247                         chan->qh->next_active_frame =
1248                                 dwc2_frame_num_dec(frame_number, 1);
1249                 }
1250
1251                 if (wire_frame & 1)
1252                         *hcchar |= HCCHAR_ODDFRM;
1253                 else
1254                         *hcchar &= ~HCCHAR_ODDFRM;
1255         }
1256 }
1257
1258 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1259 {
1260         /* Set up the initial PID for the transfer */
1261         if (chan->speed == USB_SPEED_HIGH) {
1262                 if (chan->ep_is_in) {
1263                         if (chan->multi_count == 1)
1264                                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1265                         else if (chan->multi_count == 2)
1266                                 chan->data_pid_start = DWC2_HC_PID_DATA1;
1267                         else
1268                                 chan->data_pid_start = DWC2_HC_PID_DATA2;
1269                 } else {
1270                         if (chan->multi_count == 1)
1271                                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1272                         else
1273                                 chan->data_pid_start = DWC2_HC_PID_MDATA;
1274                 }
1275         } else {
1276                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1277         }
1278 }
1279
1280 /**
1281  * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1282  * the Host Channel
1283  *
1284  * @hsotg: Programming view of DWC_otg controller
1285  * @chan:  Information needed to initialize the host channel
1286  *
1287  * This function should only be called in Slave mode. For a channel associated
1288  * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1289  * associated with a periodic EP, the periodic Tx FIFO is written.
1290  *
1291  * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1292  * the number of bytes written to the Tx FIFO.
1293  */
1294 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1295                                  struct dwc2_host_chan *chan)
1296 {
1297         u32 i;
1298         u32 remaining_count;
1299         u32 byte_count;
1300         u32 dword_count;
1301         u32 __iomem *data_fifo;
1302         u32 *data_buf = (u32 *)chan->xfer_buf;
1303
1304         if (dbg_hc(chan))
1305                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1306
1307         data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
1308
1309         remaining_count = chan->xfer_len - chan->xfer_count;
1310         if (remaining_count > chan->max_packet)
1311                 byte_count = chan->max_packet;
1312         else
1313                 byte_count = remaining_count;
1314
1315         dword_count = (byte_count + 3) / 4;
1316
1317         if (((unsigned long)data_buf & 0x3) == 0) {
1318                 /* xfer_buf is DWORD aligned */
1319                 for (i = 0; i < dword_count; i++, data_buf++)
1320                         dwc2_writel(*data_buf, data_fifo);
1321         } else {
1322                 /* xfer_buf is not DWORD aligned */
1323                 for (i = 0; i < dword_count; i++, data_buf++) {
1324                         u32 data = data_buf[0] | data_buf[1] << 8 |
1325                                    data_buf[2] << 16 | data_buf[3] << 24;
1326                         dwc2_writel(data, data_fifo);
1327                 }
1328         }
1329
1330         chan->xfer_count += byte_count;
1331         chan->xfer_buf += byte_count;
1332 }
1333
1334 /**
1335  * dwc2_hc_do_ping() - Starts a PING transfer
1336  *
1337  * @hsotg: Programming view of DWC_otg controller
1338  * @chan:  Information needed to initialize the host channel
1339  *
1340  * This function should only be called in Slave mode. The Do Ping bit is set in
1341  * the HCTSIZ register, then the channel is enabled.
1342  */
1343 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1344                             struct dwc2_host_chan *chan)
1345 {
1346         u32 hcchar;
1347         u32 hctsiz;
1348
1349         if (dbg_hc(chan))
1350                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1351                          chan->hc_num);
1352
1353         hctsiz = TSIZ_DOPNG;
1354         hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1355         dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1356
1357         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1358         hcchar |= HCCHAR_CHENA;
1359         hcchar &= ~HCCHAR_CHDIS;
1360         dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1361 }
1362
1363 /**
1364  * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1365  * channel and starts the transfer
1366  *
1367  * @hsotg: Programming view of DWC_otg controller
1368  * @chan:  Information needed to initialize the host channel. The xfer_len value
1369  *         may be reduced to accommodate the max widths of the XferSize and
1370  *         PktCnt fields in the HCTSIZn register. The multi_count value may be
1371  *         changed to reflect the final xfer_len value.
1372  *
1373  * This function may be called in either Slave mode or DMA mode. In Slave mode,
1374  * the caller must ensure that there is sufficient space in the request queue
1375  * and Tx Data FIFO.
1376  *
1377  * For an OUT transfer in Slave mode, it loads a data packet into the
1378  * appropriate FIFO. If necessary, additional data packets are loaded in the
1379  * Host ISR.
1380  *
1381  * For an IN transfer in Slave mode, a data packet is requested. The data
1382  * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1383  * additional data packets are requested in the Host ISR.
1384  *
1385  * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1386  * register along with a packet count of 1 and the channel is enabled. This
1387  * causes a single PING transaction to occur. Other fields in HCTSIZ are
1388  * simply set to 0 since no data transfer occurs in this case.
1389  *
1390  * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1391  * all the information required to perform the subsequent data transfer. In
1392  * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1393  * controller performs the entire PING protocol, then starts the data
1394  * transfer.
1395  */
1396 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1397                                    struct dwc2_host_chan *chan)
1398 {
1399         u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
1400         u16 max_hc_pkt_count = hsotg->params.max_packet_count;
1401         u32 hcchar;
1402         u32 hctsiz = 0;
1403         u16 num_packets;
1404         u32 ec_mc;
1405
1406         if (dbg_hc(chan))
1407                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1408
1409         if (chan->do_ping) {
1410                 if (!hsotg->params.host_dma) {
1411                         if (dbg_hc(chan))
1412                                 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1413                         dwc2_hc_do_ping(hsotg, chan);
1414                         chan->xfer_started = 1;
1415                         return;
1416                 }
1417
1418                 if (dbg_hc(chan))
1419                         dev_vdbg(hsotg->dev, "ping, DMA\n");
1420
1421                 hctsiz |= TSIZ_DOPNG;
1422         }
1423
1424         if (chan->do_split) {
1425                 if (dbg_hc(chan))
1426                         dev_vdbg(hsotg->dev, "split\n");
1427                 num_packets = 1;
1428
1429                 if (chan->complete_split && !chan->ep_is_in)
1430                         /*
1431                          * For CSPLIT OUT Transfer, set the size to 0 so the
1432                          * core doesn't expect any data written to the FIFO
1433                          */
1434                         chan->xfer_len = 0;
1435                 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1436                         chan->xfer_len = chan->max_packet;
1437                 else if (!chan->ep_is_in && chan->xfer_len > 188)
1438                         chan->xfer_len = 188;
1439
1440                 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1441                           TSIZ_XFERSIZE_MASK;
1442
1443                 /* For split set ec_mc for immediate retries */
1444                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1445                     chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1446                         ec_mc = 3;
1447                 else
1448                         ec_mc = 1;
1449         } else {
1450                 if (dbg_hc(chan))
1451                         dev_vdbg(hsotg->dev, "no split\n");
1452                 /*
1453                  * Ensure that the transfer length and packet count will fit
1454                  * in the widths allocated for them in the HCTSIZn register
1455                  */
1456                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1457                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1458                         /*
1459                          * Make sure the transfer size is no larger than one
1460                          * (micro)frame's worth of data. (A check was done
1461                          * when the periodic transfer was accepted to ensure
1462                          * that a (micro)frame's worth of data can be
1463                          * programmed into a channel.)
1464                          */
1465                         u32 max_periodic_len =
1466                                 chan->multi_count * chan->max_packet;
1467
1468                         if (chan->xfer_len > max_periodic_len)
1469                                 chan->xfer_len = max_periodic_len;
1470                 } else if (chan->xfer_len > max_hc_xfer_size) {
1471                         /*
1472                          * Make sure that xfer_len is a multiple of max packet
1473                          * size
1474                          */
1475                         chan->xfer_len =
1476                                 max_hc_xfer_size - chan->max_packet + 1;
1477                 }
1478
1479                 if (chan->xfer_len > 0) {
1480                         num_packets = (chan->xfer_len + chan->max_packet - 1) /
1481                                         chan->max_packet;
1482                         if (num_packets > max_hc_pkt_count) {
1483                                 num_packets = max_hc_pkt_count;
1484                                 chan->xfer_len = num_packets * chan->max_packet;
1485                         }
1486                 } else {
1487                         /* Need 1 packet for transfer length of 0 */
1488                         num_packets = 1;
1489                 }
1490
1491                 if (chan->ep_is_in)
1492                         /*
1493                          * Always program an integral # of max packets for IN
1494                          * transfers
1495                          */
1496                         chan->xfer_len = num_packets * chan->max_packet;
1497
1498                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1499                     chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1500                         /*
1501                          * Make sure that the multi_count field matches the
1502                          * actual transfer length
1503                          */
1504                         chan->multi_count = num_packets;
1505
1506                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1507                         dwc2_set_pid_isoc(chan);
1508
1509                 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1510                           TSIZ_XFERSIZE_MASK;
1511
1512                 /* The ec_mc gets the multi_count for non-split */
1513                 ec_mc = chan->multi_count;
1514         }
1515
1516         chan->start_pkt_count = num_packets;
1517         hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1518         hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1519                   TSIZ_SC_MC_PID_MASK;
1520         dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1521         if (dbg_hc(chan)) {
1522                 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1523                          hctsiz, chan->hc_num);
1524
1525                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1526                          chan->hc_num);
1527                 dev_vdbg(hsotg->dev, "   Xfer Size: %d\n",
1528                          (hctsiz & TSIZ_XFERSIZE_MASK) >>
1529                          TSIZ_XFERSIZE_SHIFT);
1530                 dev_vdbg(hsotg->dev, "   Num Pkts: %d\n",
1531                          (hctsiz & TSIZ_PKTCNT_MASK) >>
1532                          TSIZ_PKTCNT_SHIFT);
1533                 dev_vdbg(hsotg->dev, "   Start PID: %d\n",
1534                          (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1535                          TSIZ_SC_MC_PID_SHIFT);
1536         }
1537
1538         if (hsotg->params.host_dma) {
1539                 dwc2_writel((u32)chan->xfer_dma,
1540                             hsotg->regs + HCDMA(chan->hc_num));
1541                 if (dbg_hc(chan))
1542                         dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1543                                  (unsigned long)chan->xfer_dma, chan->hc_num);
1544         }
1545
1546         /* Start the split */
1547         if (chan->do_split) {
1548                 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
1549
1550                 hcsplt |= HCSPLT_SPLTENA;
1551                 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
1552         }
1553
1554         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1555         hcchar &= ~HCCHAR_MULTICNT_MASK;
1556         hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1557         dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1558
1559         if (hcchar & HCCHAR_CHDIS)
1560                 dev_warn(hsotg->dev,
1561                          "%s: chdis set, channel %d, hcchar 0x%08x\n",
1562                          __func__, chan->hc_num, hcchar);
1563
1564         /* Set host channel enable after all other setup is complete */
1565         hcchar |= HCCHAR_CHENA;
1566         hcchar &= ~HCCHAR_CHDIS;
1567
1568         if (dbg_hc(chan))
1569                 dev_vdbg(hsotg->dev, "   Multi Cnt: %d\n",
1570                          (hcchar & HCCHAR_MULTICNT_MASK) >>
1571                          HCCHAR_MULTICNT_SHIFT);
1572
1573         dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1574         if (dbg_hc(chan))
1575                 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1576                          chan->hc_num);
1577
1578         chan->xfer_started = 1;
1579         chan->requests++;
1580
1581         if (!hsotg->params.host_dma &&
1582             !chan->ep_is_in && chan->xfer_len > 0)
1583                 /* Load OUT packet into the appropriate Tx FIFO */
1584                 dwc2_hc_write_packet(hsotg, chan);
1585 }
1586
1587 /**
1588  * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1589  * host channel and starts the transfer in Descriptor DMA mode
1590  *
1591  * @hsotg: Programming view of DWC_otg controller
1592  * @chan:  Information needed to initialize the host channel
1593  *
1594  * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1595  * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1596  * with micro-frame bitmap.
1597  *
1598  * Initializes HCDMA register with descriptor list address and CTD value then
1599  * starts the transfer via enabling the channel.
1600  */
1601 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1602                                  struct dwc2_host_chan *chan)
1603 {
1604         u32 hcchar;
1605         u32 hctsiz = 0;
1606
1607         if (chan->do_ping)
1608                 hctsiz |= TSIZ_DOPNG;
1609
1610         if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1611                 dwc2_set_pid_isoc(chan);
1612
1613         /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1614         hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1615                   TSIZ_SC_MC_PID_MASK;
1616
1617         /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1618         hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1619
1620         /* Non-zero only for high-speed interrupt endpoints */
1621         hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1622
1623         if (dbg_hc(chan)) {
1624                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1625                          chan->hc_num);
1626                 dev_vdbg(hsotg->dev, "   Start PID: %d\n",
1627                          chan->data_pid_start);
1628                 dev_vdbg(hsotg->dev, "   NTD: %d\n", chan->ntd - 1);
1629         }
1630
1631         dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1632
1633         dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1634                                    chan->desc_list_sz, DMA_TO_DEVICE);
1635
1636         dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num));
1637
1638         if (dbg_hc(chan))
1639                 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1640                          &chan->desc_list_addr, chan->hc_num);
1641
1642         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1643         hcchar &= ~HCCHAR_MULTICNT_MASK;
1644         hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1645                   HCCHAR_MULTICNT_MASK;
1646
1647         if (hcchar & HCCHAR_CHDIS)
1648                 dev_warn(hsotg->dev,
1649                          "%s: chdis set, channel %d, hcchar 0x%08x\n",
1650                          __func__, chan->hc_num, hcchar);
1651
1652         /* Set host channel enable after all other setup is complete */
1653         hcchar |= HCCHAR_CHENA;
1654         hcchar &= ~HCCHAR_CHDIS;
1655
1656         if (dbg_hc(chan))
1657                 dev_vdbg(hsotg->dev, "   Multi Cnt: %d\n",
1658                          (hcchar & HCCHAR_MULTICNT_MASK) >>
1659                          HCCHAR_MULTICNT_SHIFT);
1660
1661         dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1662         if (dbg_hc(chan))
1663                 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1664                          chan->hc_num);
1665
1666         chan->xfer_started = 1;
1667         chan->requests++;
1668 }
1669
1670 /**
1671  * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1672  * a previous call to dwc2_hc_start_transfer()
1673  *
1674  * @hsotg: Programming view of DWC_otg controller
1675  * @chan:  Information needed to initialize the host channel
1676  *
1677  * The caller must ensure there is sufficient space in the request queue and Tx
1678  * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1679  * the controller acts autonomously to complete transfers programmed to a host
1680  * channel.
1681  *
1682  * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1683  * if there is any data remaining to be queued. For an IN transfer, another
1684  * data packet is always requested. For the SETUP phase of a control transfer,
1685  * this function does nothing.
1686  *
1687  * Return: 1 if a new request is queued, 0 if no more requests are required
1688  * for this transfer
1689  */
1690 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1691                                      struct dwc2_host_chan *chan)
1692 {
1693         if (dbg_hc(chan))
1694                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1695                          chan->hc_num);
1696
1697         if (chan->do_split)
1698                 /* SPLITs always queue just once per channel */
1699                 return 0;
1700
1701         if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1702                 /* SETUPs are queued only once since they can't be NAK'd */
1703                 return 0;
1704
1705         if (chan->ep_is_in) {
1706                 /*
1707                  * Always queue another request for other IN transfers. If
1708                  * back-to-back INs are issued and NAKs are received for both,
1709                  * the driver may still be processing the first NAK when the
1710                  * second NAK is received. When the interrupt handler clears
1711                  * the NAK interrupt for the first NAK, the second NAK will
1712                  * not be seen. So we can't depend on the NAK interrupt
1713                  * handler to requeue a NAK'd request. Instead, IN requests
1714                  * are issued each time this function is called. When the
1715                  * transfer completes, the extra requests for the channel will
1716                  * be flushed.
1717                  */
1718                 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1719
1720                 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1721                 hcchar |= HCCHAR_CHENA;
1722                 hcchar &= ~HCCHAR_CHDIS;
1723                 if (dbg_hc(chan))
1724                         dev_vdbg(hsotg->dev, "   IN xfer: hcchar = 0x%08x\n",
1725                                  hcchar);
1726                 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1727                 chan->requests++;
1728                 return 1;
1729         }
1730
1731         /* OUT transfers */
1732
1733         if (chan->xfer_count < chan->xfer_len) {
1734                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1735                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1736                         u32 hcchar = dwc2_readl(hsotg->regs +
1737                                                 HCCHAR(chan->hc_num));
1738
1739                         dwc2_hc_set_even_odd_frame(hsotg, chan,
1740                                                    &hcchar);
1741                 }
1742
1743                 /* Load OUT packet into the appropriate Tx FIFO */
1744                 dwc2_hc_write_packet(hsotg, chan);
1745                 chan->requests++;
1746                 return 1;
1747         }
1748
1749         return 0;
1750 }
1751
1752 /*
1753  * =========================================================================
1754  *  HCD
1755  * =========================================================================
1756  */
1757
1758 /*
1759  * Processes all the URBs in a single list of QHs. Completes them with
1760  * -ETIMEDOUT and frees the QTD.
1761  *
1762  * Must be called with interrupt disabled and spinlock held
1763  */
1764 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1765                                       struct list_head *qh_list)
1766 {
1767         struct dwc2_qh *qh, *qh_tmp;
1768         struct dwc2_qtd *qtd, *qtd_tmp;
1769
1770         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1771                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1772                                          qtd_list_entry) {
1773                         dwc2_host_complete(hsotg, qtd, -ECONNRESET);
1774                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1775                 }
1776         }
1777 }
1778
1779 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1780                               struct list_head *qh_list)
1781 {
1782         struct dwc2_qtd *qtd, *qtd_tmp;
1783         struct dwc2_qh *qh, *qh_tmp;
1784         unsigned long flags;
1785
1786         if (!qh_list->next)
1787                 /* The list hasn't been initialized yet */
1788                 return;
1789
1790         spin_lock_irqsave(&hsotg->lock, flags);
1791
1792         /* Ensure there are no QTDs or URBs left */
1793         dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1794
1795         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1796                 dwc2_hcd_qh_unlink(hsotg, qh);
1797
1798                 /* Free each QTD in the QH's QTD list */
1799                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1800                                          qtd_list_entry)
1801                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1802
1803                 if (qh->channel && qh->channel->qh == qh)
1804                         qh->channel->qh = NULL;
1805
1806                 spin_unlock_irqrestore(&hsotg->lock, flags);
1807                 dwc2_hcd_qh_free(hsotg, qh);
1808                 spin_lock_irqsave(&hsotg->lock, flags);
1809         }
1810
1811         spin_unlock_irqrestore(&hsotg->lock, flags);
1812 }
1813
1814 /*
1815  * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1816  * and periodic schedules. The QTD associated with each URB is removed from
1817  * the schedule and freed. This function may be called when a disconnect is
1818  * detected or when the HCD is being stopped.
1819  *
1820  * Must be called with interrupt disabled and spinlock held
1821  */
1822 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1823 {
1824         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1825         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting);
1826         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1827         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1828         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1829         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1830         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1831 }
1832
1833 /**
1834  * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1835  *
1836  * @hsotg: Pointer to struct dwc2_hsotg
1837  */
1838 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1839 {
1840         u32 hprt0;
1841
1842         if (hsotg->op_state == OTG_STATE_B_HOST) {
1843                 /*
1844                  * Reset the port. During a HNP mode switch the reset
1845                  * needs to occur within 1ms and have a duration of at
1846                  * least 50ms.
1847                  */
1848                 hprt0 = dwc2_read_hprt0(hsotg);
1849                 hprt0 |= HPRT0_RST;
1850                 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1851         }
1852
1853         queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1854                            msecs_to_jiffies(50));
1855 }
1856
1857 /* Must be called with interrupt disabled and spinlock held */
1858 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1859 {
1860         int num_channels = hsotg->params.host_channels;
1861         struct dwc2_host_chan *channel;
1862         u32 hcchar;
1863         int i;
1864
1865         if (!hsotg->params.host_dma) {
1866                 /* Flush out any channel requests in slave mode */
1867                 for (i = 0; i < num_channels; i++) {
1868                         channel = hsotg->hc_ptr_array[i];
1869                         if (!list_empty(&channel->hc_list_entry))
1870                                 continue;
1871                         hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1872                         if (hcchar & HCCHAR_CHENA) {
1873                                 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1874                                 hcchar |= HCCHAR_CHDIS;
1875                                 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1876                         }
1877                 }
1878         }
1879
1880         for (i = 0; i < num_channels; i++) {
1881                 channel = hsotg->hc_ptr_array[i];
1882                 if (!list_empty(&channel->hc_list_entry))
1883                         continue;
1884                 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1885                 if (hcchar & HCCHAR_CHENA) {
1886                         /* Halt the channel */
1887                         hcchar |= HCCHAR_CHDIS;
1888                         dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1889                 }
1890
1891                 dwc2_hc_cleanup(hsotg, channel);
1892                 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1893                 /*
1894                  * Added for Descriptor DMA to prevent channel double cleanup in
1895                  * release_channel_ddma(), which is called from ep_disable when
1896                  * device disconnects
1897                  */
1898                 channel->qh = NULL;
1899         }
1900         /* All channels have been freed, mark them available */
1901         if (hsotg->params.uframe_sched) {
1902                 hsotg->available_host_channels =
1903                         hsotg->params.host_channels;
1904         } else {
1905                 hsotg->non_periodic_channels = 0;
1906                 hsotg->periodic_channels = 0;
1907         }
1908 }
1909
1910 /**
1911  * dwc2_hcd_connect() - Handles connect of the HCD
1912  *
1913  * @hsotg: Pointer to struct dwc2_hsotg
1914  *
1915  * Must be called with interrupt disabled and spinlock held
1916  */
1917 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1918 {
1919         if (hsotg->lx_state != DWC2_L0)
1920                 usb_hcd_resume_root_hub(hsotg->priv);
1921
1922         hsotg->flags.b.port_connect_status_change = 1;
1923         hsotg->flags.b.port_connect_status = 1;
1924 }
1925
1926 /**
1927  * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1928  *
1929  * @hsotg: Pointer to struct dwc2_hsotg
1930  * @force: If true, we won't try to reconnect even if we see device connected.
1931  *
1932  * Must be called with interrupt disabled and spinlock held
1933  */
1934 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1935 {
1936         u32 intr;
1937         u32 hprt0;
1938
1939         /* Set status flags for the hub driver */
1940         hsotg->flags.b.port_connect_status_change = 1;
1941         hsotg->flags.b.port_connect_status = 0;
1942
1943         /*
1944          * Shutdown any transfers in process by clearing the Tx FIFO Empty
1945          * interrupt mask and status bits and disabling subsequent host
1946          * channel interrupts.
1947          */
1948         intr = dwc2_readl(hsotg->regs + GINTMSK);
1949         intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
1950         dwc2_writel(intr, hsotg->regs + GINTMSK);
1951         intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
1952         dwc2_writel(intr, hsotg->regs + GINTSTS);
1953
1954         /*
1955          * Turn off the vbus power only if the core has transitioned to device
1956          * mode. If still in host mode, need to keep power on to detect a
1957          * reconnection.
1958          */
1959         if (dwc2_is_device_mode(hsotg)) {
1960                 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
1961                         dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
1962                         dwc2_writel(0, hsotg->regs + HPRT0);
1963                 }
1964
1965                 dwc2_disable_host_interrupts(hsotg);
1966         }
1967
1968         /* Respond with an error status to all URBs in the schedule */
1969         dwc2_kill_all_urbs(hsotg);
1970
1971         if (dwc2_is_host_mode(hsotg))
1972                 /* Clean up any host channels that were in use */
1973                 dwc2_hcd_cleanup_channels(hsotg);
1974
1975         dwc2_host_disconnect(hsotg);
1976
1977         /*
1978          * Add an extra check here to see if we're actually connected but
1979          * we don't have a detection interrupt pending.  This can happen if:
1980          *   1. hardware sees connect
1981          *   2. hardware sees disconnect
1982          *   3. hardware sees connect
1983          *   4. dwc2_port_intr() - clears connect interrupt
1984          *   5. dwc2_handle_common_intr() - calls here
1985          *
1986          * Without the extra check here we will end calling disconnect
1987          * and won't get any future interrupts to handle the connect.
1988          */
1989         if (!force) {
1990                 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
1991                 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
1992                         dwc2_hcd_connect(hsotg);
1993         }
1994 }
1995
1996 /**
1997  * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
1998  *
1999  * @hsotg: Pointer to struct dwc2_hsotg
2000  */
2001 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
2002 {
2003         if (hsotg->bus_suspended) {
2004                 hsotg->flags.b.port_suspend_change = 1;
2005                 usb_hcd_resume_root_hub(hsotg->priv);
2006         }
2007
2008         if (hsotg->lx_state == DWC2_L1)
2009                 hsotg->flags.b.port_l1_change = 1;
2010 }
2011
2012 /**
2013  * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
2014  *
2015  * @hsotg: Pointer to struct dwc2_hsotg
2016  *
2017  * Must be called with interrupt disabled and spinlock held
2018  */
2019 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
2020 {
2021         dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
2022
2023         /*
2024          * The root hub should be disconnected before this function is called.
2025          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
2026          * and the QH lists (via ..._hcd_endpoint_disable).
2027          */
2028
2029         /* Turn off all host-specific interrupts */
2030         dwc2_disable_host_interrupts(hsotg);
2031
2032         /* Turn off the vbus power */
2033         dev_dbg(hsotg->dev, "PortPower off\n");
2034         dwc2_writel(0, hsotg->regs + HPRT0);
2035 }
2036
2037 /* Caller must hold driver lock */
2038 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
2039                                 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
2040                                 struct dwc2_qtd *qtd)
2041 {
2042         u32 intr_mask;
2043         int retval;
2044         int dev_speed;
2045
2046         if (!hsotg->flags.b.port_connect_status) {
2047                 /* No longer connected */
2048                 dev_err(hsotg->dev, "Not connected\n");
2049                 return -ENODEV;
2050         }
2051
2052         dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
2053
2054         /* Some configurations cannot support LS traffic on a FS root port */
2055         if ((dev_speed == USB_SPEED_LOW) &&
2056             (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
2057             (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
2058                 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2059                 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2060
2061                 if (prtspd == HPRT0_SPD_FULL_SPEED)
2062                         return -ENODEV;
2063         }
2064
2065         if (!qtd)
2066                 return -EINVAL;
2067
2068         dwc2_hcd_qtd_init(qtd, urb);
2069         retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
2070         if (retval) {
2071                 dev_err(hsotg->dev,
2072                         "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
2073                         retval);
2074                 return retval;
2075         }
2076
2077         intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
2078         if (!(intr_mask & GINTSTS_SOF)) {
2079                 enum dwc2_transaction_type tr_type;
2080
2081                 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
2082                     !(qtd->urb->flags & URB_GIVEBACK_ASAP))
2083                         /*
2084                          * Do not schedule SG transactions until qtd has
2085                          * URB_GIVEBACK_ASAP set
2086                          */
2087                         return 0;
2088
2089                 tr_type = dwc2_hcd_select_transactions(hsotg);
2090                 if (tr_type != DWC2_TRANSACTION_NONE)
2091                         dwc2_hcd_queue_transactions(hsotg, tr_type);
2092         }
2093
2094         return 0;
2095 }
2096
2097 /* Must be called with interrupt disabled and spinlock held */
2098 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
2099                                 struct dwc2_hcd_urb *urb)
2100 {
2101         struct dwc2_qh *qh;
2102         struct dwc2_qtd *urb_qtd;
2103
2104         urb_qtd = urb->qtd;
2105         if (!urb_qtd) {
2106                 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
2107                 return -EINVAL;
2108         }
2109
2110         qh = urb_qtd->qh;
2111         if (!qh) {
2112                 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
2113                 return -EINVAL;
2114         }
2115
2116         urb->priv = NULL;
2117
2118         if (urb_qtd->in_process && qh->channel) {
2119                 dwc2_dump_channel_info(hsotg, qh->channel);
2120
2121                 /* The QTD is in process (it has been assigned to a channel) */
2122                 if (hsotg->flags.b.port_connect_status)
2123                         /*
2124                          * If still connected (i.e. in host mode), halt the
2125                          * channel so it can be used for other transfers. If
2126                          * no longer connected, the host registers can't be
2127                          * written to halt the channel since the core is in
2128                          * device mode.
2129                          */
2130                         dwc2_hc_halt(hsotg, qh->channel,
2131                                      DWC2_HC_XFER_URB_DEQUEUE);
2132         }
2133
2134         /*
2135          * Free the QTD and clean up the associated QH. Leave the QH in the
2136          * schedule if it has any remaining QTDs.
2137          */
2138         if (!hsotg->params.dma_desc_enable) {
2139                 u8 in_process = urb_qtd->in_process;
2140
2141                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2142                 if (in_process) {
2143                         dwc2_hcd_qh_deactivate(hsotg, qh, 0);
2144                         qh->channel = NULL;
2145                 } else if (list_empty(&qh->qtd_list)) {
2146                         dwc2_hcd_qh_unlink(hsotg, qh);
2147                 }
2148         } else {
2149                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2150         }
2151
2152         return 0;
2153 }
2154
2155 /* Must NOT be called with interrupt disabled or spinlock held */
2156 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
2157                                      struct usb_host_endpoint *ep, int retry)
2158 {
2159         struct dwc2_qtd *qtd, *qtd_tmp;
2160         struct dwc2_qh *qh;
2161         unsigned long flags;
2162         int rc;
2163
2164         spin_lock_irqsave(&hsotg->lock, flags);
2165
2166         qh = ep->hcpriv;
2167         if (!qh) {
2168                 rc = -EINVAL;
2169                 goto err;
2170         }
2171
2172         while (!list_empty(&qh->qtd_list) && retry--) {
2173                 if (retry == 0) {
2174                         dev_err(hsotg->dev,
2175                                 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
2176                         rc = -EBUSY;
2177                         goto err;
2178                 }
2179
2180                 spin_unlock_irqrestore(&hsotg->lock, flags);
2181                 msleep(20);
2182                 spin_lock_irqsave(&hsotg->lock, flags);
2183                 qh = ep->hcpriv;
2184                 if (!qh) {
2185                         rc = -EINVAL;
2186                         goto err;
2187                 }
2188         }
2189
2190         dwc2_hcd_qh_unlink(hsotg, qh);
2191
2192         /* Free each QTD in the QH's QTD list */
2193         list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
2194                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2195
2196         ep->hcpriv = NULL;
2197
2198         if (qh->channel && qh->channel->qh == qh)
2199                 qh->channel->qh = NULL;
2200
2201         spin_unlock_irqrestore(&hsotg->lock, flags);
2202
2203         dwc2_hcd_qh_free(hsotg, qh);
2204
2205         return 0;
2206
2207 err:
2208         ep->hcpriv = NULL;
2209         spin_unlock_irqrestore(&hsotg->lock, flags);
2210
2211         return rc;
2212 }
2213
2214 /* Must be called with interrupt disabled and spinlock held */
2215 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2216                                    struct usb_host_endpoint *ep)
2217 {
2218         struct dwc2_qh *qh = ep->hcpriv;
2219
2220         if (!qh)
2221                 return -EINVAL;
2222
2223         qh->data_toggle = DWC2_HC_PID_DATA0;
2224
2225         return 0;
2226 }
2227
2228 /**
2229  * dwc2_core_init() - Initializes the DWC_otg controller registers and
2230  * prepares the core for device mode or host mode operation
2231  *
2232  * @hsotg:         Programming view of the DWC_otg controller
2233  * @initial_setup: If true then this is the first init for this instance.
2234  */
2235 static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2236 {
2237         u32 usbcfg, otgctl;
2238         int retval;
2239
2240         dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2241
2242         usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2243
2244         /* Set ULPI External VBUS bit if needed */
2245         usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
2246         if (hsotg->params.phy_ulpi_ext_vbus)
2247                 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
2248
2249         /* Set external TS Dline pulsing bit if needed */
2250         usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
2251         if (hsotg->params.ts_dline)
2252                 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2253
2254         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2255
2256         /*
2257          * Reset the Controller
2258          *
2259          * We only need to reset the controller if this is a re-init.
2260          * For the first init we know for sure that earlier code reset us (it
2261          * needed to in order to properly detect various parameters).
2262          */
2263         if (!initial_setup) {
2264                 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
2265                 if (retval) {
2266                         dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2267                                 __func__);
2268                         return retval;
2269                 }
2270         }
2271
2272         /*
2273          * This needs to happen in FS mode before any other programming occurs
2274          */
2275         retval = dwc2_phy_init(hsotg, initial_setup);
2276         if (retval)
2277                 return retval;
2278
2279         /* Program the GAHBCFG Register */
2280         retval = dwc2_gahbcfg_init(hsotg);
2281         if (retval)
2282                 return retval;
2283
2284         /* Program the GUSBCFG register */
2285         dwc2_gusbcfg_init(hsotg);
2286
2287         /* Program the GOTGCTL register */
2288         otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2289         otgctl &= ~GOTGCTL_OTGVER;
2290         dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2291
2292         /* Clear the SRP success bit for FS-I2c */
2293         hsotg->srp_success = 0;
2294
2295         /* Enable common interrupts */
2296         dwc2_enable_common_interrupts(hsotg);
2297
2298         /*
2299          * Do device or host initialization based on mode during PCD and
2300          * HCD initialization
2301          */
2302         if (dwc2_is_host_mode(hsotg)) {
2303                 dev_dbg(hsotg->dev, "Host Mode\n");
2304                 hsotg->op_state = OTG_STATE_A_HOST;
2305         } else {
2306                 dev_dbg(hsotg->dev, "Device Mode\n");
2307                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2308         }
2309
2310         return 0;
2311 }
2312
2313 /**
2314  * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2315  * Host mode
2316  *
2317  * @hsotg: Programming view of DWC_otg controller
2318  *
2319  * This function flushes the Tx and Rx FIFOs and flushes any entries in the
2320  * request queues. Host channels are reset to ensure that they are ready for
2321  * performing transfers.
2322  */
2323 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2324 {
2325         u32 hcfg, hfir, otgctl;
2326
2327         dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2328
2329         /* Restart the Phy Clock */
2330         dwc2_writel(0, hsotg->regs + PCGCTL);
2331
2332         /* Initialize Host Configuration Register */
2333         dwc2_init_fs_ls_pclk_sel(hsotg);
2334         if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2335             hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2336                 hcfg = dwc2_readl(hsotg->regs + HCFG);
2337                 hcfg |= HCFG_FSLSSUPP;
2338                 dwc2_writel(hcfg, hsotg->regs + HCFG);
2339         }
2340
2341         /*
2342          * This bit allows dynamic reloading of the HFIR register during
2343          * runtime. This bit needs to be programmed during initial configuration
2344          * and its value must not be changed during runtime.
2345          */
2346         if (hsotg->params.reload_ctl) {
2347                 hfir = dwc2_readl(hsotg->regs + HFIR);
2348                 hfir |= HFIR_RLDCTRL;
2349                 dwc2_writel(hfir, hsotg->regs + HFIR);
2350         }
2351
2352         if (hsotg->params.dma_desc_enable) {
2353                 u32 op_mode = hsotg->hw_params.op_mode;
2354
2355                 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2356                     !hsotg->hw_params.dma_desc_enable ||
2357                     op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
2358                     op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
2359                     op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
2360                         dev_err(hsotg->dev,
2361                                 "Hardware does not support descriptor DMA mode -\n");
2362                         dev_err(hsotg->dev,
2363                                 "falling back to buffer DMA mode.\n");
2364                         hsotg->params.dma_desc_enable = false;
2365                 } else {
2366                         hcfg = dwc2_readl(hsotg->regs + HCFG);
2367                         hcfg |= HCFG_DESCDMA;
2368                         dwc2_writel(hcfg, hsotg->regs + HCFG);
2369                 }
2370         }
2371
2372         /* Configure data FIFO sizes */
2373         dwc2_config_fifos(hsotg);
2374
2375         /* TODO - check this */
2376         /* Clear Host Set HNP Enable in the OTG Control Register */
2377         otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2378         otgctl &= ~GOTGCTL_HSTSETHNPEN;
2379         dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2380
2381         /* Make sure the FIFOs are flushed */
2382         dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2383         dwc2_flush_rx_fifo(hsotg);
2384
2385         /* Clear Host Set HNP Enable in the OTG Control Register */
2386         otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2387         otgctl &= ~GOTGCTL_HSTSETHNPEN;
2388         dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2389
2390         if (!hsotg->params.dma_desc_enable) {
2391                 int num_channels, i;
2392                 u32 hcchar;
2393
2394                 /* Flush out any leftover queued requests */
2395                 num_channels = hsotg->params.host_channels;
2396                 for (i = 0; i < num_channels; i++) {
2397                         hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2398                         hcchar &= ~HCCHAR_CHENA;
2399                         hcchar |= HCCHAR_CHDIS;
2400                         hcchar &= ~HCCHAR_EPDIR;
2401                         dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2402                 }
2403
2404                 /* Halt all channels to put them into a known state */
2405                 for (i = 0; i < num_channels; i++) {
2406                         int count = 0;
2407
2408                         hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2409                         hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2410                         hcchar &= ~HCCHAR_EPDIR;
2411                         dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2412                         dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2413                                 __func__, i);
2414                         do {
2415                                 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2416                                 if (++count > 1000) {
2417                                         dev_err(hsotg->dev,
2418                                                 "Unable to clear enable on channel %d\n",
2419                                                 i);
2420                                         break;
2421                                 }
2422                                 udelay(1);
2423                         } while (hcchar & HCCHAR_CHENA);
2424                 }
2425         }
2426
2427         /* Turn on the vbus power */
2428         dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2429         if (hsotg->op_state == OTG_STATE_A_HOST) {
2430                 u32 hprt0 = dwc2_read_hprt0(hsotg);
2431
2432                 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2433                         !!(hprt0 & HPRT0_PWR));
2434                 if (!(hprt0 & HPRT0_PWR)) {
2435                         hprt0 |= HPRT0_PWR;
2436                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
2437                 }
2438         }
2439
2440         dwc2_enable_host_interrupts(hsotg);
2441 }
2442
2443 /*
2444  * Initializes dynamic portions of the DWC_otg HCD state
2445  *
2446  * Must be called with interrupt disabled and spinlock held
2447  */
2448 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2449 {
2450         struct dwc2_host_chan *chan, *chan_tmp;
2451         int num_channels;
2452         int i;
2453
2454         hsotg->flags.d32 = 0;
2455         hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
2456
2457         if (hsotg->params.uframe_sched) {
2458                 hsotg->available_host_channels =
2459                         hsotg->params.host_channels;
2460         } else {
2461                 hsotg->non_periodic_channels = 0;
2462                 hsotg->periodic_channels = 0;
2463         }
2464
2465         /*
2466          * Put all channels in the free channel list and clean up channel
2467          * states
2468          */
2469         list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2470                                  hc_list_entry)
2471                 list_del_init(&chan->hc_list_entry);
2472
2473         num_channels = hsotg->params.host_channels;
2474         for (i = 0; i < num_channels; i++) {
2475                 chan = hsotg->hc_ptr_array[i];
2476                 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2477                 dwc2_hc_cleanup(hsotg, chan);
2478         }
2479
2480         /* Initialize the DWC core for host mode operation */
2481         dwc2_core_host_init(hsotg);
2482 }
2483
2484 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2485                                struct dwc2_host_chan *chan,
2486                                struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2487 {
2488         int hub_addr, hub_port;
2489
2490         chan->do_split = 1;
2491         chan->xact_pos = qtd->isoc_split_pos;
2492         chan->complete_split = qtd->complete_split;
2493         dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2494         chan->hub_addr = (u8)hub_addr;
2495         chan->hub_port = (u8)hub_port;
2496 }
2497
2498 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2499                               struct dwc2_host_chan *chan,
2500                               struct dwc2_qtd *qtd)
2501 {
2502         struct dwc2_hcd_urb *urb = qtd->urb;
2503         struct dwc2_hcd_iso_packet_desc *frame_desc;
2504
2505         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
2506         case USB_ENDPOINT_XFER_CONTROL:
2507                 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
2508
2509                 switch (qtd->control_phase) {
2510                 case DWC2_CONTROL_SETUP:
2511                         dev_vdbg(hsotg->dev, "  Control setup transaction\n");
2512                         chan->do_ping = 0;
2513                         chan->ep_is_in = 0;
2514                         chan->data_pid_start = DWC2_HC_PID_SETUP;
2515                         if (hsotg->params.host_dma)
2516                                 chan->xfer_dma = urb->setup_dma;
2517                         else
2518                                 chan->xfer_buf = urb->setup_packet;
2519                         chan->xfer_len = 8;
2520                         break;
2521
2522                 case DWC2_CONTROL_DATA:
2523                         dev_vdbg(hsotg->dev, "  Control data transaction\n");
2524                         chan->data_pid_start = qtd->data_toggle;
2525                         break;
2526
2527                 case DWC2_CONTROL_STATUS:
2528                         /*
2529                          * Direction is opposite of data direction or IN if no
2530                          * data
2531                          */
2532                         dev_vdbg(hsotg->dev, "  Control status transaction\n");
2533                         if (urb->length == 0)
2534                                 chan->ep_is_in = 1;
2535                         else
2536                                 chan->ep_is_in =
2537                                         dwc2_hcd_is_pipe_out(&urb->pipe_info);
2538                         if (chan->ep_is_in)
2539                                 chan->do_ping = 0;
2540                         chan->data_pid_start = DWC2_HC_PID_DATA1;
2541                         chan->xfer_len = 0;
2542                         if (hsotg->params.host_dma)
2543                                 chan->xfer_dma = hsotg->status_buf_dma;
2544                         else
2545                                 chan->xfer_buf = hsotg->status_buf;
2546                         break;
2547                 }
2548                 break;
2549
2550         case USB_ENDPOINT_XFER_BULK:
2551                 chan->ep_type = USB_ENDPOINT_XFER_BULK;
2552                 break;
2553
2554         case USB_ENDPOINT_XFER_INT:
2555                 chan->ep_type = USB_ENDPOINT_XFER_INT;
2556                 break;
2557
2558         case USB_ENDPOINT_XFER_ISOC:
2559                 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
2560                 if (hsotg->params.dma_desc_enable)
2561                         break;
2562
2563                 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
2564                 frame_desc->status = 0;
2565
2566                 if (hsotg->params.host_dma) {
2567                         chan->xfer_dma = urb->dma;
2568                         chan->xfer_dma += frame_desc->offset +
2569                                         qtd->isoc_split_offset;
2570                 } else {
2571                         chan->xfer_buf = urb->buf;
2572                         chan->xfer_buf += frame_desc->offset +
2573                                         qtd->isoc_split_offset;
2574                 }
2575
2576                 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2577
2578                 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
2579                         if (chan->xfer_len <= 188)
2580                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
2581                         else
2582                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
2583                 }
2584                 break;
2585         }
2586 }
2587
2588 #define DWC2_USB_DMA_ALIGN 4
2589
2590 struct dma_aligned_buffer {
2591         void *kmalloc_ptr;
2592         void *old_xfer_buffer;
2593         u8 data[0];
2594 };
2595
2596 static void dwc2_free_dma_aligned_buffer(struct urb *urb)
2597 {
2598         struct dma_aligned_buffer *temp;
2599
2600         if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2601                 return;
2602
2603         temp = container_of(urb->transfer_buffer,
2604                             struct dma_aligned_buffer, data);
2605
2606         if (usb_urb_dir_in(urb))
2607                 memcpy(temp->old_xfer_buffer, temp->data,
2608                        urb->transfer_buffer_length);
2609         urb->transfer_buffer = temp->old_xfer_buffer;
2610         kfree(temp->kmalloc_ptr);
2611
2612         urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2613 }
2614
2615 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
2616 {
2617         struct dma_aligned_buffer *temp, *kmalloc_ptr;
2618         size_t kmalloc_size;
2619
2620         if (urb->num_sgs || urb->sg ||
2621             urb->transfer_buffer_length == 0 ||
2622             !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
2623                 return 0;
2624
2625         /* Allocate a buffer with enough padding for alignment */
2626         kmalloc_size = urb->transfer_buffer_length +
2627                 sizeof(struct dma_aligned_buffer) + DWC2_USB_DMA_ALIGN - 1;
2628
2629         kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2630         if (!kmalloc_ptr)
2631                 return -ENOMEM;
2632
2633         /* Position our struct dma_aligned_buffer such that data is aligned */
2634         temp = PTR_ALIGN(kmalloc_ptr + 1, DWC2_USB_DMA_ALIGN) - 1;
2635         temp->kmalloc_ptr = kmalloc_ptr;
2636         temp->old_xfer_buffer = urb->transfer_buffer;
2637         if (usb_urb_dir_out(urb))
2638                 memcpy(temp->data, urb->transfer_buffer,
2639                        urb->transfer_buffer_length);
2640         urb->transfer_buffer = temp->data;
2641
2642         urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2643
2644         return 0;
2645 }
2646
2647 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2648                                 gfp_t mem_flags)
2649 {
2650         int ret;
2651
2652         /* We assume setup_dma is always aligned; warn if not */
2653         WARN_ON_ONCE(urb->setup_dma &&
2654                      (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
2655
2656         ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
2657         if (ret)
2658                 return ret;
2659
2660         ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2661         if (ret)
2662                 dwc2_free_dma_aligned_buffer(urb);
2663
2664         return ret;
2665 }
2666
2667 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2668 {
2669         usb_hcd_unmap_urb_for_dma(hcd, urb);
2670         dwc2_free_dma_aligned_buffer(urb);
2671 }
2672
2673 /**
2674  * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2675  * channel and initializes the host channel to perform the transactions. The
2676  * host channel is removed from the free list.
2677  *
2678  * @hsotg: The HCD state structure
2679  * @qh:    Transactions from the first QTD for this QH are selected and assigned
2680  *         to a free host channel
2681  */
2682 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2683 {
2684         struct dwc2_host_chan *chan;
2685         struct dwc2_hcd_urb *urb;
2686         struct dwc2_qtd *qtd;
2687
2688         if (dbg_qh(qh))
2689                 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
2690
2691         if (list_empty(&qh->qtd_list)) {
2692                 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
2693                 return -ENOMEM;
2694         }
2695
2696         if (list_empty(&hsotg->free_hc_list)) {
2697                 dev_dbg(hsotg->dev, "No free channel to assign\n");
2698                 return -ENOMEM;
2699         }
2700
2701         chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2702                                 hc_list_entry);
2703
2704         /* Remove host channel from free list */
2705         list_del_init(&chan->hc_list_entry);
2706
2707         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
2708         urb = qtd->urb;
2709         qh->channel = chan;
2710         qtd->in_process = 1;
2711
2712         /*
2713          * Use usb_pipedevice to determine device address. This address is
2714          * 0 before the SET_ADDRESS command and the correct address afterward.
2715          */
2716         chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
2717         chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
2718         chan->speed = qh->dev_speed;
2719         chan->max_packet = dwc2_max_packet(qh->maxp);
2720
2721         chan->xfer_started = 0;
2722         chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2723         chan->error_state = (qtd->error_count > 0);
2724         chan->halt_on_queue = 0;
2725         chan->halt_pending = 0;
2726         chan->requests = 0;
2727
2728         /*
2729          * The following values may be modified in the transfer type section
2730          * below. The xfer_len value may be reduced when the transfer is
2731          * started to accommodate the max widths of the XferSize and PktCnt
2732          * fields in the HCTSIZn register.
2733          */
2734
2735         chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
2736         if (chan->ep_is_in)
2737                 chan->do_ping = 0;
2738         else
2739                 chan->do_ping = qh->ping_state;
2740
2741         chan->data_pid_start = qh->data_toggle;
2742         chan->multi_count = 1;
2743
2744         if (urb->actual_length > urb->length &&
2745             !dwc2_hcd_is_pipe_in(&urb->pipe_info))
2746                 urb->actual_length = urb->length;
2747
2748         if (hsotg->params.host_dma)
2749                 chan->xfer_dma = urb->dma + urb->actual_length;
2750         else
2751                 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
2752
2753         chan->xfer_len = urb->length - urb->actual_length;
2754         chan->xfer_count = 0;
2755
2756         /* Set the split attributes if required */
2757         if (qh->do_split)
2758                 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2759         else
2760                 chan->do_split = 0;
2761
2762         /* Set the transfer attributes */
2763         dwc2_hc_init_xfer(hsotg, chan, qtd);
2764
2765         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2766             chan->ep_type == USB_ENDPOINT_XFER_ISOC)
2767                 /*
2768                  * This value may be modified when the transfer is started
2769                  * to reflect the actual transfer length
2770                  */
2771                 chan->multi_count = dwc2_hb_mult(qh->maxp);
2772
2773         if (hsotg->params.dma_desc_enable) {
2774                 chan->desc_list_addr = qh->desc_list_dma;
2775                 chan->desc_list_sz = qh->desc_list_sz;
2776         }
2777
2778         dwc2_hc_init(hsotg, chan);
2779         chan->qh = qh;
2780
2781         return 0;
2782 }
2783
2784 /**
2785  * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2786  * schedule and assigns them to available host channels. Called from the HCD
2787  * interrupt handler functions.
2788  *
2789  * @hsotg: The HCD state structure
2790  *
2791  * Return: The types of new transactions that were assigned to host channels
2792  */
2793 enum dwc2_transaction_type dwc2_hcd_select_transactions(
2794                 struct dwc2_hsotg *hsotg)
2795 {
2796         enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
2797         struct list_head *qh_ptr;
2798         struct dwc2_qh *qh;
2799         int num_channels;
2800
2801 #ifdef DWC2_DEBUG_SOF
2802         dev_vdbg(hsotg->dev, "  Select Transactions\n");
2803 #endif
2804
2805         /* Process entries in the periodic ready list */
2806         qh_ptr = hsotg->periodic_sched_ready.next;
2807         while (qh_ptr != &hsotg->periodic_sched_ready) {
2808                 if (list_empty(&hsotg->free_hc_list))
2809                         break;
2810                 if (hsotg->params.uframe_sched) {
2811                         if (hsotg->available_host_channels <= 1)
2812                                 break;
2813                         hsotg->available_host_channels--;
2814                 }
2815                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2816                 if (dwc2_assign_and_init_hc(hsotg, qh))
2817                         break;
2818
2819                 /*
2820                  * Move the QH from the periodic ready schedule to the
2821                  * periodic assigned schedule
2822                  */
2823                 qh_ptr = qh_ptr->next;
2824                 list_move_tail(&qh->qh_list_entry,
2825                                &hsotg->periodic_sched_assigned);
2826                 ret_val = DWC2_TRANSACTION_PERIODIC;
2827         }
2828
2829         /*
2830          * Process entries in the inactive portion of the non-periodic
2831          * schedule. Some free host channels may not be used if they are
2832          * reserved for periodic transfers.
2833          */
2834         num_channels = hsotg->params.host_channels;
2835         qh_ptr = hsotg->non_periodic_sched_inactive.next;
2836         while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
2837                 if (!hsotg->params.uframe_sched &&
2838                     hsotg->non_periodic_channels >= num_channels -
2839                                                 hsotg->periodic_channels)
2840                         break;
2841                 if (list_empty(&hsotg->free_hc_list))
2842                         break;
2843                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2844                 if (hsotg->params.uframe_sched) {
2845                         if (hsotg->available_host_channels < 1)
2846                                 break;
2847                         hsotg->available_host_channels--;
2848                 }
2849
2850                 if (dwc2_assign_and_init_hc(hsotg, qh))
2851                         break;
2852
2853                 /*
2854                  * Move the QH from the non-periodic inactive schedule to the
2855                  * non-periodic active schedule
2856                  */
2857                 qh_ptr = qh_ptr->next;
2858                 list_move_tail(&qh->qh_list_entry,
2859                                &hsotg->non_periodic_sched_active);
2860
2861                 if (ret_val == DWC2_TRANSACTION_NONE)
2862                         ret_val = DWC2_TRANSACTION_NON_PERIODIC;
2863                 else
2864                         ret_val = DWC2_TRANSACTION_ALL;
2865
2866                 if (!hsotg->params.uframe_sched)
2867                         hsotg->non_periodic_channels++;
2868         }
2869
2870         return ret_val;
2871 }
2872
2873 /**
2874  * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2875  * a host channel associated with either a periodic or non-periodic transfer
2876  *
2877  * @hsotg: The HCD state structure
2878  * @chan:  Host channel descriptor associated with either a periodic or
2879  *         non-periodic transfer
2880  * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
2881  *                     for periodic transfers or the non-periodic Tx FIFO
2882  *                     for non-periodic transfers
2883  *
2884  * Return: 1 if a request is queued and more requests may be needed to
2885  * complete the transfer, 0 if no more requests are required for this
2886  * transfer, -1 if there is insufficient space in the Tx FIFO
2887  *
2888  * This function assumes that there is space available in the appropriate
2889  * request queue. For an OUT transfer or SETUP transaction in Slave mode,
2890  * it checks whether space is available in the appropriate Tx FIFO.
2891  *
2892  * Must be called with interrupt disabled and spinlock held
2893  */
2894 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
2895                                   struct dwc2_host_chan *chan,
2896                                   u16 fifo_dwords_avail)
2897 {
2898         int retval = 0;
2899
2900         if (chan->do_split)
2901                 /* Put ourselves on the list to keep order straight */
2902                 list_move_tail(&chan->split_order_list_entry,
2903                                &hsotg->split_order);
2904
2905         if (hsotg->params.host_dma) {
2906                 if (hsotg->params.dma_desc_enable) {
2907                         if (!chan->xfer_started ||
2908                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2909                                 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
2910                                 chan->qh->ping_state = 0;
2911                         }
2912                 } else if (!chan->xfer_started) {
2913                         dwc2_hc_start_transfer(hsotg, chan);
2914                         chan->qh->ping_state = 0;
2915                 }
2916         } else if (chan->halt_pending) {
2917                 /* Don't queue a request if the channel has been halted */
2918         } else if (chan->halt_on_queue) {
2919                 dwc2_hc_halt(hsotg, chan, chan->halt_status);
2920         } else if (chan->do_ping) {
2921                 if (!chan->xfer_started)
2922                         dwc2_hc_start_transfer(hsotg, chan);
2923         } else if (!chan->ep_is_in ||
2924                    chan->data_pid_start == DWC2_HC_PID_SETUP) {
2925                 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
2926                         if (!chan->xfer_started) {
2927                                 dwc2_hc_start_transfer(hsotg, chan);
2928                                 retval = 1;
2929                         } else {
2930                                 retval = dwc2_hc_continue_transfer(hsotg, chan);
2931                         }
2932                 } else {
2933                         retval = -1;
2934                 }
2935         } else {
2936                 if (!chan->xfer_started) {
2937                         dwc2_hc_start_transfer(hsotg, chan);
2938                         retval = 1;
2939                 } else {
2940                         retval = dwc2_hc_continue_transfer(hsotg, chan);
2941                 }
2942         }
2943
2944         return retval;
2945 }
2946
2947 /*
2948  * Processes periodic channels for the next frame and queues transactions for
2949  * these channels to the DWC_otg controller. After queueing transactions, the
2950  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
2951  * to queue as Periodic Tx FIFO or request queue space becomes available.
2952  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
2953  *
2954  * Must be called with interrupt disabled and spinlock held
2955  */
2956 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
2957 {
2958         struct list_head *qh_ptr;
2959         struct dwc2_qh *qh;
2960         u32 tx_status;
2961         u32 fspcavail;
2962         u32 gintmsk;
2963         int status;
2964         bool no_queue_space = false;
2965         bool no_fifo_space = false;
2966         u32 qspcavail;
2967
2968         /* If empty list then just adjust interrupt enables */
2969         if (list_empty(&hsotg->periodic_sched_assigned))
2970                 goto exit;
2971
2972         if (dbg_perio())
2973                 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
2974
2975         tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2976         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2977                     TXSTS_QSPCAVAIL_SHIFT;
2978         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2979                     TXSTS_FSPCAVAIL_SHIFT;
2980
2981         if (dbg_perio()) {
2982                 dev_vdbg(hsotg->dev, "  P Tx Req Queue Space Avail (before queue): %d\n",
2983                          qspcavail);
2984                 dev_vdbg(hsotg->dev, "  P Tx FIFO Space Avail (before queue): %d\n",
2985                          fspcavail);
2986         }
2987
2988         qh_ptr = hsotg->periodic_sched_assigned.next;
2989         while (qh_ptr != &hsotg->periodic_sched_assigned) {
2990                 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2991                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2992                             TXSTS_QSPCAVAIL_SHIFT;
2993                 if (qspcavail == 0) {
2994                         no_queue_space = true;
2995                         break;
2996                 }
2997
2998                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2999                 if (!qh->channel) {
3000                         qh_ptr = qh_ptr->next;
3001                         continue;
3002                 }
3003
3004                 /* Make sure EP's TT buffer is clean before queueing qtds */
3005                 if (qh->tt_buffer_dirty) {
3006                         qh_ptr = qh_ptr->next;
3007                         continue;
3008                 }
3009
3010                 /*
3011                  * Set a flag if we're queuing high-bandwidth in slave mode.
3012                  * The flag prevents any halts to get into the request queue in
3013                  * the middle of multiple high-bandwidth packets getting queued.
3014                  */
3015                 if (!hsotg->params.host_dma &&
3016                     qh->channel->multi_count > 1)
3017                         hsotg->queuing_high_bandwidth = 1;
3018
3019                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3020                             TXSTS_FSPCAVAIL_SHIFT;
3021                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3022                 if (status < 0) {
3023                         no_fifo_space = true;
3024                         break;
3025                 }
3026
3027                 /*
3028                  * In Slave mode, stay on the current transfer until there is
3029                  * nothing more to do or the high-bandwidth request count is
3030                  * reached. In DMA mode, only need to queue one request. The
3031                  * controller automatically handles multiple packets for
3032                  * high-bandwidth transfers.
3033                  */
3034                 if (hsotg->params.host_dma || status == 0 ||
3035                     qh->channel->requests == qh->channel->multi_count) {
3036                         qh_ptr = qh_ptr->next;
3037                         /*
3038                          * Move the QH from the periodic assigned schedule to
3039                          * the periodic queued schedule
3040                          */
3041                         list_move_tail(&qh->qh_list_entry,
3042                                        &hsotg->periodic_sched_queued);
3043
3044                         /* done queuing high bandwidth */
3045                         hsotg->queuing_high_bandwidth = 0;
3046                 }
3047         }
3048
3049 exit:
3050         if (no_queue_space || no_fifo_space ||
3051             (!hsotg->params.host_dma &&
3052              !list_empty(&hsotg->periodic_sched_assigned))) {
3053                 /*
3054                  * May need to queue more transactions as the request
3055                  * queue or Tx FIFO empties. Enable the periodic Tx
3056                  * FIFO empty interrupt. (Always use the half-empty
3057                  * level to ensure that new requests are loaded as
3058                  * soon as possible.)
3059                  */
3060                 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3061                 if (!(gintmsk & GINTSTS_PTXFEMP)) {
3062                         gintmsk |= GINTSTS_PTXFEMP;
3063                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3064                 }
3065         } else {
3066                 /*
3067                  * Disable the Tx FIFO empty interrupt since there are
3068                  * no more transactions that need to be queued right
3069                  * now. This function is called from interrupt
3070                  * handlers to queue more transactions as transfer
3071                  * states change.
3072                  */
3073                 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3074                 if (gintmsk & GINTSTS_PTXFEMP) {
3075                         gintmsk &= ~GINTSTS_PTXFEMP;
3076                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3077                 }
3078         }
3079 }
3080
3081 /*
3082  * Processes active non-periodic channels and queues transactions for these
3083  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3084  * FIFO Empty interrupt is enabled if there are more transactions to queue as
3085  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3086  * FIFO Empty interrupt is disabled.
3087  *
3088  * Must be called with interrupt disabled and spinlock held
3089  */
3090 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3091 {
3092         struct list_head *orig_qh_ptr;
3093         struct dwc2_qh *qh;
3094         u32 tx_status;
3095         u32 qspcavail;
3096         u32 fspcavail;
3097         u32 gintmsk;
3098         int status;
3099         int no_queue_space = 0;
3100         int no_fifo_space = 0;
3101         int more_to_do = 0;
3102
3103         dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3104
3105         tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3106         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3107                     TXSTS_QSPCAVAIL_SHIFT;
3108         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3109                     TXSTS_FSPCAVAIL_SHIFT;
3110         dev_vdbg(hsotg->dev, "  NP Tx Req Queue Space Avail (before queue): %d\n",
3111                  qspcavail);
3112         dev_vdbg(hsotg->dev, "  NP Tx FIFO Space Avail (before queue): %d\n",
3113                  fspcavail);
3114
3115         /*
3116          * Keep track of the starting point. Skip over the start-of-list
3117          * entry.
3118          */
3119         if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3120                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3121         orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3122
3123         /*
3124          * Process once through the active list or until no more space is
3125          * available in the request queue or the Tx FIFO
3126          */
3127         do {
3128                 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3129                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3130                             TXSTS_QSPCAVAIL_SHIFT;
3131                 if (!hsotg->params.host_dma && qspcavail == 0) {
3132                         no_queue_space = 1;
3133                         break;
3134                 }
3135
3136                 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3137                                 qh_list_entry);
3138                 if (!qh->channel)
3139                         goto next;
3140
3141                 /* Make sure EP's TT buffer is clean before queueing qtds */
3142                 if (qh->tt_buffer_dirty)
3143                         goto next;
3144
3145                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3146                             TXSTS_FSPCAVAIL_SHIFT;
3147                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3148
3149                 if (status > 0) {
3150                         more_to_do = 1;
3151                 } else if (status < 0) {
3152                         no_fifo_space = 1;
3153                         break;
3154                 }
3155 next:
3156                 /* Advance to next QH, skipping start-of-list entry */
3157                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3158                 if (hsotg->non_periodic_qh_ptr ==
3159                                 &hsotg->non_periodic_sched_active)
3160                         hsotg->non_periodic_qh_ptr =
3161                                         hsotg->non_periodic_qh_ptr->next;
3162         } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3163
3164         if (!hsotg->params.host_dma) {
3165                 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3166                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3167                             TXSTS_QSPCAVAIL_SHIFT;
3168                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3169                             TXSTS_FSPCAVAIL_SHIFT;
3170                 dev_vdbg(hsotg->dev,
3171                          "  NP Tx Req Queue Space Avail (after queue): %d\n",
3172                          qspcavail);
3173                 dev_vdbg(hsotg->dev,
3174                          "  NP Tx FIFO Space Avail (after queue): %d\n",
3175                          fspcavail);
3176
3177                 if (more_to_do || no_queue_space || no_fifo_space) {
3178                         /*
3179                          * May need to queue more transactions as the request
3180                          * queue or Tx FIFO empties. Enable the non-periodic
3181                          * Tx FIFO empty interrupt. (Always use the half-empty
3182                          * level to ensure that new requests are loaded as
3183                          * soon as possible.)
3184                          */
3185                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3186                         gintmsk |= GINTSTS_NPTXFEMP;
3187                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3188                 } else {
3189                         /*
3190                          * Disable the Tx FIFO empty interrupt since there are
3191                          * no more transactions that need to be queued right
3192                          * now. This function is called from interrupt
3193                          * handlers to queue more transactions as transfer
3194                          * states change.
3195                          */
3196                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3197                         gintmsk &= ~GINTSTS_NPTXFEMP;
3198                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3199                 }
3200         }
3201 }
3202
3203 /**
3204  * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3205  * and queues transactions for these channels to the DWC_otg controller. Called
3206  * from the HCD interrupt handler functions.
3207  *
3208  * @hsotg:   The HCD state structure
3209  * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3210  *           or both)
3211  *
3212  * Must be called with interrupt disabled and spinlock held
3213  */
3214 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3215                                  enum dwc2_transaction_type tr_type)
3216 {
3217 #ifdef DWC2_DEBUG_SOF
3218         dev_vdbg(hsotg->dev, "Queue Transactions\n");
3219 #endif
3220         /* Process host channels associated with periodic transfers */
3221         if (tr_type == DWC2_TRANSACTION_PERIODIC ||
3222             tr_type == DWC2_TRANSACTION_ALL)
3223                 dwc2_process_periodic_channels(hsotg);
3224
3225         /* Process host channels associated with non-periodic transfers */
3226         if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
3227             tr_type == DWC2_TRANSACTION_ALL) {
3228                 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3229                         dwc2_process_non_periodic_channels(hsotg);
3230                 } else {
3231                         /*
3232                          * Ensure NP Tx FIFO empty interrupt is disabled when
3233                          * there are no non-periodic transfers to process
3234                          */
3235                         u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3236
3237                         gintmsk &= ~GINTSTS_NPTXFEMP;
3238                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3239                 }
3240         }
3241 }
3242
3243 static void dwc2_conn_id_status_change(struct work_struct *work)
3244 {
3245         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3246                                                 wf_otg);
3247         u32 count = 0;
3248         u32 gotgctl;
3249         unsigned long flags;
3250
3251         dev_dbg(hsotg->dev, "%s()\n", __func__);
3252
3253         gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3254         dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3255         dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3256                 !!(gotgctl & GOTGCTL_CONID_B));
3257
3258         /* B-Device connector (Device Mode) */
3259         if (gotgctl & GOTGCTL_CONID_B) {
3260                 /* Wait for switch to device mode */
3261                 dev_dbg(hsotg->dev, "connId B\n");
3262                 if (hsotg->bus_suspended) {
3263                         dev_info(hsotg->dev,
3264                                  "Do port resume before switching to device mode\n");
3265                         dwc2_port_resume(hsotg);
3266                 }
3267                 while (!dwc2_is_device_mode(hsotg)) {
3268                         dev_info(hsotg->dev,
3269                                  "Waiting for Peripheral Mode, Mode=%s\n",
3270                                  dwc2_is_host_mode(hsotg) ? "Host" :
3271                                  "Peripheral");
3272                         msleep(20);
3273                         /*
3274                          * Sometimes the initial GOTGCTRL read is wrong, so
3275                          * check it again and jump to host mode if that was
3276                          * the case.
3277                          */
3278                         gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3279                         if (!(gotgctl & GOTGCTL_CONID_B))
3280                                 goto host;
3281                         if (++count > 250)
3282                                 break;
3283                 }
3284                 if (count > 250)
3285                         dev_err(hsotg->dev,
3286                                 "Connection id status change timed out\n");
3287                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3288                 dwc2_core_init(hsotg, false);
3289                 dwc2_enable_global_interrupts(hsotg);
3290                 spin_lock_irqsave(&hsotg->lock, flags);
3291                 dwc2_hsotg_core_init_disconnected(hsotg, false);
3292                 spin_unlock_irqrestore(&hsotg->lock, flags);
3293                 dwc2_hsotg_core_connect(hsotg);
3294         } else {
3295 host:
3296                 /* A-Device connector (Host Mode) */
3297                 dev_dbg(hsotg->dev, "connId A\n");
3298                 while (!dwc2_is_host_mode(hsotg)) {
3299                         dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3300                                  dwc2_is_host_mode(hsotg) ?
3301                                  "Host" : "Peripheral");
3302                         msleep(20);
3303                         if (++count > 250)
3304                                 break;
3305                 }
3306                 if (count > 250)
3307                         dev_err(hsotg->dev,
3308                                 "Connection id status change timed out\n");
3309
3310                 spin_lock_irqsave(&hsotg->lock, flags);
3311                 dwc2_hsotg_disconnect(hsotg);
3312                 spin_unlock_irqrestore(&hsotg->lock, flags);
3313
3314                 hsotg->op_state = OTG_STATE_A_HOST;
3315                 /* Initialize the Core for Host mode */
3316                 dwc2_core_init(hsotg, false);
3317                 dwc2_enable_global_interrupts(hsotg);
3318                 dwc2_hcd_start(hsotg);
3319         }
3320 }
3321
3322 static void dwc2_wakeup_detected(struct timer_list *t)
3323 {
3324         struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer);
3325         u32 hprt0;
3326
3327         dev_dbg(hsotg->dev, "%s()\n", __func__);
3328
3329         /*
3330          * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
3331          * so that OPT tests pass with all PHYs.)
3332          */
3333         hprt0 = dwc2_read_hprt0(hsotg);
3334         dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3335         hprt0 &= ~HPRT0_RES;
3336         dwc2_writel(hprt0, hsotg->regs + HPRT0);
3337         dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3338                 dwc2_readl(hsotg->regs + HPRT0));
3339
3340         dwc2_hcd_rem_wakeup(hsotg);
3341         hsotg->bus_suspended = false;
3342
3343         /* Change to L0 state */
3344         hsotg->lx_state = DWC2_L0;
3345 }
3346
3347 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3348 {
3349         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3350
3351         return hcd->self.b_hnp_enable;
3352 }
3353
3354 /* Must NOT be called with interrupt disabled or spinlock held */
3355 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3356 {
3357         unsigned long flags;
3358         u32 hprt0;
3359         u32 pcgctl;
3360         u32 gotgctl;
3361
3362         dev_dbg(hsotg->dev, "%s()\n", __func__);
3363
3364         spin_lock_irqsave(&hsotg->lock, flags);
3365
3366         if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3367                 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3368                 gotgctl |= GOTGCTL_HSTSETHNPEN;
3369                 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
3370                 hsotg->op_state = OTG_STATE_A_SUSPEND;
3371         }
3372
3373         hprt0 = dwc2_read_hprt0(hsotg);
3374         hprt0 |= HPRT0_SUSP;
3375         dwc2_writel(hprt0, hsotg->regs + HPRT0);
3376
3377         hsotg->bus_suspended = true;
3378
3379         /*
3380          * If hibernation is supported, Phy clock will be suspended
3381          * after registers are backuped.
3382          */
3383         if (!hsotg->params.hibernation) {
3384                 /* Suspend the Phy Clock */
3385                 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3386                 pcgctl |= PCGCTL_STOPPCLK;
3387                 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3388                 udelay(10);
3389         }
3390
3391         /* For HNP the bus must be suspended for at least 200ms */
3392         if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3393                 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3394                 pcgctl &= ~PCGCTL_STOPPCLK;
3395                 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3396
3397                 spin_unlock_irqrestore(&hsotg->lock, flags);
3398
3399                 msleep(200);
3400         } else {
3401                 spin_unlock_irqrestore(&hsotg->lock, flags);
3402         }
3403 }
3404
3405 /* Must NOT be called with interrupt disabled or spinlock held */
3406 static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3407 {
3408         unsigned long flags;
3409         u32 hprt0;
3410         u32 pcgctl;
3411
3412         spin_lock_irqsave(&hsotg->lock, flags);
3413
3414         /*
3415          * If hibernation is supported, Phy clock is already resumed
3416          * after registers restore.
3417          */
3418         if (!hsotg->params.hibernation) {
3419                 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3420                 pcgctl &= ~PCGCTL_STOPPCLK;
3421                 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3422                 spin_unlock_irqrestore(&hsotg->lock, flags);
3423                 msleep(20);
3424                 spin_lock_irqsave(&hsotg->lock, flags);
3425         }
3426
3427         hprt0 = dwc2_read_hprt0(hsotg);
3428         hprt0 |= HPRT0_RES;
3429         hprt0 &= ~HPRT0_SUSP;
3430         dwc2_writel(hprt0, hsotg->regs + HPRT0);
3431         spin_unlock_irqrestore(&hsotg->lock, flags);
3432
3433         msleep(USB_RESUME_TIMEOUT);
3434
3435         spin_lock_irqsave(&hsotg->lock, flags);
3436         hprt0 = dwc2_read_hprt0(hsotg);
3437         hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
3438         dwc2_writel(hprt0, hsotg->regs + HPRT0);
3439         hsotg->bus_suspended = false;
3440         spin_unlock_irqrestore(&hsotg->lock, flags);
3441 }
3442
3443 /* Handles hub class-specific requests */
3444 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3445                                 u16 wvalue, u16 windex, char *buf, u16 wlength)
3446 {
3447         struct usb_hub_descriptor *hub_desc;
3448         int retval = 0;
3449         u32 hprt0;
3450         u32 port_status;
3451         u32 speed;
3452         u32 pcgctl;
3453
3454         switch (typereq) {
3455         case ClearHubFeature:
3456                 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3457
3458                 switch (wvalue) {
3459                 case C_HUB_LOCAL_POWER:
3460                 case C_HUB_OVER_CURRENT:
3461                         /* Nothing required here */
3462                         break;
3463
3464                 default:
3465                         retval = -EINVAL;
3466                         dev_err(hsotg->dev,
3467                                 "ClearHubFeature request %1xh unknown\n",
3468                                 wvalue);
3469                 }
3470                 break;
3471
3472         case ClearPortFeature:
3473                 if (wvalue != USB_PORT_FEAT_L1)
3474                         if (!windex || windex > 1)
3475                                 goto error;
3476                 switch (wvalue) {
3477                 case USB_PORT_FEAT_ENABLE:
3478                         dev_dbg(hsotg->dev,
3479                                 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3480                         hprt0 = dwc2_read_hprt0(hsotg);
3481                         hprt0 |= HPRT0_ENA;
3482                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
3483                         break;
3484
3485                 case USB_PORT_FEAT_SUSPEND:
3486                         dev_dbg(hsotg->dev,
3487                                 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
3488
3489                         if (hsotg->bus_suspended)
3490                                 dwc2_port_resume(hsotg);
3491                         break;
3492
3493                 case USB_PORT_FEAT_POWER:
3494                         dev_dbg(hsotg->dev,
3495                                 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3496                         hprt0 = dwc2_read_hprt0(hsotg);
3497                         hprt0 &= ~HPRT0_PWR;
3498                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
3499                         break;
3500
3501                 case USB_PORT_FEAT_INDICATOR:
3502                         dev_dbg(hsotg->dev,
3503                                 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
3504                         /* Port indicator not supported */
3505                         break;
3506
3507                 case USB_PORT_FEAT_C_CONNECTION:
3508                         /*
3509                          * Clears driver's internal Connect Status Change flag
3510                          */
3511                         dev_dbg(hsotg->dev,
3512                                 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
3513                         hsotg->flags.b.port_connect_status_change = 0;
3514                         break;
3515
3516                 case USB_PORT_FEAT_C_RESET:
3517                         /* Clears driver's internal Port Reset Change flag */
3518                         dev_dbg(hsotg->dev,
3519                                 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
3520                         hsotg->flags.b.port_reset_change = 0;
3521                         break;
3522
3523                 case USB_PORT_FEAT_C_ENABLE:
3524                         /*
3525                          * Clears the driver's internal Port Enable/Disable
3526                          * Change flag
3527                          */
3528                         dev_dbg(hsotg->dev,
3529                                 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
3530                         hsotg->flags.b.port_enable_change = 0;
3531                         break;
3532
3533                 case USB_PORT_FEAT_C_SUSPEND:
3534                         /*
3535                          * Clears the driver's internal Port Suspend Change
3536                          * flag, which is set when resume signaling on the host
3537                          * port is complete
3538                          */
3539                         dev_dbg(hsotg->dev,
3540                                 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
3541                         hsotg->flags.b.port_suspend_change = 0;
3542                         break;
3543
3544                 case USB_PORT_FEAT_C_PORT_L1:
3545                         dev_dbg(hsotg->dev,
3546                                 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
3547                         hsotg->flags.b.port_l1_change = 0;
3548                         break;
3549
3550                 case USB_PORT_FEAT_C_OVER_CURRENT:
3551                         dev_dbg(hsotg->dev,
3552                                 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
3553                         hsotg->flags.b.port_over_current_change = 0;
3554                         break;
3555
3556                 default:
3557                         retval = -EINVAL;
3558                         dev_err(hsotg->dev,
3559                                 "ClearPortFeature request %1xh unknown or unsupported\n",
3560                                 wvalue);
3561                 }
3562                 break;
3563
3564         case GetHubDescriptor:
3565                 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3566                 hub_desc = (struct usb_hub_descriptor *)buf;
3567                 hub_desc->bDescLength = 9;
3568                 hub_desc->bDescriptorType = USB_DT_HUB;
3569                 hub_desc->bNbrPorts = 1;
3570                 hub_desc->wHubCharacteristics =
3571                         cpu_to_le16(HUB_CHAR_COMMON_LPSM |
3572                                     HUB_CHAR_INDV_PORT_OCPM);
3573                 hub_desc->bPwrOn2PwrGood = 1;
3574                 hub_desc->bHubContrCurrent = 0;
3575                 hub_desc->u.hs.DeviceRemovable[0] = 0;
3576                 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
3577                 break;
3578
3579         case GetHubStatus:
3580                 dev_dbg(hsotg->dev, "GetHubStatus\n");
3581                 memset(buf, 0, 4);
3582                 break;
3583
3584         case GetPortStatus:
3585                 dev_vdbg(hsotg->dev,
3586                          "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
3587                          hsotg->flags.d32);
3588                 if (!windex || windex > 1)
3589                         goto error;
3590
3591                 port_status = 0;
3592                 if (hsotg->flags.b.port_connect_status_change)
3593                         port_status |= USB_PORT_STAT_C_CONNECTION << 16;
3594                 if (hsotg->flags.b.port_enable_change)
3595                         port_status |= USB_PORT_STAT_C_ENABLE << 16;
3596                 if (hsotg->flags.b.port_suspend_change)
3597                         port_status |= USB_PORT_STAT_C_SUSPEND << 16;
3598                 if (hsotg->flags.b.port_l1_change)
3599                         port_status |= USB_PORT_STAT_C_L1 << 16;
3600                 if (hsotg->flags.b.port_reset_change)
3601                         port_status |= USB_PORT_STAT_C_RESET << 16;
3602                 if (hsotg->flags.b.port_over_current_change) {
3603                         dev_warn(hsotg->dev, "Overcurrent change detected\n");
3604                         port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3605                 }
3606
3607                 if (!hsotg->flags.b.port_connect_status) {
3608                         /*
3609                          * The port is disconnected, which means the core is
3610                          * either in device mode or it soon will be. Just
3611                          * return 0's for the remainder of the port status
3612                          * since the port register can't be read if the core
3613                          * is in device mode.
3614                          */
3615                         *(__le32 *)buf = cpu_to_le32(port_status);
3616                         break;
3617                 }
3618
3619                 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
3620                 dev_vdbg(hsotg->dev, "  HPRT0: 0x%08x\n", hprt0);
3621
3622                 if (hprt0 & HPRT0_CONNSTS)
3623                         port_status |= USB_PORT_STAT_CONNECTION;
3624                 if (hprt0 & HPRT0_ENA)
3625                         port_status |= USB_PORT_STAT_ENABLE;
3626                 if (hprt0 & HPRT0_SUSP)
3627                         port_status |= USB_PORT_STAT_SUSPEND;
3628                 if (hprt0 & HPRT0_OVRCURRACT)
3629                         port_status |= USB_PORT_STAT_OVERCURRENT;
3630                 if (hprt0 & HPRT0_RST)
3631                         port_status |= USB_PORT_STAT_RESET;
3632                 if (hprt0 & HPRT0_PWR)
3633                         port_status |= USB_PORT_STAT_POWER;
3634
3635                 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
3636                 if (speed == HPRT0_SPD_HIGH_SPEED)
3637                         port_status |= USB_PORT_STAT_HIGH_SPEED;
3638                 else if (speed == HPRT0_SPD_LOW_SPEED)
3639                         port_status |= USB_PORT_STAT_LOW_SPEED;
3640
3641                 if (hprt0 & HPRT0_TSTCTL_MASK)
3642                         port_status |= USB_PORT_STAT_TEST;
3643                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
3644
3645                 if (hsotg->params.dma_desc_fs_enable) {
3646                         /*
3647                          * Enable descriptor DMA only if a full speed
3648                          * device is connected.
3649                          */
3650                         if (hsotg->new_connection &&
3651                             ((port_status &
3652                               (USB_PORT_STAT_CONNECTION |
3653                                USB_PORT_STAT_HIGH_SPEED |
3654                                USB_PORT_STAT_LOW_SPEED)) ==
3655                                USB_PORT_STAT_CONNECTION)) {
3656                                 u32 hcfg;
3657
3658                                 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3659                                 hsotg->params.dma_desc_enable = true;
3660                                 hcfg = dwc2_readl(hsotg->regs + HCFG);
3661                                 hcfg |= HCFG_DESCDMA;
3662                                 dwc2_writel(hcfg, hsotg->regs + HCFG);
3663                                 hsotg->new_connection = false;
3664                         }
3665                 }
3666
3667                 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
3668                 *(__le32 *)buf = cpu_to_le32(port_status);
3669                 break;
3670
3671         case SetHubFeature:
3672                 dev_dbg(hsotg->dev, "SetHubFeature\n");
3673                 /* No HUB features supported */
3674                 break;
3675
3676         case SetPortFeature:
3677                 dev_dbg(hsotg->dev, "SetPortFeature\n");
3678                 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
3679                         goto error;
3680
3681                 if (!hsotg->flags.b.port_connect_status) {
3682                         /*
3683                          * The port is disconnected, which means the core is
3684                          * either in device mode or it soon will be. Just
3685                          * return without doing anything since the port
3686                          * register can't be written if the core is in device
3687                          * mode.
3688                          */
3689                         break;
3690                 }
3691
3692                 switch (wvalue) {
3693                 case USB_PORT_FEAT_SUSPEND:
3694                         dev_dbg(hsotg->dev,
3695                                 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
3696                         if (windex != hsotg->otg_port)
3697                                 goto error;
3698                         dwc2_port_suspend(hsotg, windex);
3699                         break;
3700
3701                 case USB_PORT_FEAT_POWER:
3702                         dev_dbg(hsotg->dev,
3703                                 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3704                         hprt0 = dwc2_read_hprt0(hsotg);
3705                         hprt0 |= HPRT0_PWR;
3706                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
3707                         break;
3708
3709                 case USB_PORT_FEAT_RESET:
3710                         hprt0 = dwc2_read_hprt0(hsotg);
3711                         dev_dbg(hsotg->dev,
3712                                 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3713                         pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3714                         pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
3715                         dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3716                         /* ??? Original driver does this */
3717                         dwc2_writel(0, hsotg->regs + PCGCTL);
3718
3719                         hprt0 = dwc2_read_hprt0(hsotg);
3720                         /* Clear suspend bit if resetting from suspend state */
3721                         hprt0 &= ~HPRT0_SUSP;
3722
3723                         /*
3724                          * When B-Host the Port reset bit is set in the Start
3725                          * HCD Callback function, so that the reset is started
3726                          * within 1ms of the HNP success interrupt
3727                          */
3728                         if (!dwc2_hcd_is_b_host(hsotg)) {
3729                                 hprt0 |= HPRT0_PWR | HPRT0_RST;
3730                                 dev_dbg(hsotg->dev,
3731                                         "In host mode, hprt0=%08x\n", hprt0);
3732                                 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3733                         }
3734
3735                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3736                         msleep(50);
3737                         hprt0 &= ~HPRT0_RST;
3738                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
3739                         hsotg->lx_state = DWC2_L0; /* Now back to On state */
3740                         break;
3741
3742                 case USB_PORT_FEAT_INDICATOR:
3743                         dev_dbg(hsotg->dev,
3744                                 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
3745                         /* Not supported */
3746                         break;
3747
3748                 case USB_PORT_FEAT_TEST:
3749                         hprt0 = dwc2_read_hprt0(hsotg);
3750                         dev_dbg(hsotg->dev,
3751                                 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3752                         hprt0 &= ~HPRT0_TSTCTL_MASK;
3753                         hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
3754                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
3755                         break;
3756
3757                 default:
3758                         retval = -EINVAL;
3759                         dev_err(hsotg->dev,
3760                                 "SetPortFeature %1xh unknown or unsupported\n",
3761                                 wvalue);
3762                         break;
3763                 }
3764                 break;
3765
3766         default:
3767 error:
3768                 retval = -EINVAL;
3769                 dev_dbg(hsotg->dev,
3770                         "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
3771                         typereq, windex, wvalue);
3772                 break;
3773         }
3774
3775         return retval;
3776 }
3777
3778 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3779 {
3780         int retval;
3781
3782         if (port != 1)
3783                 return -EINVAL;
3784
3785         retval = (hsotg->flags.b.port_connect_status_change ||
3786                   hsotg->flags.b.port_reset_change ||
3787                   hsotg->flags.b.port_enable_change ||
3788                   hsotg->flags.b.port_suspend_change ||
3789                   hsotg->flags.b.port_over_current_change);
3790
3791         if (retval) {
3792                 dev_dbg(hsotg->dev,
3793                         "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
3794                 dev_dbg(hsotg->dev, "  port_connect_status_change: %d\n",
3795                         hsotg->flags.b.port_connect_status_change);
3796                 dev_dbg(hsotg->dev, "  port_reset_change: %d\n",
3797                         hsotg->flags.b.port_reset_change);
3798                 dev_dbg(hsotg->dev, "  port_enable_change: %d\n",
3799                         hsotg->flags.b.port_enable_change);
3800                 dev_dbg(hsotg->dev, "  port_suspend_change: %d\n",
3801                         hsotg->flags.b.port_suspend_change);
3802                 dev_dbg(hsotg->dev, "  port_over_current_change: %d\n",
3803                         hsotg->flags.b.port_over_current_change);
3804         }
3805
3806         return retval;
3807 }
3808
3809 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3810 {
3811         u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3812
3813 #ifdef DWC2_DEBUG_SOF
3814         dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
3815                  (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
3816 #endif
3817         return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3818 }
3819
3820 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3821 {
3822         u32 hprt = dwc2_readl(hsotg->regs + HPRT0);
3823         u32 hfir = dwc2_readl(hsotg->regs + HFIR);
3824         u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3825         unsigned int us_per_frame;
3826         unsigned int frame_number;
3827         unsigned int remaining;
3828         unsigned int interval;
3829         unsigned int phy_clks;
3830
3831         /* High speed has 125 us per (micro) frame; others are 1 ms per */
3832         us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125;
3833
3834         /* Extract fields */
3835         frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3836         remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT;
3837         interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT;
3838
3839         /*
3840          * Number of phy clocks since the last tick of the frame number after
3841          * "us" has passed.
3842          */
3843         phy_clks = (interval - remaining) +
3844                    DIV_ROUND_UP(interval * us, us_per_frame);
3845
3846         return dwc2_frame_num_inc(frame_number, phy_clks / interval);
3847 }
3848
3849 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3850 {
3851         return hsotg->op_state == OTG_STATE_B_HOST;
3852 }
3853
3854 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3855                                                int iso_desc_count,
3856                                                gfp_t mem_flags)
3857 {
3858         struct dwc2_hcd_urb *urb;
3859         u32 size = sizeof(*urb) + iso_desc_count *
3860                    sizeof(struct dwc2_hcd_iso_packet_desc);
3861
3862         urb = kzalloc(size, mem_flags);
3863         if (urb)
3864                 urb->packet_count = iso_desc_count;
3865         return urb;
3866 }
3867
3868 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3869                                       struct dwc2_hcd_urb *urb, u8 dev_addr,
3870                                       u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
3871 {
3872         if (dbg_perio() ||
3873             ep_type == USB_ENDPOINT_XFER_BULK ||
3874             ep_type == USB_ENDPOINT_XFER_CONTROL)
3875                 dev_vdbg(hsotg->dev,
3876                          "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
3877                          dev_addr, ep_num, ep_dir, ep_type, mps);
3878         urb->pipe_info.dev_addr = dev_addr;
3879         urb->pipe_info.ep_num = ep_num;
3880         urb->pipe_info.pipe_type = ep_type;
3881         urb->pipe_info.pipe_dir = ep_dir;
3882         urb->pipe_info.mps = mps;
3883 }
3884
3885 /*
3886  * NOTE: This function will be removed once the peripheral controller code
3887  * is integrated and the driver is stable
3888  */
3889 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
3890 {
3891 #ifdef DEBUG
3892         struct dwc2_host_chan *chan;
3893         struct dwc2_hcd_urb *urb;
3894         struct dwc2_qtd *qtd;
3895         int num_channels;
3896         u32 np_tx_status;
3897         u32 p_tx_status;
3898         int i;
3899
3900         num_channels = hsotg->params.host_channels;
3901         dev_dbg(hsotg->dev, "\n");
3902         dev_dbg(hsotg->dev,
3903                 "************************************************************\n");
3904         dev_dbg(hsotg->dev, "HCD State:\n");
3905         dev_dbg(hsotg->dev, "  Num channels: %d\n", num_channels);
3906
3907         for (i = 0; i < num_channels; i++) {
3908                 chan = hsotg->hc_ptr_array[i];
3909                 dev_dbg(hsotg->dev, "  Channel %d:\n", i);
3910                 dev_dbg(hsotg->dev,
3911                         "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3912                         chan->dev_addr, chan->ep_num, chan->ep_is_in);
3913                 dev_dbg(hsotg->dev, "    speed: %d\n", chan->speed);
3914                 dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
3915                 dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
3916                 dev_dbg(hsotg->dev, "    data_pid_start: %d\n",
3917                         chan->data_pid_start);
3918                 dev_dbg(hsotg->dev, "    multi_count: %d\n", chan->multi_count);
3919                 dev_dbg(hsotg->dev, "    xfer_started: %d\n",
3920                         chan->xfer_started);
3921                 dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
3922                 dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
3923                         (unsigned long)chan->xfer_dma);
3924                 dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
3925                 dev_dbg(hsotg->dev, "    xfer_count: %d\n", chan->xfer_count);
3926                 dev_dbg(hsotg->dev, "    halt_on_queue: %d\n",
3927                         chan->halt_on_queue);
3928                 dev_dbg(hsotg->dev, "    halt_pending: %d\n",
3929                         chan->halt_pending);
3930                 dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
3931                 dev_dbg(hsotg->dev, "    do_split: %d\n", chan->do_split);
3932                 dev_dbg(hsotg->dev, "    complete_split: %d\n",
3933                         chan->complete_split);
3934                 dev_dbg(hsotg->dev, "    hub_addr: %d\n", chan->hub_addr);
3935                 dev_dbg(hsotg->dev, "    hub_port: %d\n", chan->hub_port);
3936                 dev_dbg(hsotg->dev, "    xact_pos: %d\n", chan->xact_pos);
3937                 dev_dbg(hsotg->dev, "    requests: %d\n", chan->requests);
3938                 dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
3939
3940                 if (chan->xfer_started) {
3941                         u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
3942
3943                         hfnum = dwc2_readl(hsotg->regs + HFNUM);
3944                         hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
3945                         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
3946                         hcint = dwc2_readl(hsotg->regs + HCINT(i));
3947                         hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
3948                         dev_dbg(hsotg->dev, "    hfnum: 0x%08x\n", hfnum);
3949                         dev_dbg(hsotg->dev, "    hcchar: 0x%08x\n", hcchar);
3950                         dev_dbg(hsotg->dev, "    hctsiz: 0x%08x\n", hctsiz);
3951                         dev_dbg(hsotg->dev, "    hcint: 0x%08x\n", hcint);
3952                         dev_dbg(hsotg->dev, "    hcintmsk: 0x%08x\n", hcintmsk);
3953                 }
3954
3955                 if (!(chan->xfer_started && chan->qh))
3956                         continue;
3957
3958                 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
3959                         if (!qtd->in_process)
3960                                 break;
3961                         urb = qtd->urb;
3962                         dev_dbg(hsotg->dev, "    URB Info:\n");
3963                         dev_dbg(hsotg->dev, "      qtd: %p, urb: %p\n",
3964                                 qtd, urb);
3965                         if (urb) {
3966                                 dev_dbg(hsotg->dev,
3967                                         "      Dev: %d, EP: %d %s\n",
3968                                         dwc2_hcd_get_dev_addr(&urb->pipe_info),
3969                                         dwc2_hcd_get_ep_num(&urb->pipe_info),
3970                                         dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
3971                                         "IN" : "OUT");
3972                                 dev_dbg(hsotg->dev,
3973                                         "      Max packet size: %d\n",
3974                                         dwc2_hcd_get_mps(&urb->pipe_info));
3975                                 dev_dbg(hsotg->dev,
3976                                         "      transfer_buffer: %p\n",
3977                                         urb->buf);
3978                                 dev_dbg(hsotg->dev,
3979                                         "      transfer_dma: %08lx\n",
3980                                         (unsigned long)urb->dma);
3981                                 dev_dbg(hsotg->dev,
3982                                         "      transfer_buffer_length: %d\n",
3983                                         urb->length);
3984                                 dev_dbg(hsotg->dev, "      actual_length: %d\n",
3985                                         urb->actual_length);
3986                         }
3987                 }
3988         }
3989
3990         dev_dbg(hsotg->dev, "  non_periodic_channels: %d\n",
3991                 hsotg->non_periodic_channels);
3992         dev_dbg(hsotg->dev, "  periodic_channels: %d\n",
3993                 hsotg->periodic_channels);
3994         dev_dbg(hsotg->dev, "  periodic_usecs: %d\n", hsotg->periodic_usecs);
3995         np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3996         dev_dbg(hsotg->dev, "  NP Tx Req Queue Space Avail: %d\n",
3997                 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
3998         dev_dbg(hsotg->dev, "  NP Tx FIFO Space Avail: %d\n",
3999                 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4000         p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
4001         dev_dbg(hsotg->dev, "  P Tx Req Queue Space Avail: %d\n",
4002                 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4003         dev_dbg(hsotg->dev, "  P Tx FIFO Space Avail: %d\n",
4004                 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4005         dwc2_hcd_dump_frrem(hsotg);
4006         dwc2_dump_global_registers(hsotg);
4007         dwc2_dump_host_registers(hsotg);
4008         dev_dbg(hsotg->dev,
4009                 "************************************************************\n");
4010         dev_dbg(hsotg->dev, "\n");
4011 #endif
4012 }
4013
4014 /*
4015  * NOTE: This function will be removed once the peripheral controller code
4016  * is integrated and the driver is stable
4017  */
4018 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
4019 {
4020 #ifdef DWC2_DUMP_FRREM
4021         dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
4022         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4023                 hsotg->frrem_samples, hsotg->frrem_accum,
4024                 hsotg->frrem_samples > 0 ?
4025                 hsotg->frrem_accum / hsotg->frrem_samples : 0);
4026         dev_dbg(hsotg->dev, "\n");
4027         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
4028         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4029                 hsotg->hfnum_7_samples,
4030                 hsotg->hfnum_7_frrem_accum,
4031                 hsotg->hfnum_7_samples > 0 ?
4032                 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
4033         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
4034         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4035                 hsotg->hfnum_0_samples,
4036                 hsotg->hfnum_0_frrem_accum,
4037                 hsotg->hfnum_0_samples > 0 ?
4038                 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
4039         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
4040         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4041                 hsotg->hfnum_other_samples,
4042                 hsotg->hfnum_other_frrem_accum,
4043                 hsotg->hfnum_other_samples > 0 ?
4044                 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
4045                 0);
4046         dev_dbg(hsotg->dev, "\n");
4047         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
4048         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4049                 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
4050                 hsotg->hfnum_7_samples_a > 0 ?
4051                 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
4052         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
4053         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4054                 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
4055                 hsotg->hfnum_0_samples_a > 0 ?
4056                 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
4057         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
4058         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4059                 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
4060                 hsotg->hfnum_other_samples_a > 0 ?
4061                 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
4062                 : 0);
4063         dev_dbg(hsotg->dev, "\n");
4064         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
4065         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4066                 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
4067                 hsotg->hfnum_7_samples_b > 0 ?
4068                 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
4069         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
4070         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4071                 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
4072                 (hsotg->hfnum_0_samples_b > 0) ?
4073                 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
4074         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
4075         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4076                 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
4077                 (hsotg->hfnum_other_samples_b > 0) ?
4078                 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
4079                 : 0);
4080 #endif
4081 }
4082
4083 struct wrapper_priv_data {
4084         struct dwc2_hsotg *hsotg;
4085 };
4086
4087 /* Gets the dwc2_hsotg from a usb_hcd */
4088 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
4089 {
4090         struct wrapper_priv_data *p;
4091
4092         p = (struct wrapper_priv_data *)&hcd->hcd_priv;
4093         return p->hsotg;
4094 }
4095
4096 /**
4097  * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
4098  *
4099  * This will get the dwc2_tt structure (and ttport) associated with the given
4100  * context (which is really just a struct urb pointer).
4101  *
4102  * The first time this is called for a given TT we allocate memory for our
4103  * structure.  When everyone is done and has called dwc2_host_put_tt_info()
4104  * then the refcount for the structure will go to 0 and we'll free it.
4105  *
4106  * @hsotg:     The HCD state structure for the DWC OTG controller.
4107  * @qh:        The QH structure.
4108  * @context:   The priv pointer from a struct dwc2_hcd_urb.
4109  * @mem_flags: Flags for allocating memory.
4110  * @ttport:    We'll return this device's port number here.  That's used to
4111  *             reference into the bitmap if we're on a multi_tt hub.
4112  *
4113  * Return: a pointer to a struct dwc2_tt.  Don't forget to call
4114  *         dwc2_host_put_tt_info()!  Returns NULL upon memory alloc failure.
4115  */
4116
4117 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4118                                       gfp_t mem_flags, int *ttport)
4119 {
4120         struct urb *urb = context;
4121         struct dwc2_tt *dwc_tt = NULL;
4122
4123         if (urb->dev->tt) {
4124                 *ttport = urb->dev->ttport;
4125
4126                 dwc_tt = urb->dev->tt->hcpriv;
4127                 if (!dwc_tt) {
4128                         size_t bitmap_size;
4129
4130                         /*
4131                          * For single_tt we need one schedule.  For multi_tt
4132                          * we need one per port.
4133                          */
4134                         bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP *
4135                                       sizeof(dwc_tt->periodic_bitmaps[0]);
4136                         if (urb->dev->tt->multi)
4137                                 bitmap_size *= urb->dev->tt->hub->maxchild;
4138
4139                         dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
4140                                          mem_flags);
4141                         if (!dwc_tt)
4142                                 return NULL;
4143
4144                         dwc_tt->usb_tt = urb->dev->tt;
4145                         dwc_tt->usb_tt->hcpriv = dwc_tt;
4146                 }
4147
4148                 dwc_tt->refcount++;
4149         }
4150
4151         return dwc_tt;
4152 }
4153
4154 /**
4155  * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4156  *
4157  * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
4158  * of the structure are done.
4159  *
4160  * It's OK to call this with NULL.
4161  *
4162  * @hsotg:     The HCD state structure for the DWC OTG controller.
4163  * @dwc_tt:    The pointer returned by dwc2_host_get_tt_info.
4164  */
4165 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4166 {
4167         /* Model kfree and make put of NULL a no-op */
4168         if (!dwc_tt)
4169                 return;
4170
4171         WARN_ON(dwc_tt->refcount < 1);
4172
4173         dwc_tt->refcount--;
4174         if (!dwc_tt->refcount) {
4175                 dwc_tt->usb_tt->hcpriv = NULL;
4176                 kfree(dwc_tt);
4177         }
4178 }
4179
4180 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4181 {
4182         struct urb *urb = context;
4183
4184         return urb->dev->speed;
4185 }
4186
4187 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4188                                         struct urb *urb)
4189 {
4190         struct usb_bus *bus = hcd_to_bus(hcd);
4191
4192         if (urb->interval)
4193                 bus->bandwidth_allocated += bw / urb->interval;
4194         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4195                 bus->bandwidth_isoc_reqs++;
4196         else
4197                 bus->bandwidth_int_reqs++;
4198 }
4199
4200 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4201                                     struct urb *urb)
4202 {
4203         struct usb_bus *bus = hcd_to_bus(hcd);
4204
4205         if (urb->interval)
4206                 bus->bandwidth_allocated -= bw / urb->interval;
4207         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4208                 bus->bandwidth_isoc_reqs--;
4209         else
4210                 bus->bandwidth_int_reqs--;
4211 }
4212
4213 /*
4214  * Sets the final status of an URB and returns it to the upper layer. Any
4215  * required cleanup of the URB is performed.
4216  *
4217  * Must be called with interrupt disabled and spinlock held
4218  */
4219 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4220                         int status)
4221 {
4222         struct urb *urb;
4223         int i;
4224
4225         if (!qtd) {
4226                 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4227                 return;
4228         }
4229
4230         if (!qtd->urb) {
4231                 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4232                 return;
4233         }
4234
4235         urb = qtd->urb->priv;
4236         if (!urb) {
4237                 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
4238                 return;
4239         }
4240
4241         urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
4242
4243         if (dbg_urb(urb))
4244                 dev_vdbg(hsotg->dev,
4245                          "%s: urb %p device %d ep %d-%s status %d actual %d\n",
4246                          __func__, urb, usb_pipedevice(urb->pipe),
4247                          usb_pipeendpoint(urb->pipe),
4248                          usb_pipein(urb->pipe) ? "IN" : "OUT", status,
4249                          urb->actual_length);
4250
4251         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4252                 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
4253                 for (i = 0; i < urb->number_of_packets; ++i) {
4254                         urb->iso_frame_desc[i].actual_length =
4255                                 dwc2_hcd_urb_get_iso_desc_actual_length(
4256                                                 qtd->urb, i);
4257                         urb->iso_frame_desc[i].status =
4258                                 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
4259                 }
4260         }
4261
4262         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
4263                 for (i = 0; i < urb->number_of_packets; i++)
4264                         dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4265                                  i, urb->iso_frame_desc[i].status);
4266         }
4267
4268         urb->status = status;
4269         if (!status) {
4270                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
4271                     urb->actual_length < urb->transfer_buffer_length)
4272                         urb->status = -EREMOTEIO;
4273         }
4274
4275         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4276             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4277                 struct usb_host_endpoint *ep = urb->ep;
4278
4279                 if (ep)
4280                         dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4281                                         dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4282                                         urb);
4283         }
4284
4285         usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
4286         urb->hcpriv = NULL;
4287         kfree(qtd->urb);
4288         qtd->urb = NULL;
4289
4290         usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
4291 }
4292
4293 /*
4294  * Work queue function for starting the HCD when A-Cable is connected
4295  */
4296 static void dwc2_hcd_start_func(struct work_struct *work)
4297 {
4298         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4299                                                 start_work.work);
4300
4301         dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4302         dwc2_host_start(hsotg);
4303 }
4304
4305 /*
4306  * Reset work queue function
4307  */
4308 static void dwc2_hcd_reset_func(struct work_struct *work)
4309 {
4310         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4311                                                 reset_work.work);
4312         unsigned long flags;
4313         u32 hprt0;
4314
4315         dev_dbg(hsotg->dev, "USB RESET function called\n");
4316
4317         spin_lock_irqsave(&hsotg->lock, flags);
4318
4319         hprt0 = dwc2_read_hprt0(hsotg);
4320         hprt0 &= ~HPRT0_RST;
4321         dwc2_writel(hprt0, hsotg->regs + HPRT0);
4322         hsotg->flags.b.port_reset_change = 1;
4323
4324         spin_unlock_irqrestore(&hsotg->lock, flags);
4325 }
4326
4327 /*
4328  * =========================================================================
4329  *  Linux HC Driver Functions
4330  * =========================================================================
4331  */
4332
4333 /*
4334  * Initializes the DWC_otg controller and its root hub and prepares it for host
4335  * mode operation. Activates the root port. Returns 0 on success and a negative
4336  * error code on failure.
4337  */
4338 static int _dwc2_hcd_start(struct usb_hcd *hcd)
4339 {
4340         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4341         struct usb_bus *bus = hcd_to_bus(hcd);
4342         unsigned long flags;
4343
4344         dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4345
4346         spin_lock_irqsave(&hsotg->lock, flags);
4347         hsotg->lx_state = DWC2_L0;
4348         hcd->state = HC_STATE_RUNNING;
4349         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4350
4351         if (dwc2_is_device_mode(hsotg)) {
4352                 spin_unlock_irqrestore(&hsotg->lock, flags);
4353                 return 0;       /* why 0 ?? */
4354         }
4355
4356         dwc2_hcd_reinit(hsotg);
4357
4358         /* Initialize and connect root hub if one is not already attached */
4359         if (bus->root_hub) {
4360                 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4361                 /* Inform the HUB driver to resume */
4362                 usb_hcd_resume_root_hub(hcd);
4363         }
4364
4365         spin_unlock_irqrestore(&hsotg->lock, flags);
4366         return 0;
4367 }
4368
4369 /*
4370  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4371  * stopped.
4372  */
4373 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
4374 {
4375         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4376         unsigned long flags;
4377
4378         /* Turn off all host-specific interrupts */
4379         dwc2_disable_host_interrupts(hsotg);
4380
4381         /* Wait for interrupt processing to finish */
4382         synchronize_irq(hcd->irq);
4383
4384         spin_lock_irqsave(&hsotg->lock, flags);
4385         /* Ensure hcd is disconnected */
4386         dwc2_hcd_disconnect(hsotg, true);
4387         dwc2_hcd_stop(hsotg);
4388         hsotg->lx_state = DWC2_L3;
4389         hcd->state = HC_STATE_HALT;
4390         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4391         spin_unlock_irqrestore(&hsotg->lock, flags);
4392
4393         usleep_range(1000, 3000);
4394 }
4395
4396 static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4397 {
4398         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4399         unsigned long flags;
4400         int ret = 0;
4401         u32 hprt0;
4402
4403         spin_lock_irqsave(&hsotg->lock, flags);
4404
4405         if (dwc2_is_device_mode(hsotg))
4406                 goto unlock;
4407
4408         if (hsotg->lx_state != DWC2_L0)
4409                 goto unlock;
4410
4411         if (!HCD_HW_ACCESSIBLE(hcd))
4412                 goto unlock;
4413
4414         if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
4415                 goto unlock;
4416
4417         if (!hsotg->params.hibernation)
4418                 goto skip_power_saving;
4419
4420         /*
4421          * Drive USB suspend and disable port Power
4422          * if usb bus is not suspended.
4423          */
4424         if (!hsotg->bus_suspended) {
4425                 hprt0 = dwc2_read_hprt0(hsotg);
4426                 hprt0 |= HPRT0_SUSP;
4427                 hprt0 &= ~HPRT0_PWR;
4428                 dwc2_writel(hprt0, hsotg->regs + HPRT0);
4429         }
4430
4431         /* Enter hibernation */
4432         ret = dwc2_enter_hibernation(hsotg);
4433         if (ret) {
4434                 if (ret != -ENOTSUPP)
4435                         dev_err(hsotg->dev,
4436                                 "enter hibernation failed\n");
4437                 goto skip_power_saving;
4438         }
4439
4440         /* Ask phy to be suspended */
4441         if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4442                 spin_unlock_irqrestore(&hsotg->lock, flags);
4443                 usb_phy_set_suspend(hsotg->uphy, true);
4444                 spin_lock_irqsave(&hsotg->lock, flags);
4445         }
4446
4447         /* After entering hibernation, hardware is no more accessible */
4448         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4449
4450 skip_power_saving:
4451         hsotg->lx_state = DWC2_L2;
4452 unlock:
4453         spin_unlock_irqrestore(&hsotg->lock, flags);
4454
4455         return ret;
4456 }
4457
4458 static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4459 {
4460         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4461         unsigned long flags;
4462         int ret = 0;
4463
4464         spin_lock_irqsave(&hsotg->lock, flags);
4465
4466         if (dwc2_is_device_mode(hsotg))
4467                 goto unlock;
4468
4469         if (hsotg->lx_state != DWC2_L2)
4470                 goto unlock;
4471
4472         if (!hsotg->params.hibernation) {
4473                 hsotg->lx_state = DWC2_L0;
4474                 goto unlock;
4475         }
4476
4477         /*
4478          * Set HW accessible bit before powering on the controller
4479          * since an interrupt may rise.
4480          */
4481         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4482
4483         /*
4484          * Enable power if not already done.
4485          * This must not be spinlocked since duration
4486          * of this call is unknown.
4487          */
4488         if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4489                 spin_unlock_irqrestore(&hsotg->lock, flags);
4490                 usb_phy_set_suspend(hsotg->uphy, false);
4491                 spin_lock_irqsave(&hsotg->lock, flags);
4492         }
4493
4494         /* Exit hibernation */
4495         ret = dwc2_exit_hibernation(hsotg, true);
4496         if (ret && (ret != -ENOTSUPP))
4497                 dev_err(hsotg->dev, "exit hibernation failed\n");
4498
4499         hsotg->lx_state = DWC2_L0;
4500
4501         spin_unlock_irqrestore(&hsotg->lock, flags);
4502
4503         if (hsotg->bus_suspended) {
4504                 spin_lock_irqsave(&hsotg->lock, flags);
4505                 hsotg->flags.b.port_suspend_change = 1;
4506                 spin_unlock_irqrestore(&hsotg->lock, flags);
4507                 dwc2_port_resume(hsotg);
4508         } else {
4509                 /* Wait for controller to correctly update D+/D- level */
4510                 usleep_range(3000, 5000);
4511
4512                 /*
4513                  * Clear Port Enable and Port Status changes.
4514                  * Enable Port Power.
4515                  */
4516                 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET |
4517                                 HPRT0_ENACHG, hsotg->regs + HPRT0);
4518                 /* Wait for controller to detect Port Connect */
4519                 usleep_range(5000, 7000);
4520         }
4521
4522         return ret;
4523 unlock:
4524         spin_unlock_irqrestore(&hsotg->lock, flags);
4525
4526         return ret;
4527 }
4528
4529 /* Returns the current frame number */
4530 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
4531 {
4532         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4533
4534         return dwc2_hcd_get_frame_number(hsotg);
4535 }
4536
4537 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
4538                                char *fn_name)
4539 {
4540 #ifdef VERBOSE_DEBUG
4541         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4542         char *pipetype = NULL;
4543         char *speed = NULL;
4544
4545         dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4546         dev_vdbg(hsotg->dev, "  Device address: %d\n",
4547                  usb_pipedevice(urb->pipe));
4548         dev_vdbg(hsotg->dev, "  Endpoint: %d, %s\n",
4549                  usb_pipeendpoint(urb->pipe),
4550                  usb_pipein(urb->pipe) ? "IN" : "OUT");
4551
4552         switch (usb_pipetype(urb->pipe)) {
4553         case PIPE_CONTROL:
4554                 pipetype = "CONTROL";
4555                 break;
4556         case PIPE_BULK:
4557                 pipetype = "BULK";
4558                 break;
4559         case PIPE_INTERRUPT:
4560                 pipetype = "INTERRUPT";
4561                 break;
4562         case PIPE_ISOCHRONOUS:
4563                 pipetype = "ISOCHRONOUS";
4564                 break;
4565         }
4566
4567         dev_vdbg(hsotg->dev, "  Endpoint type: %s %s (%s)\n", pipetype,
4568                  usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
4569                  "IN" : "OUT");
4570
4571         switch (urb->dev->speed) {
4572         case USB_SPEED_HIGH:
4573                 speed = "HIGH";
4574                 break;
4575         case USB_SPEED_FULL:
4576                 speed = "FULL";
4577                 break;
4578         case USB_SPEED_LOW:
4579                 speed = "LOW";
4580                 break;
4581         default:
4582                 speed = "UNKNOWN";
4583                 break;
4584         }
4585
4586         dev_vdbg(hsotg->dev, "  Speed: %s\n", speed);
4587         dev_vdbg(hsotg->dev, "  Max packet size: %d\n",
4588                  usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
4589         dev_vdbg(hsotg->dev, "  Data buffer length: %d\n",
4590                  urb->transfer_buffer_length);
4591         dev_vdbg(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
4592                  urb->transfer_buffer, (unsigned long)urb->transfer_dma);
4593         dev_vdbg(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
4594                  urb->setup_packet, (unsigned long)urb->setup_dma);
4595         dev_vdbg(hsotg->dev, "  Interval: %d\n", urb->interval);
4596
4597         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4598                 int i;
4599
4600                 for (i = 0; i < urb->number_of_packets; i++) {
4601                         dev_vdbg(hsotg->dev, "  ISO Desc %d:\n", i);
4602                         dev_vdbg(hsotg->dev, "    offset: %d, length %d\n",
4603                                  urb->iso_frame_desc[i].offset,
4604                                  urb->iso_frame_desc[i].length);
4605                 }
4606         }
4607 #endif
4608 }
4609
4610 /*
4611  * Starts processing a USB transfer request specified by a USB Request Block
4612  * (URB). mem_flags indicates the type of memory allocation to use while
4613  * processing this URB.
4614  */
4615 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4616                                  gfp_t mem_flags)
4617 {
4618         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4619         struct usb_host_endpoint *ep = urb->ep;
4620         struct dwc2_hcd_urb *dwc2_urb;
4621         int i;
4622         int retval;
4623         int alloc_bandwidth = 0;
4624         u8 ep_type = 0;
4625         u32 tflags = 0;
4626         void *buf;
4627         unsigned long flags;
4628         struct dwc2_qh *qh;
4629         bool qh_allocated = false;
4630         struct dwc2_qtd *qtd;
4631
4632         if (dbg_urb(urb)) {
4633                 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4634                 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
4635         }
4636
4637         if (!ep)
4638                 return -EINVAL;
4639
4640         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4641             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4642                 spin_lock_irqsave(&hsotg->lock, flags);
4643                 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4644                         alloc_bandwidth = 1;
4645                 spin_unlock_irqrestore(&hsotg->lock, flags);
4646         }
4647
4648         switch (usb_pipetype(urb->pipe)) {
4649         case PIPE_CONTROL:
4650                 ep_type = USB_ENDPOINT_XFER_CONTROL;
4651                 break;
4652         case PIPE_ISOCHRONOUS:
4653                 ep_type = USB_ENDPOINT_XFER_ISOC;
4654                 break;
4655         case PIPE_BULK:
4656                 ep_type = USB_ENDPOINT_XFER_BULK;
4657                 break;
4658         case PIPE_INTERRUPT:
4659                 ep_type = USB_ENDPOINT_XFER_INT;
4660                 break;
4661         }
4662
4663         dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4664                                       mem_flags);
4665         if (!dwc2_urb)
4666                 return -ENOMEM;
4667
4668         dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4669                                   usb_pipeendpoint(urb->pipe), ep_type,
4670                                   usb_pipein(urb->pipe),
4671                                   usb_maxpacket(urb->dev, urb->pipe,
4672                                                 !(usb_pipein(urb->pipe))));
4673
4674         buf = urb->transfer_buffer;
4675
4676         if (hcd->self.uses_dma) {
4677                 if (!buf && (urb->transfer_dma & 3)) {
4678                         dev_err(hsotg->dev,
4679                                 "%s: unaligned transfer with no transfer_buffer",
4680                                 __func__);
4681                         retval = -EINVAL;
4682                         goto fail0;
4683                 }
4684         }
4685
4686         if (!(urb->transfer_flags & URB_NO_INTERRUPT))
4687                 tflags |= URB_GIVEBACK_ASAP;
4688         if (urb->transfer_flags & URB_ZERO_PACKET)
4689                 tflags |= URB_SEND_ZERO_PACKET;
4690
4691         dwc2_urb->priv = urb;
4692         dwc2_urb->buf = buf;
4693         dwc2_urb->dma = urb->transfer_dma;
4694         dwc2_urb->length = urb->transfer_buffer_length;
4695         dwc2_urb->setup_packet = urb->setup_packet;
4696         dwc2_urb->setup_dma = urb->setup_dma;
4697         dwc2_urb->flags = tflags;
4698         dwc2_urb->interval = urb->interval;
4699         dwc2_urb->status = -EINPROGRESS;
4700
4701         for (i = 0; i < urb->number_of_packets; ++i)
4702                 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
4703                                                  urb->iso_frame_desc[i].offset,
4704                                                  urb->iso_frame_desc[i].length);
4705
4706         urb->hcpriv = dwc2_urb;
4707         qh = (struct dwc2_qh *)ep->hcpriv;
4708         /* Create QH for the endpoint if it doesn't exist */
4709         if (!qh) {
4710                 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4711                 if (!qh) {
4712                         retval = -ENOMEM;
4713                         goto fail0;
4714                 }
4715                 ep->hcpriv = qh;
4716                 qh_allocated = true;
4717         }
4718
4719         qtd = kzalloc(sizeof(*qtd), mem_flags);
4720         if (!qtd) {
4721                 retval = -ENOMEM;
4722                 goto fail1;
4723         }
4724
4725         spin_lock_irqsave(&hsotg->lock, flags);
4726         retval = usb_hcd_link_urb_to_ep(hcd, urb);
4727         if (retval)
4728                 goto fail2;
4729
4730         retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4731         if (retval)
4732                 goto fail3;
4733
4734         if (alloc_bandwidth) {
4735                 dwc2_allocate_bus_bandwidth(hcd,
4736                                 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4737                                 urb);
4738         }
4739
4740         spin_unlock_irqrestore(&hsotg->lock, flags);
4741
4742         return 0;
4743
4744 fail3:
4745         dwc2_urb->priv = NULL;
4746         usb_hcd_unlink_urb_from_ep(hcd, urb);
4747         if (qh_allocated && qh->channel && qh->channel->qh == qh)
4748                 qh->channel->qh = NULL;
4749 fail2:
4750         spin_unlock_irqrestore(&hsotg->lock, flags);
4751         urb->hcpriv = NULL;
4752         kfree(qtd);
4753         qtd = NULL;
4754 fail1:
4755         if (qh_allocated) {
4756                 struct dwc2_qtd *qtd2, *qtd2_tmp;
4757
4758                 ep->hcpriv = NULL;
4759                 dwc2_hcd_qh_unlink(hsotg, qh);
4760                 /* Free each QTD in the QH's QTD list */
4761                 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
4762                                          qtd_list_entry)
4763                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4764                 dwc2_hcd_qh_free(hsotg, qh);
4765         }
4766 fail0:
4767         kfree(dwc2_urb);
4768
4769         return retval;
4770 }
4771
4772 /*
4773  * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
4774  */
4775 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
4776                                  int status)
4777 {
4778         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4779         int rc;
4780         unsigned long flags;
4781
4782         dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4783         dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
4784
4785         spin_lock_irqsave(&hsotg->lock, flags);
4786
4787         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
4788         if (rc)
4789                 goto out;
4790
4791         if (!urb->hcpriv) {
4792                 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4793                 goto out;
4794         }
4795
4796         rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4797
4798         usb_hcd_unlink_urb_from_ep(hcd, urb);
4799
4800         kfree(urb->hcpriv);
4801         urb->hcpriv = NULL;
4802
4803         /* Higher layer software sets URB status */
4804         spin_unlock(&hsotg->lock);
4805         usb_hcd_giveback_urb(hcd, urb, status);
4806         spin_lock(&hsotg->lock);
4807
4808         dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4809         dev_dbg(hsotg->dev, "  urb->status = %d\n", urb->status);
4810 out:
4811         spin_unlock_irqrestore(&hsotg->lock, flags);
4812
4813         return rc;
4814 }
4815
4816 /*
4817  * Frees resources in the DWC_otg controller related to a given endpoint. Also
4818  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
4819  * must already be dequeued.
4820  */
4821 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
4822                                        struct usb_host_endpoint *ep)
4823 {
4824         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4825
4826         dev_dbg(hsotg->dev,
4827                 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
4828                 ep->desc.bEndpointAddress, ep->hcpriv);
4829         dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4830 }
4831
4832 /*
4833  * Resets endpoint specific parameter values, in current version used to reset
4834  * the data toggle (as a WA). This function can be called from usb_clear_halt
4835  * routine.
4836  */
4837 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
4838                                      struct usb_host_endpoint *ep)
4839 {
4840         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4841         unsigned long flags;
4842
4843         dev_dbg(hsotg->dev,
4844                 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
4845                 ep->desc.bEndpointAddress);
4846
4847         spin_lock_irqsave(&hsotg->lock, flags);
4848         dwc2_hcd_endpoint_reset(hsotg, ep);
4849         spin_unlock_irqrestore(&hsotg->lock, flags);
4850 }
4851
4852 /*
4853  * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4854  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
4855  * interrupt.
4856  *
4857  * This function is called by the USB core when an interrupt occurs
4858  */
4859 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
4860 {
4861         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4862
4863         return dwc2_handle_hcd_intr(hsotg);
4864 }
4865
4866 /*
4867  * Creates Status Change bitmap for the root hub and root port. The bitmap is
4868  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
4869  * is the status change indicator for the single root port. Returns 1 if either
4870  * change indicator is 1, otherwise returns 0.
4871  */
4872 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
4873 {
4874         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4875
4876         buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4877         return buf[0] != 0;
4878 }
4879
4880 /* Handles hub class-specific requests */
4881 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
4882                                  u16 windex, char *buf, u16 wlength)
4883 {
4884         int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
4885                                           wvalue, windex, buf, wlength);
4886         return retval;
4887 }
4888
4889 /* Handles hub TT buffer clear completions */
4890 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
4891                                                struct usb_host_endpoint *ep)
4892 {
4893         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4894         struct dwc2_qh *qh;
4895         unsigned long flags;
4896
4897         qh = ep->hcpriv;
4898         if (!qh)
4899                 return;
4900
4901         spin_lock_irqsave(&hsotg->lock, flags);
4902         qh->tt_buffer_dirty = 0;
4903
4904         if (hsotg->flags.b.port_connect_status)
4905                 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
4906
4907         spin_unlock_irqrestore(&hsotg->lock, flags);
4908 }
4909
4910 /*
4911  * HPRT0_SPD_HIGH_SPEED: high speed
4912  * HPRT0_SPD_FULL_SPEED: full speed
4913  */
4914 static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed)
4915 {
4916         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4917
4918         if (hsotg->params.speed == speed)
4919                 return;
4920
4921         hsotg->params.speed = speed;
4922         queue_work(hsotg->wq_otg, &hsotg->wf_otg);
4923 }
4924
4925 static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
4926 {
4927         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4928
4929         if (!hsotg->params.change_speed_quirk)
4930                 return;
4931
4932         /*
4933          * On removal, set speed to default high-speed.
4934          */
4935         if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN &&
4936             udev->parent->speed < USB_SPEED_HIGH) {
4937                 dev_info(hsotg->dev, "Set speed to default high-speed\n");
4938                 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
4939         }
4940 }
4941
4942 static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
4943 {
4944         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4945
4946         if (!hsotg->params.change_speed_quirk)
4947                 return 0;
4948
4949         if (udev->speed == USB_SPEED_HIGH) {
4950                 dev_info(hsotg->dev, "Set speed to high-speed\n");
4951                 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
4952         } else if ((udev->speed == USB_SPEED_FULL ||
4953                                 udev->speed == USB_SPEED_LOW)) {
4954                 /*
4955                  * Change speed setting to full-speed if there's
4956                  * a full-speed or low-speed device plugged in.
4957                  */
4958                 dev_info(hsotg->dev, "Set speed to full-speed\n");
4959                 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED);
4960         }
4961
4962         return 0;
4963 }
4964
4965 static struct hc_driver dwc2_hc_driver = {
4966         .description = "dwc2_hsotg",
4967         .product_desc = "DWC OTG Controller",
4968         .hcd_priv_size = sizeof(struct wrapper_priv_data),
4969
4970         .irq = _dwc2_hcd_irq,
4971         .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
4972
4973         .start = _dwc2_hcd_start,
4974         .stop = _dwc2_hcd_stop,
4975         .urb_enqueue = _dwc2_hcd_urb_enqueue,
4976         .urb_dequeue = _dwc2_hcd_urb_dequeue,
4977         .endpoint_disable = _dwc2_hcd_endpoint_disable,
4978         .endpoint_reset = _dwc2_hcd_endpoint_reset,
4979         .get_frame_number = _dwc2_hcd_get_frame_number,
4980
4981         .hub_status_data = _dwc2_hcd_hub_status_data,
4982         .hub_control = _dwc2_hcd_hub_control,
4983         .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
4984
4985         .bus_suspend = _dwc2_hcd_suspend,
4986         .bus_resume = _dwc2_hcd_resume,
4987
4988         .map_urb_for_dma        = dwc2_map_urb_for_dma,
4989         .unmap_urb_for_dma      = dwc2_unmap_urb_for_dma,
4990 };
4991
4992 /*
4993  * Frees secondary storage associated with the dwc2_hsotg structure contained
4994  * in the struct usb_hcd field
4995  */
4996 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
4997 {
4998         u32 ahbcfg;
4999         u32 dctl;
5000         int i;
5001
5002         dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
5003
5004         /* Free memory for QH/QTD lists */
5005         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
5006         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting);
5007         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
5008         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
5009         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
5010         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
5011         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
5012
5013         /* Free memory for the host channels */
5014         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
5015                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
5016
5017                 if (chan) {
5018                         dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
5019                                 i, chan);
5020                         hsotg->hc_ptr_array[i] = NULL;
5021                         kfree(chan);
5022                 }
5023         }
5024
5025         if (hsotg->params.host_dma) {
5026                 if (hsotg->status_buf) {
5027                         dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
5028                                           hsotg->status_buf,
5029                                           hsotg->status_buf_dma);
5030                         hsotg->status_buf = NULL;
5031                 }
5032         } else {
5033                 kfree(hsotg->status_buf);
5034                 hsotg->status_buf = NULL;
5035         }
5036
5037         ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
5038
5039         /* Disable all interrupts */
5040         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
5041         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
5042         dwc2_writel(0, hsotg->regs + GINTMSK);
5043
5044         if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
5045                 dctl = dwc2_readl(hsotg->regs + DCTL);
5046                 dctl |= DCTL_SFTDISCON;
5047                 dwc2_writel(dctl, hsotg->regs + DCTL);
5048         }
5049
5050         if (hsotg->wq_otg) {
5051                 if (!cancel_work_sync(&hsotg->wf_otg))
5052                         flush_workqueue(hsotg->wq_otg);
5053                 destroy_workqueue(hsotg->wq_otg);
5054         }
5055
5056         del_timer(&hsotg->wkp_timer);
5057 }
5058
5059 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
5060 {
5061         /* Turn off all host-specific interrupts */
5062         dwc2_disable_host_interrupts(hsotg);
5063
5064         dwc2_hcd_free(hsotg);
5065 }
5066
5067 /*
5068  * Initializes the HCD. This function allocates memory for and initializes the
5069  * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
5070  * USB bus with the core and calls the hc_driver->start() function. It returns
5071  * a negative error on failure.
5072  */
5073 int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
5074 {
5075         struct platform_device *pdev = to_platform_device(hsotg->dev);
5076         struct resource *res;
5077         struct usb_hcd *hcd;
5078         struct dwc2_host_chan *channel;
5079         u32 hcfg;
5080         int i, num_channels;
5081         int retval;
5082
5083         if (usb_disabled())
5084                 return -ENODEV;
5085
5086         dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
5087
5088         retval = -ENOMEM;
5089
5090         hcfg = dwc2_readl(hsotg->regs + HCFG);
5091         dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5092
5093 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5094         hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
5095                                          FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
5096         if (!hsotg->frame_num_array)
5097                 goto error1;
5098         hsotg->last_frame_num_array = kzalloc(
5099                         sizeof(*hsotg->last_frame_num_array) *
5100                         FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
5101         if (!hsotg->last_frame_num_array)
5102                 goto error1;
5103 #endif
5104         hsotg->last_frame_num = HFNUM_MAX_FRNUM;
5105
5106         /* Check if the bus driver or platform code has setup a dma_mask */
5107         if (hsotg->params.host_dma &&
5108             !hsotg->dev->dma_mask) {
5109                 dev_warn(hsotg->dev,
5110                          "dma_mask not set, disabling DMA\n");
5111                 hsotg->params.host_dma = false;
5112                 hsotg->params.dma_desc_enable = false;
5113         }
5114
5115         /* Set device flags indicating whether the HCD supports DMA */
5116         if (hsotg->params.host_dma) {
5117                 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5118                         dev_warn(hsotg->dev, "can't set DMA mask\n");
5119                 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5120                         dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
5121         }
5122
5123         if (hsotg->params.change_speed_quirk) {
5124                 dwc2_hc_driver.free_dev = dwc2_free_dev;
5125                 dwc2_hc_driver.reset_device = dwc2_reset_device;
5126         }
5127
5128         hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5129         if (!hcd)
5130                 goto error1;
5131
5132         if (!hsotg->params.host_dma)
5133                 hcd->self.uses_dma = 0;
5134
5135         hcd->has_tt = 1;
5136
5137         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5138         hcd->rsrc_start = res->start;
5139         hcd->rsrc_len = resource_size(res);
5140
5141         ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
5142         hsotg->priv = hcd;
5143
5144         /*
5145          * Disable the global interrupt until all the interrupt handlers are
5146          * installed
5147          */
5148         dwc2_disable_global_interrupts(hsotg);
5149
5150         /* Initialize the DWC_otg core, and select the Phy type */
5151         retval = dwc2_core_init(hsotg, true);
5152         if (retval)
5153                 goto error2;
5154
5155         /* Create new workqueue and init work */
5156         retval = -ENOMEM;
5157         hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
5158         if (!hsotg->wq_otg) {
5159                 dev_err(hsotg->dev, "Failed to create workqueue\n");
5160                 goto error2;
5161         }
5162         INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5163
5164         timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0);
5165
5166         /* Initialize the non-periodic schedule */
5167         INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5168         INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting);
5169         INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5170
5171         /* Initialize the periodic schedule */
5172         INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5173         INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5174         INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5175         INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5176
5177         INIT_LIST_HEAD(&hsotg->split_order);
5178
5179         /*
5180          * Create a host channel descriptor for each host channel implemented
5181          * in the controller. Initialize the channel descriptor array.
5182          */
5183         INIT_LIST_HEAD(&hsotg->free_hc_list);
5184         num_channels = hsotg->params.host_channels;
5185         memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5186
5187         for (i = 0; i < num_channels; i++) {
5188                 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
5189                 if (!channel)
5190                         goto error3;
5191                 channel->hc_num = i;
5192                 INIT_LIST_HEAD(&channel->split_order_list_entry);
5193                 hsotg->hc_ptr_array[i] = channel;
5194         }
5195
5196         /* Initialize hsotg start work */
5197         INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5198
5199         /* Initialize port reset work */
5200         INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5201
5202         /*
5203          * Allocate space for storing data on status transactions. Normally no
5204          * data is sent, but this space acts as a bit bucket. This must be
5205          * done after usb_add_hcd since that function allocates the DMA buffer
5206          * pool.
5207          */
5208         if (hsotg->params.host_dma)
5209                 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5210                                         DWC2_HCD_STATUS_BUF_SIZE,
5211                                         &hsotg->status_buf_dma, GFP_KERNEL);
5212         else
5213                 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5214                                           GFP_KERNEL);
5215
5216         if (!hsotg->status_buf)
5217                 goto error3;
5218
5219         /*
5220          * Create kmem caches to handle descriptor buffers in descriptor
5221          * DMA mode.
5222          * Alignment must be set to 512 bytes.
5223          */
5224         if (hsotg->params.dma_desc_enable ||
5225             hsotg->params.dma_desc_fs_enable) {
5226                 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
5227                                 sizeof(struct dwc2_dma_desc) *
5228                                 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
5229                                 NULL);
5230                 if (!hsotg->desc_gen_cache) {
5231                         dev_err(hsotg->dev,
5232                                 "unable to create dwc2 generic desc cache\n");
5233
5234                         /*
5235                          * Disable descriptor dma mode since it will not be
5236                          * usable.
5237                          */
5238                         hsotg->params.dma_desc_enable = false;
5239                         hsotg->params.dma_desc_fs_enable = false;
5240                 }
5241
5242                 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
5243                                 sizeof(struct dwc2_dma_desc) *
5244                                 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
5245                 if (!hsotg->desc_hsisoc_cache) {
5246                         dev_err(hsotg->dev,
5247                                 "unable to create dwc2 hs isoc desc cache\n");
5248
5249                         kmem_cache_destroy(hsotg->desc_gen_cache);
5250
5251                         /*
5252                          * Disable descriptor dma mode since it will not be
5253                          * usable.
5254                          */
5255                         hsotg->params.dma_desc_enable = false;
5256                         hsotg->params.dma_desc_fs_enable = false;
5257                 }
5258         }
5259
5260         hsotg->otg_port = 1;
5261         hsotg->frame_list = NULL;
5262         hsotg->frame_list_dma = 0;
5263         hsotg->periodic_qh_count = 0;
5264
5265         /* Initiate lx_state to L3 disconnected state */
5266         hsotg->lx_state = DWC2_L3;
5267
5268         hcd->self.otg_port = hsotg->otg_port;
5269
5270         /* Don't support SG list at this point */
5271         hcd->self.sg_tablesize = 0;
5272
5273         if (!IS_ERR_OR_NULL(hsotg->uphy))
5274                 otg_set_host(hsotg->uphy->otg, &hcd->self);
5275
5276         /*
5277          * Finish generic HCD initialization and start the HCD. This function
5278          * allocates the DMA buffer pool, registers the USB bus, requests the
5279          * IRQ line, and calls hcd_start method.
5280          */
5281         retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED);
5282         if (retval < 0)
5283                 goto error4;
5284
5285         device_wakeup_enable(hcd->self.controller);
5286
5287         dwc2_hcd_dump_state(hsotg);
5288
5289         dwc2_enable_global_interrupts(hsotg);
5290
5291         return 0;
5292
5293 error4:
5294         kmem_cache_destroy(hsotg->desc_gen_cache);
5295         kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5296 error3:
5297         dwc2_hcd_release(hsotg);
5298 error2:
5299         usb_put_hcd(hcd);
5300 error1:
5301
5302 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5303         kfree(hsotg->last_frame_num_array);
5304         kfree(hsotg->frame_num_array);
5305 #endif
5306
5307         dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
5308         return retval;
5309 }
5310
5311 /*
5312  * Removes the HCD.
5313  * Frees memory and resources associated with the HCD and deregisters the bus.
5314  */
5315 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
5316 {
5317         struct usb_hcd *hcd;
5318
5319         dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
5320
5321         hcd = dwc2_hsotg_to_hcd(hsotg);
5322         dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
5323
5324         if (!hcd) {
5325                 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5326                         __func__);
5327                 return;
5328         }
5329
5330         if (!IS_ERR_OR_NULL(hsotg->uphy))
5331                 otg_set_host(hsotg->uphy->otg, NULL);
5332
5333         usb_remove_hcd(hcd);
5334         hsotg->priv = NULL;
5335
5336         kmem_cache_destroy(hsotg->desc_gen_cache);
5337         kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5338
5339         dwc2_hcd_release(hsotg);
5340         usb_put_hcd(hcd);
5341
5342 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5343         kfree(hsotg->last_frame_num_array);
5344         kfree(hsotg->frame_num_array);
5345 #endif
5346 }
5347
5348 /**
5349  * dwc2_backup_host_registers() - Backup controller host registers.
5350  * When suspending usb bus, registers needs to be backuped
5351  * if controller power is disabled once suspended.
5352  *
5353  * @hsotg: Programming view of the DWC_otg controller
5354  */
5355 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5356 {
5357         struct dwc2_hregs_backup *hr;
5358         int i;
5359
5360         dev_dbg(hsotg->dev, "%s\n", __func__);
5361
5362         /* Backup Host regs */
5363         hr = &hsotg->hr_backup;
5364         hr->hcfg = dwc2_readl(hsotg->regs + HCFG);
5365         hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
5366         for (i = 0; i < hsotg->params.host_channels; ++i)
5367                 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i));
5368
5369         hr->hprt0 = dwc2_read_hprt0(hsotg);
5370         hr->hfir = dwc2_readl(hsotg->regs + HFIR);
5371         hr->valid = true;
5372
5373         return 0;
5374 }
5375
5376 /**
5377  * dwc2_restore_host_registers() - Restore controller host registers.
5378  * When resuming usb bus, device registers needs to be restored
5379  * if controller power were disabled.
5380  *
5381  * @hsotg: Programming view of the DWC_otg controller
5382  */
5383 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5384 {
5385         struct dwc2_hregs_backup *hr;
5386         int i;
5387
5388         dev_dbg(hsotg->dev, "%s\n", __func__);
5389
5390         /* Restore host regs */
5391         hr = &hsotg->hr_backup;
5392         if (!hr->valid) {
5393                 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5394                         __func__);
5395                 return -EINVAL;
5396         }
5397         hr->valid = false;
5398
5399         dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
5400         dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK);
5401
5402         for (i = 0; i < hsotg->params.host_channels; ++i)
5403                 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));
5404
5405         dwc2_writel(hr->hprt0, hsotg->regs + HPRT0);
5406         dwc2_writel(hr->hfir, hsotg->regs + HFIR);
5407         hsotg->frame_number = 0;
5408
5409         return 0;
5410 }