drivers/gpu/drm/bridge/ite-it6505.c

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5 #include <linux/bits.h>
   6 #include <linux/delay.h>
   7 #include <linux/device.h>
   8 #include <linux/err.h>
   9 #include <linux/extcon.h>
  10 #include <linux/fs.h>
  11 #include <linux/gpio/consumer.h>
  12 #include <linux/i2c.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/types.h>
  20 #include <linux/wait.h>
  21
  22 #include <crypto/hash.h>
  23
  24 #include <drm/display/drm_dp_helper.h>
  25 #include <drm/display/drm_hdcp_helper.h>
  26 #include <drm/drm_atomic_helper.h>
  27 #include <drm/drm_bridge.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/drm_print.h>
  31 #include <drm/drm_probe_helper.h>
  32
  33 #include <sound/hdmi-codec.h>
  34
  35 #define REG_IC_VER 0x04
  36
  37 #define REG_RESET_CTRL 0x05
  38 #define VIDEO_RESET BIT(0)
  39 #define AUDIO_RESET BIT(1)
  40 #define ALL_LOGIC_RESET BIT(2)
  41 #define AUX_RESET BIT(3)
  42 #define HDCP_RESET BIT(4)
  43
  44 #define INT_STATUS_01 0x06
  45 #define INT_MASK_01 0x09
  46 #define INT_HPD_CHANGE 0
  47 #define INT_RECEIVE_HPD_IRQ 1
  48 #define INT_SCDT_CHANGE 2
  49 #define INT_HDCP_FAIL 3
  50 #define INT_HDCP_DONE 4
  51 #define BIT_OFFSET(x) (((x) - INT_STATUS_01) * BITS_PER_BYTE)
  52 #define BIT_INT_HPD INT_HPD_CHANGE
  53 #define BIT_INT_HPD_IRQ INT_RECEIVE_HPD_IRQ
  54 #define BIT_INT_SCDT INT_SCDT_CHANGE
  55 #define BIT_INT_HDCP_FAIL INT_HDCP_FAIL
  56 #define BIT_INT_HDCP_DONE INT_HDCP_DONE
  57
  58 #define INT_STATUS_02 0x07
  59 #define INT_MASK_02 0x0A
  60 #define INT_AUX_CMD_FAIL 0
  61 #define INT_HDCP_KSV_CHECK 1
  62 #define INT_AUDIO_FIFO_ERROR 2
  63 #define BIT_INT_AUX_CMD_FAIL (BIT_OFFSET(0x07) + INT_AUX_CMD_FAIL)
  64 #define BIT_INT_HDCP_KSV_CHECK (BIT_OFFSET(0x07) + INT_HDCP_KSV_CHECK)
  65 #define BIT_INT_AUDIO_FIFO_ERROR (BIT_OFFSET(0x07) + INT_AUDIO_FIFO_ERROR)
  66
  67 #define INT_STATUS_03 0x08
  68 #define INT_MASK_03 0x0B
  69 #define INT_LINK_TRAIN_FAIL 4
  70 #define INT_VID_FIFO_ERROR 5
  71 #define INT_IO_LATCH_FIFO_OVERFLOW 7
  72 #define BIT_INT_LINK_TRAIN_FAIL (BIT_OFFSET(0x08) + INT_LINK_TRAIN_FAIL)
  73 #define BIT_INT_VID_FIFO_ERROR (BIT_OFFSET(0x08) + INT_VID_FIFO_ERROR)
  74 #define BIT_INT_IO_FIFO_OVERFLOW (BIT_OFFSET(0x08) + INT_IO_LATCH_FIFO_OVERFLOW)
  75
  76 #define REG_SYSTEM_STS 0x0D
  77 #define INT_STS BIT(0)
  78 #define HPD_STS BIT(1)
  79 #define VIDEO_STB BIT(2)
  80
  81 #define REG_LINK_TRAIN_STS 0x0E
  82 #define LINK_STATE_CR BIT(2)
  83 #define LINK_STATE_EQ BIT(3)
  84 #define LINK_STATE_NORP BIT(4)
  85
  86 #define REG_BANK_SEL 0x0F
  87 #define REG_CLK_CTRL0 0x10
  88 #define M_PCLK_DELAY 0x03
  89
  90 #define REG_AUX_OPT 0x11
  91 #define AUX_AUTO_RST BIT(0)
  92 #define AUX_FIX_FREQ BIT(3)
  93
  94 #define REG_DATA_CTRL0 0x12
  95 #define VIDEO_LATCH_EDGE BIT(4)
  96 #define ENABLE_PCLK_COUNTER BIT(7)
  97
  98 #define REG_PCLK_COUNTER_VALUE 0x13
  99
 100 #define REG_501_FIFO_CTRL 0x15
 101 #define RST_501_FIFO BIT(1)
 102
 103 #define REG_TRAIN_CTRL0 0x16
 104 #define FORCE_LBR BIT(0)
 105 #define LANE_COUNT_MASK 0x06
 106 #define LANE_SWAP BIT(3)
 107 #define SPREAD_AMP_5 BIT(4)
 108 #define FORCE_CR_DONE BIT(5)
 109 #define FORCE_EQ_DONE BIT(6)
 110
 111 #define REG_TRAIN_CTRL1 0x17
 112 #define AUTO_TRAIN BIT(0)
 113 #define MANUAL_TRAIN BIT(1)
 114 #define FORCE_RETRAIN BIT(2)
 115
 116 #define REG_AUX_CTRL 0x23
 117 #define CLR_EDID_FIFO BIT(0)
 118 #define AUX_USER_MODE BIT(1)
 119 #define AUX_NO_SEGMENT_WR BIT(6)
 120 #define AUX_EN_FIFO_READ BIT(7)
 121
 122 #define REG_AUX_ADR_0_7 0x24
 123 #define REG_AUX_ADR_8_15 0x25
 124 #define REG_AUX_ADR_16_19 0x26
 125 #define REG_AUX_OUT_DATA0 0x27
 126
 127 #define REG_AUX_CMD_REQ 0x2B
 128 #define AUX_BUSY BIT(5)
 129
 130 #define REG_AUX_DATA_0_7 0x2C
 131 #define REG_AUX_DATA_8_15 0x2D
 132 #define REG_AUX_DATA_16_23 0x2E
 133 #define REG_AUX_DATA_24_31 0x2F
 134
 135 #define REG_AUX_DATA_FIFO 0x2F
 136
 137 #define REG_AUX_ERROR_STS 0x9F
 138 #define M_AUX_REQ_FAIL 0x03
 139
 140 #define REG_HDCP_CTRL1 0x38
 141 #define HDCP_CP_ENABLE BIT(0)
 142
 143 #define REG_HDCP_TRIGGER 0x39
 144 #define HDCP_TRIGGER_START  BIT(0)
 145 #define HDCP_TRIGGER_CPIRQ  BIT(1)
 146 #define HDCP_TRIGGER_KSV_DONE  BIT(4)
 147 #define HDCP_TRIGGER_KSV_FAIL BIT(5)
 148
 149 #define REG_HDCP_CTRL2 0x3A
 150 #define HDCP_AN_SEL BIT(0)
 151 #define HDCP_AN_GEN BIT(1)
 152 #define HDCP_HW_HPDIRQ_ACT BIT(2)
 153 #define HDCP_EN_M0_READ BIT(5)
 154
 155 #define REG_M0_0_7 0x4C
 156 #define REG_AN_0_7 0x4C
 157 #define REG_SP_CTRL0 0x58
 158 #define REG_IP_CTRL1 0x59
 159 #define REG_IP_CTRL2 0x5A
 160
 161 #define REG_LINK_DRV 0x5C
 162 #define DRV_HS BIT(1)
 163
 164 #define REG_DRV_LN_DATA_SEL 0x5D
 165
 166 #define REG_AUX 0x5E
 167
 168 #define REG_VID_BUS_CTRL0 0x60
 169 #define IN_DDR BIT(2)
 170 #define DDR_CD (0x01 << 6)
 171
 172 #define REG_VID_BUS_CTRL1 0x61
 173 #define TX_FIFO_RESET BIT(1)
 174
 175 #define REG_INPUT_CTRL 0xA0
 176 #define INPUT_HSYNC_POL BIT(0)
 177 #define INPUT_VSYNC_POL BIT(2)
 178 #define INPUT_INTERLACED BIT(4)
 179
 180 #define REG_INPUT_HTOTAL 0xA1
 181 #define REG_INPUT_HACTIVE_START 0xA3
 182 #define REG_INPUT_HACTIVE_WIDTH 0xA5
 183 #define REG_INPUT_HFRONT_PORCH 0xA7
 184 #define REG_INPUT_HSYNC_WIDTH 0xA9
 185 #define REG_INPUT_VTOTAL 0xAB
 186 #define REG_INPUT_VACTIVE_START 0xAD
 187 #define REG_INPUT_VACTIVE_WIDTH 0xAF
 188 #define REG_INPUT_VFRONT_PORCH 0xB1
 189 #define REG_INPUT_VSYNC_WIDTH 0xB3
 190
 191 #define REG_AUDIO_SRC_CTRL 0xB8
 192 #define M_AUDIO_I2S_EN 0x0F
 193 #define EN_I2S0 BIT(0)
 194 #define EN_I2S1 BIT(1)
 195 #define EN_I2S2 BIT(2)
 196 #define EN_I2S3 BIT(3)
 197 #define AUDIO_FIFO_RESET BIT(7)
 198
 199 #define REG_AUDIO_FMT 0xB9
 200 #define REG_AUDIO_FIFO_SEL 0xBA
 201
 202 #define REG_AUDIO_CTRL0 0xBB
 203 #define AUDIO_FULL_PKT BIT(4)
 204 #define AUDIO_16B_BOUND BIT(5)
 205
 206 #define REG_AUDIO_CTRL1 0xBC
 207 #define REG_AUDIO_INPUT_FREQ 0xBE
 208
 209 #define REG_IEC958_STS0 0xBF
 210 #define REG_IEC958_STS1 0xC0
 211 #define REG_IEC958_STS2 0xC1
 212 #define REG_IEC958_STS3 0xC2
 213 #define REG_IEC958_STS4 0xC3
 214
 215 #define REG_HPD_IRQ_TIME 0xC9
 216 #define REG_AUX_DEBUG_MODE 0xCA
 217 #define REG_AUX_OPT2 0xCB
 218 #define REG_HDCP_OPT 0xCE
 219 #define REG_USER_DRV_PRE 0xCF
 220
 221 #define REG_DATA_MUTE_CTRL 0xD3
 222 #define ENABLE_ENHANCED_FRAME BIT(0)
 223 #define ENABLE_AUTO_VIDEO_FIFO_RESET BIT(1)
 224 #define EN_VID_MUTE BIT(4)
 225 #define EN_AUD_MUTE BIT(5)
 226
 227 #define REG_TIME_STMP_CTRL 0xD4
 228 #define EN_ENHANCE_VID_STMP BIT(0)
 229 #define EN_ENHANCE_AUD_STMP BIT(2)
 230 #define M_STAMP_STEP 0x30
 231 #define EN_SSC_GAT BIT(6)
 232
 233 #define REG_INFOFRAME_CTRL 0xE8
 234 #define EN_AVI_PKT BIT(0)
 235 #define EN_AUD_PKT BIT(1)
 236 #define EN_MPG_PKT BIT(2)
 237 #define EN_GEN_PKT BIT(3)
 238 #define EN_VID_TIME_STMP BIT(4)
 239 #define EN_AUD_TIME_STMP BIT(5)
 240 #define EN_VID_CTRL_PKT (EN_AVI_PKT | EN_VID_TIME_STMP)
 241 #define EN_AUD_CTRL_PKT (EN_AUD_PKT | EN_AUD_TIME_STMP)
 242
 243 #define REG_AUDIO_N_0_7 0xDE
 244 #define REG_AUDIO_N_8_15 0xDF
 245 #define REG_AUDIO_N_16_23 0xE0
 246
 247 #define REG_AVI_INFO_DB1 0xE9
 248 #define REG_AVI_INFO_DB2 0xEA
 249 #define REG_AVI_INFO_DB3 0xEB
 250 #define REG_AVI_INFO_DB4 0xEC
 251 #define REG_AVI_INFO_DB5 0xED
 252 #define REG_AVI_INFO_SUM 0xF6
 253
 254 #define REG_AUD_INFOFRAM_DB1 0xF7
 255 #define REG_AUD_INFOFRAM_DB2 0xF8
 256 #define REG_AUD_INFOFRAM_DB3 0xF9
 257 #define REG_AUD_INFOFRAM_DB4 0xFA
 258 #define REG_AUD_INFOFRAM_SUM 0xFB
 259
 260 /* the following six registers are in bank1 */
 261 #define REG_DRV_0_DB_800_MV 0x7E
 262 #define REG_PRE_0_DB_800_MV 0x7F
 263 #define REG_PRE_3P5_DB_800_MV 0x81
 264 #define REG_SSC_CTRL0 0x88
 265 #define REG_SSC_CTRL1 0x89
 266 #define REG_SSC_CTRL2 0x8A
 267
 268 #define RBR DP_LINK_BW_1_62
 269 #define HBR DP_LINK_BW_2_7
 270 #define HBR2 DP_LINK_BW_5_4
 271 #define HBR3 DP_LINK_BW_8_1
 272
 273 #define DPCD_V_1_1 0x11
 274 #define MISC_VERB 0xF0
 275 #define MISC_VERC 0x70
 276 #define I2S_INPUT_FORMAT_STANDARD 0
 277 #define I2S_INPUT_FORMAT_32BIT 1
 278 #define I2S_INPUT_LEFT_JUSTIFIED 0
 279 #define I2S_INPUT_RIGHT_JUSTIFIED 1
 280 #define I2S_DATA_1T_DELAY 0
 281 #define I2S_DATA_NO_DELAY 1
 282 #define I2S_WS_LEFT_CHANNEL 0
 283 #define I2S_WS_RIGHT_CHANNEL 1
 284 #define I2S_DATA_MSB_FIRST 0
 285 #define I2S_DATA_LSB_FIRST 1
 286 #define WORD_LENGTH_16BIT 0
 287 #define WORD_LENGTH_18BIT 1
 288 #define WORD_LENGTH_20BIT 2
 289 #define WORD_LENGTH_24BIT 3
 290 #define DEBUGFS_DIR_NAME "it6505-debugfs"
 291 #define READ_BUFFER_SIZE 400
 292
 293 /* Vendor option */
 294 #define HDCP_DESIRED 1
 295 #define MAX_LANE_COUNT 4
 296 #define MAX_LINK_RATE HBR
 297 #define AUTO_TRAIN_RETRY 3
 298 #define MAX_HDCP_DOWN_STREAM_COUNT 10
 299 #define MAX_CR_LEVEL 0x03
 300 #define MAX_EQ_LEVEL 0x03
 301 #define AUX_WAIT_TIMEOUT_MS 15
 302 #define AUX_FIFO_MAX_SIZE 32
 303 #define PIXEL_CLK_DELAY 1
 304 #define PIXEL_CLK_INVERSE 0
 305 #define ADJUST_PHASE_THRESHOLD 80000
 306 #define DPI_PIXEL_CLK_MAX 95000
 307 #define HDCP_SHA1_FIFO_LEN (MAX_HDCP_DOWN_STREAM_COUNT * 5 + 10)
 308 #define DEFAULT_PWR_ON 0
 309 #define DEFAULT_DRV_HOLD 0
 310
 311 #define AUDIO_SELECT I2S
 312 #define AUDIO_TYPE LPCM
 313 #define AUDIO_SAMPLE_RATE SAMPLE_RATE_48K
 314 #define AUDIO_CHANNEL_COUNT 2
 315 #define I2S_INPUT_FORMAT I2S_INPUT_FORMAT_32BIT
 316 #define I2S_JUSTIFIED I2S_INPUT_LEFT_JUSTIFIED
 317 #define I2S_DATA_DELAY I2S_DATA_1T_DELAY
 318 #define I2S_WS_CHANNEL I2S_WS_LEFT_CHANNEL
 319 #define I2S_DATA_SEQUENCE I2S_DATA_MSB_FIRST
 320 #define AUDIO_WORD_LENGTH WORD_LENGTH_24BIT
 321
 322 enum aux_cmd_type {
 323         CMD_AUX_NATIVE_READ = 0x0,
 324         CMD_AUX_NATIVE_WRITE = 0x5,
 325         CMD_AUX_I2C_EDID_READ = 0xB,
 326 };
 327
 328 enum aux_cmd_reply {
 329         REPLY_ACK,
 330         REPLY_NACK,
 331         REPLY_DEFER,
 332 };
 333
 334 enum link_train_status {
 335         LINK_IDLE,
 336         LINK_BUSY,
 337         LINK_OK,
 338 };
 339
 340 enum hdcp_state {
 341         HDCP_AUTH_IDLE,
 342         HDCP_AUTH_GOING,
 343         HDCP_AUTH_DONE,
 344 };
 345
 346 struct it6505_platform_data {
 347         struct regulator *pwr18;
 348         struct regulator *ovdd;
 349         struct gpio_desc *gpiod_reset;
 350 };
 351
 352 enum it6505_audio_select {
 353         I2S = 0,
 354         SPDIF,
 355 };
 356
 357 enum it6505_audio_sample_rate {
 358         SAMPLE_RATE_24K = 0x6,
 359         SAMPLE_RATE_32K = 0x3,
 360         SAMPLE_RATE_48K = 0x2,
 361         SAMPLE_RATE_96K = 0xA,
 362         SAMPLE_RATE_192K = 0xE,
 363         SAMPLE_RATE_44_1K = 0x0,
 364         SAMPLE_RATE_88_2K = 0x8,
 365         SAMPLE_RATE_176_4K = 0xC,
 366 };
 367
 368 enum it6505_audio_type {
 369         LPCM = 0,
 370         NLPCM,
 371         DSS,
 372 };
 373
 374 struct it6505_audio_data {
 375         enum it6505_audio_select select;
 376         enum it6505_audio_sample_rate sample_rate;
 377         enum it6505_audio_type type;
 378         u8 word_length;
 379         u8 channel_count;
 380         u8 i2s_input_format;
 381         u8 i2s_justified;
 382         u8 i2s_data_delay;
 383         u8 i2s_ws_channel;
 384         u8 i2s_data_sequence;
 385 };
 386
 387 struct it6505_audio_sample_rate_map {
 388         enum it6505_audio_sample_rate rate;
 389         int sample_rate_value;
 390 };
 391
 392 struct it6505_drm_dp_link {
 393         unsigned char revision;
 394         unsigned int rate;
 395         unsigned int num_lanes;
 396         unsigned long capabilities;
 397 };
 398
 399 struct debugfs_entries {
 400         char *name;
 401         const struct file_operations *fops;
 402 };
 403
 404 struct it6505 {
 405         struct drm_dp_aux aux;
 406         struct drm_bridge bridge;
 407         struct i2c_client *client;
 408         struct it6505_drm_dp_link link;
 409         struct it6505_platform_data pdata;
 410         /*
 411          * Mutex protects extcon and interrupt functions from interfering
 412          * each other.
 413          */
 414         struct mutex extcon_lock;
 415         struct mutex mode_lock; /* used to bridge_detect */
 416         struct mutex aux_lock; /* used to aux data transfers */
 417         struct regmap *regmap;
 418         struct drm_display_mode source_output_mode;
 419         struct drm_display_mode video_info;
 420         struct notifier_block event_nb;
 421         struct extcon_dev *extcon;
 422         struct work_struct extcon_wq;
 423         int extcon_state;
 424         enum drm_connector_status connector_status;
 425         enum link_train_status link_state;
 426         struct work_struct link_works;
 427         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 428         u8 lane_count;
 429         u8 link_rate_bw_code;
 430         u8 sink_count;
 431         bool step_train;
 432         bool branch_device;
 433         bool enable_ssc;
 434         bool lane_swap_disabled;
 435         bool lane_swap;
 436         bool powered;
 437         bool hpd_state;
 438         u32 afe_setting;
 439         u32 max_dpi_pixel_clock;
 440         u32 max_lane_count;
 441         enum hdcp_state hdcp_status;
 442         struct delayed_work hdcp_work;
 443         struct work_struct hdcp_wait_ksv_list;
 444         struct completion extcon_completion;
 445         u8 auto_train_retry;
 446         bool hdcp_desired;
 447         bool is_repeater;
 448         u8 hdcp_down_stream_count;
 449         u8 bksvs[DRM_HDCP_KSV_LEN];
 450         u8 sha1_input[HDCP_SHA1_FIFO_LEN];
 451         bool enable_enhanced_frame;
 452         hdmi_codec_plugged_cb plugged_cb;
 453         struct device *codec_dev;
 454         struct delayed_work delayed_audio;
 455         struct it6505_audio_data audio;
 456         struct dentry *debugfs;
 457
 458         /* it6505 driver hold option */
 459         bool enable_drv_hold;
 460
 461         struct edid *cached_edid;
 462 };
 463
 464 struct it6505_step_train_para {
 465         u8 voltage_swing[MAX_LANE_COUNT];
 466         u8 pre_emphasis[MAX_LANE_COUNT];
 467 };
 468
 469 /*
 470  * Vendor option afe settings for different platforms
 471  * 0: without FPC cable
 472  * 1: with FPC cable
 473  */
 474
 475 static const u8 afe_setting_table[][3] = {
 476         {0x82, 0x00, 0x45},
 477         {0x93, 0x2A, 0x85}
 478 };
 479
 480 static const struct it6505_audio_sample_rate_map audio_sample_rate_map[] = {
 481         {SAMPLE_RATE_24K, 24000},
 482         {SAMPLE_RATE_32K, 32000},
 483         {SAMPLE_RATE_48K, 48000},
 484         {SAMPLE_RATE_96K, 96000},
 485         {SAMPLE_RATE_192K, 192000},
 486         {SAMPLE_RATE_44_1K, 44100},
 487         {SAMPLE_RATE_88_2K, 88200},
 488         {SAMPLE_RATE_176_4K, 176400},
 489 };
 490
 491 static const struct regmap_range it6505_bridge_volatile_ranges[] = {
 492         { .range_min = 0, .range_max = 0xFF },
 493 };
 494
 495 static const struct regmap_access_table it6505_bridge_volatile_table = {
 496         .yes_ranges = it6505_bridge_volatile_ranges,
 497         .n_yes_ranges = ARRAY_SIZE(it6505_bridge_volatile_ranges),
 498 };
 499
 500 static const struct regmap_config it6505_regmap_config = {
 501         .reg_bits = 8,
 502         .val_bits = 8,
 503         .volatile_table = &it6505_bridge_volatile_table,
 504         .cache_type = REGCACHE_NONE,
 505 };
 506
 507 static int it6505_read(struct it6505 *it6505, unsigned int reg_addr)
 508 {
 509         unsigned int value;
 510         int err;
 511         struct device *dev = &it6505->client->dev;
 512
 513         if (!it6505->powered)
 514                 return -ENODEV;
 515
 516         err = regmap_read(it6505->regmap, reg_addr, &value);
 517         if (err < 0) {
 518                 dev_err(dev, "read failed reg[0x%x] err: %d", reg_addr, err);
 519                 return err;
 520         }
 521
 522         return value;
 523 }
 524
 525 static int it6505_write(struct it6505 *it6505, unsigned int reg_addr,
 526                         unsigned int reg_val)
 527 {
 528         int err;
 529         struct device *dev = &it6505->client->dev;
 530
 531         if (!it6505->powered)
 532                 return -ENODEV;
 533
 534         err = regmap_write(it6505->regmap, reg_addr, reg_val);
 535
 536         if (err < 0) {
 537                 dev_err(dev, "write failed reg[0x%x] = 0x%x err = %d",
 538                         reg_addr, reg_val, err);
 539                 return err;
 540         }
 541
 542         return 0;
 543 }
 544
 545 static int it6505_set_bits(struct it6505 *it6505, unsigned int reg,
 546                            unsigned int mask, unsigned int value)
 547 {
 548         int err;
 549         struct device *dev = &it6505->client->dev;
 550
 551         if (!it6505->powered)
 552                 return -ENODEV;
 553
 554         err = regmap_update_bits(it6505->regmap, reg, mask, value);
 555         if (err < 0) {
 556                 dev_err(dev, "write reg[0x%x] = 0x%x mask = 0x%x failed err %d",
 557                         reg, value, mask, err);
 558                 return err;
 559         }
 560
 561         return 0;
 562 }
 563
 564 static void it6505_debug_print(struct it6505 *it6505, unsigned int reg,
 565                                const char *prefix)
 566 {
 567         struct device *dev = &it6505->client->dev;
 568         int val;
 569
 570         if (!drm_debug_enabled(DRM_UT_DRIVER))
 571                 return;
 572
 573         val = it6505_read(it6505, reg);
 574         if (val < 0)
 575                 DRM_DEV_DEBUG_DRIVER(dev, "%s reg[%02x] read error (%d)",
 576                                      prefix, reg, val);
 577         else
 578                 DRM_DEV_DEBUG_DRIVER(dev, "%s reg[%02x] = 0x%02x", prefix, reg,
 579                                      val);
 580 }
 581
 582 static int it6505_dpcd_read(struct it6505 *it6505, unsigned long offset)
 583 {
 584         u8 value;
 585         int ret;
 586         struct device *dev = &it6505->client->dev;
 587
 588         ret = drm_dp_dpcd_readb(&it6505->aux, offset, &value);
 589         if (ret < 0) {
 590                 dev_err(dev, "DPCD read failed [0x%lx] ret: %d", offset, ret);
 591                 return ret;
 592         }
 593         return value;
 594 }
 595
 596 static int it6505_dpcd_write(struct it6505 *it6505, unsigned long offset,
 597                              u8 datain)
 598 {
 599         int ret;
 600         struct device *dev = &it6505->client->dev;
 601
 602         ret = drm_dp_dpcd_writeb(&it6505->aux, offset, datain);
 603         if (ret < 0) {
 604                 dev_err(dev, "DPCD write failed [0x%lx] ret: %d", offset, ret);
 605                 return ret;
 606         }
 607         return 0;
 608 }
 609
 610 static int it6505_get_dpcd(struct it6505 *it6505, int offset, u8 *dpcd, int num)
 611 {
 612         int ret;
 613         struct device *dev = &it6505->client->dev;
 614
 615         ret = drm_dp_dpcd_read(&it6505->aux, offset, dpcd, num);
 616
 617         if (ret < 0)
 618                 return ret;
 619
 620         DRM_DEV_DEBUG_DRIVER(dev, "ret = %d DPCD[0x%x] = 0x%*ph", ret, offset,
 621                              num, dpcd);
 622
 623         return 0;
 624 }
 625
 626 static void it6505_dump(struct it6505 *it6505)
 627 {
 628         unsigned int i, j;
 629         u8 regs[16];
 630         struct device *dev = &it6505->client->dev;
 631
 632         for (i = 0; i <= 0xff; i += 16) {
 633                 for (j = 0; j < 16; j++)
 634                         regs[j] = it6505_read(it6505, i + j);
 635
 636                 DRM_DEV_DEBUG_DRIVER(dev, "[0x%02x] = %16ph", i, regs);
 637         }
 638 }
 639
 640 static bool it6505_get_sink_hpd_status(struct it6505 *it6505)
 641 {
 642         int reg_0d;
 643
 644         reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
 645
 646         if (reg_0d < 0)
 647                 return false;
 648
 649         return reg_0d & HPD_STS;
 650 }
 651
 652 static int it6505_read_word(struct it6505 *it6505, unsigned int reg)
 653 {
 654         int val0, val1;
 655
 656         val0 = it6505_read(it6505, reg);
 657         if (val0 < 0)
 658                 return val0;
 659
 660         val1 = it6505_read(it6505, reg + 1);
 661         if (val1 < 0)
 662                 return val1;
 663
 664         return (val1 << 8) | val0;
 665 }
 666
 667 static void it6505_calc_video_info(struct it6505 *it6505)
 668 {
 669         struct device *dev = &it6505->client->dev;
 670         int hsync_pol, vsync_pol, interlaced;
 671         int htotal, hdes, hdew, hfph, hsyncw;
 672         int vtotal, vdes, vdew, vfph, vsyncw;
 673         int rddata, i, pclk, sum = 0;
 674
 675         usleep_range(10000, 15000);
 676         rddata = it6505_read(it6505, REG_INPUT_CTRL);
 677         hsync_pol = rddata & INPUT_HSYNC_POL;
 678         vsync_pol = (rddata & INPUT_VSYNC_POL) >> 2;
 679         interlaced = (rddata & INPUT_INTERLACED) >> 4;
 680
 681         htotal = it6505_read_word(it6505, REG_INPUT_HTOTAL) & 0x1FFF;
 682         hdes = it6505_read_word(it6505, REG_INPUT_HACTIVE_START) & 0x1FFF;
 683         hdew = it6505_read_word(it6505, REG_INPUT_HACTIVE_WIDTH) & 0x1FFF;
 684         hfph = it6505_read_word(it6505, REG_INPUT_HFRONT_PORCH) & 0x1FFF;
 685         hsyncw = it6505_read_word(it6505, REG_INPUT_HSYNC_WIDTH) & 0x1FFF;
 686
 687         vtotal = it6505_read_word(it6505, REG_INPUT_VTOTAL) & 0xFFF;
 688         vdes = it6505_read_word(it6505, REG_INPUT_VACTIVE_START) & 0xFFF;
 689         vdew = it6505_read_word(it6505, REG_INPUT_VACTIVE_WIDTH) & 0xFFF;
 690         vfph = it6505_read_word(it6505, REG_INPUT_VFRONT_PORCH) & 0xFFF;
 691         vsyncw = it6505_read_word(it6505, REG_INPUT_VSYNC_WIDTH) & 0xFFF;
 692
 693         DRM_DEV_DEBUG_DRIVER(dev, "hsync_pol:%d, vsync_pol:%d, interlaced:%d",
 694                              hsync_pol, vsync_pol, interlaced);
 695         DRM_DEV_DEBUG_DRIVER(dev, "hactive_start:%d, vactive_start:%d",
 696                              hdes, vdes);
 697
 698         for (i = 0; i < 3; i++) {
 699                 it6505_set_bits(it6505, REG_DATA_CTRL0, ENABLE_PCLK_COUNTER,
 700                                 ENABLE_PCLK_COUNTER);
 701                 usleep_range(10000, 15000);
 702                 it6505_set_bits(it6505, REG_DATA_CTRL0, ENABLE_PCLK_COUNTER,
 703                                 0x00);
 704                 rddata = it6505_read_word(it6505, REG_PCLK_COUNTER_VALUE) &
 705                          0xFFF;
 706
 707                 sum += rddata;
 708         }
 709
 710         if (sum == 0) {
 711                 DRM_DEV_DEBUG_DRIVER(dev, "calc video timing error");
 712                 return;
 713         }
 714
 715         sum /= 3;
 716         pclk = 13500 * 2048 / sum;
 717         it6505->video_info.clock = pclk;
 718         it6505->video_info.hdisplay = hdew;
 719         it6505->video_info.hsync_start = hdew + hfph;
 720         it6505->video_info.hsync_end = hdew + hfph + hsyncw;
 721         it6505->video_info.htotal = htotal;
 722         it6505->video_info.vdisplay = vdew;
 723         it6505->video_info.vsync_start = vdew + vfph;
 724         it6505->video_info.vsync_end = vdew + vfph + vsyncw;
 725         it6505->video_info.vtotal = vtotal;
 726
 727         DRM_DEV_DEBUG_DRIVER(dev, DRM_MODE_FMT,
 728                              DRM_MODE_ARG(&it6505->video_info));
 729 }
 730
 731 static int it6505_drm_dp_link_set_power(struct drm_dp_aux *aux,
 732                                         struct it6505_drm_dp_link *link,
 733                                         u8 mode)
 734 {
 735         u8 value;
 736         int err;
 737
 738         /* DP_SET_POWER register is only available on DPCD v1.1 and later */
 739         if (link->revision < DPCD_V_1_1)
 740                 return 0;
 741
 742         err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
 743         if (err < 0)
 744                 return err;
 745
 746         value &= ~DP_SET_POWER_MASK;
 747         value |= mode;
 748
 749         err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
 750         if (err < 0)
 751                 return err;
 752
 753         if (mode == DP_SET_POWER_D0) {
 754                 /*
 755                  * According to the DP 1.1 specification, a "Sink Device must
 756                  * exit the power saving state within 1 ms" (Section 2.5.3.1,
 757                  * Table 5-52, "Sink Control Field" (register 0x600).
 758                  */
 759                 usleep_range(1000, 2000);
 760         }
 761
 762         return 0;
 763 }
 764
 765 static void it6505_clear_int(struct it6505 *it6505)
 766 {
 767         it6505_write(it6505, INT_STATUS_01, 0xFF);
 768         it6505_write(it6505, INT_STATUS_02, 0xFF);
 769         it6505_write(it6505, INT_STATUS_03, 0xFF);
 770 }
 771
 772 static void it6505_int_mask_enable(struct it6505 *it6505)
 773 {
 774         it6505_write(it6505, INT_MASK_01, BIT(INT_HPD_CHANGE) |
 775                      BIT(INT_RECEIVE_HPD_IRQ) | BIT(INT_SCDT_CHANGE) |
 776                      BIT(INT_HDCP_FAIL) | BIT(INT_HDCP_DONE));
 777
 778         it6505_write(it6505, INT_MASK_02, BIT(INT_AUX_CMD_FAIL) |
 779                      BIT(INT_HDCP_KSV_CHECK) | BIT(INT_AUDIO_FIFO_ERROR));
 780
 781         it6505_write(it6505, INT_MASK_03, BIT(INT_LINK_TRAIN_FAIL) |
 782                      BIT(INT_VID_FIFO_ERROR) | BIT(INT_IO_LATCH_FIFO_OVERFLOW));
 783 }
 784
 785 static void it6505_int_mask_disable(struct it6505 *it6505)
 786 {
 787         it6505_write(it6505, INT_MASK_01, 0x00);
 788         it6505_write(it6505, INT_MASK_02, 0x00);
 789         it6505_write(it6505, INT_MASK_03, 0x00);
 790 }
 791
 792 static void it6505_lane_termination_on(struct it6505 *it6505)
 793 {
 794         int regcf;
 795
 796         regcf = it6505_read(it6505, REG_USER_DRV_PRE);
 797
 798         if (regcf == MISC_VERB)
 799                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x00);
 800
 801         if (regcf == MISC_VERC) {
 802                 if (it6505->lane_swap) {
 803                         switch (it6505->lane_count) {
 804                         case 1:
 805                         case 2:
 806                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 807                                                 0x0C, 0x08);
 808                                 break;
 809                         default:
 810                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 811                                                 0x0C, 0x0C);
 812                                 break;
 813                         }
 814                 } else {
 815                         switch (it6505->lane_count) {
 816                         case 1:
 817                         case 2:
 818                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 819                                                 0x0C, 0x04);
 820                                 break;
 821                         default:
 822                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 823                                                 0x0C, 0x0C);
 824                                 break;
 825                         }
 826                 }
 827         }
 828 }
 829
 830 static void it6505_lane_termination_off(struct it6505 *it6505)
 831 {
 832         int regcf;
 833
 834         regcf = it6505_read(it6505, REG_USER_DRV_PRE);
 835
 836         if (regcf == MISC_VERB)
 837                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x80);
 838
 839         if (regcf == MISC_VERC)
 840                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x0C, 0x00);
 841 }
 842
 843 static void it6505_lane_power_on(struct it6505 *it6505)
 844 {
 845         it6505_set_bits(it6505, REG_LINK_DRV, 0xF1,
 846                         (it6505->lane_swap ?
 847                                  GENMASK(7, 8 - it6505->lane_count) :
 848                                  GENMASK(3 + it6505->lane_count, 4)) |
 849                                 0x01);
 850 }
 851
 852 static void it6505_lane_power_off(struct it6505 *it6505)
 853 {
 854         it6505_set_bits(it6505, REG_LINK_DRV, 0xF0, 0x00);
 855 }
 856
 857 static void it6505_lane_off(struct it6505 *it6505)
 858 {
 859         it6505_lane_power_off(it6505);
 860         it6505_lane_termination_off(it6505);
 861 }
 862
 863 static void it6505_aux_termination_on(struct it6505 *it6505)
 864 {
 865         int regcf;
 866
 867         regcf = it6505_read(it6505, REG_USER_DRV_PRE);
 868
 869         if (regcf == MISC_VERB)
 870                 it6505_lane_termination_on(it6505);
 871
 872         if (regcf == MISC_VERC)
 873                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x80);
 874 }
 875
 876 static void it6505_aux_power_on(struct it6505 *it6505)
 877 {
 878         it6505_set_bits(it6505, REG_AUX, 0x02, 0x02);
 879 }
 880
 881 static void it6505_aux_on(struct it6505 *it6505)
 882 {
 883         it6505_aux_power_on(it6505);
 884         it6505_aux_termination_on(it6505);
 885 }
 886
 887 static void it6505_aux_reset(struct it6505 *it6505)
 888 {
 889         it6505_set_bits(it6505, REG_RESET_CTRL, AUX_RESET, AUX_RESET);
 890         it6505_set_bits(it6505, REG_RESET_CTRL, AUX_RESET, 0x00);
 891 }
 892
 893 static void it6505_reset_logic(struct it6505 *it6505)
 894 {
 895         regmap_write(it6505->regmap, REG_RESET_CTRL, ALL_LOGIC_RESET);
 896         usleep_range(1000, 1500);
 897 }
 898
 899 static bool it6505_aux_op_finished(struct it6505 *it6505)
 900 {
 901         int reg2b = it6505_read(it6505, REG_AUX_CMD_REQ);
 902
 903         if (reg2b < 0)
 904                 return false;
 905
 906         return (reg2b & AUX_BUSY) == 0;
 907 }
 908
 909 static int it6505_aux_wait(struct it6505 *it6505)
 910 {
 911         int status;
 912         unsigned long timeout;
 913         struct device *dev = &it6505->client->dev;
 914
 915         timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
 916
 917         while (!it6505_aux_op_finished(it6505)) {
 918                 if (time_after(jiffies, timeout)) {
 919                         dev_err(dev, "Timed out waiting AUX to finish");
 920                         return -ETIMEDOUT;
 921                 }
 922                 usleep_range(1000, 2000);
 923         }
 924
 925         status = it6505_read(it6505, REG_AUX_ERROR_STS);
 926         if (status < 0) {
 927                 dev_err(dev, "Failed to read AUX channel: %d", status);
 928                 return status;
 929         }
 930
 931         return 0;
 932 }
 933
 934 static ssize_t it6505_aux_operation(struct it6505 *it6505,
 935                                     enum aux_cmd_type cmd,
 936                                     unsigned int address, u8 *buffer,
 937                                     size_t size, enum aux_cmd_reply *reply)
 938 {
 939         int i, ret;
 940         bool aux_write_check = false;
 941
 942         if (!it6505_get_sink_hpd_status(it6505))
 943                 return -EIO;
 944
 945         /* set AUX user mode */
 946         it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, AUX_USER_MODE);
 947
 948 aux_op_start:
 949         if (cmd == CMD_AUX_I2C_EDID_READ) {
 950                 /* AUX EDID FIFO has max length of AUX_FIFO_MAX_SIZE bytes. */
 951                 size = min_t(size_t, size, AUX_FIFO_MAX_SIZE);
 952                 /* Enable AUX FIFO read back and clear FIFO */
 953                 it6505_set_bits(it6505, REG_AUX_CTRL,
 954                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO,
 955                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO);
 956
 957                 it6505_set_bits(it6505, REG_AUX_CTRL,
 958                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO,
 959                                 AUX_EN_FIFO_READ);
 960         } else {
 961                 /* The DP AUX transmit buffer has 4 bytes. */
 962                 size = min_t(size_t, size, 4);
 963                 it6505_set_bits(it6505, REG_AUX_CTRL, AUX_NO_SEGMENT_WR,
 964                                 AUX_NO_SEGMENT_WR);
 965         }
 966
 967         /* Start Address[7:0] */
 968         it6505_write(it6505, REG_AUX_ADR_0_7, (address >> 0) & 0xFF);
 969         /* Start Address[15:8] */
 970         it6505_write(it6505, REG_AUX_ADR_8_15, (address >> 8) & 0xFF);
 971         /* WriteNum[3:0]+StartAdr[19:16] */
 972         it6505_write(it6505, REG_AUX_ADR_16_19,
 973                      ((address >> 16) & 0x0F) | ((size - 1) << 4));
 974
 975         if (cmd == CMD_AUX_NATIVE_WRITE)
 976                 regmap_bulk_write(it6505->regmap, REG_AUX_OUT_DATA0, buffer,
 977                                   size);
 978
 979         /* Aux Fire */
 980         it6505_write(it6505, REG_AUX_CMD_REQ, cmd);
 981
 982         ret = it6505_aux_wait(it6505);
 983         if (ret < 0)
 984                 goto aux_op_err;
 985
 986         ret = it6505_read(it6505, REG_AUX_ERROR_STS);
 987         if (ret < 0)
 988                 goto aux_op_err;
 989
 990         switch ((ret >> 6) & 0x3) {
 991         case 0:
 992                 *reply = REPLY_ACK;
 993                 break;
 994         case 1:
 995                 *reply = REPLY_DEFER;
 996                 ret = -EAGAIN;
 997                 goto aux_op_err;
 998         case 2:
 999                 *reply = REPLY_NACK;
1000                 ret = -EIO;
1001                 goto aux_op_err;
1002         case 3:
1003                 ret = -ETIMEDOUT;
1004                 goto aux_op_err;
1005         }
1006
1007         /* Read back Native Write data */
1008         if (cmd == CMD_AUX_NATIVE_WRITE) {
1009                 aux_write_check = true;
1010                 cmd = CMD_AUX_NATIVE_READ;
1011                 goto aux_op_start;
1012         }
1013
1014         if (cmd == CMD_AUX_I2C_EDID_READ) {
1015                 for (i = 0; i < size; i++) {
1016                         ret = it6505_read(it6505, REG_AUX_DATA_FIFO);
1017                         if (ret < 0)
1018                                 goto aux_op_err;
1019                         buffer[i] = ret;
1020                 }
1021         } else {
1022                 for (i = 0; i < size; i++) {
1023                         ret = it6505_read(it6505, REG_AUX_DATA_0_7 + i);
1024                         if (ret < 0)
1025                                 goto aux_op_err;
1026
1027                         if (aux_write_check && buffer[size - 1 - i] != ret) {
1028                                 ret = -EINVAL;
1029                                 goto aux_op_err;
1030                         }
1031
1032                         buffer[size - 1 - i] = ret;
1033                 }
1034         }
1035
1036         ret = i;
1037
1038 aux_op_err:
1039         if (cmd == CMD_AUX_I2C_EDID_READ) {
1040                 /* clear AUX FIFO */
1041                 it6505_set_bits(it6505, REG_AUX_CTRL,
1042                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO,
1043                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO);
1044                 it6505_set_bits(it6505, REG_AUX_CTRL,
1045                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO, 0x00);
1046         }
1047
1048         /* Leave AUX user mode */
1049         it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, 0);
1050
1051         return ret;
1052 }
1053
1054 static ssize_t it6505_aux_do_transfer(struct it6505 *it6505,
1055                                       enum aux_cmd_type cmd,
1056                                       unsigned int address, u8 *buffer,
1057                                       size_t size, enum aux_cmd_reply *reply)
1058 {
1059         int i, ret_size, ret = 0, request_size;
1060
1061         mutex_lock(&it6505->aux_lock);
1062         for (i = 0; i < size; i += 4) {
1063                 request_size = min((int)size - i, 4);
1064                 ret_size = it6505_aux_operation(it6505, cmd, address + i,
1065                                                 buffer + i, request_size,
1066                                                 reply);
1067                 if (ret_size < 0) {
1068                         ret = ret_size;
1069                         goto aux_op_err;
1070                 }
1071
1072                 ret += ret_size;
1073         }
1074
1075 aux_op_err:
1076         mutex_unlock(&it6505->aux_lock);
1077         return ret;
1078 }
1079
1080 static ssize_t it6505_aux_transfer(struct drm_dp_aux *aux,
1081                                    struct drm_dp_aux_msg *msg)
1082 {
1083         struct it6505 *it6505 = container_of(aux, struct it6505, aux);
1084         u8 cmd;
1085         bool is_i2c = !(msg->request & DP_AUX_NATIVE_WRITE);
1086         int ret;
1087         enum aux_cmd_reply reply;
1088
1089         /* IT6505 doesn't support arbitrary I2C read / write. */
1090         if (is_i2c)
1091                 return -EINVAL;
1092
1093         switch (msg->request) {
1094         case DP_AUX_NATIVE_READ:
1095                 cmd = CMD_AUX_NATIVE_READ;
1096                 break;
1097         case DP_AUX_NATIVE_WRITE:
1098                 cmd = CMD_AUX_NATIVE_WRITE;
1099                 break;
1100         default:
1101                 return -EINVAL;
1102         }
1103
1104         ret = it6505_aux_do_transfer(it6505, cmd, msg->address, msg->buffer,
1105                                      msg->size, &reply);
1106         if (ret < 0)
1107                 return ret;
1108
1109         switch (reply) {
1110         case REPLY_ACK:
1111                 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
1112                 break;
1113         case REPLY_NACK:
1114                 msg->reply = DP_AUX_NATIVE_REPLY_NACK;
1115                 break;
1116         case REPLY_DEFER:
1117                 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
1118                 break;
1119         }
1120
1121         return ret;
1122 }
1123
1124 static int it6505_get_edid_block(void *data, u8 *buf, unsigned int block,
1125                                  size_t len)
1126 {
1127         struct it6505 *it6505 = data;
1128         struct device *dev = &it6505->client->dev;
1129         enum aux_cmd_reply reply;
1130         int offset, ret, aux_retry = 100;
1131
1132         it6505_aux_reset(it6505);
1133         DRM_DEV_DEBUG_DRIVER(dev, "block number = %d", block);
1134
1135         for (offset = 0; offset < EDID_LENGTH;) {
1136                 ret = it6505_aux_do_transfer(it6505, CMD_AUX_I2C_EDID_READ,
1137                                              block * EDID_LENGTH + offset,
1138                                              buf + offset, 8, &reply);
1139
1140                 if (ret < 0 && ret != -EAGAIN)
1141                         return ret;
1142
1143                 switch (reply) {
1144                 case REPLY_ACK:
1145                         DRM_DEV_DEBUG_DRIVER(dev, "[0x%02x]: %8ph", offset,
1146                                              buf + offset);
1147                         offset += 8;
1148                         aux_retry = 100;
1149                         break;
1150                 case REPLY_NACK:
1151                         return -EIO;
1152                 case REPLY_DEFER:
1153                         msleep(20);
1154                         if (!(--aux_retry))
1155                                 return -EIO;
1156                 }
1157         }
1158
1159         return 0;
1160 }
1161
1162 static void it6505_variable_config(struct it6505 *it6505)
1163 {
1164         it6505->link_rate_bw_code = HBR;
1165         it6505->lane_count = MAX_LANE_COUNT;
1166         it6505->link_state = LINK_IDLE;
1167         it6505->hdcp_desired = HDCP_DESIRED;
1168         it6505->auto_train_retry = AUTO_TRAIN_RETRY;
1169         it6505->audio.select = AUDIO_SELECT;
1170         it6505->audio.sample_rate = AUDIO_SAMPLE_RATE;
1171         it6505->audio.channel_count = AUDIO_CHANNEL_COUNT;
1172         it6505->audio.type = AUDIO_TYPE;
1173         it6505->audio.i2s_input_format = I2S_INPUT_FORMAT;
1174         it6505->audio.i2s_justified = I2S_JUSTIFIED;
1175         it6505->audio.i2s_data_delay = I2S_DATA_DELAY;
1176         it6505->audio.i2s_ws_channel = I2S_WS_CHANNEL;
1177         it6505->audio.i2s_data_sequence = I2S_DATA_SEQUENCE;
1178         it6505->audio.word_length = AUDIO_WORD_LENGTH;
1179         memset(it6505->sha1_input, 0, sizeof(it6505->sha1_input));
1180         memset(it6505->bksvs, 0, sizeof(it6505->bksvs));
1181 }
1182
1183 static int it6505_send_video_infoframe(struct it6505 *it6505,
1184                                        struct hdmi_avi_infoframe *frame)
1185 {
1186         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1187         int err;
1188         struct device *dev = &it6505->client->dev;
1189
1190         err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
1191         if (err < 0) {
1192                 dev_err(dev, "Failed to pack AVI infoframe: %d", err);
1193                 return err;
1194         }
1195
1196         err = it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AVI_PKT, 0x00);
1197         if (err)
1198                 return err;
1199
1200         err = regmap_bulk_write(it6505->regmap, REG_AVI_INFO_DB1,
1201                                 buffer + HDMI_INFOFRAME_HEADER_SIZE,
1202                                 frame->length);
1203         if (err)
1204                 return err;
1205
1206         err = it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AVI_PKT,
1207                               EN_AVI_PKT);
1208         if (err)
1209                 return err;
1210
1211         return 0;
1212 }
1213
1214 static void it6505_get_extcon_property(struct it6505 *it6505)
1215 {
1216         int err;
1217         union extcon_property_value property;
1218         struct device *dev = &it6505->client->dev;
1219
1220         if (it6505->extcon && !it6505->lane_swap_disabled) {
1221                 err = extcon_get_property(it6505->extcon, EXTCON_DISP_DP,
1222                                           EXTCON_PROP_USB_TYPEC_POLARITY,
1223                                           &property);
1224                 if (err) {
1225                         dev_err(dev, "get property fail!");
1226                         return;
1227                 }
1228                 it6505->lane_swap = property.intval;
1229         }
1230 }
1231
1232 static void it6505_clk_phase_adjustment(struct it6505 *it6505,
1233                                         const struct drm_display_mode *mode)
1234 {
1235         int clock = mode->clock;
1236
1237         it6505_set_bits(it6505, REG_CLK_CTRL0, M_PCLK_DELAY,
1238                         clock < ADJUST_PHASE_THRESHOLD ? PIXEL_CLK_DELAY : 0);
1239         it6505_set_bits(it6505, REG_DATA_CTRL0, VIDEO_LATCH_EDGE,
1240                         PIXEL_CLK_INVERSE << 4);
1241 }
1242
1243 static void it6505_link_reset_step_train(struct it6505 *it6505)
1244 {
1245         it6505_set_bits(it6505, REG_TRAIN_CTRL0,
1246                         FORCE_CR_DONE | FORCE_EQ_DONE, 0x00);
1247         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1248                           DP_TRAINING_PATTERN_DISABLE);
1249 }
1250
1251 static void it6505_init(struct it6505 *it6505)
1252 {
1253         it6505_write(it6505, REG_AUX_OPT, AUX_AUTO_RST | AUX_FIX_FREQ);
1254         it6505_write(it6505, REG_AUX_CTRL, AUX_NO_SEGMENT_WR);
1255         it6505_write(it6505, REG_HDCP_CTRL2, HDCP_AN_SEL | HDCP_HW_HPDIRQ_ACT);
1256         it6505_write(it6505, REG_VID_BUS_CTRL0, IN_DDR | DDR_CD);
1257         it6505_write(it6505, REG_VID_BUS_CTRL1, 0x01);
1258         it6505_write(it6505, REG_AUDIO_CTRL0, AUDIO_16B_BOUND);
1259
1260         /* chip internal setting, don't modify */
1261         it6505_write(it6505, REG_HPD_IRQ_TIME, 0xF5);
1262         it6505_write(it6505, REG_AUX_DEBUG_MODE, 0x4D);
1263         it6505_write(it6505, REG_AUX_OPT2, 0x17);
1264         it6505_write(it6505, REG_HDCP_OPT, 0x60);
1265         it6505_write(it6505, REG_DATA_MUTE_CTRL,
1266                      EN_VID_MUTE | EN_AUD_MUTE | ENABLE_AUTO_VIDEO_FIFO_RESET);
1267         it6505_write(it6505, REG_TIME_STMP_CTRL,
1268                      EN_SSC_GAT | EN_ENHANCE_VID_STMP | EN_ENHANCE_AUD_STMP);
1269         it6505_write(it6505, REG_INFOFRAME_CTRL, 0x00);
1270         it6505_write(it6505, REG_BANK_SEL, 0x01);
1271         it6505_write(it6505, REG_DRV_0_DB_800_MV,
1272                      afe_setting_table[it6505->afe_setting][0]);
1273         it6505_write(it6505, REG_PRE_0_DB_800_MV,
1274                      afe_setting_table[it6505->afe_setting][1]);
1275         it6505_write(it6505, REG_PRE_3P5_DB_800_MV,
1276                      afe_setting_table[it6505->afe_setting][2]);
1277         it6505_write(it6505, REG_SSC_CTRL0, 0x9E);
1278         it6505_write(it6505, REG_SSC_CTRL1, 0x1C);
1279         it6505_write(it6505, REG_SSC_CTRL2, 0x42);
1280         it6505_write(it6505, REG_BANK_SEL, 0x00);
1281 }
1282
1283 static void it6505_video_disable(struct it6505 *it6505)
1284 {
1285         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1286         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00);
1287         it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1288 }
1289
1290 static void it6505_video_reset(struct it6505 *it6505)
1291 {
1292         it6505_link_reset_step_train(it6505);
1293         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1294         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00);
1295         it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1296         it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, RST_501_FIFO);
1297         it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, 0x00);
1298         it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, 0x00);
1299 }
1300
1301 static void it6505_update_video_parameter(struct it6505 *it6505,
1302                                           const struct drm_display_mode *mode)
1303 {
1304         it6505_clk_phase_adjustment(it6505, mode);
1305         it6505_video_disable(it6505);
1306 }
1307
1308 static bool it6505_audio_input(struct it6505 *it6505)
1309 {
1310         int reg05, regbe;
1311
1312         reg05 = it6505_read(it6505, REG_RESET_CTRL);
1313         it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, 0x00);
1314         usleep_range(3000, 4000);
1315         regbe = it6505_read(it6505, REG_AUDIO_INPUT_FREQ);
1316         it6505_write(it6505, REG_RESET_CTRL, reg05);
1317
1318         return regbe != 0xFF;
1319 }
1320
1321 static void it6505_setup_audio_channel_status(struct it6505 *it6505)
1322 {
1323         enum it6505_audio_sample_rate sample_rate = it6505->audio.sample_rate;
1324         u8 audio_word_length_map[] = { 0x02, 0x04, 0x03, 0x0B };
1325
1326         /* Channel Status */
1327         it6505_write(it6505, REG_IEC958_STS0, it6505->audio.type << 1);
1328         it6505_write(it6505, REG_IEC958_STS1, 0x00);
1329         it6505_write(it6505, REG_IEC958_STS2, 0x00);
1330         it6505_write(it6505, REG_IEC958_STS3, sample_rate);
1331         it6505_write(it6505, REG_IEC958_STS4, (~sample_rate << 4) |
1332                      audio_word_length_map[it6505->audio.word_length]);
1333 }
1334
1335 static void it6505_setup_audio_format(struct it6505 *it6505)
1336 {
1337         /* I2S MODE */
1338         it6505_write(it6505, REG_AUDIO_FMT,
1339                      (it6505->audio.word_length << 5) |
1340                      (it6505->audio.i2s_data_sequence << 4) |
1341                      (it6505->audio.i2s_ws_channel << 3) |
1342                      (it6505->audio.i2s_data_delay << 2) |
1343                      (it6505->audio.i2s_justified << 1) |
1344                      it6505->audio.i2s_input_format);
1345         if (it6505->audio.select == SPDIF) {
1346                 it6505_write(it6505, REG_AUDIO_FIFO_SEL, 0x00);
1347                 /* 0x30 = 128*FS */
1348                 it6505_set_bits(it6505, REG_AUX_OPT, 0xF0, 0x30);
1349         } else {
1350                 it6505_write(it6505, REG_AUDIO_FIFO_SEL, 0xE4);
1351         }
1352
1353         it6505_write(it6505, REG_AUDIO_CTRL0, 0x20);
1354         it6505_write(it6505, REG_AUDIO_CTRL1, 0x00);
1355 }
1356
1357 static void it6505_enable_audio_source(struct it6505 *it6505)
1358 {
1359         unsigned int audio_source_count;
1360
1361         audio_source_count = BIT(DIV_ROUND_UP(it6505->audio.channel_count, 2))
1362                                  - 1;
1363
1364         audio_source_count |= it6505->audio.select << 4;
1365
1366         it6505_write(it6505, REG_AUDIO_SRC_CTRL, audio_source_count);
1367 }
1368
1369 static void it6505_enable_audio_infoframe(struct it6505 *it6505)
1370 {
1371         struct device *dev = &it6505->client->dev;
1372         u8 audio_info_ca[] = { 0x00, 0x00, 0x01, 0x03, 0x07, 0x0B, 0x0F, 0x1F };
1373
1374         DRM_DEV_DEBUG_DRIVER(dev, "infoframe channel_allocation:0x%02x",
1375                              audio_info_ca[it6505->audio.channel_count - 1]);
1376
1377         it6505_write(it6505, REG_AUD_INFOFRAM_DB1, it6505->audio.channel_count
1378                      - 1);
1379         it6505_write(it6505, REG_AUD_INFOFRAM_DB2, 0x00);
1380         it6505_write(it6505, REG_AUD_INFOFRAM_DB3,
1381                      audio_info_ca[it6505->audio.channel_count - 1]);
1382         it6505_write(it6505, REG_AUD_INFOFRAM_DB4, 0x00);
1383         it6505_write(it6505, REG_AUD_INFOFRAM_SUM, 0x00);
1384
1385         /* Enable Audio InfoFrame */
1386         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AUD_CTRL_PKT,
1387                         EN_AUD_CTRL_PKT);
1388 }
1389
1390 static void it6505_disable_audio(struct it6505 *it6505)
1391 {
1392         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_AUD_MUTE, EN_AUD_MUTE);
1393         it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, M_AUDIO_I2S_EN, 0x00);
1394         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AUD_CTRL_PKT, 0x00);
1395         it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, AUDIO_RESET);
1396 }
1397
1398 static void it6505_enable_audio(struct it6505 *it6505)
1399 {
1400         struct device *dev = &it6505->client->dev;
1401         int regbe;
1402
1403         DRM_DEV_DEBUG_DRIVER(dev, "start");
1404         it6505_disable_audio(it6505);
1405
1406         it6505_setup_audio_channel_status(it6505);
1407         it6505_setup_audio_format(it6505);
1408         it6505_enable_audio_source(it6505);
1409         it6505_enable_audio_infoframe(it6505);
1410
1411         it6505_write(it6505, REG_AUDIO_N_0_7, 0x00);
1412         it6505_write(it6505, REG_AUDIO_N_8_15, 0x80);
1413         it6505_write(it6505, REG_AUDIO_N_16_23, 0x00);
1414
1415         it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, AUDIO_FIFO_RESET,
1416                         AUDIO_FIFO_RESET);
1417         it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, AUDIO_FIFO_RESET, 0x00);
1418         it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, 0x00);
1419         regbe = it6505_read(it6505, REG_AUDIO_INPUT_FREQ);
1420         DRM_DEV_DEBUG_DRIVER(dev, "regbe:0x%02x audio input fs: %d.%d kHz",
1421                              regbe, 6750 / regbe, (6750 % regbe) * 10 / regbe);
1422         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_AUD_MUTE, 0x00);
1423 }
1424
1425 static bool it6505_use_step_train_check(struct it6505 *it6505)
1426 {
1427         if (it6505->link.revision >= 0x12)
1428                 return it6505->dpcd[DP_TRAINING_AUX_RD_INTERVAL] >= 0x01;
1429
1430         return true;
1431 }
1432
1433 static void it6505_parse_link_capabilities(struct it6505 *it6505)
1434 {
1435         struct device *dev = &it6505->client->dev;
1436         struct it6505_drm_dp_link *link = &it6505->link;
1437         int bcaps;
1438
1439         if (it6505->dpcd[0] == 0) {
1440                 dev_err(dev, "DPCD is not initialized");
1441                 return;
1442         }
1443
1444         memset(link, 0, sizeof(*link));
1445
1446         link->revision = it6505->dpcd[0];
1447         link->rate = drm_dp_bw_code_to_link_rate(it6505->dpcd[1]);
1448         link->num_lanes = it6505->dpcd[2] & DP_MAX_LANE_COUNT_MASK;
1449
1450         if (it6505->dpcd[2] & DP_ENHANCED_FRAME_CAP)
1451                 link->capabilities = DP_ENHANCED_FRAME_CAP;
1452
1453         DRM_DEV_DEBUG_DRIVER(dev, "DPCD Rev.: %d.%d",
1454                              link->revision >> 4, link->revision & 0x0F);
1455
1456         DRM_DEV_DEBUG_DRIVER(dev, "Sink max link rate: %d.%02d Gbps per lane",
1457                              link->rate / 100000, link->rate / 1000 % 100);
1458
1459         it6505->link_rate_bw_code = drm_dp_link_rate_to_bw_code(link->rate);
1460         DRM_DEV_DEBUG_DRIVER(dev, "link rate bw code:0x%02x",
1461                              it6505->link_rate_bw_code);
1462         it6505->link_rate_bw_code = min_t(int, it6505->link_rate_bw_code,
1463                                           MAX_LINK_RATE);
1464
1465         it6505->lane_count = link->num_lanes;
1466         DRM_DEV_DEBUG_DRIVER(dev, "Sink support %d lanes training",
1467                              it6505->lane_count);
1468         it6505->lane_count = min_t(int, it6505->lane_count,
1469                                    it6505->max_lane_count);
1470
1471         it6505->branch_device = drm_dp_is_branch(it6505->dpcd);
1472         DRM_DEV_DEBUG_DRIVER(dev, "Sink %sbranch device",
1473                              it6505->branch_device ? "" : "Not ");
1474
1475         it6505->enable_enhanced_frame = link->capabilities;
1476         DRM_DEV_DEBUG_DRIVER(dev, "Sink %sSupport Enhanced Framing",
1477                              it6505->enable_enhanced_frame ? "" : "Not ");
1478
1479         it6505->enable_ssc = (it6505->dpcd[DP_MAX_DOWNSPREAD] &
1480                                 DP_MAX_DOWNSPREAD_0_5);
1481         DRM_DEV_DEBUG_DRIVER(dev, "Maximum Down-Spread: %s, %ssupport SSC!",
1482                              it6505->enable_ssc ? "0.5" : "0",
1483                              it6505->enable_ssc ? "" : "Not ");
1484
1485         it6505->step_train = it6505_use_step_train_check(it6505);
1486         if (it6505->step_train)
1487                 DRM_DEV_DEBUG_DRIVER(dev, "auto train fail, will step train");
1488
1489         bcaps = it6505_dpcd_read(it6505, DP_AUX_HDCP_BCAPS);
1490         DRM_DEV_DEBUG_DRIVER(dev, "bcaps:0x%02x", bcaps);
1491         if (bcaps & DP_BCAPS_HDCP_CAPABLE) {
1492                 it6505->is_repeater = (bcaps & DP_BCAPS_REPEATER_PRESENT);
1493                 DRM_DEV_DEBUG_DRIVER(dev, "Support HDCP! Downstream is %s!",
1494                                      it6505->is_repeater ? "repeater" :
1495                                      "receiver");
1496         } else {
1497                 DRM_DEV_DEBUG_DRIVER(dev, "Sink not support HDCP!");
1498                 it6505->hdcp_desired = false;
1499         }
1500         DRM_DEV_DEBUG_DRIVER(dev, "HDCP %s",
1501                              it6505->hdcp_desired ? "desired" : "undesired");
1502 }
1503
1504 static void it6505_setup_ssc(struct it6505 *it6505)
1505 {
1506         it6505_set_bits(it6505, REG_TRAIN_CTRL0, SPREAD_AMP_5,
1507                         it6505->enable_ssc ? SPREAD_AMP_5 : 0x00);
1508         if (it6505->enable_ssc) {
1509                 it6505_write(it6505, REG_BANK_SEL, 0x01);
1510                 it6505_write(it6505, REG_SSC_CTRL0, 0x9E);
1511                 it6505_write(it6505, REG_SSC_CTRL1, 0x1C);
1512                 it6505_write(it6505, REG_SSC_CTRL2, 0x42);
1513                 it6505_write(it6505, REG_BANK_SEL, 0x00);
1514                 it6505_write(it6505, REG_SP_CTRL0, 0x07);
1515                 it6505_write(it6505, REG_IP_CTRL1, 0x29);
1516                 it6505_write(it6505, REG_IP_CTRL2, 0x03);
1517                 /* Stamp Interrupt Step */
1518                 it6505_set_bits(it6505, REG_TIME_STMP_CTRL, M_STAMP_STEP,
1519                                 0x10);
1520                 it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL,
1521                                   DP_SPREAD_AMP_0_5);
1522         } else {
1523                 it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL, 0x00);
1524                 it6505_set_bits(it6505, REG_TIME_STMP_CTRL, M_STAMP_STEP,
1525                                 0x00);
1526         }
1527 }
1528
1529 static inline void it6505_link_rate_setup(struct it6505 *it6505)
1530 {
1531         it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_LBR,
1532                         (it6505->link_rate_bw_code == RBR) ? FORCE_LBR : 0x00);
1533         it6505_set_bits(it6505, REG_LINK_DRV, DRV_HS,
1534                         (it6505->link_rate_bw_code == RBR) ? 0x00 : DRV_HS);
1535 }
1536
1537 static void it6505_lane_count_setup(struct it6505 *it6505)
1538 {
1539         it6505_get_extcon_property(it6505);
1540         it6505_set_bits(it6505, REG_TRAIN_CTRL0, LANE_SWAP,
1541                         it6505->lane_swap ? LANE_SWAP : 0x00);
1542         it6505_set_bits(it6505, REG_TRAIN_CTRL0, LANE_COUNT_MASK,
1543                         (it6505->lane_count - 1) << 1);
1544 }
1545
1546 static void it6505_link_training_setup(struct it6505 *it6505)
1547 {
1548         struct device *dev = &it6505->client->dev;
1549
1550         if (it6505->enable_enhanced_frame)
1551                 it6505_set_bits(it6505, REG_DATA_MUTE_CTRL,
1552                                 ENABLE_ENHANCED_FRAME, ENABLE_ENHANCED_FRAME);
1553
1554         it6505_link_rate_setup(it6505);
1555         it6505_lane_count_setup(it6505);
1556         it6505_setup_ssc(it6505);
1557         DRM_DEV_DEBUG_DRIVER(dev,
1558                              "%s, %d lanes, %sable ssc, %sable enhanced frame",
1559                              it6505->link_rate_bw_code != RBR ? "HBR" : "RBR",
1560                              it6505->lane_count,
1561                              it6505->enable_ssc ? "en" : "dis",
1562                              it6505->enable_enhanced_frame ? "en" : "dis");
1563 }
1564
1565 static bool it6505_link_start_auto_train(struct it6505 *it6505)
1566 {
1567         int timeout = 500, link_training_state;
1568         bool state = false;
1569
1570         mutex_lock(&it6505->aux_lock);
1571         it6505_set_bits(it6505, REG_TRAIN_CTRL0,
1572                         FORCE_CR_DONE | FORCE_EQ_DONE, 0x00);
1573         it6505_write(it6505, REG_TRAIN_CTRL1, FORCE_RETRAIN);
1574         it6505_write(it6505, REG_TRAIN_CTRL1, AUTO_TRAIN);
1575
1576         while (timeout > 0) {
1577                 usleep_range(1000, 2000);
1578                 link_training_state = it6505_read(it6505, REG_LINK_TRAIN_STS);
1579
1580                 if (link_training_state > 0 &&
1581                     (link_training_state & LINK_STATE_NORP)) {
1582                         state = true;
1583                         goto unlock;
1584                 }
1585
1586                 timeout--;
1587         }
1588 unlock:
1589         mutex_unlock(&it6505->aux_lock);
1590
1591         return state;
1592 }
1593
1594 static int it6505_drm_dp_link_configure(struct it6505 *it6505)
1595 {
1596         u8 values[2];
1597         int err;
1598         struct drm_dp_aux *aux = &it6505->aux;
1599
1600         values[0] = it6505->link_rate_bw_code;
1601         values[1] = it6505->lane_count;
1602
1603         if (it6505->enable_enhanced_frame)
1604                 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1605
1606         err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
1607         if (err < 0)
1608                 return err;
1609
1610         return 0;
1611 }
1612
1613 static bool it6505_check_voltage_swing_max(u8 lane_voltage_swing_pre_emphasis)
1614 {
1615         return ((lane_voltage_swing_pre_emphasis & 0x03) == MAX_CR_LEVEL);
1616 }
1617
1618 static bool it6505_check_pre_emphasis_max(u8 lane_voltage_swing_pre_emphasis)
1619 {
1620         return ((lane_voltage_swing_pre_emphasis & 0x03) == MAX_EQ_LEVEL);
1621 }
1622
1623 static bool it6505_check_max_voltage_swing_reached(u8 *lane_voltage_swing,
1624                                                    u8 lane_count)
1625 {
1626         u8 i;
1627
1628         for (i = 0; i < lane_count; i++) {
1629                 if (lane_voltage_swing[i] & DP_TRAIN_MAX_SWING_REACHED)
1630                         return true;
1631         }
1632
1633         return false;
1634 }
1635
1636 static bool
1637 step_train_lane_voltage_para_set(struct it6505 *it6505,
1638                                  struct it6505_step_train_para
1639                                  *lane_voltage_pre_emphasis,
1640                                  u8 *lane_voltage_pre_emphasis_set)
1641 {
1642         u8 *voltage_swing = lane_voltage_pre_emphasis->voltage_swing;
1643         u8 *pre_emphasis = lane_voltage_pre_emphasis->pre_emphasis;
1644         u8 i;
1645
1646         for (i = 0; i < it6505->lane_count; i++) {
1647                 voltage_swing[i] &= 0x03;
1648                 lane_voltage_pre_emphasis_set[i] = voltage_swing[i];
1649                 if (it6505_check_voltage_swing_max(voltage_swing[i]))
1650                         lane_voltage_pre_emphasis_set[i] |=
1651                                 DP_TRAIN_MAX_SWING_REACHED;
1652
1653                 pre_emphasis[i] &= 0x03;
1654                 lane_voltage_pre_emphasis_set[i] |= pre_emphasis[i]
1655                         << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1656                 if (it6505_check_pre_emphasis_max(pre_emphasis[i]))
1657                         lane_voltage_pre_emphasis_set[i] |=
1658                                 DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1659                 it6505_dpcd_write(it6505, DP_TRAINING_LANE0_SET + i,
1660                                   lane_voltage_pre_emphasis_set[i]);
1661
1662                 if (lane_voltage_pre_emphasis_set[i] !=
1663                     it6505_dpcd_read(it6505, DP_TRAINING_LANE0_SET + i))
1664                         return false;
1665         }
1666
1667         return true;
1668 }
1669
1670 static bool
1671 it6505_step_cr_train(struct it6505 *it6505,
1672                      struct it6505_step_train_para *lane_voltage_pre_emphasis)
1673 {
1674         u8 loop_count = 0, i = 0, j;
1675         u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };
1676         u8 lane_level_config[MAX_LANE_COUNT] = { 0 };
1677         int pre_emphasis_adjust = -1, voltage_swing_adjust = -1;
1678         const struct drm_dp_aux *aux = &it6505->aux;
1679
1680         it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL,
1681                           it6505->enable_ssc ? DP_SPREAD_AMP_0_5 : 0x00);
1682         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1683                           DP_TRAINING_PATTERN_1);
1684
1685         while (loop_count < 5 && i < 10) {
1686                 i++;
1687                 if (!step_train_lane_voltage_para_set(it6505,
1688                                                       lane_voltage_pre_emphasis,
1689                                                       lane_level_config))
1690                         continue;
1691                 drm_dp_link_train_clock_recovery_delay(aux, it6505->dpcd);
1692                 drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
1693
1694                 if (drm_dp_clock_recovery_ok(link_status, it6505->lane_count)) {
1695                         it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_CR_DONE,
1696                                         FORCE_CR_DONE);
1697                         return true;
1698                 }
1699                 DRM_DEV_DEBUG_DRIVER(&it6505->client->dev, "cr not done");
1700
1701                 if (it6505_check_max_voltage_swing_reached(lane_level_config,
1702                                                            it6505->lane_count))
1703                         goto cr_train_fail;
1704
1705                 for (j = 0; j < it6505->lane_count; j++) {
1706                         lane_voltage_pre_emphasis->voltage_swing[j] =
1707                                 drm_dp_get_adjust_request_voltage(link_status,
1708                                                                   j) >>
1709                                 DP_TRAIN_VOLTAGE_SWING_SHIFT;
1710                         lane_voltage_pre_emphasis->pre_emphasis[j] =
1711                         drm_dp_get_adjust_request_pre_emphasis(link_status,
1712                                                                j) >>
1713                                         DP_TRAIN_PRE_EMPHASIS_SHIFT;
1714                         if (voltage_swing_adjust ==
1715                              lane_voltage_pre_emphasis->voltage_swing[j] &&
1716                             pre_emphasis_adjust ==
1717                              lane_voltage_pre_emphasis->pre_emphasis[j]) {
1718                                 loop_count++;
1719                                 continue;
1720                         }
1721
1722                         voltage_swing_adjust =
1723                                 lane_voltage_pre_emphasis->voltage_swing[j];
1724                         pre_emphasis_adjust =
1725                                 lane_voltage_pre_emphasis->pre_emphasis[j];
1726                         loop_count = 0;
1727
1728                         if (voltage_swing_adjust + pre_emphasis_adjust >
1729                             MAX_EQ_LEVEL)
1730                                 lane_voltage_pre_emphasis->voltage_swing[j] =
1731                                         MAX_EQ_LEVEL -
1732                                         lane_voltage_pre_emphasis
1733                                                 ->pre_emphasis[j];
1734                 }
1735         }
1736
1737 cr_train_fail:
1738         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1739                           DP_TRAINING_PATTERN_DISABLE);
1740
1741         return false;
1742 }
1743
1744 static bool
1745 it6505_step_eq_train(struct it6505 *it6505,
1746                      struct it6505_step_train_para *lane_voltage_pre_emphasis)
1747 {
1748         u8 loop_count = 0, i, link_status[DP_LINK_STATUS_SIZE] = { 0 };
1749         u8 lane_level_config[MAX_LANE_COUNT] = { 0 };
1750         const struct drm_dp_aux *aux = &it6505->aux;
1751
1752         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1753                           DP_TRAINING_PATTERN_2);
1754
1755         while (loop_count < 6) {
1756                 loop_count++;
1757
1758                 if (!step_train_lane_voltage_para_set(it6505,
1759                                                       lane_voltage_pre_emphasis,
1760                                                       lane_level_config))
1761                         continue;
1762
1763                 drm_dp_link_train_channel_eq_delay(aux, it6505->dpcd);
1764                 drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
1765
1766                 if (!drm_dp_clock_recovery_ok(link_status, it6505->lane_count))
1767                         goto eq_train_fail;
1768
1769                 if (drm_dp_channel_eq_ok(link_status, it6505->lane_count)) {
1770                         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1771                                           DP_TRAINING_PATTERN_DISABLE);
1772                         it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_EQ_DONE,
1773                                         FORCE_EQ_DONE);
1774                         return true;
1775                 }
1776                 DRM_DEV_DEBUG_DRIVER(&it6505->client->dev, "eq not done");
1777
1778                 for (i = 0; i < it6505->lane_count; i++) {
1779                         lane_voltage_pre_emphasis->voltage_swing[i] =
1780                                 drm_dp_get_adjust_request_voltage(link_status,
1781                                                                   i) >>
1782                                 DP_TRAIN_VOLTAGE_SWING_SHIFT;
1783                         lane_voltage_pre_emphasis->pre_emphasis[i] =
1784                         drm_dp_get_adjust_request_pre_emphasis(link_status,
1785                                                                i) >>
1786                                         DP_TRAIN_PRE_EMPHASIS_SHIFT;
1787
1788                         if (lane_voltage_pre_emphasis->voltage_swing[i] +
1789                                     lane_voltage_pre_emphasis->pre_emphasis[i] >
1790                             MAX_EQ_LEVEL)
1791                                 lane_voltage_pre_emphasis->voltage_swing[i] =
1792                                         0x03 - lane_voltage_pre_emphasis
1793                                                        ->pre_emphasis[i];
1794                 }
1795         }
1796
1797 eq_train_fail:
1798         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1799                           DP_TRAINING_PATTERN_DISABLE);
1800         return false;
1801 }
1802
1803 static bool it6505_link_start_step_train(struct it6505 *it6505)
1804 {
1805         int err;
1806         struct it6505_step_train_para lane_voltage_pre_emphasis = {
1807                 .voltage_swing = { 0 },
1808                 .pre_emphasis = { 0 },
1809         };
1810
1811         DRM_DEV_DEBUG_DRIVER(&it6505->client->dev, "start");
1812         err = it6505_drm_dp_link_configure(it6505);
1813
1814         if (err < 0)
1815                 return false;
1816         if (!it6505_step_cr_train(it6505, &lane_voltage_pre_emphasis))
1817                 return false;
1818         if (!it6505_step_eq_train(it6505, &lane_voltage_pre_emphasis))
1819                 return false;
1820         return true;
1821 }
1822
1823 static bool it6505_get_video_status(struct it6505 *it6505)
1824 {
1825         int reg_0d;
1826
1827         reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
1828
1829         if (reg_0d < 0)
1830                 return false;
1831
1832         return reg_0d & VIDEO_STB;
1833 }
1834
1835 static void it6505_reset_hdcp(struct it6505 *it6505)
1836 {
1837         it6505->hdcp_status = HDCP_AUTH_IDLE;
1838         /* Disable CP_Desired */
1839         it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, 0x00);
1840         it6505_set_bits(it6505, REG_RESET_CTRL, HDCP_RESET, HDCP_RESET);
1841 }
1842
1843 static void it6505_start_hdcp(struct it6505 *it6505)
1844 {
1845         struct device *dev = &it6505->client->dev;
1846
1847         DRM_DEV_DEBUG_DRIVER(dev, "start");
1848         it6505_reset_hdcp(it6505);
1849         queue_delayed_work(system_wq, &it6505->hdcp_work,
1850                            msecs_to_jiffies(2400));
1851 }
1852
1853 static void it6505_stop_hdcp(struct it6505 *it6505)
1854 {
1855         it6505_reset_hdcp(it6505);
1856         cancel_delayed_work(&it6505->hdcp_work);
1857 }
1858
1859 static bool it6505_hdcp_is_ksv_valid(u8 *ksv)
1860 {
1861         int i, ones = 0;
1862
1863         /* KSV has 20 1's and 20 0's */
1864         for (i = 0; i < DRM_HDCP_KSV_LEN; i++)
1865                 ones += hweight8(ksv[i]);
1866         if (ones != 20)
1867                 return false;
1868         return true;
1869 }
1870
1871 static void it6505_hdcp_part1_auth(struct it6505 *it6505)
1872 {
1873         struct device *dev = &it6505->client->dev;
1874         u8 hdcp_bcaps;
1875
1876         it6505_set_bits(it6505, REG_RESET_CTRL, HDCP_RESET, 0x00);
1877         /* Disable CP_Desired */
1878         it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, 0x00);
1879
1880         usleep_range(1000, 1500);
1881         hdcp_bcaps = it6505_dpcd_read(it6505, DP_AUX_HDCP_BCAPS);
1882         DRM_DEV_DEBUG_DRIVER(dev, "DPCD[0x68028]: 0x%02x",
1883                              hdcp_bcaps);
1884
1885         if (!hdcp_bcaps)
1886                 return;
1887
1888         /* clear the repeater List Chk Done and fail bit */
1889         it6505_set_bits(it6505, REG_HDCP_TRIGGER,
1890                         HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL,
1891                         0x00);
1892
1893         /* Enable An Generator */
1894         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_AN_GEN, HDCP_AN_GEN);
1895         /* delay1ms(10);*/
1896         usleep_range(10000, 15000);
1897         /* Stop An Generator */
1898         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_AN_GEN, 0x00);
1899
1900         it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, HDCP_CP_ENABLE);
1901
1902         it6505_set_bits(it6505, REG_HDCP_TRIGGER, HDCP_TRIGGER_START,
1903                         HDCP_TRIGGER_START);
1904
1905         it6505->hdcp_status = HDCP_AUTH_GOING;
1906 }
1907
1908 static int it6505_sha1_digest(struct it6505 *it6505, u8 *sha1_input,
1909                               unsigned int size, u8 *output_av)
1910 {
1911         struct shash_desc *desc;
1912         struct crypto_shash *tfm;
1913         int err;
1914         struct device *dev = &it6505->client->dev;
1915
1916         tfm = crypto_alloc_shash("sha1", 0, 0);
1917         if (IS_ERR(tfm)) {
1918                 dev_err(dev, "crypto_alloc_shash sha1 failed");
1919                 return PTR_ERR(tfm);
1920         }
1921         desc = kzalloc(sizeof(*desc) + crypto_shash_descsize(tfm), GFP_KERNEL);
1922         if (!desc) {
1923                 crypto_free_shash(tfm);
1924                 return -ENOMEM;
1925         }
1926
1927         desc->tfm = tfm;
1928         err = crypto_shash_digest(desc, sha1_input, size, output_av);
1929         if (err)
1930                 dev_err(dev, "crypto_shash_digest sha1 failed");
1931
1932         crypto_free_shash(tfm);
1933         kfree(desc);
1934         return err;
1935 }
1936
1937 static int it6505_setup_sha1_input(struct it6505 *it6505, u8 *sha1_input)
1938 {
1939         struct device *dev = &it6505->client->dev;
1940         u8 binfo[2];
1941         int down_stream_count, i, err, msg_count = 0;
1942
1943         err = it6505_get_dpcd(it6505, DP_AUX_HDCP_BINFO, binfo,
1944                               ARRAY_SIZE(binfo));
1945
1946         if (err < 0) {
1947                 dev_err(dev, "Read binfo value Fail");
1948                 return err;
1949         }
1950
1951         down_stream_count = binfo[0] & 0x7F;
1952         DRM_DEV_DEBUG_DRIVER(dev, "binfo:0x%*ph", (int)ARRAY_SIZE(binfo),
1953                              binfo);
1954
1955         if ((binfo[0] & BIT(7)) || (binfo[1] & BIT(3))) {
1956                 dev_err(dev, "HDCP max cascade device exceed");
1957                 return 0;
1958         }
1959
1960         if (!down_stream_count ||
1961             down_stream_count > MAX_HDCP_DOWN_STREAM_COUNT) {
1962                 dev_err(dev, "HDCP down stream count Error %d",
1963                         down_stream_count);
1964                 return 0;
1965         }
1966
1967         for (i = 0; i < down_stream_count; i++) {
1968                 err = it6505_get_dpcd(it6505, DP_AUX_HDCP_KSV_FIFO +
1969                                       (i % 3) * DRM_HDCP_KSV_LEN,
1970                                       sha1_input + msg_count,
1971                                       DRM_HDCP_KSV_LEN);
1972
1973                 if (err < 0)
1974                         return err;
1975
1976                 msg_count += 5;
1977         }
1978
1979         it6505->hdcp_down_stream_count = down_stream_count;
1980         sha1_input[msg_count++] = binfo[0];
1981         sha1_input[msg_count++] = binfo[1];
1982
1983         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_EN_M0_READ,
1984                         HDCP_EN_M0_READ);
1985
1986         err = regmap_bulk_read(it6505->regmap, REG_M0_0_7,
1987                                sha1_input + msg_count, 8);
1988
1989         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_EN_M0_READ, 0x00);
1990
1991         if (err < 0) {
1992                 dev_err(dev, " Warning, Read M value Fail");
1993                 return err;
1994         }
1995
1996         msg_count += 8;
1997
1998         return msg_count;
1999 }
2000
2001 static bool it6505_hdcp_part2_ksvlist_check(struct it6505 *it6505)
2002 {
2003         struct device *dev = &it6505->client->dev;
2004         u8 av[5][4], bv[5][4];
2005         int i, err;
2006
2007         i = it6505_setup_sha1_input(it6505, it6505->sha1_input);
2008         if (i <= 0) {
2009                 dev_err(dev, "SHA-1 Input length error %d", i);
2010                 return false;
2011         }
2012
2013         it6505_sha1_digest(it6505, it6505->sha1_input, i, (u8 *)av);
2014
2015         err = it6505_get_dpcd(it6505, DP_AUX_HDCP_V_PRIME(0), (u8 *)bv,
2016                               sizeof(bv));
2017
2018         if (err < 0) {
2019                 dev_err(dev, "Read V' value Fail");
2020                 return false;
2021         }
2022
2023         for (i = 0; i < 5; i++)
2024                 if (bv[i][3] != av[i][0] || bv[i][2] != av[i][1] ||
2025                     bv[i][1] != av[i][2] || bv[i][0] != av[i][3])
2026                         return false;
2027
2028         DRM_DEV_DEBUG_DRIVER(dev, "V' all match!!");
2029         return true;
2030 }
2031
2032 static void it6505_hdcp_wait_ksv_list(struct work_struct *work)
2033 {
2034         struct it6505 *it6505 = container_of(work, struct it6505,
2035                                              hdcp_wait_ksv_list);
2036         struct device *dev = &it6505->client->dev;
2037         unsigned int timeout = 5000;
2038         u8 bstatus = 0;
2039         bool ksv_list_check;
2040
2041         timeout /= 20;
2042         while (timeout > 0) {
2043                 if (!it6505_get_sink_hpd_status(it6505))
2044                         return;
2045
2046                 bstatus = it6505_dpcd_read(it6505, DP_AUX_HDCP_BSTATUS);
2047
2048                 if (bstatus & DP_BSTATUS_READY)
2049                         break;
2050
2051                 msleep(20);
2052                 timeout--;
2053         }
2054
2055         if (timeout == 0) {
2056                 DRM_DEV_DEBUG_DRIVER(dev, "timeout and ksv list wait failed");
2057                 goto timeout;
2058         }
2059
2060         ksv_list_check = it6505_hdcp_part2_ksvlist_check(it6505);
2061         DRM_DEV_DEBUG_DRIVER(dev, "ksv list ready, ksv list check %s",
2062                              ksv_list_check ? "pass" : "fail");
2063         if (ksv_list_check) {
2064                 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2065                                 HDCP_TRIGGER_KSV_DONE, HDCP_TRIGGER_KSV_DONE);
2066                 return;
2067         }
2068 timeout:
2069         it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2070                         HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL,
2071                         HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL);
2072 }
2073
2074 static void it6505_hdcp_work(struct work_struct *work)
2075 {
2076         struct it6505 *it6505 = container_of(work, struct it6505,
2077                                              hdcp_work.work);
2078         struct device *dev = &it6505->client->dev;
2079         int ret;
2080         u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };
2081
2082         DRM_DEV_DEBUG_DRIVER(dev, "start");
2083
2084         if (!it6505_get_sink_hpd_status(it6505))
2085                 return;
2086
2087         ret = drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
2088         DRM_DEV_DEBUG_DRIVER(dev, "ret: %d link_status: %*ph", ret,
2089                              (int)sizeof(link_status), link_status);
2090
2091         if (ret < 0 || !drm_dp_channel_eq_ok(link_status, it6505->lane_count) ||
2092             !it6505_get_video_status(it6505)) {
2093                 DRM_DEV_DEBUG_DRIVER(dev, "link train not done or no video");
2094                 return;
2095         }
2096
2097         ret = it6505_get_dpcd(it6505, DP_AUX_HDCP_BKSV, it6505->bksvs,
2098                               ARRAY_SIZE(it6505->bksvs));
2099         if (ret < 0) {
2100                 dev_err(dev, "fail to get bksv  ret: %d", ret);
2101                 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2102                                 HDCP_TRIGGER_KSV_FAIL, HDCP_TRIGGER_KSV_FAIL);
2103         }
2104
2105         DRM_DEV_DEBUG_DRIVER(dev, "bksv = 0x%*ph",
2106                              (int)ARRAY_SIZE(it6505->bksvs), it6505->bksvs);
2107
2108         if (!it6505_hdcp_is_ksv_valid(it6505->bksvs)) {
2109                 dev_err(dev, "Display Port bksv not valid");
2110                 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2111                                 HDCP_TRIGGER_KSV_FAIL, HDCP_TRIGGER_KSV_FAIL);
2112         }
2113
2114         it6505_hdcp_part1_auth(it6505);
2115 }
2116
2117 static void it6505_show_hdcp_info(struct it6505 *it6505)
2118 {
2119         struct device *dev = &it6505->client->dev;
2120         int i;
2121         u8 *sha1 = it6505->sha1_input;
2122
2123         DRM_DEV_DEBUG_DRIVER(dev, "hdcp_status: %d is_repeater: %d",
2124                              it6505->hdcp_status, it6505->is_repeater);
2125         DRM_DEV_DEBUG_DRIVER(dev, "bksv = 0x%*ph",
2126                              (int)ARRAY_SIZE(it6505->bksvs), it6505->bksvs);
2127
2128         if (it6505->is_repeater) {
2129                 DRM_DEV_DEBUG_DRIVER(dev, "hdcp_down_stream_count: %d",
2130                                      it6505->hdcp_down_stream_count);
2131                 DRM_DEV_DEBUG_DRIVER(dev, "sha1_input: 0x%*ph",
2132                                      (int)ARRAY_SIZE(it6505->sha1_input),
2133                                      it6505->sha1_input);
2134                 for (i = 0; i < it6505->hdcp_down_stream_count; i++) {
2135                         DRM_DEV_DEBUG_DRIVER(dev, "KSV_%d = 0x%*ph", i,
2136                                              DRM_HDCP_KSV_LEN, sha1);
2137                         sha1 += DRM_HDCP_KSV_LEN;
2138                 }
2139                 DRM_DEV_DEBUG_DRIVER(dev, "binfo: 0x%2ph M0: 0x%8ph",
2140                                      sha1, sha1 + 2);
2141         }
2142 }
2143
2144 static void it6505_stop_link_train(struct it6505 *it6505)
2145 {
2146         it6505->link_state = LINK_IDLE;
2147         cancel_work_sync(&it6505->link_works);
2148         it6505_write(it6505, REG_TRAIN_CTRL1, FORCE_RETRAIN);
2149 }
2150
2151 static void it6505_link_train_ok(struct it6505 *it6505)
2152 {
2153         struct device *dev = &it6505->client->dev;
2154
2155         it6505->link_state = LINK_OK;
2156         /* disalbe mute enable avi info frame */
2157         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, 0x00);
2158         it6505_set_bits(it6505, REG_INFOFRAME_CTRL,
2159                         EN_VID_CTRL_PKT, EN_VID_CTRL_PKT);
2160
2161         if (it6505_audio_input(it6505)) {
2162                 DRM_DEV_DEBUG_DRIVER(dev, "Enable audio!");
2163                 it6505_enable_audio(it6505);
2164         }
2165
2166         if (it6505->hdcp_desired)
2167                 it6505_start_hdcp(it6505);
2168 }
2169
2170 static void it6505_link_step_train_process(struct it6505 *it6505)
2171 {
2172         struct device *dev = &it6505->client->dev;
2173         int ret, i, step_retry = 3;
2174
2175         DRM_DEV_DEBUG_DRIVER(dev, "Start step train");
2176
2177         if (it6505->sink_count == 0) {
2178                 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d, force eq",
2179                                      it6505->sink_count);
2180                 it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_EQ_DONE,
2181                                 FORCE_EQ_DONE);
2182                 return;
2183         }
2184
2185         if (!it6505->step_train) {
2186                 DRM_DEV_DEBUG_DRIVER(dev, "not support step train");
2187                 return;
2188         }
2189
2190         /* step training start here */
2191         for (i = 0; i < step_retry; i++) {
2192                 it6505_link_reset_step_train(it6505);
2193                 ret = it6505_link_start_step_train(it6505);
2194                 DRM_DEV_DEBUG_DRIVER(dev, "step train %s, retry:%d times",
2195                                      ret ? "pass" : "failed", i + 1);
2196                 if (ret) {
2197                         it6505_link_train_ok(it6505);
2198                         return;
2199                 }
2200         }
2201
2202         DRM_DEV_DEBUG_DRIVER(dev, "training fail");
2203         it6505->link_state = LINK_IDLE;
2204         it6505_video_reset(it6505);
2205 }
2206
2207 static void it6505_link_training_work(struct work_struct *work)
2208 {
2209         struct it6505 *it6505 = container_of(work, struct it6505, link_works);
2210         struct device *dev = &it6505->client->dev;
2211         int ret;
2212
2213         DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count: %d",
2214                              it6505->sink_count);
2215
2216         if (!it6505_get_sink_hpd_status(it6505))
2217                 return;
2218
2219         it6505_link_training_setup(it6505);
2220         it6505_reset_hdcp(it6505);
2221         it6505_aux_reset(it6505);
2222
2223         if (it6505->auto_train_retry < 1) {
2224                 it6505_link_step_train_process(it6505);
2225                 return;
2226         }
2227
2228         ret = it6505_link_start_auto_train(it6505);
2229         DRM_DEV_DEBUG_DRIVER(dev, "auto train %s, auto_train_retry: %d",
2230                              ret ? "pass" : "failed", it6505->auto_train_retry);
2231         it6505->auto_train_retry--;
2232
2233         if (ret) {
2234                 it6505_link_train_ok(it6505);
2235                 return;
2236         }
2237
2238         it6505_dump(it6505);
2239 }
2240
2241 static void it6505_plugged_status_to_codec(struct it6505 *it6505)
2242 {
2243         enum drm_connector_status status = it6505->connector_status;
2244
2245         if (it6505->plugged_cb && it6505->codec_dev)
2246                 it6505->plugged_cb(it6505->codec_dev,
2247                                    status == connector_status_connected);
2248 }
2249
2250 static void it6505_remove_edid(struct it6505 *it6505)
2251 {
2252         kfree(it6505->cached_edid);
2253         it6505->cached_edid = NULL;
2254 }
2255
2256 static int it6505_process_hpd_irq(struct it6505 *it6505)
2257 {
2258         struct device *dev = &it6505->client->dev;
2259         int ret, dpcd_sink_count, dp_irq_vector, bstatus;
2260         u8 link_status[DP_LINK_STATUS_SIZE];
2261
2262         if (!it6505_get_sink_hpd_status(it6505)) {
2263                 DRM_DEV_DEBUG_DRIVER(dev, "HPD_IRQ HPD low");
2264                 it6505->sink_count = 0;
2265                 return 0;
2266         }
2267
2268         ret = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2269         if (ret < 0)
2270                 return ret;
2271
2272         dpcd_sink_count = DP_GET_SINK_COUNT(ret);
2273         DRM_DEV_DEBUG_DRIVER(dev, "dpcd_sink_count: %d it6505->sink_count:%d",
2274                              dpcd_sink_count, it6505->sink_count);
2275
2276         if (it6505->branch_device && dpcd_sink_count != it6505->sink_count) {
2277                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2278                 it6505->sink_count = dpcd_sink_count;
2279                 it6505_reset_logic(it6505);
2280                 it6505_int_mask_enable(it6505);
2281                 it6505_init(it6505);
2282                 it6505_remove_edid(it6505);
2283                 return 0;
2284         }
2285
2286         dp_irq_vector = it6505_dpcd_read(it6505, DP_DEVICE_SERVICE_IRQ_VECTOR);
2287         if (dp_irq_vector < 0)
2288                 return dp_irq_vector;
2289
2290         DRM_DEV_DEBUG_DRIVER(dev, "dp_irq_vector = 0x%02x", dp_irq_vector);
2291
2292         if (dp_irq_vector & DP_CP_IRQ) {
2293                 it6505_set_bits(it6505, REG_HDCP_TRIGGER, HDCP_TRIGGER_CPIRQ,
2294                                 HDCP_TRIGGER_CPIRQ);
2295
2296                 bstatus = it6505_dpcd_read(it6505, DP_AUX_HDCP_BSTATUS);
2297                 if (bstatus < 0)
2298                         return bstatus;
2299
2300                 DRM_DEV_DEBUG_DRIVER(dev, "Bstatus = 0x%02x", bstatus);
2301         }
2302
2303         ret = drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
2304         if (ret < 0) {
2305                 dev_err(dev, "Fail to read link status ret: %d", ret);
2306                 return ret;
2307         }
2308
2309         DRM_DEV_DEBUG_DRIVER(dev, "link status = 0x%*ph",
2310                              (int)ARRAY_SIZE(link_status), link_status);
2311
2312         if (!drm_dp_channel_eq_ok(link_status, it6505->lane_count)) {
2313                 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2314                 it6505_video_reset(it6505);
2315         }
2316
2317         return 0;
2318 }
2319
2320 static void it6505_irq_hpd(struct it6505 *it6505)
2321 {
2322         struct device *dev = &it6505->client->dev;
2323         int dp_sink_count;
2324
2325         it6505->hpd_state = it6505_get_sink_hpd_status(it6505);
2326         DRM_DEV_DEBUG_DRIVER(dev, "hpd change interrupt, change to %s",
2327                              it6505->hpd_state ? "high" : "low");
2328
2329         if (it6505->hpd_state) {
2330                 wait_for_completion_timeout(&it6505->extcon_completion,
2331                                             msecs_to_jiffies(1000));
2332                 it6505_aux_on(it6505);
2333                 if (it6505->dpcd[0] == 0) {
2334                         it6505_get_dpcd(it6505, DP_DPCD_REV, it6505->dpcd,
2335                                         ARRAY_SIZE(it6505->dpcd));
2336                         it6505_variable_config(it6505);
2337                         it6505_parse_link_capabilities(it6505);
2338                 }
2339                 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2340
2341                 it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2342                                              DP_SET_POWER_D0);
2343                 dp_sink_count = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2344                 it6505->sink_count = DP_GET_SINK_COUNT(dp_sink_count);
2345
2346                 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count: %d",
2347                                      it6505->sink_count);
2348
2349                 it6505_lane_termination_on(it6505);
2350                 it6505_lane_power_on(it6505);
2351
2352                 /*
2353                  * for some dongle which issue HPD_irq
2354                  * when sink count change from  0->1
2355                  * it6505 not able to receive HPD_IRQ
2356                  * if HW never go into trainig done
2357                  */
2358
2359                 if (it6505->branch_device && it6505->sink_count == 0)
2360                         schedule_work(&it6505->link_works);
2361
2362                 if (!it6505_get_video_status(it6505))
2363                         it6505_video_reset(it6505);
2364         } else {
2365                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2366                 it6505_remove_edid(it6505);
2367
2368                 if (it6505->hdcp_desired)
2369                         it6505_stop_hdcp(it6505);
2370
2371                 it6505_video_disable(it6505);
2372                 it6505_disable_audio(it6505);
2373                 it6505_stop_link_train(it6505);
2374                 it6505_lane_off(it6505);
2375                 it6505_link_reset_step_train(it6505);
2376         }
2377
2378         if (it6505->bridge.dev)
2379                 drm_helper_hpd_irq_event(it6505->bridge.dev);
2380 }
2381
2382 static void it6505_irq_hpd_irq(struct it6505 *it6505)
2383 {
2384         struct device *dev = &it6505->client->dev;
2385
2386         DRM_DEV_DEBUG_DRIVER(dev, "hpd_irq interrupt");
2387
2388         if (it6505_process_hpd_irq(it6505) < 0)
2389                 DRM_DEV_DEBUG_DRIVER(dev, "process hpd_irq fail!");
2390 }
2391
2392 static void it6505_irq_scdt(struct it6505 *it6505)
2393 {
2394         struct device *dev = &it6505->client->dev;
2395         bool data;
2396
2397         data = it6505_get_video_status(it6505);
2398         DRM_DEV_DEBUG_DRIVER(dev, "video stable change interrupt, %s",
2399                              data ? "stable" : "unstable");
2400         it6505_calc_video_info(it6505);
2401         it6505_link_reset_step_train(it6505);
2402
2403         if (data)
2404                 schedule_work(&it6505->link_works);
2405 }
2406
2407 static void it6505_irq_hdcp_done(struct it6505 *it6505)
2408 {
2409         struct device *dev = &it6505->client->dev;
2410
2411         DRM_DEV_DEBUG_DRIVER(dev, "hdcp done interrupt");
2412         it6505->hdcp_status = HDCP_AUTH_DONE;
2413         it6505_show_hdcp_info(it6505);
2414 }
2415
2416 static void it6505_irq_hdcp_fail(struct it6505 *it6505)
2417 {
2418         struct device *dev = &it6505->client->dev;
2419
2420         DRM_DEV_DEBUG_DRIVER(dev, "hdcp fail interrupt");
2421         it6505->hdcp_status = HDCP_AUTH_IDLE;
2422         it6505_show_hdcp_info(it6505);
2423         it6505_start_hdcp(it6505);
2424 }
2425
2426 static void it6505_irq_aux_cmd_fail(struct it6505 *it6505)
2427 {
2428         struct device *dev = &it6505->client->dev;
2429
2430         DRM_DEV_DEBUG_DRIVER(dev, "AUX PC Request Fail Interrupt");
2431 }
2432
2433 static void it6505_irq_hdcp_ksv_check(struct it6505 *it6505)
2434 {
2435         struct device *dev = &it6505->client->dev;
2436
2437         DRM_DEV_DEBUG_DRIVER(dev, "HDCP event Interrupt");
2438         schedule_work(&it6505->hdcp_wait_ksv_list);
2439 }
2440
2441 static void it6505_irq_audio_fifo_error(struct it6505 *it6505)
2442 {
2443         struct device *dev = &it6505->client->dev;
2444
2445         DRM_DEV_DEBUG_DRIVER(dev, "audio fifo error Interrupt");
2446
2447         if (it6505_audio_input(it6505))
2448                 it6505_enable_audio(it6505);
2449 }
2450
2451 static void it6505_irq_link_train_fail(struct it6505 *it6505)
2452 {
2453         struct device *dev = &it6505->client->dev;
2454
2455         DRM_DEV_DEBUG_DRIVER(dev, "link training fail interrupt");
2456         schedule_work(&it6505->link_works);
2457 }
2458
2459 static void it6505_irq_video_fifo_error(struct it6505 *it6505)
2460 {
2461         struct device *dev = &it6505->client->dev;
2462
2463         DRM_DEV_DEBUG_DRIVER(dev, "video fifo overflow interrupt");
2464         it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2465         flush_work(&it6505->link_works);
2466         it6505_stop_hdcp(it6505);
2467         it6505_video_reset(it6505);
2468 }
2469
2470 static void it6505_irq_io_latch_fifo_overflow(struct it6505 *it6505)
2471 {
2472         struct device *dev = &it6505->client->dev;
2473
2474         DRM_DEV_DEBUG_DRIVER(dev, "IO latch fifo overflow interrupt");
2475         it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2476         flush_work(&it6505->link_works);
2477         it6505_stop_hdcp(it6505);
2478         it6505_video_reset(it6505);
2479 }
2480
2481 static bool it6505_test_bit(unsigned int bit, const unsigned int *addr)
2482 {
2483         return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE));
2484 }
2485
2486 static irqreturn_t it6505_int_threaded_handler(int unused, void *data)
2487 {
2488         struct it6505 *it6505 = data;
2489         struct device *dev = &it6505->client->dev;
2490         static const struct {
2491                 int bit;
2492                 void (*handler)(struct it6505 *it6505);
2493         } irq_vec[] = {
2494                 { BIT_INT_HPD, it6505_irq_hpd },
2495                 { BIT_INT_HPD_IRQ, it6505_irq_hpd_irq },
2496                 { BIT_INT_SCDT, it6505_irq_scdt },
2497                 { BIT_INT_HDCP_FAIL, it6505_irq_hdcp_fail },
2498                 { BIT_INT_HDCP_DONE, it6505_irq_hdcp_done },
2499                 { BIT_INT_AUX_CMD_FAIL, it6505_irq_aux_cmd_fail },
2500                 { BIT_INT_HDCP_KSV_CHECK, it6505_irq_hdcp_ksv_check },
2501                 { BIT_INT_AUDIO_FIFO_ERROR, it6505_irq_audio_fifo_error },
2502                 { BIT_INT_LINK_TRAIN_FAIL, it6505_irq_link_train_fail },
2503                 { BIT_INT_VID_FIFO_ERROR, it6505_irq_video_fifo_error },
2504                 { BIT_INT_IO_FIFO_OVERFLOW, it6505_irq_io_latch_fifo_overflow },
2505         };
2506         int int_status[3], i;
2507
2508         if (it6505->enable_drv_hold || pm_runtime_get_if_in_use(dev) <= 0)
2509                 return IRQ_HANDLED;
2510
2511         int_status[0] = it6505_read(it6505, INT_STATUS_01);
2512         int_status[1] = it6505_read(it6505, INT_STATUS_02);
2513         int_status[2] = it6505_read(it6505, INT_STATUS_03);
2514
2515         it6505_write(it6505, INT_STATUS_01, int_status[0]);
2516         it6505_write(it6505, INT_STATUS_02, int_status[1]);
2517         it6505_write(it6505, INT_STATUS_03, int_status[2]);
2518
2519         DRM_DEV_DEBUG_DRIVER(dev, "reg06 = 0x%02x", int_status[0]);
2520         DRM_DEV_DEBUG_DRIVER(dev, "reg07 = 0x%02x", int_status[1]);
2521         DRM_DEV_DEBUG_DRIVER(dev, "reg08 = 0x%02x", int_status[2]);
2522         it6505_debug_print(it6505, REG_SYSTEM_STS, "");
2523
2524         if (it6505_test_bit(irq_vec[0].bit, (unsigned int *)int_status))
2525                 irq_vec[0].handler(it6505);
2526
2527         if (it6505->hpd_state) {
2528                 for (i = 1; i < ARRAY_SIZE(irq_vec); i++) {
2529                         if (it6505_test_bit(irq_vec[i].bit, (unsigned int *)int_status))
2530                                 irq_vec[i].handler(it6505);
2531                 }
2532         }
2533
2534         pm_runtime_put_sync(dev);
2535
2536         return IRQ_HANDLED;
2537 }
2538
2539 static int it6505_poweron(struct it6505 *it6505)
2540 {
2541         struct device *dev = &it6505->client->dev;
2542         struct it6505_platform_data *pdata = &it6505->pdata;
2543         int err;
2544
2545         DRM_DEV_DEBUG_DRIVER(dev, "it6505 start powered on");
2546
2547         if (it6505->powered) {
2548                 DRM_DEV_DEBUG_DRIVER(dev, "it6505 already powered on");
2549                 return 0;
2550         }
2551
2552         if (pdata->pwr18) {
2553                 err = regulator_enable(pdata->pwr18);
2554                 if (err) {
2555                         DRM_DEV_DEBUG_DRIVER(dev, "Failed to enable VDD18: %d",
2556                                              err);
2557                         return err;
2558                 }
2559         }
2560
2561         if (pdata->ovdd) {
2562                 /* time interval between IVDD and OVDD at least be 1ms */
2563                 usleep_range(1000, 2000);
2564                 err = regulator_enable(pdata->ovdd);
2565                 if (err) {
2566                         regulator_disable(pdata->pwr18);
2567                         return err;
2568                 }
2569         }
2570         /* time interval between OVDD and SYSRSTN at least be 10ms */
2571         if (pdata->gpiod_reset) {
2572                 usleep_range(10000, 20000);
2573                 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
2574                 usleep_range(1000, 2000);
2575                 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
2576                 usleep_range(10000, 20000);
2577         }
2578
2579         it6505->powered = true;
2580         it6505_reset_logic(it6505);
2581         it6505_int_mask_enable(it6505);
2582         it6505_init(it6505);
2583         it6505_lane_off(it6505);
2584
2585         return 0;
2586 }
2587
2588 static int it6505_poweroff(struct it6505 *it6505)
2589 {
2590         struct device *dev = &it6505->client->dev;
2591         struct it6505_platform_data *pdata = &it6505->pdata;
2592         int err;
2593
2594         DRM_DEV_DEBUG_DRIVER(dev, "it6505 start power off");
2595
2596         if (!it6505->powered) {
2597                 DRM_DEV_DEBUG_DRIVER(dev, "power had been already off");
2598                 return 0;
2599         }
2600
2601         if (pdata->gpiod_reset)
2602                 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
2603
2604         if (pdata->pwr18) {
2605                 err = regulator_disable(pdata->pwr18);
2606                 if (err)
2607                         return err;
2608         }
2609
2610         if (pdata->ovdd) {
2611                 err = regulator_disable(pdata->ovdd);
2612                 if (err)
2613                         return err;
2614         }
2615
2616         it6505->powered = false;
2617         it6505->sink_count = 0;
2618
2619         return 0;
2620 }
2621
2622 static enum drm_connector_status it6505_detect(struct it6505 *it6505)
2623 {
2624         struct device *dev = &it6505->client->dev;
2625         enum drm_connector_status status = connector_status_disconnected;
2626         int dp_sink_count;
2627
2628         DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d powered:%d",
2629                              it6505->sink_count, it6505->powered);
2630
2631         mutex_lock(&it6505->mode_lock);
2632
2633         if (!it6505->powered)
2634                 goto unlock;
2635
2636         if (it6505->enable_drv_hold) {
2637                 status = it6505->hpd_state ? connector_status_connected :
2638                                              connector_status_disconnected;
2639                 goto unlock;
2640         }
2641
2642         if (it6505->hpd_state) {
2643                 it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2644                                              DP_SET_POWER_D0);
2645                 dp_sink_count = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2646                 it6505->sink_count = DP_GET_SINK_COUNT(dp_sink_count);
2647                 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d branch:%d",
2648                                      it6505->sink_count, it6505->branch_device);
2649
2650                 if (it6505->branch_device) {
2651                         status = (it6505->sink_count != 0) ?
2652                                  connector_status_connected :
2653                                  connector_status_disconnected;
2654                 } else {
2655                         status = connector_status_connected;
2656                 }
2657         } else {
2658                 it6505->sink_count = 0;
2659                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2660         }
2661
2662 unlock:
2663         if (it6505->connector_status != status) {
2664                 it6505->connector_status = status;
2665                 it6505_plugged_status_to_codec(it6505);
2666         }
2667
2668         mutex_unlock(&it6505->mode_lock);
2669
2670         return status;
2671 }
2672
2673 static int it6505_extcon_notifier(struct notifier_block *self,
2674                                   unsigned long event, void *ptr)
2675 {
2676         struct it6505 *it6505 = container_of(self, struct it6505, event_nb);
2677
2678         schedule_work(&it6505->extcon_wq);
2679         return NOTIFY_DONE;
2680 }
2681
2682 static void it6505_extcon_work(struct work_struct *work)
2683 {
2684         struct it6505 *it6505 = container_of(work, struct it6505, extcon_wq);
2685         struct device *dev = &it6505->client->dev;
2686         int state, ret;
2687
2688         if (it6505->enable_drv_hold)
2689                 return;
2690
2691         mutex_lock(&it6505->extcon_lock);
2692
2693         state = extcon_get_state(it6505->extcon, EXTCON_DISP_DP);
2694         DRM_DEV_DEBUG_DRIVER(dev, "EXTCON_DISP_DP = 0x%02x", state);
2695
2696         if (state == it6505->extcon_state || unlikely(state < 0))
2697                 goto unlock;
2698         it6505->extcon_state = state;
2699         if (state) {
2700                 DRM_DEV_DEBUG_DRIVER(dev, "start to power on");
2701                 msleep(100);
2702                 ret = pm_runtime_get_sync(dev);
2703
2704                 /*
2705                  * On system resume, extcon_work can be triggered before
2706                  * pm_runtime_force_resume re-enables runtime power management.
2707                  * Handling the error here to make sure the bridge is powered on.
2708                  */
2709                 if (ret < 0)
2710                         it6505_poweron(it6505);
2711
2712                 complete_all(&it6505->extcon_completion);
2713         } else {
2714                 DRM_DEV_DEBUG_DRIVER(dev, "start to power off");
2715                 pm_runtime_put_sync(dev);
2716                 reinit_completion(&it6505->extcon_completion);
2717
2718                 drm_helper_hpd_irq_event(it6505->bridge.dev);
2719                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2720                 DRM_DEV_DEBUG_DRIVER(dev, "power off it6505 success!");
2721         }
2722
2723 unlock:
2724         mutex_unlock(&it6505->extcon_lock);
2725 }
2726
2727 static int it6505_use_notifier_module(struct it6505 *it6505)
2728 {
2729         int ret;
2730         struct device *dev = &it6505->client->dev;
2731
2732         it6505->event_nb.notifier_call = it6505_extcon_notifier;
2733         INIT_WORK(&it6505->extcon_wq, it6505_extcon_work);
2734         ret = devm_extcon_register_notifier(&it6505->client->dev,
2735                                             it6505->extcon, EXTCON_DISP_DP,
2736                                             &it6505->event_nb);
2737         if (ret) {
2738                 dev_err(dev, "failed to register notifier for DP");
2739                 return ret;
2740         }
2741
2742         schedule_work(&it6505->extcon_wq);
2743
2744         return 0;
2745 }
2746
2747 static void it6505_remove_notifier_module(struct it6505 *it6505)
2748 {
2749         if (it6505->extcon) {
2750                 devm_extcon_unregister_notifier(&it6505->client->dev,
2751                                                 it6505->extcon, EXTCON_DISP_DP,
2752                                                 &it6505->event_nb);
2753
2754                 flush_work(&it6505->extcon_wq);
2755         }
2756 }
2757
2758 static void __maybe_unused it6505_delayed_audio(struct work_struct *work)
2759 {
2760         struct it6505 *it6505 = container_of(work, struct it6505,
2761                                              delayed_audio.work);
2762
2763         DRM_DEV_DEBUG_DRIVER(&it6505->client->dev, "start");
2764
2765         if (!it6505->powered)
2766                 return;
2767
2768         if (!it6505->enable_drv_hold)
2769                 it6505_enable_audio(it6505);
2770 }
2771
2772 static int __maybe_unused it6505_audio_setup_hw_params(struct it6505 *it6505,
2773                                                        struct hdmi_codec_params
2774                                                        *params)
2775 {
2776         struct device *dev = &it6505->client->dev;
2777         int i = 0;
2778
2779         DRM_DEV_DEBUG_DRIVER(dev, "%s %d Hz, %d bit, %d channels\n", __func__,
2780                              params->sample_rate, params->sample_width,
2781                              params->cea.channels);
2782
2783         if (!it6505->bridge.encoder)
2784                 return -ENODEV;
2785
2786         if (params->cea.channels <= 1 || params->cea.channels > 8) {
2787                 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support",
2788                                      it6505->audio.channel_count);
2789                 return -EINVAL;
2790         }
2791
2792         it6505->audio.channel_count = params->cea.channels;
2793
2794         while (i < ARRAY_SIZE(audio_sample_rate_map) &&
2795                params->sample_rate !=
2796                        audio_sample_rate_map[i].sample_rate_value) {
2797                 i++;
2798         }
2799         if (i == ARRAY_SIZE(audio_sample_rate_map)) {
2800                 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d Hz not support",
2801                                      params->sample_rate);
2802                 return -EINVAL;
2803         }
2804         it6505->audio.sample_rate = audio_sample_rate_map[i].rate;
2805
2806         switch (params->sample_width) {
2807         case 16:
2808                 it6505->audio.word_length = WORD_LENGTH_16BIT;
2809                 break;
2810         case 18:
2811                 it6505->audio.word_length = WORD_LENGTH_18BIT;
2812                 break;
2813         case 20:
2814                 it6505->audio.word_length = WORD_LENGTH_20BIT;
2815                 break;
2816         case 24:
2817         case 32:
2818                 it6505->audio.word_length = WORD_LENGTH_24BIT;
2819                 break;
2820         default:
2821                 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support",
2822                                      params->sample_width);
2823                 return -EINVAL;
2824         }
2825
2826         return 0;
2827 }
2828
2829 static void __maybe_unused it6505_audio_shutdown(struct device *dev, void *data)
2830 {
2831         struct it6505 *it6505 = dev_get_drvdata(dev);
2832
2833         if (it6505->powered)
2834                 it6505_disable_audio(it6505);
2835 }
2836
2837 static int __maybe_unused it6505_audio_hook_plugged_cb(struct device *dev,
2838                                                        void *data,
2839                                                        hdmi_codec_plugged_cb fn,
2840                                                        struct device *codec_dev)
2841 {
2842         struct it6505 *it6505 = data;
2843
2844         it6505->plugged_cb = fn;
2845         it6505->codec_dev = codec_dev;
2846         it6505_plugged_status_to_codec(it6505);
2847
2848         return 0;
2849 }
2850
2851 static inline struct it6505 *bridge_to_it6505(struct drm_bridge *bridge)
2852 {
2853         return container_of(bridge, struct it6505, bridge);
2854 }
2855
2856 static int it6505_bridge_attach(struct drm_bridge *bridge,
2857                                 enum drm_bridge_attach_flags flags)
2858 {
2859         struct it6505 *it6505 = bridge_to_it6505(bridge);
2860         struct device *dev = &it6505->client->dev;
2861         int ret;
2862
2863         if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
2864                 DRM_ERROR("DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied");
2865                 return -EINVAL;
2866         }
2867
2868         if (!bridge->encoder) {
2869                 dev_err(dev, "Parent encoder object not found");
2870                 return -ENODEV;
2871         }
2872
2873         /* Register aux channel */
2874         it6505->aux.drm_dev = bridge->dev;
2875
2876         ret = drm_dp_aux_register(&it6505->aux);
2877
2878         if (ret < 0) {
2879                 dev_err(dev, "Failed to register aux: %d", ret);
2880                 return ret;
2881         }
2882
2883         if (it6505->extcon) {
2884                 ret = it6505_use_notifier_module(it6505);
2885                 if (ret < 0) {
2886                         dev_err(dev, "use notifier module failed");
2887                         return ret;
2888                 }
2889         }
2890
2891         return 0;
2892 }
2893
2894 static void it6505_bridge_detach(struct drm_bridge *bridge)
2895 {
2896         struct it6505 *it6505 = bridge_to_it6505(bridge);
2897
2898         flush_work(&it6505->link_works);
2899         it6505_remove_notifier_module(it6505);
2900 }
2901
2902 static enum drm_mode_status
2903 it6505_bridge_mode_valid(struct drm_bridge *bridge,
2904                          const struct drm_display_info *info,
2905                          const struct drm_display_mode *mode)
2906 {
2907         struct it6505 *it6505 = bridge_to_it6505(bridge);
2908
2909         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2910                 return MODE_NO_INTERLACE;
2911
2912         if (mode->clock > it6505->max_dpi_pixel_clock)
2913                 return MODE_CLOCK_HIGH;
2914
2915         it6505->video_info.clock = mode->clock;
2916
2917         return MODE_OK;
2918 }
2919
2920 static void it6505_bridge_atomic_enable(struct drm_bridge *bridge,
2921                                         struct drm_bridge_state *old_state)
2922 {
2923         struct it6505 *it6505 = bridge_to_it6505(bridge);
2924         struct device *dev = &it6505->client->dev;
2925         struct drm_atomic_state *state = old_state->base.state;
2926         struct hdmi_avi_infoframe frame;
2927         struct drm_crtc_state *crtc_state;
2928         struct drm_connector_state *conn_state;
2929         struct drm_display_mode *mode;
2930         struct drm_connector *connector;
2931         int ret;
2932
2933         DRM_DEV_DEBUG_DRIVER(dev, "start");
2934
2935         connector = drm_atomic_get_new_connector_for_encoder(state,
2936                                                              bridge->encoder);
2937
2938         if (WARN_ON(!connector))
2939                 return;
2940
2941         conn_state = drm_atomic_get_new_connector_state(state, connector);
2942
2943         if (WARN_ON(!conn_state))
2944                 return;
2945
2946         crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
2947
2948         if (WARN_ON(!crtc_state))
2949                 return;
2950
2951         mode = &crtc_state->adjusted_mode;
2952
2953         if (WARN_ON(!mode))
2954                 return;
2955
2956         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame,
2957                                                        connector,
2958                                                        mode);
2959         if (ret)
2960                 dev_err(dev, "Failed to setup AVI infoframe: %d", ret);
2961
2962         it6505_update_video_parameter(it6505, mode);
2963
2964         ret = it6505_send_video_infoframe(it6505, &frame);
2965
2966         if (ret)
2967                 dev_err(dev, "Failed to send AVI infoframe: %d", ret);
2968
2969         it6505_int_mask_enable(it6505);
2970         it6505_video_reset(it6505);
2971
2972         it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2973                                      DP_SET_POWER_D0);
2974 }
2975
2976 static void it6505_bridge_atomic_disable(struct drm_bridge *bridge,
2977                                          struct drm_bridge_state *old_state)
2978 {
2979         struct it6505 *it6505 = bridge_to_it6505(bridge);
2980         struct device *dev = &it6505->client->dev;
2981
2982         DRM_DEV_DEBUG_DRIVER(dev, "start");
2983
2984         if (it6505->powered) {
2985                 it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2986                                              DP_SET_POWER_D3);
2987                 it6505_video_disable(it6505);
2988         }
2989 }
2990
2991 static void it6505_bridge_atomic_pre_enable(struct drm_bridge *bridge,
2992                                             struct drm_bridge_state *old_state)
2993 {
2994         struct it6505 *it6505 = bridge_to_it6505(bridge);
2995         struct device *dev = &it6505->client->dev;
2996
2997         DRM_DEV_DEBUG_DRIVER(dev, "start");
2998
2999         pm_runtime_get_sync(dev);
3000 }
3001
3002 static void it6505_bridge_atomic_post_disable(struct drm_bridge *bridge,
3003                                               struct drm_bridge_state *old_state)
3004 {
3005         struct it6505 *it6505 = bridge_to_it6505(bridge);
3006         struct device *dev = &it6505->client->dev;
3007
3008         DRM_DEV_DEBUG_DRIVER(dev, "start");
3009
3010         pm_runtime_put_sync(dev);
3011 }
3012
3013 static enum drm_connector_status
3014 it6505_bridge_detect(struct drm_bridge *bridge)
3015 {
3016         struct it6505 *it6505 = bridge_to_it6505(bridge);
3017
3018         return it6505_detect(it6505);
3019 }
3020
3021 static struct edid *it6505_bridge_get_edid(struct drm_bridge *bridge,
3022                                            struct drm_connector *connector)
3023 {
3024         struct it6505 *it6505 = bridge_to_it6505(bridge);
3025         struct device *dev = &it6505->client->dev;
3026
3027         if (!it6505->cached_edid) {
3028                 it6505->cached_edid = drm_do_get_edid(connector, it6505_get_edid_block,
3029                                                       it6505);
3030
3031                 if (!it6505->cached_edid) {
3032                         DRM_DEV_DEBUG_DRIVER(dev, "failed to get edid!");
3033                         return NULL;
3034                 }
3035         }
3036
3037         return drm_edid_duplicate(it6505->cached_edid);
3038 }
3039
3040 static const struct drm_bridge_funcs it6505_bridge_funcs = {
3041         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
3042         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
3043         .atomic_reset = drm_atomic_helper_bridge_reset,
3044         .attach = it6505_bridge_attach,
3045         .detach = it6505_bridge_detach,
3046         .mode_valid = it6505_bridge_mode_valid,
3047         .atomic_enable = it6505_bridge_atomic_enable,
3048         .atomic_disable = it6505_bridge_atomic_disable,
3049         .atomic_pre_enable = it6505_bridge_atomic_pre_enable,
3050         .atomic_post_disable = it6505_bridge_atomic_post_disable,
3051         .detect = it6505_bridge_detect,
3052         .get_edid = it6505_bridge_get_edid,
3053 };
3054
3055 static __maybe_unused int it6505_bridge_resume(struct device *dev)
3056 {
3057         struct it6505 *it6505 = dev_get_drvdata(dev);
3058
3059         return it6505_poweron(it6505);
3060 }
3061
3062 static __maybe_unused int it6505_bridge_suspend(struct device *dev)
3063 {
3064         struct it6505 *it6505 = dev_get_drvdata(dev);
3065
3066         return it6505_poweroff(it6505);
3067 }
3068
3069 static const struct dev_pm_ops it6505_bridge_pm_ops = {
3070         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
3071         SET_RUNTIME_PM_OPS(it6505_bridge_suspend, it6505_bridge_resume, NULL)
3072 };
3073
3074 static int it6505_init_pdata(struct it6505 *it6505)
3075 {
3076         struct it6505_platform_data *pdata = &it6505->pdata;
3077         struct device *dev = &it6505->client->dev;
3078
3079         /* 1.0V digital core power regulator  */
3080         pdata->pwr18 = devm_regulator_get(dev, "pwr18");
3081         if (IS_ERR(pdata->pwr18)) {
3082                 dev_err(dev, "pwr18 regulator not found");
3083                 return PTR_ERR(pdata->pwr18);
3084         }
3085
3086         pdata->ovdd = devm_regulator_get(dev, "ovdd");
3087         if (IS_ERR(pdata->ovdd)) {
3088                 dev_err(dev, "ovdd regulator not found");
3089                 return PTR_ERR(pdata->ovdd);
3090         }
3091
3092         pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
3093         if (IS_ERR(pdata->gpiod_reset)) {
3094                 dev_err(dev, "gpiod_reset gpio not found");
3095                 return PTR_ERR(pdata->gpiod_reset);
3096         }
3097
3098         return 0;
3099 }
3100
3101 static int it6505_get_data_lanes_count(const struct device_node *endpoint,
3102                                        const unsigned int min,
3103                                        const unsigned int max)
3104 {
3105         int ret;
3106
3107         ret = of_property_count_u32_elems(endpoint, "data-lanes");
3108         if (ret < 0)
3109                 return ret;
3110
3111         if (ret < min || ret > max)
3112                 return -EINVAL;
3113
3114         return ret;
3115 }
3116
3117 static void it6505_parse_dt(struct it6505 *it6505)
3118 {
3119         struct device *dev = &it6505->client->dev;
3120         struct device_node *np = dev->of_node, *ep = NULL;
3121         int len;
3122         u64 link_frequencies;
3123         u32 data_lanes[4];
3124         u32 *afe_setting = &it6505->afe_setting;
3125         u32 *max_lane_count = &it6505->max_lane_count;
3126         u32 *max_dpi_pixel_clock = &it6505->max_dpi_pixel_clock;
3127
3128         it6505->lane_swap_disabled =
3129                 device_property_read_bool(dev, "no-laneswap");
3130
3131         if (it6505->lane_swap_disabled)
3132                 it6505->lane_swap = false;
3133
3134         if (device_property_read_u32(dev, "afe-setting", afe_setting) == 0) {
3135                 if (*afe_setting >= ARRAY_SIZE(afe_setting_table)) {
3136                         dev_err(dev, "afe setting error, use default");
3137                         *afe_setting = 0;
3138                 }
3139         } else {
3140                 *afe_setting = 0;
3141         }
3142
3143         ep = of_graph_get_endpoint_by_regs(np, 1, 0);
3144         of_node_put(ep);
3145
3146         if (ep) {
3147                 len = it6505_get_data_lanes_count(ep, 1, 4);
3148
3149                 if (len > 0 && len != 3) {
3150                         of_property_read_u32_array(ep, "data-lanes",
3151                                                    data_lanes, len);
3152                         *max_lane_count = len;
3153                 } else {
3154                         *max_lane_count = MAX_LANE_COUNT;
3155                         dev_err(dev, "error data-lanes, use default");
3156                 }
3157         } else {
3158                 *max_lane_count = MAX_LANE_COUNT;
3159                 dev_err(dev, "error endpoint, use default");
3160         }
3161
3162         ep = of_graph_get_endpoint_by_regs(np, 0, 0);
3163         of_node_put(ep);
3164
3165         if (ep) {
3166                 len = of_property_read_variable_u64_array(ep,
3167                                                           "link-frequencies",
3168                                                           &link_frequencies, 0,
3169                                                           1);
3170                 if (len >= 0) {
3171                         do_div(link_frequencies, 1000);
3172                         if (link_frequencies > 297000) {
3173                                 dev_err(dev,
3174                                         "max pixel clock error, use default");
3175                                 *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
3176                         } else {
3177                                 *max_dpi_pixel_clock = link_frequencies;
3178                         }
3179                 } else {
3180                         dev_err(dev, "error link frequencies, use default");
3181                         *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
3182                 }
3183         } else {
3184                 dev_err(dev, "error endpoint, use default");
3185                 *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
3186         }
3187
3188         DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %u, max_lane_count: %u",
3189                              it6505->afe_setting, it6505->max_lane_count);
3190         DRM_DEV_DEBUG_DRIVER(dev, "using max_dpi_pixel_clock: %u kHz",
3191                              it6505->max_dpi_pixel_clock);
3192 }
3193
3194 static ssize_t receive_timing_debugfs_show(struct file *file, char __user *buf,
3195                                            size_t len, loff_t *ppos)
3196 {
3197         struct it6505 *it6505 = file->private_data;
3198         struct drm_display_mode *vid = &it6505->video_info;
3199         u8 read_buf[READ_BUFFER_SIZE];
3200         u8 *str = read_buf, *end = read_buf + READ_BUFFER_SIZE;
3201         ssize_t ret, count;
3202
3203         if (!it6505)
3204                 return -ENODEV;
3205
3206         it6505_calc_video_info(it6505);
3207         str += scnprintf(str, end - str, "---video timing---\n");
3208         str += scnprintf(str, end - str, "PCLK:%d.%03dMHz\n",
3209                          vid->clock / 1000, vid->clock % 1000);
3210         str += scnprintf(str, end - str, "HTotal:%d\n", vid->htotal);
3211         str += scnprintf(str, end - str, "HActive:%d\n", vid->hdisplay);
3212         str += scnprintf(str, end - str, "HFrontPorch:%d\n",
3213                          vid->hsync_start - vid->hdisplay);
3214         str += scnprintf(str, end - str, "HSyncWidth:%d\n",
3215                          vid->hsync_end - vid->hsync_start);
3216         str += scnprintf(str, end - str, "HBackPorch:%d\n",
3217                          vid->htotal - vid->hsync_end);
3218         str += scnprintf(str, end - str, "VTotal:%d\n", vid->vtotal);
3219         str += scnprintf(str, end - str, "VActive:%d\n", vid->vdisplay);
3220         str += scnprintf(str, end - str, "VFrontPorch:%d\n",
3221                          vid->vsync_start - vid->vdisplay);
3222         str += scnprintf(str, end - str, "VSyncWidth:%d\n",
3223                          vid->vsync_end - vid->vsync_start);
3224         str += scnprintf(str, end - str, "VBackPorch:%d\n",
3225                          vid->vtotal - vid->vsync_end);
3226
3227         count = str - read_buf;
3228         ret = simple_read_from_buffer(buf, len, ppos, read_buf, count);
3229
3230         return ret;
3231 }
3232
3233 static int force_power_on_off_debugfs_write(void *data, u64 value)
3234 {
3235         struct it6505 *it6505 = data;
3236
3237         if (!it6505)
3238                 return -ENODEV;
3239
3240         if (value)
3241                 it6505_poweron(it6505);
3242         else
3243                 it6505_poweroff(it6505);
3244
3245         return 0;
3246 }
3247
3248 static int enable_drv_hold_debugfs_show(void *data, u64 *buf)
3249 {
3250         struct it6505 *it6505 = data;
3251
3252         if (!it6505)
3253                 return -ENODEV;
3254
3255         *buf = it6505->enable_drv_hold;
3256
3257         return 0;
3258 }
3259
3260 static int enable_drv_hold_debugfs_write(void *data, u64 drv_hold)
3261 {
3262         struct it6505 *it6505 = data;
3263
3264         if (!it6505)
3265                 return -ENODEV;
3266
3267         it6505->enable_drv_hold = drv_hold;
3268
3269         if (it6505->enable_drv_hold) {
3270                 it6505_int_mask_disable(it6505);
3271         } else {
3272                 it6505_clear_int(it6505);
3273                 it6505_int_mask_enable(it6505);
3274
3275                 if (it6505->powered) {
3276                         it6505->connector_status =
3277                                         it6505_get_sink_hpd_status(it6505) ?
3278                                         connector_status_connected :
3279                                         connector_status_disconnected;
3280                 } else {
3281                         it6505->connector_status =
3282                                         connector_status_disconnected;
3283                 }
3284         }
3285
3286         return 0;
3287 }
3288
3289 static const struct file_operations receive_timing_fops = {
3290         .owner = THIS_MODULE,
3291         .open = simple_open,
3292         .read = receive_timing_debugfs_show,
3293         .llseek = default_llseek,
3294 };
3295
3296 DEFINE_DEBUGFS_ATTRIBUTE(fops_force_power, NULL,
3297                          force_power_on_off_debugfs_write, "%llu\n");
3298
3299 DEFINE_DEBUGFS_ATTRIBUTE(fops_enable_drv_hold, enable_drv_hold_debugfs_show,
3300                          enable_drv_hold_debugfs_write, "%llu\n");
3301
3302 static const struct debugfs_entries debugfs_entry[] = {
3303         { "receive_timing", &receive_timing_fops },
3304         { "force_power_on_off", &fops_force_power },
3305         { "enable_drv_hold", &fops_enable_drv_hold },
3306         { NULL, NULL },
3307 };
3308
3309 static void debugfs_create_files(struct it6505 *it6505)
3310 {
3311         int i = 0;
3312
3313         while (debugfs_entry[i].name && debugfs_entry[i].fops) {
3314                 debugfs_create_file(debugfs_entry[i].name, 0644,
3315                                     it6505->debugfs, it6505,
3316                                     debugfs_entry[i].fops);
3317                 i++;
3318         }
3319 }
3320
3321 static void debugfs_init(struct it6505 *it6505)
3322 {
3323         struct device *dev = &it6505->client->dev;
3324
3325         it6505->debugfs = debugfs_create_dir(DEBUGFS_DIR_NAME, NULL);
3326
3327         if (IS_ERR(it6505->debugfs)) {
3328                 dev_err(dev, "failed to create debugfs root");
3329                 return;
3330         }
3331
3332         debugfs_create_files(it6505);
3333 }
3334
3335 static void it6505_debugfs_remove(struct it6505 *it6505)
3336 {
3337         debugfs_remove_recursive(it6505->debugfs);
3338 }
3339
3340 static void it6505_shutdown(struct i2c_client *client)
3341 {
3342         struct it6505 *it6505 = dev_get_drvdata(&client->dev);
3343
3344         if (it6505->powered)
3345                 it6505_lane_off(it6505);
3346 }
3347
3348 static int it6505_i2c_probe(struct i2c_client *client)
3349 {
3350         struct it6505 *it6505;
3351         struct device *dev = &client->dev;
3352         struct extcon_dev *extcon;
3353         int err, intp_irq;
3354
3355         it6505 = devm_kzalloc(&client->dev, sizeof(*it6505), GFP_KERNEL);
3356         if (!it6505)
3357                 return -ENOMEM;
3358
3359         mutex_init(&it6505->extcon_lock);
3360         mutex_init(&it6505->mode_lock);
3361         mutex_init(&it6505->aux_lock);
3362
3363         it6505->bridge.of_node = client->dev.of_node;
3364         it6505->connector_status = connector_status_disconnected;
3365         it6505->client = client;
3366         i2c_set_clientdata(client, it6505);
3367
3368         /* get extcon device from DTS */
3369         extcon = extcon_get_edev_by_phandle(dev, 0);
3370         if (PTR_ERR(extcon) == -EPROBE_DEFER)
3371                 return -EPROBE_DEFER;
3372         if (IS_ERR(extcon)) {
3373                 dev_err(dev, "can not get extcon device!");
3374                 return PTR_ERR(extcon);
3375         }
3376
3377         it6505->extcon = extcon;
3378
3379         it6505->regmap = devm_regmap_init_i2c(client, &it6505_regmap_config);
3380         if (IS_ERR(it6505->regmap)) {
3381                 dev_err(dev, "regmap i2c init failed");
3382                 err = PTR_ERR(it6505->regmap);
3383                 return err;
3384         }
3385
3386         err = it6505_init_pdata(it6505);
3387         if (err) {
3388                 dev_err(dev, "Failed to initialize pdata: %d", err);
3389                 return err;
3390         }
3391
3392         it6505_parse_dt(it6505);
3393
3394         intp_irq = client->irq;
3395
3396         if (!intp_irq) {
3397                 dev_err(dev, "Failed to get INTP IRQ");
3398                 err = -ENODEV;
3399                 return err;
3400         }
3401
3402         err = devm_request_threaded_irq(&client->dev, intp_irq, NULL,
3403                                         it6505_int_threaded_handler,
3404                                         IRQF_TRIGGER_LOW | IRQF_ONESHOT,
3405                                         "it6505-intp", it6505);
3406         if (err) {
3407                 dev_err(dev, "Failed to request INTP threaded IRQ: %d", err);
3408                 return err;
3409         }
3410
3411         INIT_WORK(&it6505->link_works, it6505_link_training_work);
3412         INIT_WORK(&it6505->hdcp_wait_ksv_list, it6505_hdcp_wait_ksv_list);
3413         INIT_DELAYED_WORK(&it6505->hdcp_work, it6505_hdcp_work);
3414         init_completion(&it6505->extcon_completion);
3415         memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
3416         it6505->powered = false;
3417         it6505->enable_drv_hold = DEFAULT_DRV_HOLD;
3418
3419         if (DEFAULT_PWR_ON)
3420                 it6505_poweron(it6505);
3421
3422         DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev));
3423         debugfs_init(it6505);
3424         pm_runtime_enable(dev);
3425
3426         it6505->aux.name = "DP-AUX";
3427         it6505->aux.dev = dev;
3428         it6505->aux.transfer = it6505_aux_transfer;
3429         drm_dp_aux_init(&it6505->aux);
3430
3431         it6505->bridge.funcs = &it6505_bridge_funcs;
3432         it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
3433         it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
3434                              DRM_BRIDGE_OP_HPD;
3435         drm_bridge_add(&it6505->bridge);
3436
3437         return 0;
3438 }
3439
3440 static void it6505_i2c_remove(struct i2c_client *client)
3441 {
3442         struct it6505 *it6505 = i2c_get_clientdata(client);
3443
3444         drm_bridge_remove(&it6505->bridge);
3445         drm_dp_aux_unregister(&it6505->aux);
3446         it6505_debugfs_remove(it6505);
3447         it6505_poweroff(it6505);
3448         it6505_remove_edid(it6505);
3449 }
3450
3451 static const struct i2c_device_id it6505_id[] = {
3452         { "it6505", 0 },
3453         { }
3454 };
3455
3456 MODULE_DEVICE_TABLE(i2c, it6505_id);
3457
3458 static const struct of_device_id it6505_of_match[] = {
3459         { .compatible = "ite,it6505" },
3460         { }
3461 };
3462
3463 static struct i2c_driver it6505_i2c_driver = {
3464         .driver = {
3465                 .name = "it6505",
3466                 .of_match_table = it6505_of_match,
3467                 .pm = &it6505_bridge_pm_ops,
3468         },
3469         .probe_new = it6505_i2c_probe,
3470         .remove = it6505_i2c_remove,
3471         .shutdown = it6505_shutdown,
3472         .id_table = it6505_id,
3473 };
3474
3475 module_i2c_driver(it6505_i2c_driver);
3476
3477 MODULE_AUTHOR("Allen Chen <[email protected]>");
3478 MODULE_DESCRIPTION("IT6505 DisplayPort Transmitter driver");
3479 MODULE_LICENSE("GPL v2");