drivers/net/phy/phy-c45.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Clause 45 PHY support
   4  */
   5 #include <linux/ethtool.h>
   6 #include <linux/export.h>
   7 #include <linux/mdio.h>
   8 #include <linux/mii.h>
   9 #include <linux/phy.h>
  10
  11 #include "mdio-open-alliance.h"
  12
  13 /**
  14  * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities
  15  * @phydev: target phy_device struct
  16  */
  17 static bool genphy_c45_baset1_able(struct phy_device *phydev)
  18 {
  19         int val;
  20
  21         if (phydev->pma_extable == -ENODATA) {
  22                 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
  23                 if (val < 0)
  24                         return false;
  25
  26                 phydev->pma_extable = val;
  27         }
  28
  29         return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1);
  30 }
  31
  32 /**
  33  * genphy_c45_pma_can_sleep - checks if the PMA have sleep support
  34  * @phydev: target phy_device struct
  35  */
  36 static bool genphy_c45_pma_can_sleep(struct phy_device *phydev)
  37 {
  38         int stat1;
  39
  40         stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1);
  41         if (stat1 < 0)
  42                 return false;
  43
  44         return !!(stat1 & MDIO_STAT1_LPOWERABLE);
  45 }
  46
  47 /**
  48  * genphy_c45_pma_resume - wakes up the PMA module
  49  * @phydev: target phy_device struct
  50  */
  51 int genphy_c45_pma_resume(struct phy_device *phydev)
  52 {
  53         if (!genphy_c45_pma_can_sleep(phydev))
  54                 return -EOPNOTSUPP;
  55
  56         return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
  57                                   MDIO_CTRL1_LPOWER);
  58 }
  59 EXPORT_SYMBOL_GPL(genphy_c45_pma_resume);
  60
  61 /**
  62  * genphy_c45_pma_suspend - suspends the PMA module
  63  * @phydev: target phy_device struct
  64  */
  65 int genphy_c45_pma_suspend(struct phy_device *phydev)
  66 {
  67         if (!genphy_c45_pma_can_sleep(phydev))
  68                 return -EOPNOTSUPP;
  69
  70         return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
  71                                 MDIO_CTRL1_LPOWER);
  72 }
  73 EXPORT_SYMBOL_GPL(genphy_c45_pma_suspend);
  74
  75 /**
  76  * genphy_c45_pma_baset1_setup_master_slave - configures forced master/slave
  77  * role of BaseT1 devices.
  78  * @phydev: target phy_device struct
  79  */
  80 int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev)
  81 {
  82         int ctl = 0;
  83
  84         switch (phydev->master_slave_set) {
  85         case MASTER_SLAVE_CFG_MASTER_PREFERRED:
  86         case MASTER_SLAVE_CFG_MASTER_FORCE:
  87                 ctl = MDIO_PMA_PMD_BT1_CTRL_CFG_MST;
  88                 break;
  89         case MASTER_SLAVE_CFG_SLAVE_FORCE:
  90         case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
  91                 break;
  92         case MASTER_SLAVE_CFG_UNKNOWN:
  93         case MASTER_SLAVE_CFG_UNSUPPORTED:
  94                 return 0;
  95         default:
  96                 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
  97                 return -EOPNOTSUPP;
  98         }
  99
 100         return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
 101                              MDIO_PMA_PMD_BT1_CTRL_CFG_MST, ctl);
 102 }
 103 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_setup_master_slave);
 104
 105 /**
 106  * genphy_c45_pma_setup_forced - configures a forced speed
 107  * @phydev: target phy_device struct
 108  */
 109 int genphy_c45_pma_setup_forced(struct phy_device *phydev)
 110 {
 111         int ctrl1, ctrl2, ret;
 112
 113         /* Half duplex is not supported */
 114         if (phydev->duplex != DUPLEX_FULL)
 115                 return -EINVAL;
 116
 117         ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
 118         if (ctrl1 < 0)
 119                 return ctrl1;
 120
 121         ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2);
 122         if (ctrl2 < 0)
 123                 return ctrl2;
 124
 125         ctrl1 &= ~MDIO_CTRL1_SPEEDSEL;
 126         /*
 127          * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0.  See 45.2.1.6.1
 128          * in 802.3-2012 and 802.3-2015.
 129          */
 130         ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30);
 131
 132         switch (phydev->speed) {
 133         case SPEED_10:
 134                 if (genphy_c45_baset1_able(phydev))
 135                         ctrl2 |= MDIO_PMA_CTRL2_BASET1;
 136                 else
 137                         ctrl2 |= MDIO_PMA_CTRL2_10BT;
 138                 break;
 139         case SPEED_100:
 140                 ctrl1 |= MDIO_PMA_CTRL1_SPEED100;
 141                 ctrl2 |= MDIO_PMA_CTRL2_100BTX;
 142                 break;
 143         case SPEED_1000:
 144                 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000;
 145                 /* Assume 1000base-T */
 146                 ctrl2 |= MDIO_PMA_CTRL2_1000BT;
 147                 break;
 148         case SPEED_2500:
 149                 ctrl1 |= MDIO_CTRL1_SPEED2_5G;
 150                 /* Assume 2.5Gbase-T */
 151                 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT;
 152                 break;
 153         case SPEED_5000:
 154                 ctrl1 |= MDIO_CTRL1_SPEED5G;
 155                 /* Assume 5Gbase-T */
 156                 ctrl2 |= MDIO_PMA_CTRL2_5GBT;
 157                 break;
 158         case SPEED_10000:
 159                 ctrl1 |= MDIO_CTRL1_SPEED10G;
 160                 /* Assume 10Gbase-T */
 161                 ctrl2 |= MDIO_PMA_CTRL2_10GBT;
 162                 break;
 163         default:
 164                 return -EINVAL;
 165         }
 166
 167         ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1);
 168         if (ret < 0)
 169                 return ret;
 170
 171         ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2);
 172         if (ret < 0)
 173                 return ret;
 174
 175         if (genphy_c45_baset1_able(phydev)) {
 176                 ret = genphy_c45_pma_baset1_setup_master_slave(phydev);
 177                 if (ret < 0)
 178                         return ret;
 179         }
 180
 181         return genphy_c45_an_disable_aneg(phydev);
 182 }
 183 EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced);
 184
 185 /* Sets master/slave preference and supported technologies.
 186  * The preference is set in the BIT(4) of BASE-T1 AN
 187  * advertisement register 7.515 and whether the status
 188  * is forced or not, it is set in the BIT(12) of BASE-T1
 189  * AN advertisement register 7.514.
 190  * Sets 10BASE-T1L Ability BIT(14) in BASE-T1 autonegotiation
 191  * advertisement register [31:16] if supported.
 192  */
 193 static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev)
 194 {
 195         u16 adv_l_mask, adv_l = 0;
 196         u16 adv_m_mask, adv_m = 0;
 197         int changed = 0;
 198         int ret;
 199
 200         adv_l_mask = MDIO_AN_T1_ADV_L_FORCE_MS | MDIO_AN_T1_ADV_L_PAUSE_CAP |
 201                 MDIO_AN_T1_ADV_L_PAUSE_ASYM;
 202         adv_m_mask = MDIO_AN_T1_ADV_M_MST | MDIO_AN_T1_ADV_M_B10L;
 203
 204         switch (phydev->master_slave_set) {
 205         case MASTER_SLAVE_CFG_MASTER_FORCE:
 206                 adv_m |= MDIO_AN_T1_ADV_M_MST;
 207                 fallthrough;
 208         case MASTER_SLAVE_CFG_SLAVE_FORCE:
 209                 adv_l |= MDIO_AN_T1_ADV_L_FORCE_MS;
 210                 break;
 211         case MASTER_SLAVE_CFG_MASTER_PREFERRED:
 212                 adv_m |= MDIO_AN_T1_ADV_M_MST;
 213                 fallthrough;
 214         case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
 215                 break;
 216         case MASTER_SLAVE_CFG_UNKNOWN:
 217         case MASTER_SLAVE_CFG_UNSUPPORTED:
 218                 /* if master/slave role is not specified, do not overwrite it */
 219                 adv_l_mask &= ~MDIO_AN_T1_ADV_L_FORCE_MS;
 220                 adv_m_mask &= ~MDIO_AN_T1_ADV_M_MST;
 221                 break;
 222         default:
 223                 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
 224                 return -EOPNOTSUPP;
 225         }
 226
 227         adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising);
 228
 229         ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L,
 230                                      adv_l_mask, adv_l);
 231         if (ret < 0)
 232                 return ret;
 233         if (ret > 0)
 234                 changed = 1;
 235
 236         adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising);
 237
 238         ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M,
 239                                      adv_m_mask, adv_m);
 240         if (ret < 0)
 241                 return ret;
 242         if (ret > 0)
 243                 changed = 1;
 244
 245         return changed;
 246 }
 247
 248 /**
 249  * genphy_c45_an_config_aneg - configure advertisement registers
 250  * @phydev: target phy_device struct
 251  *
 252  * Configure advertisement registers based on modes set in phydev->advertising
 253  *
 254  * Returns negative errno code on failure, 0 if advertisement didn't change,
 255  * or 1 if advertised modes changed.
 256  */
 257 int genphy_c45_an_config_aneg(struct phy_device *phydev)
 258 {
 259         int changed = 0, ret;
 260         u32 adv;
 261
 262         linkmode_and(phydev->advertising, phydev->advertising,
 263                      phydev->supported);
 264
 265         ret = genphy_c45_an_config_eee_aneg(phydev);
 266         if (ret < 0)
 267                 return ret;
 268         else if (ret)
 269                 changed = true;
 270
 271         if (genphy_c45_baset1_able(phydev))
 272                 return genphy_c45_baset1_an_config_aneg(phydev);
 273
 274         adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
 275
 276         ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
 277                                      ADVERTISE_ALL | ADVERTISE_100BASE4 |
 278                                      ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
 279                                      adv);
 280         if (ret < 0)
 281                 return ret;
 282         if (ret > 0)
 283                 changed = 1;
 284
 285         adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
 286
 287         ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
 288                                      MDIO_AN_10GBT_CTRL_ADV10G |
 289                                      MDIO_AN_10GBT_CTRL_ADV5G |
 290                                      MDIO_AN_10GBT_CTRL_ADV2_5G, adv);
 291         if (ret < 0)
 292                 return ret;
 293         if (ret > 0)
 294                 changed = 1;
 295
 296         return changed;
 297 }
 298 EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg);
 299
 300 /**
 301  * genphy_c45_an_disable_aneg - disable auto-negotiation
 302  * @phydev: target phy_device struct
 303  *
 304  * Disable auto-negotiation in the Clause 45 PHY. The link parameters
 305  * are controlled through the PMA/PMD MMD registers.
 306  *
 307  * Returns zero on success, negative errno code on failure.
 308  */
 309 int genphy_c45_an_disable_aneg(struct phy_device *phydev)
 310 {
 311         u16 reg = MDIO_CTRL1;
 312
 313         if (genphy_c45_baset1_able(phydev))
 314                 reg = MDIO_AN_T1_CTRL;
 315
 316         return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
 317                                   MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
 318 }
 319 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
 320
 321 /**
 322  * genphy_c45_restart_aneg - Enable and restart auto-negotiation
 323  * @phydev: target phy_device struct
 324  *
 325  * This assumes that the auto-negotiation MMD is present.
 326  *
 327  * Enable and restart auto-negotiation.
 328  */
 329 int genphy_c45_restart_aneg(struct phy_device *phydev)
 330 {
 331         u16 reg = MDIO_CTRL1;
 332
 333         if (genphy_c45_baset1_able(phydev))
 334                 reg = MDIO_AN_T1_CTRL;
 335
 336         return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg,
 337                                 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
 338 }
 339 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);
 340
 341 /**
 342  * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation
 343  * @phydev: target phy_device struct
 344  * @restart: whether aneg restart is requested
 345  *
 346  * This assumes that the auto-negotiation MMD is present.
 347  *
 348  * Check, and restart auto-negotiation if needed.
 349  */
 350 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)
 351 {
 352         u16 reg = MDIO_CTRL1;
 353         int ret;
 354
 355         if (genphy_c45_baset1_able(phydev))
 356                 reg = MDIO_AN_T1_CTRL;
 357
 358         if (!restart) {
 359                 /* Configure and restart aneg if it wasn't set before */
 360                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
 361                 if (ret < 0)
 362                         return ret;
 363
 364                 if (!(ret & MDIO_AN_CTRL1_ENABLE))
 365                         restart = true;
 366         }
 367
 368         if (restart)
 369                 return genphy_c45_restart_aneg(phydev);
 370
 371         return 0;
 372 }
 373 EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg);
 374
 375 /**
 376  * genphy_c45_aneg_done - return auto-negotiation complete status
 377  * @phydev: target phy_device struct
 378  *
 379  * This assumes that the auto-negotiation MMD is present.
 380  *
 381  * Reads the status register from the auto-negotiation MMD, returning:
 382  * - positive if auto-negotiation is complete
 383  * - negative errno code on error
 384  * - zero otherwise
 385  */
 386 int genphy_c45_aneg_done(struct phy_device *phydev)
 387 {
 388         int reg = MDIO_STAT1;
 389         int val;
 390
 391         if (genphy_c45_baset1_able(phydev))
 392                 reg = MDIO_AN_T1_STAT;
 393
 394         val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
 395
 396         return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0;
 397 }
 398 EXPORT_SYMBOL_GPL(genphy_c45_aneg_done);
 399
 400 /**
 401  * genphy_c45_read_link - read the overall link status from the MMDs
 402  * @phydev: target phy_device struct
 403  *
 404  * Read the link status from the specified MMDs, and if they all indicate
 405  * that the link is up, set phydev->link to 1.  If an error is encountered,
 406  * a negative errno will be returned, otherwise zero.
 407  */
 408 int genphy_c45_read_link(struct phy_device *phydev)
 409 {
 410         u32 mmd_mask = MDIO_DEVS_PMAPMD;
 411         int val, devad;
 412         bool link = true;
 413
 414         if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
 415                 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
 416                 if (val < 0)
 417                         return val;
 418
 419                 /* Autoneg is being started, therefore disregard current
 420                  * link status and report link as down.
 421                  */
 422                 if (val & MDIO_AN_CTRL1_RESTART) {
 423                         phydev->link = 0;
 424                         return 0;
 425                 }
 426         }
 427
 428         while (mmd_mask && link) {
 429                 devad = __ffs(mmd_mask);
 430                 mmd_mask &= ~BIT(devad);
 431
 432                 /* The link state is latched low so that momentary link
 433                  * drops can be detected. Do not double-read the status
 434                  * in polling mode to detect such short link drops except
 435                  * the link was already down.
 436                  */
 437                 if (!phy_polling_mode(phydev) || !phydev->link) {
 438                         val = phy_read_mmd(phydev, devad, MDIO_STAT1);
 439                         if (val < 0)
 440                                 return val;
 441                         else if (val & MDIO_STAT1_LSTATUS)
 442                                 continue;
 443                 }
 444
 445                 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
 446                 if (val < 0)
 447                         return val;
 448
 449                 if (!(val & MDIO_STAT1_LSTATUS))
 450                         link = false;
 451         }
 452
 453         phydev->link = link;
 454
 455         return 0;
 456 }
 457 EXPORT_SYMBOL_GPL(genphy_c45_read_link);
 458
 459 /* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check
 460  * if autoneg is complete. If so read the BASE-T1 Autonegotiation
 461  * Advertisement registers filling in the link partner advertisement,
 462  * pause and asym_pause members in phydev.
 463  */
 464 static int genphy_c45_baset1_read_lpa(struct phy_device *phydev)
 465 {
 466         int val;
 467
 468         val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
 469         if (val < 0)
 470                 return val;
 471
 472         if (!(val & MDIO_AN_STAT1_COMPLETE)) {
 473                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising);
 474                 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0);
 475                 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0);
 476
 477                 phydev->pause = 0;
 478                 phydev->asym_pause = 0;
 479
 480                 return 0;
 481         }
 482
 483         linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1);
 484
 485         val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L);
 486         if (val < 0)
 487                 return val;
 488
 489         mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val);
 490         phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0;
 491         phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0;
 492
 493         val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M);
 494         if (val < 0)
 495                 return val;
 496
 497         mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val);
 498
 499         return 0;
 500 }
 501
 502 /**
 503  * genphy_c45_read_lpa - read the link partner advertisement and pause
 504  * @phydev: target phy_device struct
 505  *
 506  * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers,
 507  * filling in the link partner advertisement, pause and asym_pause members
 508  * in @phydev.  This assumes that the auto-negotiation MMD is present, and
 509  * the backplane bit (7.48.0) is clear.  Clause 45 PHY drivers are expected
 510  * to fill in the remainder of the link partner advert from vendor registers.
 511  */
 512 int genphy_c45_read_lpa(struct phy_device *phydev)
 513 {
 514         int val;
 515
 516         if (genphy_c45_baset1_able(phydev))
 517                 return genphy_c45_baset1_read_lpa(phydev);
 518
 519         val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
 520         if (val < 0)
 521                 return val;
 522
 523         if (!(val & MDIO_AN_STAT1_COMPLETE)) {
 524                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
 525                                    phydev->lp_advertising);
 526                 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
 527                 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0);
 528                 phydev->pause = 0;
 529                 phydev->asym_pause = 0;
 530
 531                 return 0;
 532         }
 533
 534         linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising,
 535                          val & MDIO_AN_STAT1_LPABLE);
 536
 537         /* Read the link partner's base page advertisement */
 538         val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
 539         if (val < 0)
 540                 return val;
 541
 542         mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val);
 543         phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0;
 544         phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0;
 545
 546         /* Read the link partner's 10G advertisement */
 547         val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
 548         if (val < 0)
 549                 return val;
 550
 551         mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val);
 552
 553         return 0;
 554 }
 555 EXPORT_SYMBOL_GPL(genphy_c45_read_lpa);
 556
 557 /**
 558  * genphy_c45_pma_baset1_read_master_slave - read forced master/slave
 559  * configuration
 560  * @phydev: target phy_device struct
 561  */
 562 int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev)
 563 {
 564         int val;
 565
 566         phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
 567         phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
 568
 569         val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL);
 570         if (val < 0)
 571                 return val;
 572
 573         if (val & MDIO_PMA_PMD_BT1_CTRL_CFG_MST) {
 574                 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
 575                 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
 576         } else {
 577                 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
 578                 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
 579         }
 580
 581         return 0;
 582 }
 583 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_master_slave);
 584
 585 /**
 586  * genphy_c45_read_pma - read link speed etc from PMA
 587  * @phydev: target phy_device struct
 588  */
 589 int genphy_c45_read_pma(struct phy_device *phydev)
 590 {
 591         int val;
 592
 593         linkmode_zero(phydev->lp_advertising);
 594
 595         val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
 596         if (val < 0)
 597                 return val;
 598
 599         switch (val & MDIO_CTRL1_SPEEDSEL) {
 600         case 0:
 601                 phydev->speed = SPEED_10;
 602                 break;
 603         case MDIO_PMA_CTRL1_SPEED100:
 604                 phydev->speed = SPEED_100;
 605                 break;
 606         case MDIO_PMA_CTRL1_SPEED1000:
 607                 phydev->speed = SPEED_1000;
 608                 break;
 609         case MDIO_CTRL1_SPEED2_5G:
 610                 phydev->speed = SPEED_2500;
 611                 break;
 612         case MDIO_CTRL1_SPEED5G:
 613                 phydev->speed = SPEED_5000;
 614                 break;
 615         case MDIO_CTRL1_SPEED10G:
 616                 phydev->speed = SPEED_10000;
 617                 break;
 618         default:
 619                 phydev->speed = SPEED_UNKNOWN;
 620                 break;
 621         }
 622
 623         phydev->duplex = DUPLEX_FULL;
 624
 625         if (genphy_c45_baset1_able(phydev)) {
 626                 val = genphy_c45_pma_baset1_read_master_slave(phydev);
 627                 if (val < 0)
 628                         return val;
 629         }
 630
 631         return 0;
 632 }
 633 EXPORT_SYMBOL_GPL(genphy_c45_read_pma);
 634
 635 /**
 636  * genphy_c45_read_mdix - read mdix status from PMA
 637  * @phydev: target phy_device struct
 638  */
 639 int genphy_c45_read_mdix(struct phy_device *phydev)
 640 {
 641         int val;
 642
 643         if (phydev->speed == SPEED_10000) {
 644                 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
 645                                    MDIO_PMA_10GBT_SWAPPOL);
 646                 if (val < 0)
 647                         return val;
 648
 649                 switch (val) {
 650                 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX:
 651                         phydev->mdix = ETH_TP_MDI;
 652                         break;
 653
 654                 case 0:
 655                         phydev->mdix = ETH_TP_MDI_X;
 656                         break;
 657
 658                 default:
 659                         phydev->mdix = ETH_TP_MDI_INVALID;
 660                         break;
 661                 }
 662         }
 663
 664         return 0;
 665 }
 666 EXPORT_SYMBOL_GPL(genphy_c45_read_mdix);
 667
 668 /**
 669  * genphy_c45_write_eee_adv - write advertised EEE link modes
 670  * @phydev: target phy_device struct
 671  * @adv: the linkmode advertisement settings
 672  */
 673 int genphy_c45_write_eee_adv(struct phy_device *phydev, unsigned long *adv)
 674 {
 675         int val, changed = 0;
 676
 677         if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) {
 678                 val = linkmode_to_mii_eee_cap1_t(adv);
 679
 680                 /* In eee_broken_modes are stored MDIO_AN_EEE_ADV specific raw
 681                  * register values.
 682                  */
 683                 val &= ~phydev->eee_broken_modes;
 684
 685                 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1
 686                  * (Register 7.60)
 687                  */
 688                 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
 689                                              MDIO_AN_EEE_ADV,
 690                                              MDIO_EEE_100TX | MDIO_EEE_1000T |
 691                                              MDIO_EEE_10GT | MDIO_EEE_1000KX |
 692                                              MDIO_EEE_10GKX4 | MDIO_EEE_10GKR,
 693                                              val);
 694                 if (val < 0)
 695                         return val;
 696                 if (val > 0)
 697                         changed = 1;
 698         }
 699
 700         if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
 701                               phydev->supported_eee)) {
 702                 val = linkmode_adv_to_mii_10base_t1_t(adv);
 703                 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register
 704                  * (Register 7.526)
 705                  */
 706                 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
 707                                              MDIO_AN_10BT1_AN_CTRL,
 708                                              MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L,
 709                                              val);
 710                 if (val < 0)
 711                         return val;
 712                 if (val > 0)
 713                         changed = 1;
 714         }
 715
 716         return changed;
 717 }
 718
 719 /**
 720  * genphy_c45_read_eee_adv - read advertised EEE link modes
 721  * @phydev: target phy_device struct
 722  * @adv: the linkmode advertisement status
 723  */
 724 int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv)
 725 {
 726         int val;
 727
 728         if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) {
 729                 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1
 730                  * (Register 7.60)
 731                  */
 732                 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
 733                 if (val < 0)
 734                         return val;
 735
 736                 mii_eee_cap1_mod_linkmode_t(adv, val);
 737         }
 738
 739         if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
 740                               phydev->supported_eee)) {
 741                 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register
 742                  * (Register 7.526)
 743                  */
 744                 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_CTRL);
 745                 if (val < 0)
 746                         return val;
 747
 748                 mii_10base_t1_adv_mod_linkmode_t(adv, val);
 749         }
 750
 751         return 0;
 752 }
 753
 754 /**
 755  * genphy_c45_read_eee_lpa - read advertised LP EEE link modes
 756  * @phydev: target phy_device struct
 757  * @lpa: the linkmode LP advertisement status
 758  */
 759 static int genphy_c45_read_eee_lpa(struct phy_device *phydev,
 760                                    unsigned long *lpa)
 761 {
 762         int val;
 763
 764         if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) {
 765                 /* IEEE 802.3-2018 45.2.7.14 EEE link partner ability 1
 766                  * (Register 7.61)
 767                  */
 768                 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
 769                 if (val < 0)
 770                         return val;
 771
 772                 mii_eee_cap1_mod_linkmode_t(lpa, val);
 773         }
 774
 775         if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
 776                               phydev->supported_eee)) {
 777                 /* IEEE 802.3cg-2019 45.2.7.26 10BASE-T1 AN status register
 778                  * (Register 7.527)
 779                  */
 780                 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_STAT);
 781                 if (val < 0)
 782                         return val;
 783
 784                 mii_10base_t1_adv_mod_linkmode_t(lpa, val);
 785         }
 786
 787         return 0;
 788 }
 789
 790 /**
 791  * genphy_c45_read_eee_cap1 - read supported EEE link modes from register 3.20
 792  * @phydev: target phy_device struct
 793  */
 794 static int genphy_c45_read_eee_cap1(struct phy_device *phydev)
 795 {
 796         int val;
 797
 798         /* IEEE 802.3-2018 45.2.3.10 EEE control and capability 1
 799          * (Register 3.20)
 800          */
 801         val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
 802         if (val < 0)
 803                 return val;
 804
 805         /* The 802.3 2018 standard says the top 2 bits are reserved and should
 806          * read as 0. Also, it seems unlikely anybody will build a PHY which
 807          * supports 100GBASE-R deep sleep all the way down to 100BASE-TX EEE.
 808          * If MDIO_PCS_EEE_ABLE is 0xffff assume EEE is not supported.
 809          */
 810         if (val == 0xffff)
 811                 return 0;
 812
 813         mii_eee_cap1_mod_linkmode_t(phydev->supported_eee, val);
 814
 815         /* Some buggy devices indicate EEE link modes in MDIO_PCS_EEE_ABLE
 816          * which they don't support as indicated by BMSR, ESTATUS etc.
 817          */
 818         linkmode_and(phydev->supported_eee, phydev->supported_eee,
 819                      phydev->supported);
 820
 821         return 0;
 822 }
 823
 824 /**
 825  * genphy_c45_read_eee_abilities - read supported EEE link modes
 826  * @phydev: target phy_device struct
 827  */
 828 int genphy_c45_read_eee_abilities(struct phy_device *phydev)
 829 {
 830         int val;
 831
 832         /* There is not indicator whether optional register
 833          * "EEE control and capability 1" (3.20) is supported. Read it only
 834          * on devices with appropriate linkmodes.
 835          */
 836         if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) {
 837                 val = genphy_c45_read_eee_cap1(phydev);
 838                 if (val)
 839                         return val;
 840         }
 841
 842         if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
 843                               phydev->supported)) {
 844                 /* IEEE 802.3cg-2019 45.2.1.186b 10BASE-T1L PMA status register
 845                  * (Register 1.2295)
 846                  */
 847                 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT);
 848                 if (val < 0)
 849                         return val;
 850
 851                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
 852                                  phydev->supported_eee,
 853                                  val & MDIO_PMA_10T1L_STAT_EEE);
 854         }
 855
 856         return 0;
 857 }
 858 EXPORT_SYMBOL_GPL(genphy_c45_read_eee_abilities);
 859
 860 /**
 861  * genphy_c45_an_config_eee_aneg - configure EEE advertisement
 862  * @phydev: target phy_device struct
 863  */
 864 int genphy_c45_an_config_eee_aneg(struct phy_device *phydev)
 865 {
 866         if (!phydev->eee_enabled) {
 867                 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv) = {};
 868
 869                 return genphy_c45_write_eee_adv(phydev, adv);
 870         }
 871
 872         return genphy_c45_write_eee_adv(phydev, phydev->advertising_eee);
 873 }
 874
 875 /**
 876  * genphy_c45_pma_read_abilities - read supported link modes from PMA
 877  * @phydev: target phy_device struct
 878  *
 879  * Read the supported link modes from the PMA Status 2 (1.8) register. If bit
 880  * 1.8.9 is set, the list of supported modes is build using the values in the
 881  * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related
 882  * modes. If bit 1.11.14 is set, then the list is also extended with the modes
 883  * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and
 884  * 5GBASET are supported.
 885  */
 886 int genphy_c45_pma_read_abilities(struct phy_device *phydev)
 887 {
 888         int val;
 889
 890         linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
 891         if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
 892                 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
 893                 if (val < 0)
 894                         return val;
 895
 896                 if (val & MDIO_AN_STAT1_ABLE)
 897                         linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
 898                                          phydev->supported);
 899         }
 900
 901         val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
 902         if (val < 0)
 903                 return val;
 904
 905         linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
 906                          phydev->supported,
 907                          val & MDIO_PMA_STAT2_10GBSR);
 908
 909         linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
 910                          phydev->supported,
 911                          val & MDIO_PMA_STAT2_10GBLR);
 912
 913         linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
 914                          phydev->supported,
 915                          val & MDIO_PMA_STAT2_10GBER);
 916
 917         if (val & MDIO_PMA_STAT2_EXTABLE) {
 918                 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
 919                 if (val < 0)
 920                         return val;
 921
 922                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
 923                                  phydev->supported,
 924                                  val & MDIO_PMA_EXTABLE_10GBLRM);
 925                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 926                                  phydev->supported,
 927                                  val & MDIO_PMA_EXTABLE_10GBT);
 928                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
 929                                  phydev->supported,
 930                                  val & MDIO_PMA_EXTABLE_10GBKX4);
 931                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
 932                                  phydev->supported,
 933                                  val & MDIO_PMA_EXTABLE_10GBKR);
 934                 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
 935                                  phydev->supported,
 936                                  val & MDIO_PMA_EXTABLE_1000BT);
 937                 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
 938                                  phydev->supported,
 939                                  val & MDIO_PMA_EXTABLE_1000BKX);
 940
 941                 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
 942                                  phydev->supported,
 943                                  val & MDIO_PMA_EXTABLE_100BTX);
 944                 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
 945                                  phydev->supported,
 946                                  val & MDIO_PMA_EXTABLE_100BTX);
 947
 948                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
 949                                  phydev->supported,
 950                                  val & MDIO_PMA_EXTABLE_10BT);
 951                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
 952                                  phydev->supported,
 953                                  val & MDIO_PMA_EXTABLE_10BT);
 954
 955                 if (val & MDIO_PMA_EXTABLE_NBT) {
 956                         val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
 957                                            MDIO_PMA_NG_EXTABLE);
 958                         if (val < 0)
 959                                 return val;
 960
 961                         linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 962                                          phydev->supported,
 963                                          val & MDIO_PMA_NG_EXTABLE_2_5GBT);
 964
 965                         linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
 966                                          phydev->supported,
 967                                          val & MDIO_PMA_NG_EXTABLE_5GBT);
 968                 }
 969
 970                 if (val & MDIO_PMA_EXTABLE_BT1) {
 971                         val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1);
 972                         if (val < 0)
 973                                 return val;
 974
 975                         linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
 976                                          phydev->supported,
 977                                          val & MDIO_PMA_PMD_BT1_B10L_ABLE);
 978
 979                         val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
 980                         if (val < 0)
 981                                 return val;
 982
 983                         linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
 984                                          phydev->supported,
 985                                          val & MDIO_AN_STAT1_ABLE);
 986                 }
 987         }
 988
 989         /* This is optional functionality. If not supported, we may get an error
 990          * which should be ignored.
 991          */
 992         genphy_c45_read_eee_abilities(phydev);
 993
 994         return 0;
 995 }
 996 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities);
 997
 998 /* Read master/slave preference from registers.
 999  * The preference is read from the BIT(4) of BASE-T1 AN
1000  * advertisement register 7.515 and whether the preference
1001  * is forced or not, it is read from BASE-T1 AN advertisement
1002  * register 7.514.
1003  */
1004 int genphy_c45_baset1_read_status(struct phy_device *phydev)
1005 {
1006         int ret;
1007         int cfg;
1008
1009         phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
1010         phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1011
1012         ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L);
1013         if (ret < 0)
1014                 return ret;
1015
1016         cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M);
1017         if (cfg < 0)
1018                 return cfg;
1019
1020         if (ret & MDIO_AN_T1_ADV_L_FORCE_MS) {
1021                 if (cfg & MDIO_AN_T1_ADV_M_MST)
1022                         phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
1023                 else
1024                         phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
1025         } else {
1026                 if (cfg & MDIO_AN_T1_ADV_M_MST)
1027                         phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED;
1028                 else
1029                         phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED;
1030         }
1031
1032         return 0;
1033 }
1034 EXPORT_SYMBOL_GPL(genphy_c45_baset1_read_status);
1035
1036 /**
1037  * genphy_c45_read_status - read PHY status
1038  * @phydev: target phy_device struct
1039  *
1040  * Reads status from PHY and sets phy_device members accordingly.
1041  */
1042 int genphy_c45_read_status(struct phy_device *phydev)
1043 {
1044         int ret;
1045
1046         ret = genphy_c45_read_link(phydev);
1047         if (ret)
1048                 return ret;
1049
1050         phydev->speed = SPEED_UNKNOWN;
1051         phydev->duplex = DUPLEX_UNKNOWN;
1052         phydev->pause = 0;
1053         phydev->asym_pause = 0;
1054
1055         if (phydev->autoneg == AUTONEG_ENABLE) {
1056                 ret = genphy_c45_read_lpa(phydev);
1057                 if (ret)
1058                         return ret;
1059
1060                 if (genphy_c45_baset1_able(phydev)) {
1061                         ret = genphy_c45_baset1_read_status(phydev);
1062                         if (ret < 0)
1063                                 return ret;
1064                 }
1065
1066                 phy_resolve_aneg_linkmode(phydev);
1067         } else {
1068                 ret = genphy_c45_read_pma(phydev);
1069         }
1070
1071         return ret;
1072 }
1073 EXPORT_SYMBOL_GPL(genphy_c45_read_status);
1074
1075 /**
1076  * genphy_c45_config_aneg - restart auto-negotiation or forced setup
1077  * @phydev: target phy_device struct
1078  *
1079  * Description: If auto-negotiation is enabled, we configure the
1080  *   advertising, and then restart auto-negotiation.  If it is not
1081  *   enabled, then we force a configuration.
1082  */
1083 int genphy_c45_config_aneg(struct phy_device *phydev)
1084 {
1085         bool changed = false;
1086         int ret;
1087
1088         if (phydev->autoneg == AUTONEG_DISABLE)
1089                 return genphy_c45_pma_setup_forced(phydev);
1090
1091         ret = genphy_c45_an_config_aneg(phydev);
1092         if (ret < 0)
1093                 return ret;
1094         if (ret > 0)
1095                 changed = true;
1096
1097         return genphy_c45_check_and_restart_aneg(phydev, changed);
1098 }
1099 EXPORT_SYMBOL_GPL(genphy_c45_config_aneg);
1100
1101 /* The gen10g_* functions are the old Clause 45 stub */
1102
1103 int gen10g_config_aneg(struct phy_device *phydev)
1104 {
1105         return 0;
1106 }
1107 EXPORT_SYMBOL_GPL(gen10g_config_aneg);
1108
1109 int genphy_c45_loopback(struct phy_device *phydev, bool enable)
1110 {
1111         return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1,
1112                               MDIO_PCS_CTRL1_LOOPBACK,
1113                               enable ? MDIO_PCS_CTRL1_LOOPBACK : 0);
1114 }
1115 EXPORT_SYMBOL_GPL(genphy_c45_loopback);
1116
1117 /**
1118  * genphy_c45_fast_retrain - configure fast retrain registers
1119  * @phydev: target phy_device struct
1120  * @enable: enable fast retrain or not
1121  *
1122  * Description: If fast-retrain is enabled, we configure PHY as
1123  *   advertising fast retrain capable and THP Bypass Request, then
1124  *   enable fast retrain. If it is not enabled, we configure fast
1125  *   retrain disabled.
1126  */
1127 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable)
1128 {
1129         int ret;
1130
1131         if (!enable)
1132                 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR,
1133                                 MDIO_PMA_10GBR_FSRT_ENABLE);
1134
1135         if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) {
1136                 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
1137                                 MDIO_AN_10GBT_CTRL_ADVFSRT2_5G);
1138                 if (ret)
1139                         return ret;
1140
1141                 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2,
1142                                 MDIO_AN_THP_BP2_5GT);
1143                 if (ret)
1144                         return ret;
1145         }
1146
1147         return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR,
1148                         MDIO_PMA_10GBR_FSRT_ENABLE);
1149 }
1150 EXPORT_SYMBOL_GPL(genphy_c45_fast_retrain);
1151
1152 /**
1153  * genphy_c45_plca_get_cfg - get PLCA configuration from standard registers
1154  * @phydev: target phy_device struct
1155  * @plca_cfg: output structure to store the PLCA configuration
1156  *
1157  * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA
1158  *   Management Registers specifications, this function can be used to retrieve
1159  *   the current PLCA configuration from the standard registers in MMD 31.
1160  */
1161 int genphy_c45_plca_get_cfg(struct phy_device *phydev,
1162                             struct phy_plca_cfg *plca_cfg)
1163 {
1164         int ret;
1165
1166         ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER);
1167         if (ret < 0)
1168                 return ret;
1169
1170         if ((ret & MDIO_OATC14_PLCA_IDM) != OATC14_IDM)
1171                 return -ENODEV;
1172
1173         plca_cfg->version = ret & ~MDIO_OATC14_PLCA_IDM;
1174
1175         ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0);
1176         if (ret < 0)
1177                 return ret;
1178
1179         plca_cfg->enabled = !!(ret & MDIO_OATC14_PLCA_EN);
1180
1181         ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1);
1182         if (ret < 0)
1183                 return ret;
1184
1185         plca_cfg->node_cnt = (ret & MDIO_OATC14_PLCA_NCNT) >> 8;
1186         plca_cfg->node_id = (ret & MDIO_OATC14_PLCA_ID);
1187
1188         ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR);
1189         if (ret < 0)
1190                 return ret;
1191
1192         plca_cfg->to_tmr = ret & MDIO_OATC14_PLCA_TOT;
1193
1194         ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST);
1195         if (ret < 0)
1196                 return ret;
1197
1198         plca_cfg->burst_cnt = (ret & MDIO_OATC14_PLCA_MAXBC) >> 8;
1199         plca_cfg->burst_tmr = (ret & MDIO_OATC14_PLCA_BTMR);
1200
1201         return 0;
1202 }
1203 EXPORT_SYMBOL_GPL(genphy_c45_plca_get_cfg);
1204
1205 /**
1206  * genphy_c45_plca_set_cfg - set PLCA configuration using standard registers
1207  * @phydev: target phy_device struct
1208  * @plca_cfg: structure containing the PLCA configuration. Fields set to -1 are
1209  * not to be changed.
1210  *
1211  * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA
1212  *   Management Registers specifications, this function can be used to modify
1213  *   the PLCA configuration using the standard registers in MMD 31.
1214  */
1215 int genphy_c45_plca_set_cfg(struct phy_device *phydev,
1216                             const struct phy_plca_cfg *plca_cfg)
1217 {
1218         u16 val = 0;
1219         int ret;
1220
1221         // PLCA IDVER is read-only
1222         if (plca_cfg->version >= 0)
1223                 return -EINVAL;
1224
1225         // first of all, disable PLCA if required
1226         if (plca_cfg->enabled == 0) {
1227                 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
1228                                          MDIO_OATC14_PLCA_CTRL0,
1229                                          MDIO_OATC14_PLCA_EN);
1230
1231                 if (ret < 0)
1232                         return ret;
1233         }
1234
1235         // check if we need to set the PLCA node count, node ID, or both
1236         if (plca_cfg->node_cnt >= 0 || plca_cfg->node_id >= 0) {
1237                 /* if one between node count and node ID is -not- to be
1238                  * changed, read the register to later perform merge/purge of
1239                  * the configuration as appropriate
1240                  */
1241                 if (plca_cfg->node_cnt < 0 || plca_cfg->node_id < 0) {
1242                         ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1243                                            MDIO_OATC14_PLCA_CTRL1);
1244
1245                         if (ret < 0)
1246                                 return ret;
1247
1248                         val = ret;
1249                 }
1250
1251                 if (plca_cfg->node_cnt >= 0)
1252                         val = (val & ~MDIO_OATC14_PLCA_NCNT) |
1253                               (plca_cfg->node_cnt << 8);
1254
1255                 if (plca_cfg->node_id >= 0)
1256                         val = (val & ~MDIO_OATC14_PLCA_ID) |
1257                               (plca_cfg->node_id);
1258
1259                 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1260                                     MDIO_OATC14_PLCA_CTRL1, val);
1261
1262                 if (ret < 0)
1263                         return ret;
1264         }
1265
1266         if (plca_cfg->to_tmr >= 0) {
1267                 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1268                                     MDIO_OATC14_PLCA_TOTMR,
1269                                     plca_cfg->to_tmr);
1270
1271                 if (ret < 0)
1272                         return ret;
1273         }
1274
1275         // check if we need to set the PLCA burst count, burst timer, or both
1276         if (plca_cfg->burst_cnt >= 0 || plca_cfg->burst_tmr >= 0) {
1277                 /* if one between burst count and burst timer is -not- to be
1278                  * changed, read the register to later perform merge/purge of
1279                  * the configuration as appropriate
1280                  */
1281                 if (plca_cfg->burst_cnt < 0 || plca_cfg->burst_tmr < 0) {
1282                         ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1283                                            MDIO_OATC14_PLCA_BURST);
1284
1285                         if (ret < 0)
1286                                 return ret;
1287
1288                         val = ret;
1289                 }
1290
1291                 if (plca_cfg->burst_cnt >= 0)
1292                         val = (val & ~MDIO_OATC14_PLCA_MAXBC) |
1293                               (plca_cfg->burst_cnt << 8);
1294
1295                 if (plca_cfg->burst_tmr >= 0)
1296                         val = (val & ~MDIO_OATC14_PLCA_BTMR) |
1297                               (plca_cfg->burst_tmr);
1298
1299                 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1300                                     MDIO_OATC14_PLCA_BURST, val);
1301
1302                 if (ret < 0)
1303                         return ret;
1304         }
1305
1306         // if we need to enable PLCA, do it at the end
1307         if (plca_cfg->enabled > 0) {
1308                 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
1309                                        MDIO_OATC14_PLCA_CTRL0,
1310                                        MDIO_OATC14_PLCA_EN);
1311
1312                 if (ret < 0)
1313                         return ret;
1314         }
1315
1316         return 0;
1317 }
1318 EXPORT_SYMBOL_GPL(genphy_c45_plca_set_cfg);
1319
1320 /**
1321  * genphy_c45_plca_get_status - get PLCA status from standard registers
1322  * @phydev: target phy_device struct
1323  * @plca_st: output structure to store the PLCA status
1324  *
1325  * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA
1326  *   Management Registers specifications, this function can be used to retrieve
1327  *   the current PLCA status information from the standard registers in MMD 31.
1328  */
1329 int genphy_c45_plca_get_status(struct phy_device *phydev,
1330                                struct phy_plca_status *plca_st)
1331 {
1332         int ret;
1333
1334         ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_STATUS);
1335         if (ret < 0)
1336                 return ret;
1337
1338         plca_st->pst = !!(ret & MDIO_OATC14_PLCA_PST);
1339         return 0;
1340 }
1341 EXPORT_SYMBOL_GPL(genphy_c45_plca_get_status);
1342
1343 /**
1344  * genphy_c45_eee_is_active - get EEE status
1345  * @phydev: target phy_device struct
1346  * @adv: variable to store advertised linkmodes
1347  * @lp: variable to store LP advertised linkmodes
1348  * @is_enabled: variable to store EEE enabled/disabled configuration value
1349  *
1350  * Description: this function will read local and link partner PHY
1351  * advertisements. Compare them return current EEE state.
1352  */
1353 int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *adv,
1354                              unsigned long *lp, bool *is_enabled)
1355 {
1356         __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp_adv) = {};
1357         __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp_lp) = {};
1358         __ETHTOOL_DECLARE_LINK_MODE_MASK(common);
1359         bool eee_enabled, eee_active;
1360         int ret;
1361
1362         ret = genphy_c45_read_eee_adv(phydev, tmp_adv);
1363         if (ret)
1364                 return ret;
1365
1366         ret = genphy_c45_read_eee_lpa(phydev, tmp_lp);
1367         if (ret)
1368                 return ret;
1369
1370         eee_enabled = !linkmode_empty(tmp_adv);
1371         linkmode_and(common, tmp_adv, tmp_lp);
1372         if (eee_enabled && !linkmode_empty(common))
1373                 eee_active = phy_check_valid(phydev->speed, phydev->duplex,
1374                                              common);
1375         else
1376                 eee_active = false;
1377
1378         if (adv)
1379                 linkmode_copy(adv, tmp_adv);
1380         if (lp)
1381                 linkmode_copy(lp, tmp_lp);
1382         if (is_enabled)
1383                 *is_enabled = eee_enabled;
1384
1385         return eee_active;
1386 }
1387 EXPORT_SYMBOL(genphy_c45_eee_is_active);
1388
1389 /**
1390  * genphy_c45_ethtool_get_eee - get EEE supported and status
1391  * @phydev: target phy_device struct
1392  * @data: ethtool_eee data
1393  *
1394  * Description: it reports the Supported/Advertisement/LP Advertisement
1395  * capabilities.
1396  */
1397 int genphy_c45_ethtool_get_eee(struct phy_device *phydev,
1398                                struct ethtool_eee *data)
1399 {
1400         __ETHTOOL_DECLARE_LINK_MODE_MASK(adv) = {};
1401         __ETHTOOL_DECLARE_LINK_MODE_MASK(lp) = {};
1402         bool overflow = false, is_enabled;
1403         int ret;
1404
1405         ret = genphy_c45_eee_is_active(phydev, adv, lp, &is_enabled);
1406         if (ret < 0)
1407                 return ret;
1408
1409         data->eee_enabled = is_enabled;
1410         data->eee_active = ret;
1411
1412         if (!ethtool_convert_link_mode_to_legacy_u32(&data->supported,
1413                                                      phydev->supported_eee))
1414                 overflow = true;
1415         if (!ethtool_convert_link_mode_to_legacy_u32(&data->advertised, adv))
1416                 overflow = true;
1417         if (!ethtool_convert_link_mode_to_legacy_u32(&data->lp_advertised, lp))
1418                 overflow = true;
1419
1420         if (overflow)
1421                 phydev_warn(phydev, "Not all supported or advertised EEE link modes were passed to the user space\n");
1422
1423         return 0;
1424 }
1425 EXPORT_SYMBOL(genphy_c45_ethtool_get_eee);
1426
1427 /**
1428  * genphy_c45_ethtool_set_eee - set EEE supported and status
1429  * @phydev: target phy_device struct
1430  * @data: ethtool_eee data
1431  *
1432  * Description: sets the Supported/Advertisement/LP Advertisement
1433  * capabilities. If eee_enabled is false, no links modes are
1434  * advertised, but the previously advertised link modes are
1435  * retained. This allows EEE to be enabled/disabled in a
1436  * non-destructive way.
1437  */
1438 int genphy_c45_ethtool_set_eee(struct phy_device *phydev,
1439                                struct ethtool_eee *data)
1440 {
1441         int ret;
1442
1443         if (data->eee_enabled) {
1444                 if (data->advertised) {
1445                         __ETHTOOL_DECLARE_LINK_MODE_MASK(adv);
1446
1447                         ethtool_convert_legacy_u32_to_link_mode(adv,
1448                                                                 data->advertised);
1449                         linkmode_andnot(adv, adv, phydev->supported_eee);
1450                         if (!linkmode_empty(adv)) {
1451                                 phydev_warn(phydev, "At least some EEE link modes are not supported.\n");
1452                                 return -EINVAL;
1453                         }
1454
1455                         ethtool_convert_legacy_u32_to_link_mode(phydev->advertising_eee,
1456                                                                 data->advertised);
1457                 } else {
1458                         linkmode_copy(phydev->advertising_eee,
1459                                       phydev->supported_eee);
1460                 }
1461
1462                 phydev->eee_enabled = true;
1463         } else {
1464                 phydev->eee_enabled = false;
1465         }
1466
1467         ret = genphy_c45_an_config_eee_aneg(phydev);
1468         if (ret < 0)
1469                 return ret;
1470         if (ret > 0)
1471                 return phy_restart_aneg(phydev);
1472
1473         return 0;
1474 }
1475 EXPORT_SYMBOL(genphy_c45_ethtool_set_eee);
1476
1477 struct phy_driver genphy_c45_driver = {
1478         .phy_id         = 0xffffffff,
1479         .phy_id_mask    = 0xffffffff,
1480         .name           = "Generic Clause 45 PHY",
1481         .read_status    = genphy_c45_read_status,
1482 };