drivers/gpu/drm/udl/udl_modeset.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Red Hat
   4  *
   5  * based in parts on udlfb.c:
   6  * Copyright (C) 2009 Roberto De Ioris <[email protected]>
   7  * Copyright (C) 2009 Jaya Kumar <[email protected]>
   8  * Copyright (C) 2009 Bernie Thompson <[email protected]>
   9
  10  */
  11
  12 #include <linux/dma-buf.h>
  13
  14 #include <drm/drm_atomic_helper.h>
  15 #include <drm/drm_crtc_helper.h>
  16 #include <drm/drm_damage_helper.h>
  17 #include <drm/drm_fourcc.h>
  18 #include <drm/drm_gem_framebuffer_helper.h>
  19 #include <drm/drm_gem_shmem_helper.h>
  20 #include <drm/drm_modeset_helper_vtables.h>
  21 #include <drm/drm_vblank.h>
  22
  23 #include "udl_drv.h"
  24
  25 #define UDL_COLOR_DEPTH_16BPP   0
  26
  27 /*
  28  * All DisplayLink bulk operations start with 0xAF, followed by specific code
  29  * All operations are written to buffers which then later get sent to device
  30  */
  31 static char *udl_set_register(char *buf, u8 reg, u8 val)
  32 {
  33         *buf++ = 0xAF;
  34         *buf++ = 0x20;
  35         *buf++ = reg;
  36         *buf++ = val;
  37         return buf;
  38 }
  39
  40 static char *udl_vidreg_lock(char *buf)
  41 {
  42         return udl_set_register(buf, 0xFF, 0x00);
  43 }
  44
  45 static char *udl_vidreg_unlock(char *buf)
  46 {
  47         return udl_set_register(buf, 0xFF, 0xFF);
  48 }
  49
  50 static char *udl_set_blank_mode(char *buf, u8 mode)
  51 {
  52         return udl_set_register(buf, UDL_REG_BLANK_MODE, mode);
  53 }
  54
  55 static char *udl_set_color_depth(char *buf, u8 selection)
  56 {
  57         return udl_set_register(buf, 0x00, selection);
  58 }
  59
  60 static char *udl_set_base16bpp(char *wrptr, u32 base)
  61 {
  62         /* the base pointer is 16 bits wide, 0x20 is hi byte. */
  63         wrptr = udl_set_register(wrptr, 0x20, base >> 16);
  64         wrptr = udl_set_register(wrptr, 0x21, base >> 8);
  65         return udl_set_register(wrptr, 0x22, base);
  66 }
  67
  68 /*
  69  * DisplayLink HW has separate 16bpp and 8bpp framebuffers.
  70  * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer
  71  */
  72 static char *udl_set_base8bpp(char *wrptr, u32 base)
  73 {
  74         wrptr = udl_set_register(wrptr, 0x26, base >> 16);
  75         wrptr = udl_set_register(wrptr, 0x27, base >> 8);
  76         return udl_set_register(wrptr, 0x28, base);
  77 }
  78
  79 static char *udl_set_register_16(char *wrptr, u8 reg, u16 value)
  80 {
  81         wrptr = udl_set_register(wrptr, reg, value >> 8);
  82         return udl_set_register(wrptr, reg+1, value);
  83 }
  84
  85 /*
  86  * This is kind of weird because the controller takes some
  87  * register values in a different byte order than other registers.
  88  */
  89 static char *udl_set_register_16be(char *wrptr, u8 reg, u16 value)
  90 {
  91         wrptr = udl_set_register(wrptr, reg, value);
  92         return udl_set_register(wrptr, reg+1, value >> 8);
  93 }
  94
  95 /*
  96  * LFSR is linear feedback shift register. The reason we have this is
  97  * because the display controller needs to minimize the clock depth of
  98  * various counters used in the display path. So this code reverses the
  99  * provided value into the lfsr16 value by counting backwards to get
 100  * the value that needs to be set in the hardware comparator to get the
 101  * same actual count. This makes sense once you read above a couple of
 102  * times and think about it from a hardware perspective.
 103  */
 104 static u16 udl_lfsr16(u16 actual_count)
 105 {
 106         u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */
 107
 108         while (actual_count--) {
 109                 lv =     ((lv << 1) |
 110                         (((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1))
 111                         & 0xFFFF;
 112         }
 113
 114         return (u16) lv;
 115 }
 116
 117 /*
 118  * This does LFSR conversion on the value that is to be written.
 119  * See LFSR explanation above for more detail.
 120  */
 121 static char *udl_set_register_lfsr16(char *wrptr, u8 reg, u16 value)
 122 {
 123         return udl_set_register_16(wrptr, reg, udl_lfsr16(value));
 124 }
 125
 126 /*
 127  * This takes a standard fbdev screeninfo struct and all of its monitor mode
 128  * details and converts them into the DisplayLink equivalent register commands.
 129   ERR(vreg(dev,               0x00, (color_depth == 16) ? 0 : 1));
 130   ERR(vreg_lfsr16(dev,        0x01, xDisplayStart));
 131   ERR(vreg_lfsr16(dev,        0x03, xDisplayEnd));
 132   ERR(vreg_lfsr16(dev,        0x05, yDisplayStart));
 133   ERR(vreg_lfsr16(dev,        0x07, yDisplayEnd));
 134   ERR(vreg_lfsr16(dev,        0x09, xEndCount));
 135   ERR(vreg_lfsr16(dev,        0x0B, hSyncStart));
 136   ERR(vreg_lfsr16(dev,        0x0D, hSyncEnd));
 137   ERR(vreg_big_endian(dev,    0x0F, hPixels));
 138   ERR(vreg_lfsr16(dev,        0x11, yEndCount));
 139   ERR(vreg_lfsr16(dev,        0x13, vSyncStart));
 140   ERR(vreg_lfsr16(dev,        0x15, vSyncEnd));
 141   ERR(vreg_big_endian(dev,    0x17, vPixels));
 142   ERR(vreg_little_endian(dev, 0x1B, pixelClock5KHz));
 143
 144   ERR(vreg(dev,               0x1F, 0));
 145
 146   ERR(vbuf(dev, WRITE_VIDREG_UNLOCK, DSIZEOF(WRITE_VIDREG_UNLOCK)));
 147  */
 148 static char *udl_set_vid_cmds(char *wrptr, struct drm_display_mode *mode)
 149 {
 150         u16 xds, yds;
 151         u16 xde, yde;
 152         u16 yec;
 153
 154         /* x display start */
 155         xds = mode->crtc_htotal - mode->crtc_hsync_start;
 156         wrptr = udl_set_register_lfsr16(wrptr, 0x01, xds);
 157         /* x display end */
 158         xde = xds + mode->crtc_hdisplay;
 159         wrptr = udl_set_register_lfsr16(wrptr, 0x03, xde);
 160
 161         /* y display start */
 162         yds = mode->crtc_vtotal - mode->crtc_vsync_start;
 163         wrptr = udl_set_register_lfsr16(wrptr, 0x05, yds);
 164         /* y display end */
 165         yde = yds + mode->crtc_vdisplay;
 166         wrptr = udl_set_register_lfsr16(wrptr, 0x07, yde);
 167
 168         /* x end count is active + blanking - 1 */
 169         wrptr = udl_set_register_lfsr16(wrptr, 0x09,
 170                                         mode->crtc_htotal - 1);
 171
 172         /* libdlo hardcodes hsync start to 1 */
 173         wrptr = udl_set_register_lfsr16(wrptr, 0x0B, 1);
 174
 175         /* hsync end is width of sync pulse + 1 */
 176         wrptr = udl_set_register_lfsr16(wrptr, 0x0D,
 177                                         mode->crtc_hsync_end - mode->crtc_hsync_start + 1);
 178
 179         /* hpixels is active pixels */
 180         wrptr = udl_set_register_16(wrptr, 0x0F, mode->hdisplay);
 181
 182         /* yendcount is vertical active + vertical blanking */
 183         yec = mode->crtc_vtotal;
 184         wrptr = udl_set_register_lfsr16(wrptr, 0x11, yec);
 185
 186         /* libdlo hardcodes vsync start to 0 */
 187         wrptr = udl_set_register_lfsr16(wrptr, 0x13, 0);
 188
 189         /* vsync end is width of vsync pulse */
 190         wrptr = udl_set_register_lfsr16(wrptr, 0x15, mode->crtc_vsync_end - mode->crtc_vsync_start);
 191
 192         /* vpixels is active pixels */
 193         wrptr = udl_set_register_16(wrptr, 0x17, mode->crtc_vdisplay);
 194
 195         wrptr = udl_set_register_16be(wrptr, 0x1B,
 196                                       mode->clock / 5);
 197
 198         return wrptr;
 199 }
 200
 201 static char *udl_dummy_render(char *wrptr)
 202 {
 203         *wrptr++ = 0xAF;
 204         *wrptr++ = 0x6A; /* copy */
 205         *wrptr++ = 0x00; /* from addr */
 206         *wrptr++ = 0x00;
 207         *wrptr++ = 0x00;
 208         *wrptr++ = 0x01; /* one pixel */
 209         *wrptr++ = 0x00; /* to address */
 210         *wrptr++ = 0x00;
 211         *wrptr++ = 0x00;
 212         return wrptr;
 213 }
 214
 215 static int udl_crtc_write_mode_to_hw(struct drm_crtc *crtc)
 216 {
 217         struct drm_device *dev = crtc->dev;
 218         struct udl_device *udl = dev->dev_private;
 219         struct urb *urb;
 220         char *buf;
 221         int retval;
 222
 223         if (udl->mode_buf_len == 0) {
 224                 DRM_ERROR("No mode set\n");
 225                 return -EINVAL;
 226         }
 227
 228         urb = udl_get_urb(dev);
 229         if (!urb)
 230                 return -ENOMEM;
 231
 232         buf = (char *)urb->transfer_buffer;
 233
 234         memcpy(buf, udl->mode_buf, udl->mode_buf_len);
 235         retval = udl_submit_urb(dev, urb, udl->mode_buf_len);
 236         DRM_DEBUG("write mode info %d\n", udl->mode_buf_len);
 237         return retval;
 238 }
 239
 240 static long udl_log_cpp(unsigned int cpp)
 241 {
 242         if (WARN_ON(!is_power_of_2(cpp)))
 243                 return -EINVAL;
 244         return __ffs(cpp);
 245 }
 246
 247 static int udl_aligned_damage_clip(struct drm_rect *clip, int x, int y,
 248                                    int width, int height)
 249 {
 250         int x1, x2;
 251
 252         if (WARN_ON_ONCE(x < 0) ||
 253             WARN_ON_ONCE(y < 0) ||
 254             WARN_ON_ONCE(width < 0) ||
 255             WARN_ON_ONCE(height < 0))
 256                 return -EINVAL;
 257
 258         x1 = ALIGN_DOWN(x, sizeof(unsigned long));
 259         x2 = ALIGN(width + (x - x1), sizeof(unsigned long)) + x1;
 260
 261         clip->x1 = x1;
 262         clip->y1 = y;
 263         clip->x2 = x2;
 264         clip->y2 = y + height;
 265
 266         return 0;
 267 }
 268
 269 int udl_handle_damage(struct drm_framebuffer *fb, int x, int y,
 270                       int width, int height)
 271 {
 272         struct drm_device *dev = fb->dev;
 273         struct dma_buf_attachment *import_attach = fb->obj[0]->import_attach;
 274         int i, ret, tmp_ret;
 275         char *cmd;
 276         struct urb *urb;
 277         struct drm_rect clip;
 278         int log_bpp;
 279         void *vaddr;
 280
 281         ret = udl_log_cpp(fb->format->cpp[0]);
 282         if (ret < 0)
 283                 return ret;
 284         log_bpp = ret;
 285
 286         ret = udl_aligned_damage_clip(&clip, x, y, width, height);
 287         if (ret)
 288                 return ret;
 289         else if ((clip.x2 > fb->width) || (clip.y2 > fb->height))
 290                 return -EINVAL;
 291
 292         if (import_attach) {
 293                 ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
 294                                                DMA_FROM_DEVICE);
 295                 if (ret)
 296                         return ret;
 297         }
 298
 299         vaddr = drm_gem_shmem_vmap(fb->obj[0]);
 300         if (IS_ERR(vaddr)) {
 301                 DRM_ERROR("failed to vmap fb\n");
 302                 goto out_dma_buf_end_cpu_access;
 303         }
 304
 305         urb = udl_get_urb(dev);
 306         if (!urb)
 307                 goto out_drm_gem_shmem_vunmap;
 308         cmd = urb->transfer_buffer;
 309
 310         for (i = clip.y1; i < clip.y2; i++) {
 311                 const int line_offset = fb->pitches[0] * i;
 312                 const int byte_offset = line_offset + (clip.x1 << log_bpp);
 313                 const int dev_byte_offset = (fb->width * i + clip.x1) << log_bpp;
 314                 const int byte_width = (clip.x2 - clip.x1) << log_bpp;
 315                 ret = udl_render_hline(dev, log_bpp, &urb, (char *)vaddr,
 316                                        &cmd, byte_offset, dev_byte_offset,
 317                                        byte_width);
 318                 if (ret)
 319                         goto out_drm_gem_shmem_vunmap;
 320         }
 321
 322         if (cmd > (char *)urb->transfer_buffer) {
 323                 /* Send partial buffer remaining before exiting */
 324                 int len;
 325                 if (cmd < (char *)urb->transfer_buffer + urb->transfer_buffer_length)
 326                         *cmd++ = 0xAF;
 327                 len = cmd - (char *)urb->transfer_buffer;
 328                 ret = udl_submit_urb(dev, urb, len);
 329         } else {
 330                 udl_urb_completion(urb);
 331         }
 332
 333         ret = 0;
 334
 335 out_drm_gem_shmem_vunmap:
 336         drm_gem_shmem_vunmap(fb->obj[0], vaddr);
 337 out_dma_buf_end_cpu_access:
 338         if (import_attach) {
 339                 tmp_ret = dma_buf_end_cpu_access(import_attach->dmabuf,
 340                                                  DMA_FROM_DEVICE);
 341                 if (tmp_ret && !ret)
 342                         ret = tmp_ret; /* only update ret if not set yet */
 343         }
 344
 345         return ret;
 346 }
 347
 348 /*
 349  * Simple display pipeline
 350  */
 351
 352 static const uint32_t udl_simple_display_pipe_formats[] = {
 353         DRM_FORMAT_RGB565,
 354         DRM_FORMAT_XRGB8888,
 355 };
 356
 357 static enum drm_mode_status
 358 udl_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe,
 359                                    const struct drm_display_mode *mode)
 360 {
 361         return MODE_OK;
 362 }
 363
 364 static void
 365 udl_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe,
 366                                struct drm_crtc_state *crtc_state,
 367                                struct drm_plane_state *plane_state)
 368 {
 369         struct drm_crtc *crtc = &pipe->crtc;
 370         struct drm_device *dev = crtc->dev;
 371         struct drm_framebuffer *fb = plane_state->fb;
 372         struct udl_device *udl = dev->dev_private;
 373         struct drm_display_mode *mode = &crtc_state->mode;
 374         char *buf;
 375         char *wrptr;
 376         int color_depth = UDL_COLOR_DEPTH_16BPP;
 377
 378         crtc_state->no_vblank = true;
 379
 380         buf = (char *)udl->mode_buf;
 381
 382         /* This first section has to do with setting the base address on the
 383          * controller associated with the display. There are 2 base
 384          * pointers, currently, we only use the 16 bpp segment.
 385          */
 386         wrptr = udl_vidreg_lock(buf);
 387         wrptr = udl_set_color_depth(wrptr, color_depth);
 388         /* set base for 16bpp segment to 0 */
 389         wrptr = udl_set_base16bpp(wrptr, 0);
 390         /* set base for 8bpp segment to end of fb */
 391         wrptr = udl_set_base8bpp(wrptr, 2 * mode->vdisplay * mode->hdisplay);
 392
 393         wrptr = udl_set_vid_cmds(wrptr, mode);
 394         wrptr = udl_set_blank_mode(wrptr, UDL_BLANK_MODE_ON);
 395         wrptr = udl_vidreg_unlock(wrptr);
 396
 397         wrptr = udl_dummy_render(wrptr);
 398
 399         udl->mode_buf_len = wrptr - buf;
 400
 401         udl_handle_damage(fb, 0, 0, fb->width, fb->height);
 402
 403         if (!crtc_state->mode_changed)
 404                 return;
 405
 406         /* enable display */
 407         udl_crtc_write_mode_to_hw(crtc);
 408 }
 409
 410 static void
 411 udl_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe)
 412 {
 413         struct drm_crtc *crtc = &pipe->crtc;
 414         struct drm_device *dev = crtc->dev;
 415         struct urb *urb;
 416         char *buf;
 417
 418         urb = udl_get_urb(dev);
 419         if (!urb)
 420                 return;
 421
 422         buf = (char *)urb->transfer_buffer;
 423         buf = udl_vidreg_lock(buf);
 424         buf = udl_set_blank_mode(buf, UDL_BLANK_MODE_POWERDOWN);
 425         buf = udl_vidreg_unlock(buf);
 426         buf = udl_dummy_render(buf);
 427
 428         udl_submit_urb(dev, urb, buf - (char *)urb->transfer_buffer);
 429 }
 430
 431 static int
 432 udl_simple_display_pipe_check(struct drm_simple_display_pipe *pipe,
 433                               struct drm_plane_state *plane_state,
 434                               struct drm_crtc_state *crtc_state)
 435 {
 436         return 0;
 437 }
 438
 439 static void
 440 udl_simple_display_pipe_update(struct drm_simple_display_pipe *pipe,
 441                                struct drm_plane_state *old_plane_state)
 442 {
 443         struct drm_plane_state *state = pipe->plane.state;
 444         struct drm_framebuffer *fb = state->fb;
 445         struct drm_rect rect;
 446
 447         if (!fb)
 448                 return;
 449
 450         if (drm_atomic_helper_damage_merged(old_plane_state, state, &rect))
 451                 udl_handle_damage(fb, rect.x1, rect.y1, rect.x2 - rect.x1,
 452                                   rect.y2 - rect.y1);
 453 }
 454
 455 static const
 456 struct drm_simple_display_pipe_funcs udl_simple_display_pipe_funcs = {
 457         .mode_valid = udl_simple_display_pipe_mode_valid,
 458         .enable = udl_simple_display_pipe_enable,
 459         .disable = udl_simple_display_pipe_disable,
 460         .check = udl_simple_display_pipe_check,
 461         .update = udl_simple_display_pipe_update,
 462         .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
 463 };
 464
 465 /*
 466  * Modesetting
 467  */
 468
 469 static const struct drm_mode_config_funcs udl_mode_funcs = {
 470         .fb_create = drm_gem_fb_create_with_dirty,
 471         .atomic_check  = drm_atomic_helper_check,
 472         .atomic_commit = drm_atomic_helper_commit,
 473 };
 474
 475 int udl_modeset_init(struct drm_device *dev)
 476 {
 477         size_t format_count = ARRAY_SIZE(udl_simple_display_pipe_formats);
 478         struct udl_device *udl = dev->dev_private;
 479         struct drm_connector *connector;
 480         int ret;
 481
 482         drm_mode_config_init(dev);
 483
 484         dev->mode_config.min_width = 640;
 485         dev->mode_config.min_height = 480;
 486
 487         dev->mode_config.max_width = 2048;
 488         dev->mode_config.max_height = 2048;
 489
 490         dev->mode_config.prefer_shadow = 0;
 491         dev->mode_config.preferred_depth = 16;
 492
 493         dev->mode_config.funcs = &udl_mode_funcs;
 494
 495         connector = udl_connector_init(dev);
 496         if (IS_ERR(connector)) {
 497                 ret = PTR_ERR(connector);
 498                 goto err_drm_mode_config_cleanup;
 499         }
 500
 501         format_count = ARRAY_SIZE(udl_simple_display_pipe_formats);
 502
 503         ret = drm_simple_display_pipe_init(dev, &udl->display_pipe,
 504                                            &udl_simple_display_pipe_funcs,
 505                                            udl_simple_display_pipe_formats,
 506                                            format_count, NULL, connector);
 507         if (ret)
 508                 goto err_drm_mode_config_cleanup;
 509
 510         drm_mode_config_reset(dev);
 511
 512         return 0;
 513
 514 err_drm_mode_config_cleanup:
 515         drm_mode_config_cleanup(dev);
 516         return ret;
 517 }
 518
 519 void udl_modeset_cleanup(struct drm_device *dev)
 520 {
 521         drm_mode_config_cleanup(dev);
 522 }