drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_gfx.h"
  29 #include "amdgpu_rlc.h"
  30 #include "amdgpu_ras.h"
  31
  32 /* delay 0.1 second to enable gfx off feature */
  33 #define GFX_OFF_DELAY_ENABLE         msecs_to_jiffies(100)
  34
  35 #define GFX_OFF_NO_DELAY 0
  36
  37 /*
  38  * GPU GFX IP block helpers function.
  39  */
  40
  41 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
  42                                 int pipe, int queue)
  43 {
  44         int bit = 0;
  45
  46         bit += mec * adev->gfx.mec.num_pipe_per_mec
  47                 * adev->gfx.mec.num_queue_per_pipe;
  48         bit += pipe * adev->gfx.mec.num_queue_per_pipe;
  49         bit += queue;
  50
  51         return bit;
  52 }
  53
  54 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
  55                                  int *mec, int *pipe, int *queue)
  56 {
  57         *queue = bit % adev->gfx.mec.num_queue_per_pipe;
  58         *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
  59                 % adev->gfx.mec.num_pipe_per_mec;
  60         *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
  61                / adev->gfx.mec.num_pipe_per_mec;
  62
  63 }
  64
  65 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
  66                                      int xcc_id, int mec, int pipe, int queue)
  67 {
  68         return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),
  69                         adev->gfx.mec_bitmap[xcc_id].queue_bitmap);
  70 }
  71
  72 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
  73                                int me, int pipe, int queue)
  74 {
  75         int bit = 0;
  76
  77         bit += me * adev->gfx.me.num_pipe_per_me
  78                 * adev->gfx.me.num_queue_per_pipe;
  79         bit += pipe * adev->gfx.me.num_queue_per_pipe;
  80         bit += queue;
  81
  82         return bit;
  83 }
  84
  85 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
  86                                 int *me, int *pipe, int *queue)
  87 {
  88         *queue = bit % adev->gfx.me.num_queue_per_pipe;
  89         *pipe = (bit / adev->gfx.me.num_queue_per_pipe)
  90                 % adev->gfx.me.num_pipe_per_me;
  91         *me = (bit / adev->gfx.me.num_queue_per_pipe)
  92                 / adev->gfx.me.num_pipe_per_me;
  93 }
  94
  95 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
  96                                     int me, int pipe, int queue)
  97 {
  98         return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue),
  99                         adev->gfx.me.queue_bitmap);
 100 }
 101
 102 /**
 103  * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
 104  *
 105  * @mask: array in which the per-shader array disable masks will be stored
 106  * @max_se: number of SEs
 107  * @max_sh: number of SHs
 108  *
 109  * The bitmask of CUs to be disabled in the shader array determined by se and
 110  * sh is stored in mask[se * max_sh + sh].
 111  */
 112 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
 113 {
 114         unsigned se, sh, cu;
 115         const char *p;
 116
 117         memset(mask, 0, sizeof(*mask) * max_se * max_sh);
 118
 119         if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
 120                 return;
 121
 122         p = amdgpu_disable_cu;
 123         for (;;) {
 124                 char *next;
 125                 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
 126                 if (ret < 3) {
 127                         DRM_ERROR("amdgpu: could not parse disable_cu\n");
 128                         return;
 129                 }
 130
 131                 if (se < max_se && sh < max_sh && cu < 16) {
 132                         DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
 133                         mask[se * max_sh + sh] |= 1u << cu;
 134                 } else {
 135                         DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
 136                                   se, sh, cu);
 137                 }
 138
 139                 next = strchr(p, ',');
 140                 if (!next)
 141                         break;
 142                 p = next + 1;
 143         }
 144 }
 145
 146 static bool amdgpu_gfx_is_graphics_multipipe_capable(struct amdgpu_device *adev)
 147 {
 148         return amdgpu_async_gfx_ring && adev->gfx.me.num_pipe_per_me > 1;
 149 }
 150
 151 static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev)
 152 {
 153         if (amdgpu_compute_multipipe != -1) {
 154                 DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
 155                          amdgpu_compute_multipipe);
 156                 return amdgpu_compute_multipipe == 1;
 157         }
 158
 159         if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))
 160                 return true;
 161
 162         /* FIXME: spreading the queues across pipes causes perf regressions
 163          * on POLARIS11 compute workloads */
 164         if (adev->asic_type == CHIP_POLARIS11)
 165                 return false;
 166
 167         return adev->gfx.mec.num_mec > 1;
 168 }
 169
 170 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
 171                                                 struct amdgpu_ring *ring)
 172 {
 173         int queue = ring->queue;
 174         int pipe = ring->pipe;
 175
 176         /* Policy: use pipe1 queue0 as high priority graphics queue if we
 177          * have more than one gfx pipe.
 178          */
 179         if (amdgpu_gfx_is_graphics_multipipe_capable(adev) &&
 180             adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) {
 181                 int me = ring->me;
 182                 int bit;
 183
 184                 bit = amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue);
 185                 if (ring == &adev->gfx.gfx_ring[bit])
 186                         return true;
 187         }
 188
 189         return false;
 190 }
 191
 192 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 193                                                struct amdgpu_ring *ring)
 194 {
 195         /* Policy: use 1st queue as high priority compute queue if we
 196          * have more than one compute queue.
 197          */
 198         if (adev->gfx.num_compute_rings > 1 &&
 199             ring == &adev->gfx.compute_ring[0])
 200                 return true;
 201
 202         return false;
 203 }
 204
 205 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
 206 {
 207         int i, j, queue, pipe;
 208         bool multipipe_policy = amdgpu_gfx_is_compute_multipipe_capable(adev);
 209         int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec *
 210                                      adev->gfx.mec.num_queue_per_pipe,
 211                                      adev->gfx.num_compute_rings);
 212         int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
 213
 214         if (multipipe_policy) {
 215                 /* policy: make queues evenly cross all pipes on MEC1 only
 216                  * for multiple xcc, just use the original policy for simplicity */
 217                 for (j = 0; j < num_xcc; j++) {
 218                         for (i = 0; i < max_queues_per_mec; i++) {
 219                                 pipe = i % adev->gfx.mec.num_pipe_per_mec;
 220                                 queue = (i / adev->gfx.mec.num_pipe_per_mec) %
 221                                          adev->gfx.mec.num_queue_per_pipe;
 222
 223                                 set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue,
 224                                         adev->gfx.mec_bitmap[j].queue_bitmap);
 225                         }
 226                 }
 227         } else {
 228                 /* policy: amdgpu owns all queues in the given pipe */
 229                 for (j = 0; j < num_xcc; j++) {
 230                         for (i = 0; i < max_queues_per_mec; ++i)
 231                                 set_bit(i, adev->gfx.mec_bitmap[j].queue_bitmap);
 232                 }
 233         }
 234
 235         for (j = 0; j < num_xcc; j++) {
 236                 dev_dbg(adev->dev, "mec queue bitmap weight=%d\n",
 237                         bitmap_weight(adev->gfx.mec_bitmap[j].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES));
 238         }
 239 }
 240
 241 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
 242 {
 243         int i, queue, pipe;
 244         bool multipipe_policy = amdgpu_gfx_is_graphics_multipipe_capable(adev);
 245         int max_queues_per_me = adev->gfx.me.num_pipe_per_me *
 246                                         adev->gfx.me.num_queue_per_pipe;
 247
 248         if (multipipe_policy) {
 249                 /* policy: amdgpu owns the first queue per pipe at this stage
 250                  * will extend to mulitple queues per pipe later */
 251                 for (i = 0; i < max_queues_per_me; i++) {
 252                         pipe = i % adev->gfx.me.num_pipe_per_me;
 253                         queue = (i / adev->gfx.me.num_pipe_per_me) %
 254                                 adev->gfx.me.num_queue_per_pipe;
 255
 256                         set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue,
 257                                 adev->gfx.me.queue_bitmap);
 258                 }
 259         } else {
 260                 for (i = 0; i < max_queues_per_me; ++i)
 261                         set_bit(i, adev->gfx.me.queue_bitmap);
 262         }
 263
 264         /* update the number of active graphics rings */
 265         adev->gfx.num_gfx_rings =
 266                 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 267 }
 268
 269 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
 270                                   struct amdgpu_ring *ring, int xcc_id)
 271 {
 272         int queue_bit;
 273         int mec, pipe, queue;
 274
 275         queue_bit = adev->gfx.mec.num_mec
 276                     * adev->gfx.mec.num_pipe_per_mec
 277                     * adev->gfx.mec.num_queue_per_pipe;
 278
 279         while (--queue_bit >= 0) {
 280                 if (test_bit(queue_bit, adev->gfx.mec_bitmap[xcc_id].queue_bitmap))
 281                         continue;
 282
 283                 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 284
 285                 /*
 286                  * 1. Using pipes 2/3 from MEC 2 seems cause problems.
 287                  * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
 288                  * only can be issued on queue 0.
 289                  */
 290                 if ((mec == 1 && pipe > 1) || queue != 0)
 291                         continue;
 292
 293                 ring->me = mec + 1;
 294                 ring->pipe = pipe;
 295                 ring->queue = queue;
 296
 297                 return 0;
 298         }
 299
 300         dev_err(adev->dev, "Failed to find a queue for KIQ\n");
 301         return -EINVAL;
 302 }
 303
 304 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 305                              struct amdgpu_ring *ring,
 306                              struct amdgpu_irq_src *irq, int xcc_id)
 307 {
 308         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 309         int r = 0;
 310
 311         spin_lock_init(&kiq->ring_lock);
 312
 313         ring->adev = NULL;
 314         ring->ring_obj = NULL;
 315         ring->use_doorbell = true;
 316         ring->xcc_id = xcc_id;
 317         ring->vm_hub = AMDGPU_GFXHUB(xcc_id);
 318         ring->doorbell_index = (adev->doorbell_index.kiq + xcc_id) << 1;
 319
 320         r = amdgpu_gfx_kiq_acquire(adev, ring, xcc_id);
 321         if (r)
 322                 return r;
 323
 324         ring->eop_gpu_addr = kiq->eop_gpu_addr;
 325         ring->no_scheduler = true;
 326         sprintf(ring->name, "kiq_%d.%d.%d.%d", xcc_id, ring->me, ring->pipe, ring->queue);
 327         r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0,
 328                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 329         if (r)
 330                 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
 331
 332         return r;
 333 }
 334
 335 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
 336 {
 337         amdgpu_ring_fini(ring);
 338 }
 339
 340 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id)
 341 {
 342         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 343
 344         amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
 345 }
 346
 347 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
 348                         unsigned hpd_size, int xcc_id)
 349 {
 350         int r;
 351         u32 *hpd;
 352         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 353
 354         r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE,
 355                                     AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
 356                                     &kiq->eop_gpu_addr, (void **)&hpd);
 357         if (r) {
 358                 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
 359                 return r;
 360         }
 361
 362         memset(hpd, 0, hpd_size);
 363
 364         r = amdgpu_bo_reserve(kiq->eop_obj, true);
 365         if (unlikely(r != 0))
 366                 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
 367         amdgpu_bo_kunmap(kiq->eop_obj);
 368         amdgpu_bo_unreserve(kiq->eop_obj);
 369
 370         return 0;
 371 }
 372
 373 /* create MQD for each compute/gfx queue */
 374 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
 375                            unsigned mqd_size, int xcc_id)
 376 {
 377         int r, i, j;
 378         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 379         struct amdgpu_ring *ring = &kiq->ring;
 380         u32 domain = AMDGPU_GEM_DOMAIN_GTT;
 381
 382         /* Only enable on gfx10 and 11 for now to avoid changing behavior on older chips */
 383         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0))
 384                 domain |= AMDGPU_GEM_DOMAIN_VRAM;
 385
 386         /* create MQD for KIQ */
 387         if (!adev->enable_mes_kiq && !ring->mqd_obj) {
 388                 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must
 389                  * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD
 390                  * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for
 391                  * KIQ MQD no matter SRIOV or Bare-metal
 392                  */
 393                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 394                                             AMDGPU_GEM_DOMAIN_VRAM |
 395                                             AMDGPU_GEM_DOMAIN_GTT,
 396                                             &ring->mqd_obj,
 397                                             &ring->mqd_gpu_addr,
 398                                             &ring->mqd_ptr);
 399                 if (r) {
 400                         dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
 401                         return r;
 402                 }
 403
 404                 /* prepare MQD backup */
 405                 kiq->mqd_backup = kmalloc(mqd_size, GFP_KERNEL);
 406                 if (!kiq->mqd_backup)
 407                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 408         }
 409
 410         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 411                 /* create MQD for each KGQ */
 412                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 413                         ring = &adev->gfx.gfx_ring[i];
 414                         if (!ring->mqd_obj) {
 415                                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 416                                                             domain, &ring->mqd_obj,
 417                                                             &ring->mqd_gpu_addr, &ring->mqd_ptr);
 418                                 if (r) {
 419                                         dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 420                                         return r;
 421                                 }
 422
 423                                 ring->mqd_size = mqd_size;
 424                                 /* prepare MQD backup */
 425                                 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
 426                                 if (!adev->gfx.me.mqd_backup[i])
 427                                         dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 428                         }
 429                 }
 430         }
 431
 432         /* create MQD for each KCQ */
 433         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 434                 j = i + xcc_id * adev->gfx.num_compute_rings;
 435                 ring = &adev->gfx.compute_ring[j];
 436                 if (!ring->mqd_obj) {
 437                         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 438                                                     domain, &ring->mqd_obj,
 439                                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
 440                         if (r) {
 441                                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 442                                 return r;
 443                         }
 444
 445                         ring->mqd_size = mqd_size;
 446                         /* prepare MQD backup */
 447                         adev->gfx.mec.mqd_backup[j + xcc_id * adev->gfx.num_compute_rings] = kmalloc(mqd_size, GFP_KERNEL);
 448                         if (!adev->gfx.mec.mqd_backup[j + xcc_id * adev->gfx.num_compute_rings])
 449                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 450                 }
 451         }
 452
 453         return 0;
 454 }
 455
 456 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id)
 457 {
 458         struct amdgpu_ring *ring = NULL;
 459         int i, j;
 460         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 461
 462         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 463                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 464                         ring = &adev->gfx.gfx_ring[i];
 465                         kfree(adev->gfx.me.mqd_backup[i]);
 466                         amdgpu_bo_free_kernel(&ring->mqd_obj,
 467                                               &ring->mqd_gpu_addr,
 468                                               &ring->mqd_ptr);
 469                 }
 470         }
 471
 472         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 473                 j = i + xcc_id * adev->gfx.num_compute_rings;
 474                 ring = &adev->gfx.compute_ring[j];
 475                 kfree(adev->gfx.mec.mqd_backup[j]);
 476                 amdgpu_bo_free_kernel(&ring->mqd_obj,
 477                                       &ring->mqd_gpu_addr,
 478                                       &ring->mqd_ptr);
 479         }
 480
 481         ring = &kiq->ring;
 482         kfree(kiq->mqd_backup);
 483         amdgpu_bo_free_kernel(&ring->mqd_obj,
 484                               &ring->mqd_gpu_addr,
 485                               &ring->mqd_ptr);
 486 }
 487
 488 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id)
 489 {
 490         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 491         struct amdgpu_ring *kiq_ring = &kiq->ring;
 492         int i, r = 0;
 493         int j;
 494
 495         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 496                 return -EINVAL;
 497
 498         spin_lock(&kiq->ring_lock);
 499         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
 500                                         adev->gfx.num_compute_rings)) {
 501                 spin_unlock(&kiq->ring_lock);
 502                 return -ENOMEM;
 503         }
 504
 505         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 506                 j = i + xcc_id * adev->gfx.num_compute_rings;
 507                 kiq->pmf->kiq_unmap_queues(kiq_ring,
 508                                            &adev->gfx.compute_ring[i],
 509                                            RESET_QUEUES, 0, 0);
 510         }
 511
 512         if (kiq_ring->sched.ready && !adev->job_hang)
 513                 r = amdgpu_ring_test_helper(kiq_ring);
 514         spin_unlock(&kiq->ring_lock);
 515
 516         return r;
 517 }
 518
 519 int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id)
 520 {
 521         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 522         struct amdgpu_ring *kiq_ring = &kiq->ring;
 523         int i, r = 0;
 524         int j;
 525
 526         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 527                 return -EINVAL;
 528
 529         spin_lock(&kiq->ring_lock);
 530         if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {
 531                 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
 532                                                 adev->gfx.num_gfx_rings)) {
 533                         spin_unlock(&kiq->ring_lock);
 534                         return -ENOMEM;
 535                 }
 536
 537                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 538                         j = i + xcc_id * adev->gfx.num_gfx_rings;
 539                         kiq->pmf->kiq_unmap_queues(kiq_ring,
 540                                                    &adev->gfx.gfx_ring[i],
 541                                                    PREEMPT_QUEUES, 0, 0);
 542                 }
 543         }
 544
 545         if (adev->gfx.kiq[0].ring.sched.ready && !adev->job_hang)
 546                 r = amdgpu_ring_test_helper(kiq_ring);
 547         spin_unlock(&kiq->ring_lock);
 548
 549         return r;
 550 }
 551
 552 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
 553                                         int queue_bit)
 554 {
 555         int mec, pipe, queue;
 556         int set_resource_bit = 0;
 557
 558         amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 559
 560         set_resource_bit = mec * 4 * 8 + pipe * 8 + queue;
 561
 562         return set_resource_bit;
 563 }
 564
 565 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id)
 566 {
 567         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 568         struct amdgpu_ring *kiq_ring = &kiq->ring;
 569         uint64_t queue_mask = 0;
 570         int r, i, j;
 571
 572         if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources)
 573                 return -EINVAL;
 574
 575         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
 576                 if (!test_bit(i, adev->gfx.mec_bitmap[xcc_id].queue_bitmap))
 577                         continue;
 578
 579                 /* This situation may be hit in the future if a new HW
 580                  * generation exposes more than 64 queues. If so, the
 581                  * definition of queue_mask needs updating */
 582                 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
 583                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
 584                         break;
 585                 }
 586
 587                 queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i));
 588         }
 589
 590         DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
 591                                                         kiq_ring->queue);
 592         spin_lock(&kiq->ring_lock);
 593         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
 594                                         adev->gfx.num_compute_rings +
 595                                         kiq->pmf->set_resources_size);
 596         if (r) {
 597                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 598                 spin_unlock(&kiq->ring_lock);
 599                 return r;
 600         }
 601
 602         if (adev->enable_mes)
 603                 queue_mask = ~0ULL;
 604
 605         kiq->pmf->kiq_set_resources(kiq_ring, queue_mask);
 606         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 607                 j = i + xcc_id * adev->gfx.num_compute_rings;
 608                         kiq->pmf->kiq_map_queues(kiq_ring,
 609                                                  &adev->gfx.compute_ring[j]);
 610         }
 611
 612         r = amdgpu_ring_test_helper(kiq_ring);
 613         spin_unlock(&kiq->ring_lock);
 614         if (r)
 615                 DRM_ERROR("KCQ enable failed\n");
 616
 617         return r;
 618 }
 619
 620 int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id)
 621 {
 622         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 623         struct amdgpu_ring *kiq_ring = &kiq->ring;
 624         int r, i, j;
 625
 626         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
 627                 return -EINVAL;
 628
 629         spin_lock(&kiq->ring_lock);
 630         /* No need to map kcq on the slave */
 631         if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {
 632                 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
 633                                                 adev->gfx.num_gfx_rings);
 634                 if (r) {
 635                         DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 636                         spin_unlock(&kiq->ring_lock);
 637                         return r;
 638                 }
 639
 640                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 641                         j = i + xcc_id * adev->gfx.num_gfx_rings;
 642                         kiq->pmf->kiq_map_queues(kiq_ring,
 643                                                  &adev->gfx.gfx_ring[i]);
 644                 }
 645         }
 646
 647         r = amdgpu_ring_test_helper(kiq_ring);
 648         spin_unlock(&kiq->ring_lock);
 649         if (r)
 650                 DRM_ERROR("KCQ enable failed\n");
 651
 652         return r;
 653 }
 654
 655 /* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
 656  *
 657  * @adev: amdgpu_device pointer
 658  * @bool enable true: enable gfx off feature, false: disable gfx off feature
 659  *
 660  * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled.
 661  * 2. other client can send request to disable gfx off feature, the request should be honored.
 662  * 3. other client can cancel their request of disable gfx off feature
 663  * 4. other client should not send request to enable gfx off feature before disable gfx off feature.
 664  */
 665
 666 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
 667 {
 668         unsigned long delay = GFX_OFF_DELAY_ENABLE;
 669
 670         if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 671                 return;
 672
 673         mutex_lock(&adev->gfx.gfx_off_mutex);
 674
 675         if (enable) {
 676                 /* If the count is already 0, it means there's an imbalance bug somewhere.
 677                  * Note that the bug may be in a different caller than the one which triggers the
 678                  * WARN_ON_ONCE.
 679                  */
 680                 if (WARN_ON_ONCE(adev->gfx.gfx_off_req_count == 0))
 681                         goto unlock;
 682
 683                 adev->gfx.gfx_off_req_count--;
 684
 685                 if (adev->gfx.gfx_off_req_count == 0 &&
 686                     !adev->gfx.gfx_off_state) {
 687                         /* If going to s2idle, no need to wait */
 688                         if (adev->in_s0ix) {
 689                                 if (!amdgpu_dpm_set_powergating_by_smu(adev,
 690                                                 AMD_IP_BLOCK_TYPE_GFX, true))
 691                                         adev->gfx.gfx_off_state = true;
 692                         } else {
 693                                 schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
 694                                               delay);
 695                         }
 696                 }
 697         } else {
 698                 if (adev->gfx.gfx_off_req_count == 0) {
 699                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
 700
 701                         if (adev->gfx.gfx_off_state &&
 702                             !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {
 703                                 adev->gfx.gfx_off_state = false;
 704
 705                                 if (adev->gfx.funcs->init_spm_golden) {
 706                                         dev_dbg(adev->dev,
 707                                                 "GFXOFF is disabled, re-init SPM golden settings\n");
 708                                         amdgpu_gfx_init_spm_golden(adev);
 709                                 }
 710                         }
 711                 }
 712
 713                 adev->gfx.gfx_off_req_count++;
 714         }
 715
 716 unlock:
 717         mutex_unlock(&adev->gfx.gfx_off_mutex);
 718 }
 719
 720 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value)
 721 {
 722         int r = 0;
 723
 724         mutex_lock(&adev->gfx.gfx_off_mutex);
 725
 726         r = amdgpu_dpm_set_residency_gfxoff(adev, value);
 727
 728         mutex_unlock(&adev->gfx.gfx_off_mutex);
 729
 730         return r;
 731 }
 732
 733 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *value)
 734 {
 735         int r = 0;
 736
 737         mutex_lock(&adev->gfx.gfx_off_mutex);
 738
 739         r = amdgpu_dpm_get_residency_gfxoff(adev, value);
 740
 741         mutex_unlock(&adev->gfx.gfx_off_mutex);
 742
 743         return r;
 744 }
 745
 746 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value)
 747 {
 748         int r = 0;
 749
 750         mutex_lock(&adev->gfx.gfx_off_mutex);
 751
 752         r = amdgpu_dpm_get_entrycount_gfxoff(adev, value);
 753
 754         mutex_unlock(&adev->gfx.gfx_off_mutex);
 755
 756         return r;
 757 }
 758
 759 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value)
 760 {
 761
 762         int r = 0;
 763
 764         mutex_lock(&adev->gfx.gfx_off_mutex);
 765
 766         r = amdgpu_dpm_get_status_gfxoff(adev, value);
 767
 768         mutex_unlock(&adev->gfx.gfx_off_mutex);
 769
 770         return r;
 771 }
 772
 773 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 774 {
 775         int r;
 776
 777         if (amdgpu_ras_is_supported(adev, ras_block->block)) {
 778                 if (!amdgpu_persistent_edc_harvesting_supported(adev))
 779                         amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX);
 780
 781                 r = amdgpu_ras_block_late_init(adev, ras_block);
 782                 if (r)
 783                         return r;
 784
 785                 if (adev->gfx.cp_ecc_error_irq.funcs) {
 786                         r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
 787                         if (r)
 788                                 goto late_fini;
 789                 }
 790         } else {
 791                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
 792         }
 793
 794         return 0;
 795 late_fini:
 796         amdgpu_ras_block_late_fini(adev, ras_block);
 797         return r;
 798 }
 799
 800 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev)
 801 {
 802         int err = 0;
 803         struct amdgpu_gfx_ras *ras = NULL;
 804
 805         /* adev->gfx.ras is NULL, which means gfx does not
 806          * support ras function, then do nothing here.
 807          */
 808         if (!adev->gfx.ras)
 809                 return 0;
 810
 811         ras = adev->gfx.ras;
 812
 813         err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
 814         if (err) {
 815                 dev_err(adev->dev, "Failed to register gfx ras block!\n");
 816                 return err;
 817         }
 818
 819         strcpy(ras->ras_block.ras_comm.name, "gfx");
 820         ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX;
 821         ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 822         adev->gfx.ras_if = &ras->ras_block.ras_comm;
 823
 824         /* If not define special ras_late_init function, use gfx default ras_late_init */
 825         if (!ras->ras_block.ras_late_init)
 826                 ras->ras_block.ras_late_init = amdgpu_gfx_ras_late_init;
 827
 828         /* If not defined special ras_cb function, use default ras_cb */
 829         if (!ras->ras_block.ras_cb)
 830                 ras->ras_block.ras_cb = amdgpu_gfx_process_ras_data_cb;
 831
 832         return 0;
 833 }
 834
 835 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev,
 836                                                 struct amdgpu_iv_entry *entry)
 837 {
 838         if (adev->gfx.ras && adev->gfx.ras->poison_consumption_handler)
 839                 return adev->gfx.ras->poison_consumption_handler(adev, entry);
 840
 841         return 0;
 842 }
 843
 844 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
 845                 void *err_data,
 846                 struct amdgpu_iv_entry *entry)
 847 {
 848         /* TODO ue will trigger an interrupt.
 849          *
 850          * When “Full RAS” is enabled, the per-IP interrupt sources should
 851          * be disabled and the driver should only look for the aggregated
 852          * interrupt via sync flood
 853          */
 854         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
 855                 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
 856                 if (adev->gfx.ras && adev->gfx.ras->ras_block.hw_ops &&
 857                     adev->gfx.ras->ras_block.hw_ops->query_ras_error_count)
 858                         adev->gfx.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
 859                 amdgpu_ras_reset_gpu(adev);
 860         }
 861         return AMDGPU_RAS_SUCCESS;
 862 }
 863
 864 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
 865                                   struct amdgpu_irq_src *source,
 866                                   struct amdgpu_iv_entry *entry)
 867 {
 868         struct ras_common_if *ras_if = adev->gfx.ras_if;
 869         struct ras_dispatch_if ih_data = {
 870                 .entry = entry,
 871         };
 872
 873         if (!ras_if)
 874                 return 0;
 875
 876         ih_data.head = *ras_if;
 877
 878         DRM_ERROR("CP ECC ERROR IRQ\n");
 879         amdgpu_ras_interrupt_dispatch(adev, &ih_data);
 880         return 0;
 881 }
 882
 883 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
 884 {
 885         signed long r, cnt = 0;
 886         unsigned long flags;
 887         uint32_t seq, reg_val_offs = 0, value = 0;
 888         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 889         struct amdgpu_ring *ring = &kiq->ring;
 890
 891         if (amdgpu_device_skip_hw_access(adev))
 892                 return 0;
 893
 894         if (adev->mes.ring.sched.ready)
 895                 return amdgpu_mes_rreg(adev, reg);
 896
 897         BUG_ON(!ring->funcs->emit_rreg);
 898
 899         spin_lock_irqsave(&kiq->ring_lock, flags);
 900         if (amdgpu_device_wb_get(adev, &reg_val_offs)) {
 901                 pr_err("critical bug! too many kiq readers\n");
 902                 goto failed_unlock;
 903         }
 904         amdgpu_ring_alloc(ring, 32);
 905         amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
 906         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 907         if (r)
 908                 goto failed_undo;
 909
 910         amdgpu_ring_commit(ring);
 911         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 912
 913         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 914
 915         /* don't wait anymore for gpu reset case because this way may
 916          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
 917          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
 918          * never return if we keep waiting in virt_kiq_rreg, which cause
 919          * gpu_recover() hang there.
 920          *
 921          * also don't wait anymore for IRQ context
 922          * */
 923         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
 924                 goto failed_kiq_read;
 925
 926         might_sleep();
 927         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 928                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 929                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 930         }
 931
 932         if (cnt > MAX_KIQ_REG_TRY)
 933                 goto failed_kiq_read;
 934
 935         mb();
 936         value = adev->wb.wb[reg_val_offs];
 937         amdgpu_device_wb_free(adev, reg_val_offs);
 938         return value;
 939
 940 failed_undo:
 941         amdgpu_ring_undo(ring);
 942 failed_unlock:
 943         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 944 failed_kiq_read:
 945         if (reg_val_offs)
 946                 amdgpu_device_wb_free(adev, reg_val_offs);
 947         dev_err(adev->dev, "failed to read reg:%x\n", reg);
 948         return ~0;
 949 }
 950
 951 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 952 {
 953         signed long r, cnt = 0;
 954         unsigned long flags;
 955         uint32_t seq;
 956         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 957         struct amdgpu_ring *ring = &kiq->ring;
 958
 959         BUG_ON(!ring->funcs->emit_wreg);
 960
 961         if (amdgpu_device_skip_hw_access(adev))
 962                 return;
 963
 964         if (adev->mes.ring.sched.ready) {
 965                 amdgpu_mes_wreg(adev, reg, v);
 966                 return;
 967         }
 968
 969         spin_lock_irqsave(&kiq->ring_lock, flags);
 970         amdgpu_ring_alloc(ring, 32);
 971         amdgpu_ring_emit_wreg(ring, reg, v);
 972         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 973         if (r)
 974                 goto failed_undo;
 975
 976         amdgpu_ring_commit(ring);
 977         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 978
 979         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 980
 981         /* don't wait anymore for gpu reset case because this way may
 982          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
 983          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
 984          * never return if we keep waiting in virt_kiq_rreg, which cause
 985          * gpu_recover() hang there.
 986          *
 987          * also don't wait anymore for IRQ context
 988          * */
 989         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
 990                 goto failed_kiq_write;
 991
 992         might_sleep();
 993         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 994
 995                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 996                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 997         }
 998
 999         if (cnt > MAX_KIQ_REG_TRY)
1000                 goto failed_kiq_write;
1001
1002         return;
1003
1004 failed_undo:
1005         amdgpu_ring_undo(ring);
1006         spin_unlock_irqrestore(&kiq->ring_lock, flags);
1007 failed_kiq_write:
1008         dev_err(adev->dev, "failed to write reg:%x\n", reg);
1009 }
1010
1011 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
1012 {
1013         if (amdgpu_num_kcq == -1) {
1014                 return 8;
1015         } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
1016                 dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");
1017                 return 8;
1018         }
1019         return amdgpu_num_kcq;
1020 }
1021
1022 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev,
1023                                   uint32_t ucode_id)
1024 {
1025         const struct gfx_firmware_header_v1_0 *cp_hdr;
1026         const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0;
1027         struct amdgpu_firmware_info *info = NULL;
1028         const struct firmware *ucode_fw;
1029         unsigned int fw_size;
1030
1031         switch (ucode_id) {
1032         case AMDGPU_UCODE_ID_CP_PFP:
1033                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1034                         adev->gfx.pfp_fw->data;
1035                 adev->gfx.pfp_fw_version =
1036                         le32_to_cpu(cp_hdr->header.ucode_version);
1037                 adev->gfx.pfp_feature_version =
1038                         le32_to_cpu(cp_hdr->ucode_feature_version);
1039                 ucode_fw = adev->gfx.pfp_fw;
1040                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1041                 break;
1042         case AMDGPU_UCODE_ID_CP_RS64_PFP:
1043                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1044                         adev->gfx.pfp_fw->data;
1045                 adev->gfx.pfp_fw_version =
1046                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1047                 adev->gfx.pfp_feature_version =
1048                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1049                 ucode_fw = adev->gfx.pfp_fw;
1050                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1051                 break;
1052         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
1053         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
1054                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1055                         adev->gfx.pfp_fw->data;
1056                 ucode_fw = adev->gfx.pfp_fw;
1057                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1058                 break;
1059         case AMDGPU_UCODE_ID_CP_ME:
1060                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1061                         adev->gfx.me_fw->data;
1062                 adev->gfx.me_fw_version =
1063                         le32_to_cpu(cp_hdr->header.ucode_version);
1064                 adev->gfx.me_feature_version =
1065                         le32_to_cpu(cp_hdr->ucode_feature_version);
1066                 ucode_fw = adev->gfx.me_fw;
1067                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1068                 break;
1069         case AMDGPU_UCODE_ID_CP_RS64_ME:
1070                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1071                         adev->gfx.me_fw->data;
1072                 adev->gfx.me_fw_version =
1073                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1074                 adev->gfx.me_feature_version =
1075                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1076                 ucode_fw = adev->gfx.me_fw;
1077                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1078                 break;
1079         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
1080         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
1081                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1082                         adev->gfx.me_fw->data;
1083                 ucode_fw = adev->gfx.me_fw;
1084                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1085                 break;
1086         case AMDGPU_UCODE_ID_CP_CE:
1087                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1088                         adev->gfx.ce_fw->data;
1089                 adev->gfx.ce_fw_version =
1090                         le32_to_cpu(cp_hdr->header.ucode_version);
1091                 adev->gfx.ce_feature_version =
1092                         le32_to_cpu(cp_hdr->ucode_feature_version);
1093                 ucode_fw = adev->gfx.ce_fw;
1094                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1095                 break;
1096         case AMDGPU_UCODE_ID_CP_MEC1:
1097                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1098                         adev->gfx.mec_fw->data;
1099                 adev->gfx.mec_fw_version =
1100                         le32_to_cpu(cp_hdr->header.ucode_version);
1101                 adev->gfx.mec_feature_version =
1102                         le32_to_cpu(cp_hdr->ucode_feature_version);
1103                 ucode_fw = adev->gfx.mec_fw;
1104                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1105                           le32_to_cpu(cp_hdr->jt_size) * 4;
1106                 break;
1107         case AMDGPU_UCODE_ID_CP_MEC1_JT:
1108                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1109                         adev->gfx.mec_fw->data;
1110                 ucode_fw = adev->gfx.mec_fw;
1111                 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
1112                 break;
1113         case AMDGPU_UCODE_ID_CP_MEC2:
1114                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1115                         adev->gfx.mec2_fw->data;
1116                 adev->gfx.mec2_fw_version =
1117                         le32_to_cpu(cp_hdr->header.ucode_version);
1118                 adev->gfx.mec2_feature_version =
1119                         le32_to_cpu(cp_hdr->ucode_feature_version);
1120                 ucode_fw = adev->gfx.mec2_fw;
1121                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1122                           le32_to_cpu(cp_hdr->jt_size) * 4;
1123                 break;
1124         case AMDGPU_UCODE_ID_CP_MEC2_JT:
1125                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1126                         adev->gfx.mec2_fw->data;
1127                 ucode_fw = adev->gfx.mec2_fw;
1128                 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
1129                 break;
1130         case AMDGPU_UCODE_ID_CP_RS64_MEC:
1131                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1132                         adev->gfx.mec_fw->data;
1133                 adev->gfx.mec_fw_version =
1134                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1135                 adev->gfx.mec_feature_version =
1136                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1137                 ucode_fw = adev->gfx.mec_fw;
1138                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1139                 break;
1140         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
1141         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
1142         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
1143         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
1144                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1145                         adev->gfx.mec_fw->data;
1146                 ucode_fw = adev->gfx.mec_fw;
1147                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1148                 break;
1149         default:
1150                 break;
1151         }
1152
1153         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1154                 info = &adev->firmware.ucode[ucode_id];
1155                 info->ucode_id = ucode_id;
1156                 info->fw = ucode_fw;
1157                 adev->firmware.fw_size += ALIGN(fw_size, PAGE_SIZE);
1158         }
1159 }
1160
1161 bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id)
1162 {
1163         return !(xcc_id % (adev->gfx.num_xcc_per_xcp ?
1164                         adev->gfx.num_xcc_per_xcp : 1));
1165 }
1166
1167 static ssize_t amdgpu_gfx_get_current_compute_partition(struct device *dev,
1168                                                 struct device_attribute *addr,
1169                                                 char *buf)
1170 {
1171         struct drm_device *ddev = dev_get_drvdata(dev);
1172         struct amdgpu_device *adev = drm_to_adev(ddev);
1173         enum amdgpu_gfx_partition mode;
1174         char *partition_mode;
1175
1176         mode = adev->gfx.funcs->query_partition_mode(adev);
1177
1178         switch (mode) {
1179         case AMDGPU_SPX_PARTITION_MODE:
1180                 partition_mode = "SPX";
1181                 break;
1182         case AMDGPU_DPX_PARTITION_MODE:
1183                 partition_mode = "DPX";
1184                 break;
1185         case AMDGPU_TPX_PARTITION_MODE:
1186                 partition_mode = "TPX";
1187                 break;
1188         case AMDGPU_QPX_PARTITION_MODE:
1189                 partition_mode = "QPX";
1190                 break;
1191         case AMDGPU_CPX_PARTITION_MODE:
1192                 partition_mode = "CPX";
1193                 break;
1194         default:
1195                 partition_mode = "UNKNOWN";
1196                 break;
1197         }
1198
1199         return sysfs_emit(buf, "%s\n", partition_mode);
1200 }
1201
1202 static ssize_t amdgpu_gfx_get_current_memory_partition(struct device *dev,
1203                                                 struct device_attribute *addr,
1204                                                 char *buf)
1205 {
1206         struct drm_device *ddev = dev_get_drvdata(dev);
1207         struct amdgpu_device *adev = drm_to_adev(ddev);
1208         enum amdgpu_memory_partition mode;
1209         static const char *partition_modes[] = {
1210                 "UNKNOWN", "NPS1", "NPS2", "NPS4", "NPS8"
1211         };
1212         BUILD_BUG_ON(ARRAY_SIZE(partition_modes) <= AMDGPU_NPS8_PARTITION_MODE);
1213
1214         mode = min((int)adev->gfx.funcs->query_mem_partition_mode(adev),
1215                 AMDGPU_NPS8_PARTITION_MODE);
1216
1217         return sysfs_emit(buf, "%s\n", partition_modes[mode]);
1218 }
1219
1220 static ssize_t amdgpu_gfx_set_compute_partition(struct device *dev,
1221                                                 struct device_attribute *addr,
1222                                                 const char *buf, size_t count)
1223 {
1224         struct drm_device *ddev = dev_get_drvdata(dev);
1225         struct amdgpu_device *adev = drm_to_adev(ddev);
1226         enum amdgpu_gfx_partition mode;
1227         int ret = 0, num_xcc;
1228
1229         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1230         if (num_xcc % 2 != 0)
1231                 return -EINVAL;
1232
1233         if (!strncasecmp("SPX", buf, strlen("SPX"))) {
1234                 mode = AMDGPU_SPX_PARTITION_MODE;
1235         } else if (!strncasecmp("DPX", buf, strlen("DPX"))) {
1236                 /*
1237                  * DPX mode needs AIDs to be in multiple of 2.
1238                  * Each AID connects 2 XCCs.
1239                  */
1240                 if (num_xcc%4)
1241                         return -EINVAL;
1242                 mode = AMDGPU_DPX_PARTITION_MODE;
1243         } else if (!strncasecmp("TPX", buf, strlen("TPX"))) {
1244                 if (num_xcc != 6)
1245                         return -EINVAL;
1246                 mode = AMDGPU_TPX_PARTITION_MODE;
1247         } else if (!strncasecmp("QPX", buf, strlen("QPX"))) {
1248                 if (num_xcc != 8)
1249                         return -EINVAL;
1250                 mode = AMDGPU_QPX_PARTITION_MODE;
1251         } else if (!strncasecmp("CPX", buf, strlen("CPX"))) {
1252                 mode = AMDGPU_CPX_PARTITION_MODE;
1253         } else {
1254                 return -EINVAL;
1255         }
1256
1257         if (!adev->kfd.init_complete)
1258                 return -EPERM;
1259
1260         mutex_lock(&adev->gfx.partition_mutex);
1261
1262         if (mode == adev->gfx.funcs->query_partition_mode(adev))
1263                 goto out;
1264
1265         ret = amdgpu_amdkfd_check_and_lock_kfd(adev);
1266         if (ret)
1267                 goto out;
1268
1269         amdgpu_amdkfd_device_fini_sw(adev);
1270
1271         adev->gfx.funcs->switch_partition_mode(adev, mode);
1272
1273         amdgpu_amdkfd_device_probe(adev);
1274         amdgpu_amdkfd_device_init(adev);
1275         /* If KFD init failed, return failure */
1276         if (!adev->kfd.init_complete)
1277                 ret = -EIO;
1278
1279         amdgpu_amdkfd_unlock_kfd(adev);
1280 out:
1281         mutex_unlock(&adev->gfx.partition_mutex);
1282
1283         if (ret)
1284                 return ret;
1285
1286         return count;
1287 }
1288
1289 static ssize_t amdgpu_gfx_get_available_compute_partition(struct device *dev,
1290                                                 struct device_attribute *addr,
1291                                                 char *buf)
1292 {
1293         struct drm_device *ddev = dev_get_drvdata(dev);
1294         struct amdgpu_device *adev = drm_to_adev(ddev);
1295         char *supported_partition;
1296
1297         /* TBD */
1298         switch (NUM_XCC(adev->gfx.xcc_mask)) {
1299         case 8:
1300                 supported_partition = "SPX, DPX, QPX, CPX";
1301                 break;
1302         case 6:
1303                 supported_partition = "SPX, TPX, CPX";
1304                 break;
1305         case 4:
1306                 supported_partition = "SPX, DPX, CPX";
1307                 break;
1308         /* this seems only existing in emulation phase */
1309         case 2:
1310                 supported_partition = "SPX, CPX";
1311                 break;
1312         default:
1313                 supported_partition = "Not supported";
1314                 break;
1315         }
1316
1317         return sysfs_emit(buf, "%s\n", supported_partition);
1318 }
1319
1320 static DEVICE_ATTR(current_compute_partition, S_IRUGO | S_IWUSR,
1321                    amdgpu_gfx_get_current_compute_partition,
1322                    amdgpu_gfx_set_compute_partition);
1323
1324 static DEVICE_ATTR(available_compute_partition, S_IRUGO,
1325                    amdgpu_gfx_get_available_compute_partition, NULL);
1326
1327 static DEVICE_ATTR(current_memory_partition, S_IRUGO,
1328                    amdgpu_gfx_get_current_memory_partition, NULL);
1329
1330 int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev)
1331 {
1332         int r;
1333
1334         r = device_create_file(adev->dev, &dev_attr_current_compute_partition);
1335         if (r)
1336                 return r;
1337
1338         r = device_create_file(adev->dev, &dev_attr_available_compute_partition);
1339         if (r)
1340                 return r;
1341
1342         r = device_create_file(adev->dev, &dev_attr_current_memory_partition);
1343         if (r)
1344                 return r;
1345
1346         return 0;
1347 }