2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/hdmi.h>
32 #include <linux/i2c.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/slab.h>
36 #include <linux/vga_switcheroo.h>
38 #include <drm/drm_displayid.h>
39 #include <drm/drm_drv.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_encoder.h>
42 #include <drm/drm_print.h>
43 #include <drm/drm_scdc_helper.h>
45 #include "drm_crtc_internal.h"
47 #define version_greater(edid, maj, min) \
48 (((edid)->version > (maj)) || \
49 ((edid)->version == (maj) && (edid)->revision > (min)))
51 #define EDID_EST_TIMINGS 16
52 #define EDID_STD_TIMINGS 8
53 #define EDID_DETAILED_TIMINGS 4
56 * EDID blocks out in the wild have a variety of bugs, try to collect
57 * them here (note that userspace may work around broken monitors first,
58 * but fixes should make their way here so that the kernel "just works"
59 * on as many displays as possible).
62 /* First detailed mode wrong, use largest 60Hz mode */
63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
64 /* Reported 135MHz pixel clock is too high, needs adjustment */
65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
66 /* Prefer the largest mode at 75 Hz */
67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
68 /* Detail timing is in cm not mm */
69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
70 /* Detailed timing descriptors have bogus size values, so just take the
71 * maximum size and use that.
73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
74 /* use +hsync +vsync for detailed mode */
75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
76 /* Force reduced-blanking timings for detailed modes */
77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
79 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
81 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
83 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
85 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
86 /* Non desktop display (i.e. HMD) */
87 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
89 struct detailed_mode_closure {
90 struct drm_connector *connector;
102 static const struct edid_quirk {
106 } edid_quirk_list[] = {
108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
127 /* Belinea 10 15 55 */
128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
131 /* Envision Peripherals, Inc. EN-7100e */
132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
133 /* Envision EN2028 */
134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
136 /* Funai Electronics PM36B */
137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
138 EDID_QUIRK_DETAILED_IN_CM },
140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
143 /* LG Philips LCD LP154W01-A5 */
144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
147 /* Samsung SyncMaster 205BW. Note: irony */
148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
149 /* Samsung SyncMaster 22[5-6]BW */
150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
156 /* ViewSonic VA2026w */
157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
159 /* Medion MD 30217 PG */
160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
162 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
163 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
165 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
166 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
168 /* Valve Index Headset */
169 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
170 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
171 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
172 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
173 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
174 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
175 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
176 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
177 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
178 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
179 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
180 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
181 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
182 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
183 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
184 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
185 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
187 /* HTC Vive and Vive Pro VR Headsets */
188 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
189 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
191 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */
192 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
193 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
194 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
196 /* Windows Mixed Reality Headsets */
197 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
198 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
199 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
200 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
201 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
202 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
203 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
204 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
206 /* Sony PlayStation VR Headset */
207 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
209 /* Sensics VR Headsets */
210 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
212 /* OSVR HDK and HDK2 VR Headsets */
213 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
217 * Autogenerated from the DMT spec.
218 * This table is copied from xfree86/modes/xf86EdidModes.c.
220 static const struct drm_display_mode drm_dmt_modes[] = {
221 /* 0x01 - 640x350@85Hz */
222 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
223 736, 832, 0, 350, 382, 385, 445, 0,
224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
225 /* 0x02 - 640x400@85Hz */
226 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
227 736, 832, 0, 400, 401, 404, 445, 0,
228 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
229 /* 0x03 - 720x400@85Hz */
230 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
231 828, 936, 0, 400, 401, 404, 446, 0,
232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
233 /* 0x04 - 640x480@60Hz */
234 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
235 752, 800, 0, 480, 490, 492, 525, 0,
236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
237 /* 0x05 - 640x480@72Hz */
238 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
239 704, 832, 0, 480, 489, 492, 520, 0,
240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
241 /* 0x06 - 640x480@75Hz */
242 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
243 720, 840, 0, 480, 481, 484, 500, 0,
244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
245 /* 0x07 - 640x480@85Hz */
246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
247 752, 832, 0, 480, 481, 484, 509, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
249 /* 0x08 - 800x600@56Hz */
250 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
251 896, 1024, 0, 600, 601, 603, 625, 0,
252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
253 /* 0x09 - 800x600@60Hz */
254 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
255 968, 1056, 0, 600, 601, 605, 628, 0,
256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
257 /* 0x0a - 800x600@72Hz */
258 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
259 976, 1040, 0, 600, 637, 643, 666, 0,
260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
261 /* 0x0b - 800x600@75Hz */
262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
263 896, 1056, 0, 600, 601, 604, 625, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
265 /* 0x0c - 800x600@85Hz */
266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
267 896, 1048, 0, 600, 601, 604, 631, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
269 /* 0x0d - 800x600@120Hz RB */
270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
271 880, 960, 0, 600, 603, 607, 636, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
273 /* 0x0e - 848x480@60Hz */
274 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
275 976, 1088, 0, 480, 486, 494, 517, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
277 /* 0x0f - 1024x768@43Hz, interlace */
278 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
279 1208, 1264, 0, 768, 768, 776, 817, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
281 DRM_MODE_FLAG_INTERLACE) },
282 /* 0x10 - 1024x768@60Hz */
283 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
284 1184, 1344, 0, 768, 771, 777, 806, 0,
285 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
286 /* 0x11 - 1024x768@70Hz */
287 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
288 1184, 1328, 0, 768, 771, 777, 806, 0,
289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
290 /* 0x12 - 1024x768@75Hz */
291 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
292 1136, 1312, 0, 768, 769, 772, 800, 0,
293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
294 /* 0x13 - 1024x768@85Hz */
295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
296 1168, 1376, 0, 768, 769, 772, 808, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
298 /* 0x14 - 1024x768@120Hz RB */
299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
300 1104, 1184, 0, 768, 771, 775, 813, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
302 /* 0x15 - 1152x864@75Hz */
303 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
304 1344, 1600, 0, 864, 865, 868, 900, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
306 /* 0x55 - 1280x720@60Hz */
307 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
308 1430, 1650, 0, 720, 725, 730, 750, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
310 /* 0x16 - 1280x768@60Hz RB */
311 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
312 1360, 1440, 0, 768, 771, 778, 790, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
314 /* 0x17 - 1280x768@60Hz */
315 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
316 1472, 1664, 0, 768, 771, 778, 798, 0,
317 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
318 /* 0x18 - 1280x768@75Hz */
319 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
320 1488, 1696, 0, 768, 771, 778, 805, 0,
321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 0x19 - 1280x768@85Hz */
323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
324 1496, 1712, 0, 768, 771, 778, 809, 0,
325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
326 /* 0x1a - 1280x768@120Hz RB */
327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
328 1360, 1440, 0, 768, 771, 778, 813, 0,
329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
330 /* 0x1b - 1280x800@60Hz RB */
331 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
332 1360, 1440, 0, 800, 803, 809, 823, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
334 /* 0x1c - 1280x800@60Hz */
335 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
336 1480, 1680, 0, 800, 803, 809, 831, 0,
337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
338 /* 0x1d - 1280x800@75Hz */
339 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
340 1488, 1696, 0, 800, 803, 809, 838, 0,
341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 0x1e - 1280x800@85Hz */
343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
344 1496, 1712, 0, 800, 803, 809, 843, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 0x1f - 1280x800@120Hz RB */
347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
348 1360, 1440, 0, 800, 803, 809, 847, 0,
349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
350 /* 0x20 - 1280x960@60Hz */
351 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
352 1488, 1800, 0, 960, 961, 964, 1000, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
354 /* 0x21 - 1280x960@85Hz */
355 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
356 1504, 1728, 0, 960, 961, 964, 1011, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 0x22 - 1280x960@120Hz RB */
359 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
360 1360, 1440, 0, 960, 963, 967, 1017, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
362 /* 0x23 - 1280x1024@60Hz */
363 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
364 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
366 /* 0x24 - 1280x1024@75Hz */
367 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
368 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 0x25 - 1280x1024@85Hz */
371 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
372 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
374 /* 0x26 - 1280x1024@120Hz RB */
375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
376 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
378 /* 0x27 - 1360x768@60Hz */
379 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
380 1536, 1792, 0, 768, 771, 777, 795, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
382 /* 0x28 - 1360x768@120Hz RB */
383 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
384 1440, 1520, 0, 768, 771, 776, 813, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
386 /* 0x51 - 1366x768@60Hz */
387 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
388 1579, 1792, 0, 768, 771, 774, 798, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
390 /* 0x56 - 1366x768@60Hz */
391 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
392 1436, 1500, 0, 768, 769, 772, 800, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x29 - 1400x1050@60Hz RB */
395 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
396 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
398 /* 0x2a - 1400x1050@60Hz */
399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
400 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
401 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
402 /* 0x2b - 1400x1050@75Hz */
403 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
404 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
406 /* 0x2c - 1400x1050@85Hz */
407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
408 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
410 /* 0x2d - 1400x1050@120Hz RB */
411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
412 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
414 /* 0x2e - 1440x900@60Hz RB */
415 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
416 1520, 1600, 0, 900, 903, 909, 926, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
418 /* 0x2f - 1440x900@60Hz */
419 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
420 1672, 1904, 0, 900, 903, 909, 934, 0,
421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
422 /* 0x30 - 1440x900@75Hz */
423 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
424 1688, 1936, 0, 900, 903, 909, 942, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 0x31 - 1440x900@85Hz */
427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
428 1696, 1952, 0, 900, 903, 909, 948, 0,
429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
430 /* 0x32 - 1440x900@120Hz RB */
431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
432 1520, 1600, 0, 900, 903, 909, 953, 0,
433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
434 /* 0x53 - 1600x900@60Hz */
435 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
436 1704, 1800, 0, 900, 901, 904, 1000, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
438 /* 0x33 - 1600x1200@60Hz */
439 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
440 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 0x34 - 1600x1200@65Hz */
443 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
444 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
446 /* 0x35 - 1600x1200@70Hz */
447 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
448 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 0x36 - 1600x1200@75Hz */
451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
454 /* 0x37 - 1600x1200@85Hz */
455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 0x38 - 1600x1200@120Hz RB */
459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
460 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
462 /* 0x39 - 1680x1050@60Hz RB */
463 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
464 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
466 /* 0x3a - 1680x1050@60Hz */
467 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
468 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
469 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
470 /* 0x3b - 1680x1050@75Hz */
471 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
472 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 0x3c - 1680x1050@85Hz */
475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
476 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
478 /* 0x3d - 1680x1050@120Hz RB */
479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
480 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
482 /* 0x3e - 1792x1344@60Hz */
483 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
484 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
486 /* 0x3f - 1792x1344@75Hz */
487 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
488 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
490 /* 0x40 - 1792x1344@120Hz RB */
491 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
492 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
494 /* 0x41 - 1856x1392@60Hz */
495 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
496 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
498 /* 0x42 - 1856x1392@75Hz */
499 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
500 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
502 /* 0x43 - 1856x1392@120Hz RB */
503 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
504 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
506 /* 0x52 - 1920x1080@60Hz */
507 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
508 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
510 /* 0x44 - 1920x1200@60Hz RB */
511 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
512 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
514 /* 0x45 - 1920x1200@60Hz */
515 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
516 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
518 /* 0x46 - 1920x1200@75Hz */
519 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
520 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
522 /* 0x47 - 1920x1200@85Hz */
523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
524 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
526 /* 0x48 - 1920x1200@120Hz RB */
527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
528 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
530 /* 0x49 - 1920x1440@60Hz */
531 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
532 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
534 /* 0x4a - 1920x1440@75Hz */
535 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
536 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
538 /* 0x4b - 1920x1440@120Hz RB */
539 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
540 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
542 /* 0x54 - 2048x1152@60Hz */
543 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
544 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
546 /* 0x4c - 2560x1600@60Hz RB */
547 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
548 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
550 /* 0x4d - 2560x1600@60Hz */
551 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
552 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
554 /* 0x4e - 2560x1600@75Hz */
555 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
556 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
558 /* 0x4f - 2560x1600@85Hz */
559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
560 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
562 /* 0x50 - 2560x1600@120Hz RB */
563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
564 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
566 /* 0x57 - 4096x2160@60Hz RB */
567 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
568 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
572 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
577 * These more or less come from the DMT spec. The 720x400 modes are
578 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
579 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
580 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
583 * The DMT modes have been fact-checked; the rest are mild guesses.
585 static const struct drm_display_mode edid_est_modes[] = {
586 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
587 968, 1056, 0, 600, 601, 605, 628, 0,
588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
589 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
590 896, 1024, 0, 600, 601, 603, 625, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
592 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
593 720, 840, 0, 480, 481, 484, 500, 0,
594 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
595 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
596 704, 832, 0, 480, 489, 492, 520, 0,
597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
598 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
599 768, 864, 0, 480, 483, 486, 525, 0,
600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
601 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
602 752, 800, 0, 480, 490, 492, 525, 0,
603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
604 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
605 846, 900, 0, 400, 421, 423, 449, 0,
606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
607 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
608 846, 900, 0, 400, 412, 414, 449, 0,
609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
610 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
611 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
613 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
614 1136, 1312, 0, 768, 769, 772, 800, 0,
615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
616 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
617 1184, 1328, 0, 768, 771, 777, 806, 0,
618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
619 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
620 1184, 1344, 0, 768, 771, 777, 806, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
622 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
623 1208, 1264, 0, 768, 768, 776, 817, 0,
624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
625 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
626 928, 1152, 0, 624, 625, 628, 667, 0,
627 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
628 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
629 896, 1056, 0, 600, 601, 604, 625, 0,
630 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
631 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
632 976, 1040, 0, 600, 637, 643, 666, 0,
633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
634 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
635 1344, 1600, 0, 864, 865, 868, 900, 0,
636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
646 static const struct minimode est3_modes[] = {
654 { 1024, 768, 85, 0 },
655 { 1152, 864, 75, 0 },
657 { 1280, 768, 60, 1 },
658 { 1280, 768, 60, 0 },
659 { 1280, 768, 75, 0 },
660 { 1280, 768, 85, 0 },
661 { 1280, 960, 60, 0 },
662 { 1280, 960, 85, 0 },
663 { 1280, 1024, 60, 0 },
664 { 1280, 1024, 85, 0 },
666 { 1360, 768, 60, 0 },
667 { 1440, 900, 60, 1 },
668 { 1440, 900, 60, 0 },
669 { 1440, 900, 75, 0 },
670 { 1440, 900, 85, 0 },
671 { 1400, 1050, 60, 1 },
672 { 1400, 1050, 60, 0 },
673 { 1400, 1050, 75, 0 },
675 { 1400, 1050, 85, 0 },
676 { 1680, 1050, 60, 1 },
677 { 1680, 1050, 60, 0 },
678 { 1680, 1050, 75, 0 },
679 { 1680, 1050, 85, 0 },
680 { 1600, 1200, 60, 0 },
681 { 1600, 1200, 65, 0 },
682 { 1600, 1200, 70, 0 },
684 { 1600, 1200, 75, 0 },
685 { 1600, 1200, 85, 0 },
686 { 1792, 1344, 60, 0 },
687 { 1792, 1344, 75, 0 },
688 { 1856, 1392, 60, 0 },
689 { 1856, 1392, 75, 0 },
690 { 1920, 1200, 60, 1 },
691 { 1920, 1200, 60, 0 },
693 { 1920, 1200, 75, 0 },
694 { 1920, 1200, 85, 0 },
695 { 1920, 1440, 60, 0 },
696 { 1920, 1440, 75, 0 },
699 static const struct minimode extra_modes[] = {
700 { 1024, 576, 60, 0 },
701 { 1366, 768, 60, 0 },
702 { 1600, 900, 60, 0 },
703 { 1680, 945, 60, 0 },
704 { 1920, 1080, 60, 0 },
705 { 2048, 1152, 60, 0 },
706 { 2048, 1536, 60, 0 },
710 * Probably taken from CEA-861 spec.
711 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
713 * Index using the VIC.
715 static const struct drm_display_mode edid_cea_modes[] = {
716 /* 0 - dummy, VICs start at 1 */
718 /* 1 - 640x480@60Hz 4:3 */
719 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
720 752, 800, 0, 480, 490, 492, 525, 0,
721 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
722 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
723 /* 2 - 720x480@60Hz 4:3 */
724 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
725 798, 858, 0, 480, 489, 495, 525, 0,
726 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
727 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
728 /* 3 - 720x480@60Hz 16:9 */
729 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
730 798, 858, 0, 480, 489, 495, 525, 0,
731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
732 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
733 /* 4 - 1280x720@60Hz 16:9 */
734 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
735 1430, 1650, 0, 720, 725, 730, 750, 0,
736 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
737 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
738 /* 5 - 1920x1080i@60Hz 16:9 */
739 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
740 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
741 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
742 DRM_MODE_FLAG_INTERLACE),
743 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
744 /* 6 - 720(1440)x480i@60Hz 4:3 */
745 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
746 801, 858, 0, 480, 488, 494, 525, 0,
747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
748 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
749 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
750 /* 7 - 720(1440)x480i@60Hz 16:9 */
751 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
752 801, 858, 0, 480, 488, 494, 525, 0,
753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
754 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
755 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
756 /* 8 - 720(1440)x240@60Hz 4:3 */
757 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
758 801, 858, 0, 240, 244, 247, 262, 0,
759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
760 DRM_MODE_FLAG_DBLCLK),
761 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
762 /* 9 - 720(1440)x240@60Hz 16:9 */
763 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
764 801, 858, 0, 240, 244, 247, 262, 0,
765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
766 DRM_MODE_FLAG_DBLCLK),
767 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
768 /* 10 - 2880x480i@60Hz 4:3 */
769 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
770 3204, 3432, 0, 480, 488, 494, 525, 0,
771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
772 DRM_MODE_FLAG_INTERLACE),
773 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
774 /* 11 - 2880x480i@60Hz 16:9 */
775 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
776 3204, 3432, 0, 480, 488, 494, 525, 0,
777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
778 DRM_MODE_FLAG_INTERLACE),
779 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
780 /* 12 - 2880x240@60Hz 4:3 */
781 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
782 3204, 3432, 0, 240, 244, 247, 262, 0,
783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
784 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
785 /* 13 - 2880x240@60Hz 16:9 */
786 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
787 3204, 3432, 0, 240, 244, 247, 262, 0,
788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
789 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
790 /* 14 - 1440x480@60Hz 4:3 */
791 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
792 1596, 1716, 0, 480, 489, 495, 525, 0,
793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
794 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
795 /* 15 - 1440x480@60Hz 16:9 */
796 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
797 1596, 1716, 0, 480, 489, 495, 525, 0,
798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
799 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
800 /* 16 - 1920x1080@60Hz 16:9 */
801 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
802 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
803 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
804 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
805 /* 17 - 720x576@50Hz 4:3 */
806 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
807 796, 864, 0, 576, 581, 586, 625, 0,
808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
810 /* 18 - 720x576@50Hz 16:9 */
811 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
812 796, 864, 0, 576, 581, 586, 625, 0,
813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
814 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
815 /* 19 - 1280x720@50Hz 16:9 */
816 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
817 1760, 1980, 0, 720, 725, 730, 750, 0,
818 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
819 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
820 /* 20 - 1920x1080i@50Hz 16:9 */
821 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
822 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
824 DRM_MODE_FLAG_INTERLACE),
825 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
826 /* 21 - 720(1440)x576i@50Hz 4:3 */
827 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
828 795, 864, 0, 576, 580, 586, 625, 0,
829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
830 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
831 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
832 /* 22 - 720(1440)x576i@50Hz 16:9 */
833 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
834 795, 864, 0, 576, 580, 586, 625, 0,
835 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
836 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
837 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
838 /* 23 - 720(1440)x288@50Hz 4:3 */
839 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
840 795, 864, 0, 288, 290, 293, 312, 0,
841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
842 DRM_MODE_FLAG_DBLCLK),
843 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
844 /* 24 - 720(1440)x288@50Hz 16:9 */
845 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
846 795, 864, 0, 288, 290, 293, 312, 0,
847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
848 DRM_MODE_FLAG_DBLCLK),
849 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
850 /* 25 - 2880x576i@50Hz 4:3 */
851 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
852 3180, 3456, 0, 576, 580, 586, 625, 0,
853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
854 DRM_MODE_FLAG_INTERLACE),
855 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
856 /* 26 - 2880x576i@50Hz 16:9 */
857 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
858 3180, 3456, 0, 576, 580, 586, 625, 0,
859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
860 DRM_MODE_FLAG_INTERLACE),
861 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
862 /* 27 - 2880x288@50Hz 4:3 */
863 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
864 3180, 3456, 0, 288, 290, 293, 312, 0,
865 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
866 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
867 /* 28 - 2880x288@50Hz 16:9 */
868 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
869 3180, 3456, 0, 288, 290, 293, 312, 0,
870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
871 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
872 /* 29 - 1440x576@50Hz 4:3 */
873 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
874 1592, 1728, 0, 576, 581, 586, 625, 0,
875 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
876 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
877 /* 30 - 1440x576@50Hz 16:9 */
878 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
879 1592, 1728, 0, 576, 581, 586, 625, 0,
880 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
881 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
882 /* 31 - 1920x1080@50Hz 16:9 */
883 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
884 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
886 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
887 /* 32 - 1920x1080@24Hz 16:9 */
888 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
889 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
890 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
891 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
892 /* 33 - 1920x1080@25Hz 16:9 */
893 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
894 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
895 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
896 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
897 /* 34 - 1920x1080@30Hz 16:9 */
898 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
899 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
900 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
901 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
902 /* 35 - 2880x480@60Hz 4:3 */
903 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
904 3192, 3432, 0, 480, 489, 495, 525, 0,
905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
906 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
907 /* 36 - 2880x480@60Hz 16:9 */
908 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
909 3192, 3432, 0, 480, 489, 495, 525, 0,
910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
911 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
912 /* 37 - 2880x576@50Hz 4:3 */
913 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
914 3184, 3456, 0, 576, 581, 586, 625, 0,
915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
916 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
917 /* 38 - 2880x576@50Hz 16:9 */
918 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
919 3184, 3456, 0, 576, 581, 586, 625, 0,
920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
921 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
922 /* 39 - 1920x1080i@50Hz 16:9 */
923 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
924 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
925 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
926 DRM_MODE_FLAG_INTERLACE),
927 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
928 /* 40 - 1920x1080i@100Hz 16:9 */
929 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
930 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
931 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
932 DRM_MODE_FLAG_INTERLACE),
933 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
934 /* 41 - 1280x720@100Hz 16:9 */
935 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
936 1760, 1980, 0, 720, 725, 730, 750, 0,
937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
938 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
939 /* 42 - 720x576@100Hz 4:3 */
940 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
941 796, 864, 0, 576, 581, 586, 625, 0,
942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
943 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
944 /* 43 - 720x576@100Hz 16:9 */
945 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
946 796, 864, 0, 576, 581, 586, 625, 0,
947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
948 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
949 /* 44 - 720(1440)x576i@100Hz 4:3 */
950 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
951 795, 864, 0, 576, 580, 586, 625, 0,
952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
953 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
954 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
955 /* 45 - 720(1440)x576i@100Hz 16:9 */
956 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
957 795, 864, 0, 576, 580, 586, 625, 0,
958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
959 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
960 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
961 /* 46 - 1920x1080i@120Hz 16:9 */
962 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
963 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
964 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
965 DRM_MODE_FLAG_INTERLACE),
966 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
967 /* 47 - 1280x720@120Hz 16:9 */
968 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
969 1430, 1650, 0, 720, 725, 730, 750, 0,
970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
971 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
972 /* 48 - 720x480@120Hz 4:3 */
973 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
974 798, 858, 0, 480, 489, 495, 525, 0,
975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
976 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
977 /* 49 - 720x480@120Hz 16:9 */
978 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
979 798, 858, 0, 480, 489, 495, 525, 0,
980 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
981 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
982 /* 50 - 720(1440)x480i@120Hz 4:3 */
983 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
984 801, 858, 0, 480, 488, 494, 525, 0,
985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
986 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
987 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
988 /* 51 - 720(1440)x480i@120Hz 16:9 */
989 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
990 801, 858, 0, 480, 488, 494, 525, 0,
991 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
992 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
993 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
994 /* 52 - 720x576@200Hz 4:3 */
995 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
996 796, 864, 0, 576, 581, 586, 625, 0,
997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
998 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
999 /* 53 - 720x576@200Hz 16:9 */
1000 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1001 796, 864, 0, 576, 581, 586, 625, 0,
1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1003 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1004 /* 54 - 720(1440)x576i@200Hz 4:3 */
1005 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1006 795, 864, 0, 576, 580, 586, 625, 0,
1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1008 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1009 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1010 /* 55 - 720(1440)x576i@200Hz 16:9 */
1011 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1012 795, 864, 0, 576, 580, 586, 625, 0,
1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1014 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1015 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1016 /* 56 - 720x480@240Hz 4:3 */
1017 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1018 798, 858, 0, 480, 489, 495, 525, 0,
1019 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1020 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1021 /* 57 - 720x480@240Hz 16:9 */
1022 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1023 798, 858, 0, 480, 489, 495, 525, 0,
1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1025 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1026 /* 58 - 720(1440)x480i@240Hz 4:3 */
1027 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1028 801, 858, 0, 480, 488, 494, 525, 0,
1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1030 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1031 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1032 /* 59 - 720(1440)x480i@240Hz 16:9 */
1033 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1034 801, 858, 0, 480, 488, 494, 525, 0,
1035 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1036 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1037 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1038 /* 60 - 1280x720@24Hz 16:9 */
1039 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1040 3080, 3300, 0, 720, 725, 730, 750, 0,
1041 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1042 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1043 /* 61 - 1280x720@25Hz 16:9 */
1044 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1045 3740, 3960, 0, 720, 725, 730, 750, 0,
1046 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1047 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1048 /* 62 - 1280x720@30Hz 16:9 */
1049 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1050 3080, 3300, 0, 720, 725, 730, 750, 0,
1051 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1052 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1053 /* 63 - 1920x1080@120Hz 16:9 */
1054 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1055 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1056 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1057 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1058 /* 64 - 1920x1080@100Hz 16:9 */
1059 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1060 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1061 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1062 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1063 /* 65 - 1280x720@24Hz 64:27 */
1064 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1065 3080, 3300, 0, 720, 725, 730, 750, 0,
1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1067 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1068 /* 66 - 1280x720@25Hz 64:27 */
1069 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1070 3740, 3960, 0, 720, 725, 730, 750, 0,
1071 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1072 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1073 /* 67 - 1280x720@30Hz 64:27 */
1074 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1075 3080, 3300, 0, 720, 725, 730, 750, 0,
1076 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1077 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1078 /* 68 - 1280x720@50Hz 64:27 */
1079 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1080 1760, 1980, 0, 720, 725, 730, 750, 0,
1081 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1082 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1083 /* 69 - 1280x720@60Hz 64:27 */
1084 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1085 1430, 1650, 0, 720, 725, 730, 750, 0,
1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1087 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1088 /* 70 - 1280x720@100Hz 64:27 */
1089 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1090 1760, 1980, 0, 720, 725, 730, 750, 0,
1091 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1092 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1093 /* 71 - 1280x720@120Hz 64:27 */
1094 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1095 1430, 1650, 0, 720, 725, 730, 750, 0,
1096 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1097 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1098 /* 72 - 1920x1080@24Hz 64:27 */
1099 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1100 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1102 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1103 /* 73 - 1920x1080@25Hz 64:27 */
1104 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1105 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1107 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1108 /* 74 - 1920x1080@30Hz 64:27 */
1109 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1110 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1111 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1112 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1113 /* 75 - 1920x1080@50Hz 64:27 */
1114 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1115 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1116 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1117 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1118 /* 76 - 1920x1080@60Hz 64:27 */
1119 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1120 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1121 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1122 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1123 /* 77 - 1920x1080@100Hz 64:27 */
1124 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1125 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1127 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1128 /* 78 - 1920x1080@120Hz 64:27 */
1129 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1130 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1132 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1133 /* 79 - 1680x720@24Hz 64:27 */
1134 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1135 3080, 3300, 0, 720, 725, 730, 750, 0,
1136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1137 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1138 /* 80 - 1680x720@25Hz 64:27 */
1139 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1140 2948, 3168, 0, 720, 725, 730, 750, 0,
1141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1142 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1143 /* 81 - 1680x720@30Hz 64:27 */
1144 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1145 2420, 2640, 0, 720, 725, 730, 750, 0,
1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1147 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1148 /* 82 - 1680x720@50Hz 64:27 */
1149 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1150 1980, 2200, 0, 720, 725, 730, 750, 0,
1151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1152 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1153 /* 83 - 1680x720@60Hz 64:27 */
1154 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1155 1980, 2200, 0, 720, 725, 730, 750, 0,
1156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1157 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1158 /* 84 - 1680x720@100Hz 64:27 */
1159 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1160 1780, 2000, 0, 720, 725, 730, 825, 0,
1161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1162 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1163 /* 85 - 1680x720@120Hz 64:27 */
1164 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1165 1780, 2000, 0, 720, 725, 730, 825, 0,
1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1167 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1168 /* 86 - 2560x1080@24Hz 64:27 */
1169 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1170 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1171 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1172 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1173 /* 87 - 2560x1080@25Hz 64:27 */
1174 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1175 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1177 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1178 /* 88 - 2560x1080@30Hz 64:27 */
1179 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1180 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1182 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1183 /* 89 - 2560x1080@50Hz 64:27 */
1184 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1185 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1187 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1188 /* 90 - 2560x1080@60Hz 64:27 */
1189 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1190 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1192 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1193 /* 91 - 2560x1080@100Hz 64:27 */
1194 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1195 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1197 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1198 /* 92 - 2560x1080@120Hz 64:27 */
1199 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1200 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1202 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1203 /* 93 - 3840x2160@24Hz 16:9 */
1204 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1205 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1207 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1208 /* 94 - 3840x2160@25Hz 16:9 */
1209 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1210 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1212 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1213 /* 95 - 3840x2160@30Hz 16:9 */
1214 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1215 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1217 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1218 /* 96 - 3840x2160@50Hz 16:9 */
1219 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1220 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1222 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1223 /* 97 - 3840x2160@60Hz 16:9 */
1224 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1225 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1227 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1228 /* 98 - 4096x2160@24Hz 256:135 */
1229 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1230 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1232 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1233 /* 99 - 4096x2160@25Hz 256:135 */
1234 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1235 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1237 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1238 /* 100 - 4096x2160@30Hz 256:135 */
1239 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1240 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1242 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1243 /* 101 - 4096x2160@50Hz 256:135 */
1244 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1245 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1247 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1248 /* 102 - 4096x2160@60Hz 256:135 */
1249 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1250 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1252 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1253 /* 103 - 3840x2160@24Hz 64:27 */
1254 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1255 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1257 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1258 /* 104 - 3840x2160@25Hz 64:27 */
1259 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1260 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1262 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1263 /* 105 - 3840x2160@30Hz 64:27 */
1264 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1265 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1267 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1268 /* 106 - 3840x2160@50Hz 64:27 */
1269 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1270 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1272 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1273 /* 107 - 3840x2160@60Hz 64:27 */
1274 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1275 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1277 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1281 * HDMI 1.4 4k modes. Index using the VIC.
1283 static const struct drm_display_mode edid_4k_modes[] = {
1284 /* 0 - dummy, VICs start at 1 */
1286 /* 1 - 3840x2160@30Hz */
1287 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1288 3840, 4016, 4104, 4400, 0,
1289 2160, 2168, 2178, 2250, 0,
1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1292 /* 2 - 3840x2160@25Hz */
1293 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1294 3840, 4896, 4984, 5280, 0,
1295 2160, 2168, 2178, 2250, 0,
1296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1298 /* 3 - 3840x2160@24Hz */
1299 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1300 3840, 5116, 5204, 5500, 0,
1301 2160, 2168, 2178, 2250, 0,
1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1304 /* 4 - 4096x2160@24Hz (SMPTE) */
1305 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1306 4096, 5116, 5204, 5500, 0,
1307 2160, 2168, 2178, 2250, 0,
1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1312 /*** DDC fetch and block validation ***/
1314 static const u8 edid_header[] = {
1315 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1319 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1320 * @raw_edid: pointer to raw base EDID block
1322 * Sanity check the header of the base EDID block.
1324 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1326 int drm_edid_header_is_valid(const u8 *raw_edid)
1330 for (i = 0; i < sizeof(edid_header); i++)
1331 if (raw_edid[i] == edid_header[i])
1336 EXPORT_SYMBOL(drm_edid_header_is_valid);
1338 static int edid_fixup __read_mostly = 6;
1339 module_param_named(edid_fixup, edid_fixup, int, 0400);
1340 MODULE_PARM_DESC(edid_fixup,
1341 "Minimum number of valid EDID header bytes (0-8, default 6)");
1343 static void drm_get_displayid(struct drm_connector *connector,
1345 static int validate_displayid(u8 *displayid, int length, int idx);
1347 static int drm_edid_block_checksum(const u8 *raw_edid)
1351 for (i = 0; i < EDID_LENGTH; i++)
1352 csum += raw_edid[i];
1357 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1359 if (memchr_inv(in_edid, 0, length))
1366 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1367 * @raw_edid: pointer to raw EDID block
1368 * @block: type of block to validate (0 for base, extension otherwise)
1369 * @print_bad_edid: if true, dump bad EDID blocks to the console
1370 * @edid_corrupt: if true, the header or checksum is invalid
1372 * Validate a base or extension EDID block and optionally dump bad blocks to
1375 * Return: True if the block is valid, false otherwise.
1377 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1381 struct edid *edid = (struct edid *)raw_edid;
1383 if (WARN_ON(!raw_edid))
1386 if (edid_fixup > 8 || edid_fixup < 0)
1390 int score = drm_edid_header_is_valid(raw_edid);
1393 *edid_corrupt = false;
1394 } else if (score >= edid_fixup) {
1395 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1396 * The corrupt flag needs to be set here otherwise, the
1397 * fix-up code here will correct the problem, the
1398 * checksum is correct and the test fails
1401 *edid_corrupt = true;
1402 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1403 memcpy(raw_edid, edid_header, sizeof(edid_header));
1406 *edid_corrupt = true;
1411 csum = drm_edid_block_checksum(raw_edid);
1414 *edid_corrupt = true;
1416 /* allow CEA to slide through, switches mangle this */
1417 if (raw_edid[0] == CEA_EXT) {
1418 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1419 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1422 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1428 /* per-block-type checks */
1429 switch (raw_edid[0]) {
1431 if (edid->version != 1) {
1432 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1436 if (edid->revision > 4)
1437 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1447 if (print_bad_edid) {
1448 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1449 pr_notice("EDID block is all zeroes\n");
1451 pr_notice("Raw EDID:\n");
1452 print_hex_dump(KERN_NOTICE,
1453 " \t", DUMP_PREFIX_NONE, 16, 1,
1454 raw_edid, EDID_LENGTH, false);
1459 EXPORT_SYMBOL(drm_edid_block_valid);
1462 * drm_edid_is_valid - sanity check EDID data
1465 * Sanity-check an entire EDID record (including extensions)
1467 * Return: True if the EDID data is valid, false otherwise.
1469 bool drm_edid_is_valid(struct edid *edid)
1472 u8 *raw = (u8 *)edid;
1477 for (i = 0; i <= edid->extensions; i++)
1478 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1483 EXPORT_SYMBOL(drm_edid_is_valid);
1485 #define DDC_SEGMENT_ADDR 0x30
1487 * drm_do_probe_ddc_edid() - get EDID information via I2C
1488 * @data: I2C device adapter
1489 * @buf: EDID data buffer to be filled
1490 * @block: 128 byte EDID block to start fetching from
1491 * @len: EDID data buffer length to fetch
1493 * Try to fetch EDID information by calling I2C driver functions.
1495 * Return: 0 on success or -1 on failure.
1498 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1500 struct i2c_adapter *adapter = data;
1501 unsigned char start = block * EDID_LENGTH;
1502 unsigned char segment = block >> 1;
1503 unsigned char xfers = segment ? 3 : 2;
1504 int ret, retries = 5;
1507 * The core I2C driver will automatically retry the transfer if the
1508 * adapter reports EAGAIN. However, we find that bit-banging transfers
1509 * are susceptible to errors under a heavily loaded machine and
1510 * generate spurious NAKs and timeouts. Retrying the transfer
1511 * of the individual block a few times seems to overcome this.
1514 struct i2c_msg msgs[] = {
1516 .addr = DDC_SEGMENT_ADDR,
1534 * Avoid sending the segment addr to not upset non-compliant
1537 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1539 if (ret == -ENXIO) {
1540 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1544 } while (ret != xfers && --retries);
1546 return ret == xfers ? 0 : -1;
1549 static void connector_bad_edid(struct drm_connector *connector,
1550 u8 *edid, int num_blocks)
1554 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1557 dev_warn(connector->dev->dev,
1558 "%s: EDID is invalid:\n",
1560 for (i = 0; i < num_blocks; i++) {
1561 u8 *block = edid + i * EDID_LENGTH;
1564 if (drm_edid_is_zero(block, EDID_LENGTH))
1565 sprintf(prefix, "\t[%02x] ZERO ", i);
1566 else if (!drm_edid_block_valid(block, i, false, NULL))
1567 sprintf(prefix, "\t[%02x] BAD ", i);
1569 sprintf(prefix, "\t[%02x] GOOD ", i);
1571 print_hex_dump(KERN_WARNING,
1572 prefix, DUMP_PREFIX_NONE, 16, 1,
1573 block, EDID_LENGTH, false);
1577 /* Get override or firmware EDID */
1578 static struct edid *drm_get_override_edid(struct drm_connector *connector)
1580 struct edid *override = NULL;
1582 if (connector->override_edid)
1583 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1586 override = drm_load_edid_firmware(connector);
1588 return IS_ERR(override) ? NULL : override;
1592 * drm_add_override_edid_modes - add modes from override/firmware EDID
1593 * @connector: connector we're probing
1595 * Add modes from the override/firmware EDID, if available. Only to be used from
1596 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1597 * failed during drm_get_edid() and caused the override/firmware EDID to be
1600 * Return: The number of modes added or 0 if we couldn't find any.
1602 int drm_add_override_edid_modes(struct drm_connector *connector)
1604 struct edid *override;
1607 override = drm_get_override_edid(connector);
1609 drm_connector_update_edid_property(connector, override);
1610 num_modes = drm_add_edid_modes(connector, override);
1613 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1614 connector->base.id, connector->name, num_modes);
1619 EXPORT_SYMBOL(drm_add_override_edid_modes);
1622 * drm_do_get_edid - get EDID data using a custom EDID block read function
1623 * @connector: connector we're probing
1624 * @get_edid_block: EDID block read function
1625 * @data: private data passed to the block read function
1627 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1628 * exposes a different interface to read EDID blocks this function can be used
1629 * to get EDID data using a custom block read function.
1631 * As in the general case the DDC bus is accessible by the kernel at the I2C
1632 * level, drivers must make all reasonable efforts to expose it as an I2C
1633 * adapter and use drm_get_edid() instead of abusing this function.
1635 * The EDID may be overridden using debugfs override_edid or firmare EDID
1636 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1637 * order. Having either of them bypasses actual EDID reads.
1639 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1641 struct edid *drm_do_get_edid(struct drm_connector *connector,
1642 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1646 int i, j = 0, valid_extensions = 0;
1648 struct edid *override;
1650 override = drm_get_override_edid(connector);
1654 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1657 /* base block fetch */
1658 for (i = 0; i < 4; i++) {
1659 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1661 if (drm_edid_block_valid(edid, 0, false,
1662 &connector->edid_corrupt))
1664 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1665 connector->null_edid_counter++;
1672 /* if there's no extensions, we're done */
1673 valid_extensions = edid[0x7e];
1674 if (valid_extensions == 0)
1675 return (struct edid *)edid;
1677 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1682 for (j = 1; j <= edid[0x7e]; j++) {
1683 u8 *block = edid + j * EDID_LENGTH;
1685 for (i = 0; i < 4; i++) {
1686 if (get_edid_block(data, block, j, EDID_LENGTH))
1688 if (drm_edid_block_valid(block, j, false, NULL))
1696 if (valid_extensions != edid[0x7e]) {
1699 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1701 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1702 edid[0x7e] = valid_extensions;
1704 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1710 for (i = 0; i <= edid[0x7e]; i++) {
1711 u8 *block = edid + i * EDID_LENGTH;
1713 if (!drm_edid_block_valid(block, i, false, NULL))
1716 memcpy(base, block, EDID_LENGTH);
1717 base += EDID_LENGTH;
1724 return (struct edid *)edid;
1727 connector_bad_edid(connector, edid, 1);
1732 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1735 * drm_probe_ddc() - probe DDC presence
1736 * @adapter: I2C adapter to probe
1738 * Return: True on success, false on failure.
1741 drm_probe_ddc(struct i2c_adapter *adapter)
1745 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1747 EXPORT_SYMBOL(drm_probe_ddc);
1750 * drm_get_edid - get EDID data, if available
1751 * @connector: connector we're probing
1752 * @adapter: I2C adapter to use for DDC
1754 * Poke the given I2C channel to grab EDID data if possible. If found,
1755 * attach it to the connector.
1757 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1759 struct edid *drm_get_edid(struct drm_connector *connector,
1760 struct i2c_adapter *adapter)
1764 if (connector->force == DRM_FORCE_OFF)
1767 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1770 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1772 drm_get_displayid(connector, edid);
1775 EXPORT_SYMBOL(drm_get_edid);
1778 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1779 * @connector: connector we're probing
1780 * @adapter: I2C adapter to use for DDC
1782 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1783 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1784 * switch DDC to the GPU which is retrieving EDID.
1786 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1788 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1789 struct i2c_adapter *adapter)
1791 struct pci_dev *pdev = connector->dev->pdev;
1794 vga_switcheroo_lock_ddc(pdev);
1795 edid = drm_get_edid(connector, adapter);
1796 vga_switcheroo_unlock_ddc(pdev);
1800 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1803 * drm_edid_duplicate - duplicate an EDID and the extensions
1804 * @edid: EDID to duplicate
1806 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1808 struct edid *drm_edid_duplicate(const struct edid *edid)
1810 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1812 EXPORT_SYMBOL(drm_edid_duplicate);
1814 /*** EDID parsing ***/
1817 * edid_vendor - match a string against EDID's obfuscated vendor field
1818 * @edid: EDID to match
1819 * @vendor: vendor string
1821 * Returns true if @vendor is in @edid, false otherwise
1823 static bool edid_vendor(const struct edid *edid, const char *vendor)
1825 char edid_vendor[3];
1827 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1828 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1829 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1830 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1832 return !strncmp(edid_vendor, vendor, 3);
1836 * edid_get_quirks - return quirk flags for a given EDID
1837 * @edid: EDID to process
1839 * This tells subsequent routines what fixes they need to apply.
1841 static u32 edid_get_quirks(const struct edid *edid)
1843 const struct edid_quirk *quirk;
1846 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1847 quirk = &edid_quirk_list[i];
1849 if (edid_vendor(edid, quirk->vendor) &&
1850 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1851 return quirk->quirks;
1857 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1858 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1861 * edid_fixup_preferred - set preferred modes based on quirk list
1862 * @connector: has mode list to fix up
1863 * @quirks: quirks list
1865 * Walk the mode list for @connector, clearing the preferred status
1866 * on existing modes and setting it anew for the right mode ala @quirks.
1868 static void edid_fixup_preferred(struct drm_connector *connector,
1871 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1872 int target_refresh = 0;
1873 int cur_vrefresh, preferred_vrefresh;
1875 if (list_empty(&connector->probed_modes))
1878 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1879 target_refresh = 60;
1880 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1881 target_refresh = 75;
1883 preferred_mode = list_first_entry(&connector->probed_modes,
1884 struct drm_display_mode, head);
1886 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1887 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1889 if (cur_mode == preferred_mode)
1892 /* Largest mode is preferred */
1893 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1894 preferred_mode = cur_mode;
1896 cur_vrefresh = cur_mode->vrefresh ?
1897 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1898 preferred_vrefresh = preferred_mode->vrefresh ?
1899 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1900 /* At a given size, try to get closest to target refresh */
1901 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1902 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1903 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1904 preferred_mode = cur_mode;
1908 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1912 mode_is_rb(const struct drm_display_mode *mode)
1914 return (mode->htotal - mode->hdisplay == 160) &&
1915 (mode->hsync_end - mode->hdisplay == 80) &&
1916 (mode->hsync_end - mode->hsync_start == 32) &&
1917 (mode->vsync_start - mode->vdisplay == 3);
1921 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1922 * @dev: Device to duplicate against
1923 * @hsize: Mode width
1924 * @vsize: Mode height
1925 * @fresh: Mode refresh rate
1926 * @rb: Mode reduced-blanking-ness
1928 * Walk the DMT mode list looking for a match for the given parameters.
1930 * Return: A newly allocated copy of the mode, or NULL if not found.
1932 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1933 int hsize, int vsize, int fresh,
1938 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1939 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1940 if (hsize != ptr->hdisplay)
1942 if (vsize != ptr->vdisplay)
1944 if (fresh != drm_mode_vrefresh(ptr))
1946 if (rb != mode_is_rb(ptr))
1949 return drm_mode_duplicate(dev, ptr);
1954 EXPORT_SYMBOL(drm_mode_find_dmt);
1956 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1959 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1963 u8 *det_base = ext + d;
1966 for (i = 0; i < n; i++)
1967 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1971 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1973 unsigned int i, n = min((int)ext[0x02], 6);
1974 u8 *det_base = ext + 5;
1977 return; /* unknown version */
1979 for (i = 0; i < n; i++)
1980 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1984 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1987 struct edid *edid = (struct edid *)raw_edid;
1992 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1993 cb(&(edid->detailed_timings[i]), closure);
1995 for (i = 1; i <= raw_edid[0x7e]; i++) {
1996 u8 *ext = raw_edid + (i * EDID_LENGTH);
1999 cea_for_each_detailed_block(ext, cb, closure);
2002 vtb_for_each_detailed_block(ext, cb, closure);
2011 is_rb(struct detailed_timing *t, void *data)
2014 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
2016 *(bool *)data = true;
2019 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2021 drm_monitor_supports_rb(struct edid *edid)
2023 if (edid->revision >= 4) {
2025 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2029 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2033 find_gtf2(struct detailed_timing *t, void *data)
2036 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
2040 /* Secondary GTF curve kicks in above some break frequency */
2042 drm_gtf2_hbreak(struct edid *edid)
2045 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2046 return r ? (r[12] * 2) : 0;
2050 drm_gtf2_2c(struct edid *edid)
2053 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2054 return r ? r[13] : 0;
2058 drm_gtf2_m(struct edid *edid)
2061 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2062 return r ? (r[15] << 8) + r[14] : 0;
2066 drm_gtf2_k(struct edid *edid)
2069 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2070 return r ? r[16] : 0;
2074 drm_gtf2_2j(struct edid *edid)
2077 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2078 return r ? r[17] : 0;
2082 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2083 * @edid: EDID block to scan
2085 static int standard_timing_level(struct edid *edid)
2087 if (edid->revision >= 2) {
2088 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2090 if (drm_gtf2_hbreak(edid))
2098 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2099 * monitors fill with ascii space (0x20) instead.
2102 bad_std_timing(u8 a, u8 b)
2104 return (a == 0x00 && b == 0x00) ||
2105 (a == 0x01 && b == 0x01) ||
2106 (a == 0x20 && b == 0x20);
2110 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2111 * @connector: connector of for the EDID block
2112 * @edid: EDID block to scan
2113 * @t: standard timing params
2115 * Take the standard timing params (in this case width, aspect, and refresh)
2116 * and convert them into a real mode using CVT/GTF/DMT.
2118 static struct drm_display_mode *
2119 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2120 struct std_timing *t)
2122 struct drm_device *dev = connector->dev;
2123 struct drm_display_mode *m, *mode = NULL;
2126 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2127 >> EDID_TIMING_ASPECT_SHIFT;
2128 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2129 >> EDID_TIMING_VFREQ_SHIFT;
2130 int timing_level = standard_timing_level(edid);
2132 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2135 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2136 hsize = t->hsize * 8 + 248;
2137 /* vrefresh_rate = vfreq + 60 */
2138 vrefresh_rate = vfreq + 60;
2139 /* the vdisplay is calculated based on the aspect ratio */
2140 if (aspect_ratio == 0) {
2141 if (edid->revision < 3)
2144 vsize = (hsize * 10) / 16;
2145 } else if (aspect_ratio == 1)
2146 vsize = (hsize * 3) / 4;
2147 else if (aspect_ratio == 2)
2148 vsize = (hsize * 4) / 5;
2150 vsize = (hsize * 9) / 16;
2152 /* HDTV hack, part 1 */
2153 if (vrefresh_rate == 60 &&
2154 ((hsize == 1360 && vsize == 765) ||
2155 (hsize == 1368 && vsize == 769))) {
2161 * If this connector already has a mode for this size and refresh
2162 * rate (because it came from detailed or CVT info), use that
2163 * instead. This way we don't have to guess at interlace or
2166 list_for_each_entry(m, &connector->probed_modes, head)
2167 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2168 drm_mode_vrefresh(m) == vrefresh_rate)
2171 /* HDTV hack, part 2 */
2172 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2173 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2177 mode->hdisplay = 1366;
2178 mode->hsync_start = mode->hsync_start - 1;
2179 mode->hsync_end = mode->hsync_end - 1;
2183 /* check whether it can be found in default mode table */
2184 if (drm_monitor_supports_rb(edid)) {
2185 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2190 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2194 /* okay, generate it */
2195 switch (timing_level) {
2199 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2203 * This is potentially wrong if there's ever a monitor with
2204 * more than one ranges section, each claiming a different
2205 * secondary GTF curve. Please don't do that.
2207 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2210 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2211 drm_mode_destroy(dev, mode);
2212 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2213 vrefresh_rate, 0, 0,
2221 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2229 * EDID is delightfully ambiguous about how interlaced modes are to be
2230 * encoded. Our internal representation is of frame height, but some
2231 * HDTV detailed timings are encoded as field height.
2233 * The format list here is from CEA, in frame size. Technically we
2234 * should be checking refresh rate too. Whatever.
2237 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2238 struct detailed_pixel_timing *pt)
2241 static const struct {
2243 } cea_interlaced[] = {
2253 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2256 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2257 if ((mode->hdisplay == cea_interlaced[i].w) &&
2258 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2259 mode->vdisplay *= 2;
2260 mode->vsync_start *= 2;
2261 mode->vsync_end *= 2;
2267 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2271 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2272 * @dev: DRM device (needed to create new mode)
2274 * @timing: EDID detailed timing info
2275 * @quirks: quirks to apply
2277 * An EDID detailed timing block contains enough info for us to create and
2278 * return a new struct drm_display_mode.
2280 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2282 struct detailed_timing *timing,
2285 struct drm_display_mode *mode;
2286 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2287 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2288 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2289 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2290 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2291 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2292 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2293 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2294 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2296 /* ignore tiny modes */
2297 if (hactive < 64 || vactive < 64)
2300 if (pt->misc & DRM_EDID_PT_STEREO) {
2301 DRM_DEBUG_KMS("stereo mode not supported\n");
2304 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2305 DRM_DEBUG_KMS("composite sync not supported\n");
2308 /* it is incorrect if hsync/vsync width is zero */
2309 if (!hsync_pulse_width || !vsync_pulse_width) {
2310 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2311 "Wrong Hsync/Vsync pulse width\n");
2315 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2316 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2323 mode = drm_mode_create(dev);
2327 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2328 timing->pixel_clock = cpu_to_le16(1088);
2330 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2332 mode->hdisplay = hactive;
2333 mode->hsync_start = mode->hdisplay + hsync_offset;
2334 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2335 mode->htotal = mode->hdisplay + hblank;
2337 mode->vdisplay = vactive;
2338 mode->vsync_start = mode->vdisplay + vsync_offset;
2339 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2340 mode->vtotal = mode->vdisplay + vblank;
2342 /* Some EDIDs have bogus h/vtotal values */
2343 if (mode->hsync_end > mode->htotal)
2344 mode->htotal = mode->hsync_end + 1;
2345 if (mode->vsync_end > mode->vtotal)
2346 mode->vtotal = mode->vsync_end + 1;
2348 drm_mode_do_interlace_quirk(mode, pt);
2350 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2351 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2354 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2355 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2356 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2357 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2360 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2361 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2363 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2364 mode->width_mm *= 10;
2365 mode->height_mm *= 10;
2368 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2369 mode->width_mm = edid->width_cm * 10;
2370 mode->height_mm = edid->height_cm * 10;
2373 mode->type = DRM_MODE_TYPE_DRIVER;
2374 mode->vrefresh = drm_mode_vrefresh(mode);
2375 drm_mode_set_name(mode);
2381 mode_in_hsync_range(const struct drm_display_mode *mode,
2382 struct edid *edid, u8 *t)
2384 int hsync, hmin, hmax;
2387 if (edid->revision >= 4)
2388 hmin += ((t[4] & 0x04) ? 255 : 0);
2390 if (edid->revision >= 4)
2391 hmax += ((t[4] & 0x08) ? 255 : 0);
2392 hsync = drm_mode_hsync(mode);
2394 return (hsync <= hmax && hsync >= hmin);
2398 mode_in_vsync_range(const struct drm_display_mode *mode,
2399 struct edid *edid, u8 *t)
2401 int vsync, vmin, vmax;
2404 if (edid->revision >= 4)
2405 vmin += ((t[4] & 0x01) ? 255 : 0);
2407 if (edid->revision >= 4)
2408 vmax += ((t[4] & 0x02) ? 255 : 0);
2409 vsync = drm_mode_vrefresh(mode);
2411 return (vsync <= vmax && vsync >= vmin);
2415 range_pixel_clock(struct edid *edid, u8 *t)
2418 if (t[9] == 0 || t[9] == 255)
2421 /* 1.4 with CVT support gives us real precision, yay */
2422 if (edid->revision >= 4 && t[10] == 0x04)
2423 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2425 /* 1.3 is pathetic, so fuzz up a bit */
2426 return t[9] * 10000 + 5001;
2430 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2431 struct detailed_timing *timing)
2434 u8 *t = (u8 *)timing;
2436 if (!mode_in_hsync_range(mode, edid, t))
2439 if (!mode_in_vsync_range(mode, edid, t))
2442 if ((max_clock = range_pixel_clock(edid, t)))
2443 if (mode->clock > max_clock)
2446 /* 1.4 max horizontal check */
2447 if (edid->revision >= 4 && t[10] == 0x04)
2448 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2451 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2457 static bool valid_inferred_mode(const struct drm_connector *connector,
2458 const struct drm_display_mode *mode)
2460 const struct drm_display_mode *m;
2463 list_for_each_entry(m, &connector->probed_modes, head) {
2464 if (mode->hdisplay == m->hdisplay &&
2465 mode->vdisplay == m->vdisplay &&
2466 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2467 return false; /* duplicated */
2468 if (mode->hdisplay <= m->hdisplay &&
2469 mode->vdisplay <= m->vdisplay)
2476 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2477 struct detailed_timing *timing)
2480 struct drm_display_mode *newmode;
2481 struct drm_device *dev = connector->dev;
2483 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2484 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2485 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2486 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2488 drm_mode_probed_add(connector, newmode);
2497 /* fix up 1366x768 mode from 1368x768;
2498 * GFT/CVT can't express 1366 width which isn't dividable by 8
2500 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2502 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2503 mode->hdisplay = 1366;
2504 mode->hsync_start--;
2506 drm_mode_set_name(mode);
2511 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2512 struct detailed_timing *timing)
2515 struct drm_display_mode *newmode;
2516 struct drm_device *dev = connector->dev;
2518 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2519 const struct minimode *m = &extra_modes[i];
2520 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2524 drm_mode_fixup_1366x768(newmode);
2525 if (!mode_in_range(newmode, edid, timing) ||
2526 !valid_inferred_mode(connector, newmode)) {
2527 drm_mode_destroy(dev, newmode);
2531 drm_mode_probed_add(connector, newmode);
2539 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2540 struct detailed_timing *timing)
2543 struct drm_display_mode *newmode;
2544 struct drm_device *dev = connector->dev;
2545 bool rb = drm_monitor_supports_rb(edid);
2547 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2548 const struct minimode *m = &extra_modes[i];
2549 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2553 drm_mode_fixup_1366x768(newmode);
2554 if (!mode_in_range(newmode, edid, timing) ||
2555 !valid_inferred_mode(connector, newmode)) {
2556 drm_mode_destroy(dev, newmode);
2560 drm_mode_probed_add(connector, newmode);
2568 do_inferred_modes(struct detailed_timing *timing, void *c)
2570 struct detailed_mode_closure *closure = c;
2571 struct detailed_non_pixel *data = &timing->data.other_data;
2572 struct detailed_data_monitor_range *range = &data->data.range;
2574 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2577 closure->modes += drm_dmt_modes_for_range(closure->connector,
2581 if (!version_greater(closure->edid, 1, 1))
2582 return; /* GTF not defined yet */
2584 switch (range->flags) {
2585 case 0x02: /* secondary gtf, XXX could do more */
2586 case 0x00: /* default gtf */
2587 closure->modes += drm_gtf_modes_for_range(closure->connector,
2591 case 0x04: /* cvt, only in 1.4+ */
2592 if (!version_greater(closure->edid, 1, 3))
2595 closure->modes += drm_cvt_modes_for_range(closure->connector,
2599 case 0x01: /* just the ranges, no formula */
2606 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2608 struct detailed_mode_closure closure = {
2609 .connector = connector,
2613 if (version_greater(edid, 1, 0))
2614 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2617 return closure.modes;
2621 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2623 int i, j, m, modes = 0;
2624 struct drm_display_mode *mode;
2625 u8 *est = ((u8 *)timing) + 6;
2627 for (i = 0; i < 6; i++) {
2628 for (j = 7; j >= 0; j--) {
2629 m = (i * 8) + (7 - j);
2630 if (m >= ARRAY_SIZE(est3_modes))
2632 if (est[i] & (1 << j)) {
2633 mode = drm_mode_find_dmt(connector->dev,
2639 drm_mode_probed_add(connector, mode);
2650 do_established_modes(struct detailed_timing *timing, void *c)
2652 struct detailed_mode_closure *closure = c;
2653 struct detailed_non_pixel *data = &timing->data.other_data;
2655 if (data->type == EDID_DETAIL_EST_TIMINGS)
2656 closure->modes += drm_est3_modes(closure->connector, timing);
2660 * add_established_modes - get est. modes from EDID and add them
2661 * @connector: connector to add mode(s) to
2662 * @edid: EDID block to scan
2664 * Each EDID block contains a bitmap of the supported "established modes" list
2665 * (defined above). Tease them out and add them to the global modes list.
2668 add_established_modes(struct drm_connector *connector, struct edid *edid)
2670 struct drm_device *dev = connector->dev;
2671 unsigned long est_bits = edid->established_timings.t1 |
2672 (edid->established_timings.t2 << 8) |
2673 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2675 struct detailed_mode_closure closure = {
2676 .connector = connector,
2680 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2681 if (est_bits & (1<<i)) {
2682 struct drm_display_mode *newmode;
2683 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2685 drm_mode_probed_add(connector, newmode);
2691 if (version_greater(edid, 1, 0))
2692 drm_for_each_detailed_block((u8 *)edid,
2693 do_established_modes, &closure);
2695 return modes + closure.modes;
2699 do_standard_modes(struct detailed_timing *timing, void *c)
2701 struct detailed_mode_closure *closure = c;
2702 struct detailed_non_pixel *data = &timing->data.other_data;
2703 struct drm_connector *connector = closure->connector;
2704 struct edid *edid = closure->edid;
2706 if (data->type == EDID_DETAIL_STD_MODES) {
2708 for (i = 0; i < 6; i++) {
2709 struct std_timing *std;
2710 struct drm_display_mode *newmode;
2712 std = &data->data.timings[i];
2713 newmode = drm_mode_std(connector, edid, std);
2715 drm_mode_probed_add(connector, newmode);
2723 * add_standard_modes - get std. modes from EDID and add them
2724 * @connector: connector to add mode(s) to
2725 * @edid: EDID block to scan
2727 * Standard modes can be calculated using the appropriate standard (DMT,
2728 * GTF or CVT. Grab them from @edid and add them to the list.
2731 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2734 struct detailed_mode_closure closure = {
2735 .connector = connector,
2739 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2740 struct drm_display_mode *newmode;
2742 newmode = drm_mode_std(connector, edid,
2743 &edid->standard_timings[i]);
2745 drm_mode_probed_add(connector, newmode);
2750 if (version_greater(edid, 1, 0))
2751 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2754 /* XXX should also look for standard codes in VTB blocks */
2756 return modes + closure.modes;
2759 static int drm_cvt_modes(struct drm_connector *connector,
2760 struct detailed_timing *timing)
2762 int i, j, modes = 0;
2763 struct drm_display_mode *newmode;
2764 struct drm_device *dev = connector->dev;
2765 struct cvt_timing *cvt;
2766 const int rates[] = { 60, 85, 75, 60, 50 };
2767 const u8 empty[3] = { 0, 0, 0 };
2769 for (i = 0; i < 4; i++) {
2770 int uninitialized_var(width), height;
2771 cvt = &(timing->data.other_data.data.cvt[i]);
2773 if (!memcmp(cvt->code, empty, 3))
2776 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2777 switch (cvt->code[1] & 0x0c) {
2779 width = height * 4 / 3;
2782 width = height * 16 / 9;
2785 width = height * 16 / 10;
2788 width = height * 15 / 9;
2792 for (j = 1; j < 5; j++) {
2793 if (cvt->code[2] & (1 << j)) {
2794 newmode = drm_cvt_mode(dev, width, height,
2798 drm_mode_probed_add(connector, newmode);
2809 do_cvt_mode(struct detailed_timing *timing, void *c)
2811 struct detailed_mode_closure *closure = c;
2812 struct detailed_non_pixel *data = &timing->data.other_data;
2814 if (data->type == EDID_DETAIL_CVT_3BYTE)
2815 closure->modes += drm_cvt_modes(closure->connector, timing);
2819 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2821 struct detailed_mode_closure closure = {
2822 .connector = connector,
2826 if (version_greater(edid, 1, 2))
2827 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2829 /* XXX should also look for CVT codes in VTB blocks */
2831 return closure.modes;
2834 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2837 do_detailed_mode(struct detailed_timing *timing, void *c)
2839 struct detailed_mode_closure *closure = c;
2840 struct drm_display_mode *newmode;
2842 if (timing->pixel_clock) {
2843 newmode = drm_mode_detailed(closure->connector->dev,
2844 closure->edid, timing,
2849 if (closure->preferred)
2850 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2853 * Detailed modes are limited to 10kHz pixel clock resolution,
2854 * so fix up anything that looks like CEA/HDMI mode, but the clock
2855 * is just slightly off.
2857 fixup_detailed_cea_mode_clock(newmode);
2859 drm_mode_probed_add(closure->connector, newmode);
2861 closure->preferred = false;
2866 * add_detailed_modes - Add modes from detailed timings
2867 * @connector: attached connector
2868 * @edid: EDID block to scan
2869 * @quirks: quirks to apply
2872 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2875 struct detailed_mode_closure closure = {
2876 .connector = connector,
2882 if (closure.preferred && !version_greater(edid, 1, 3))
2884 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2886 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2888 return closure.modes;
2891 #define AUDIO_BLOCK 0x01
2892 #define VIDEO_BLOCK 0x02
2893 #define VENDOR_BLOCK 0x03
2894 #define SPEAKER_BLOCK 0x04
2895 #define HDR_STATIC_METADATA_BLOCK 0x6
2896 #define USE_EXTENDED_TAG 0x07
2897 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2898 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
2899 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2900 #define EDID_BASIC_AUDIO (1 << 6)
2901 #define EDID_CEA_YCRCB444 (1 << 5)
2902 #define EDID_CEA_YCRCB422 (1 << 4)
2903 #define EDID_CEA_VCDB_QS (1 << 6)
2906 * Search EDID for CEA extension block.
2908 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
2910 u8 *edid_ext = NULL;
2913 /* No EDID or EDID extensions */
2914 if (edid == NULL || edid->extensions == 0)
2917 /* Find CEA extension */
2918 for (i = 0; i < edid->extensions; i++) {
2919 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2920 if (edid_ext[0] == ext_id)
2924 if (i == edid->extensions)
2931 static u8 *drm_find_displayid_extension(const struct edid *edid)
2933 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2936 static u8 *drm_find_cea_extension(const struct edid *edid)
2940 int length = EDID_LENGTH;
2941 struct displayid_block *block;
2945 /* Look for a top level CEA extension block */
2946 cea = drm_find_edid_extension(edid, CEA_EXT);
2950 /* CEA blocks can also be found embedded in a DisplayID block */
2951 displayid = drm_find_displayid_extension(edid);
2955 ret = validate_displayid(displayid, length, idx);
2959 idx += sizeof(struct displayid_hdr);
2960 for_each_displayid_db(displayid, block, idx, length) {
2961 if (block->tag == DATA_BLOCK_CTA) {
2971 * Calculate the alternate clock for the CEA mode
2972 * (60Hz vs. 59.94Hz etc.)
2975 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2977 unsigned int clock = cea_mode->clock;
2979 if (cea_mode->vrefresh % 6 != 0)
2983 * edid_cea_modes contains the 59.94Hz
2984 * variant for 240 and 480 line modes,
2985 * and the 60Hz variant otherwise.
2987 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2988 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2990 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2996 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2999 * For certain VICs the spec allows the vertical
3000 * front porch to vary by one or two lines.
3002 * cea_modes[] stores the variant with the shortest
3003 * vertical front porch. We can adjust the mode to
3004 * get the other variants by simply increasing the
3005 * vertical front porch length.
3007 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
3008 edid_cea_modes[9].vtotal != 262 ||
3009 edid_cea_modes[12].vtotal != 262 ||
3010 edid_cea_modes[13].vtotal != 262 ||
3011 edid_cea_modes[23].vtotal != 312 ||
3012 edid_cea_modes[24].vtotal != 312 ||
3013 edid_cea_modes[27].vtotal != 312 ||
3014 edid_cea_modes[28].vtotal != 312);
3016 if (((vic == 8 || vic == 9 ||
3017 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3018 ((vic == 23 || vic == 24 ||
3019 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3020 mode->vsync_start++;
3030 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3031 unsigned int clock_tolerance)
3033 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3036 if (!to_match->clock)
3039 if (to_match->picture_aspect_ratio)
3040 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3042 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
3043 struct drm_display_mode cea_mode = edid_cea_modes[vic];
3044 unsigned int clock1, clock2;
3046 /* Check both 60Hz and 59.94Hz */
3047 clock1 = cea_mode.clock;
3048 clock2 = cea_mode_alternate_clock(&cea_mode);
3050 if (abs(to_match->clock - clock1) > clock_tolerance &&
3051 abs(to_match->clock - clock2) > clock_tolerance)
3055 if (drm_mode_match(to_match, &cea_mode, match_flags))
3057 } while (cea_mode_alternate_timings(vic, &cea_mode));
3064 * drm_match_cea_mode - look for a CEA mode matching given mode
3065 * @to_match: display mode
3067 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3070 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3072 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3075 if (!to_match->clock)
3078 if (to_match->picture_aspect_ratio)
3079 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3081 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
3082 struct drm_display_mode cea_mode = edid_cea_modes[vic];
3083 unsigned int clock1, clock2;
3085 /* Check both 60Hz and 59.94Hz */
3086 clock1 = cea_mode.clock;
3087 clock2 = cea_mode_alternate_clock(&cea_mode);
3089 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3090 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3094 if (drm_mode_match(to_match, &cea_mode, match_flags))
3096 } while (cea_mode_alternate_timings(vic, &cea_mode));
3101 EXPORT_SYMBOL(drm_match_cea_mode);
3103 static bool drm_valid_cea_vic(u8 vic)
3105 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
3109 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
3110 * the input VIC from the CEA mode list
3111 * @video_code: ID given to each of the CEA modes
3113 * Returns picture aspect ratio
3115 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3117 return edid_cea_modes[video_code].picture_aspect_ratio;
3119 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
3122 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3125 * It's almost like cea_mode_alternate_clock(), we just need to add an
3126 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
3130 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3132 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3133 return hdmi_mode->clock;
3135 return cea_mode_alternate_clock(hdmi_mode);
3138 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3139 unsigned int clock_tolerance)
3141 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3144 if (!to_match->clock)
3147 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3148 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3149 unsigned int clock1, clock2;
3151 /* Make sure to also match alternate clocks */
3152 clock1 = hdmi_mode->clock;
3153 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3155 if (abs(to_match->clock - clock1) > clock_tolerance &&
3156 abs(to_match->clock - clock2) > clock_tolerance)
3159 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3167 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3168 * @to_match: display mode
3170 * An HDMI mode is one defined in the HDMI vendor specific block.
3172 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3174 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3176 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3179 if (!to_match->clock)
3182 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3183 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3184 unsigned int clock1, clock2;
3186 /* Make sure to also match alternate clocks */
3187 clock1 = hdmi_mode->clock;
3188 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3190 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3191 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3192 drm_mode_match(to_match, hdmi_mode, match_flags))
3198 static bool drm_valid_hdmi_vic(u8 vic)
3200 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3204 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3206 struct drm_device *dev = connector->dev;
3207 struct drm_display_mode *mode, *tmp;
3211 /* Don't add CEA modes if the CEA extension block is missing */
3212 if (!drm_find_cea_extension(edid))
3216 * Go through all probed modes and create a new mode
3217 * with the alternate clock for certain CEA modes.
3219 list_for_each_entry(mode, &connector->probed_modes, head) {
3220 const struct drm_display_mode *cea_mode = NULL;
3221 struct drm_display_mode *newmode;
3222 u8 vic = drm_match_cea_mode(mode);
3223 unsigned int clock1, clock2;
3225 if (drm_valid_cea_vic(vic)) {
3226 cea_mode = &edid_cea_modes[vic];
3227 clock2 = cea_mode_alternate_clock(cea_mode);
3229 vic = drm_match_hdmi_mode(mode);
3230 if (drm_valid_hdmi_vic(vic)) {
3231 cea_mode = &edid_4k_modes[vic];
3232 clock2 = hdmi_mode_alternate_clock(cea_mode);
3239 clock1 = cea_mode->clock;
3241 if (clock1 == clock2)
3244 if (mode->clock != clock1 && mode->clock != clock2)
3247 newmode = drm_mode_duplicate(dev, cea_mode);
3251 /* Carry over the stereo flags */
3252 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3255 * The current mode could be either variant. Make
3256 * sure to pick the "other" clock for the new mode.
3258 if (mode->clock != clock1)
3259 newmode->clock = clock1;
3261 newmode->clock = clock2;
3263 list_add_tail(&newmode->head, &list);
3266 list_for_each_entry_safe(mode, tmp, &list, head) {
3267 list_del(&mode->head);
3268 drm_mode_probed_add(connector, mode);
3275 static u8 svd_to_vic(u8 svd)
3277 /* 0-6 bit vic, 7th bit native mode indicator */
3278 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3284 static struct drm_display_mode *
3285 drm_display_mode_from_vic_index(struct drm_connector *connector,
3286 const u8 *video_db, u8 video_len,
3289 struct drm_device *dev = connector->dev;
3290 struct drm_display_mode *newmode;
3293 if (video_db == NULL || video_index >= video_len)
3296 /* CEA modes are numbered 1..127 */
3297 vic = svd_to_vic(video_db[video_index]);
3298 if (!drm_valid_cea_vic(vic))
3301 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3305 newmode->vrefresh = 0;
3311 * do_y420vdb_modes - Parse YCBCR 420 only modes
3312 * @connector: connector corresponding to the HDMI sink
3313 * @svds: start of the data block of CEA YCBCR 420 VDB
3314 * @len: length of the CEA YCBCR 420 VDB
3316 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3317 * which contains modes which can be supported in YCBCR 420
3318 * output format only.
3320 static int do_y420vdb_modes(struct drm_connector *connector,
3321 const u8 *svds, u8 svds_len)
3324 struct drm_device *dev = connector->dev;
3325 struct drm_display_info *info = &connector->display_info;
3326 struct drm_hdmi_info *hdmi = &info->hdmi;
3328 for (i = 0; i < svds_len; i++) {
3329 u8 vic = svd_to_vic(svds[i]);
3330 struct drm_display_mode *newmode;
3332 if (!drm_valid_cea_vic(vic))
3335 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3338 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3339 drm_mode_probed_add(connector, newmode);
3344 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3349 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3350 * @connector: connector corresponding to the HDMI sink
3351 * @vic: CEA vic for the video mode to be added in the map
3353 * Makes an entry for a videomode in the YCBCR 420 bitmap
3356 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3358 u8 vic = svd_to_vic(svd);
3359 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3361 if (!drm_valid_cea_vic(vic))
3364 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3368 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3371 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3373 for (i = 0; i < len; i++) {
3374 struct drm_display_mode *mode;
3375 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3378 * YCBCR420 capability block contains a bitmap which
3379 * gives the index of CEA modes from CEA VDB, which
3380 * can support YCBCR 420 sampling output also (apart
3381 * from RGB/YCBCR444 etc).
3382 * For example, if the bit 0 in bitmap is set,
3383 * first mode in VDB can support YCBCR420 output too.
3384 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3386 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3387 drm_add_cmdb_modes(connector, db[i]);
3389 drm_mode_probed_add(connector, mode);
3397 struct stereo_mandatory_mode {
3398 int width, height, vrefresh;
3402 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3403 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3404 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3406 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3408 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3409 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3410 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3411 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3412 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3416 stereo_match_mandatory(const struct drm_display_mode *mode,
3417 const struct stereo_mandatory_mode *stereo_mode)
3419 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3421 return mode->hdisplay == stereo_mode->width &&
3422 mode->vdisplay == stereo_mode->height &&
3423 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3424 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3427 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3429 struct drm_device *dev = connector->dev;
3430 const struct drm_display_mode *mode;
3431 struct list_head stereo_modes;
3434 INIT_LIST_HEAD(&stereo_modes);
3436 list_for_each_entry(mode, &connector->probed_modes, head) {
3437 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3438 const struct stereo_mandatory_mode *mandatory;
3439 struct drm_display_mode *new_mode;
3441 if (!stereo_match_mandatory(mode,
3442 &stereo_mandatory_modes[i]))
3445 mandatory = &stereo_mandatory_modes[i];
3446 new_mode = drm_mode_duplicate(dev, mode);
3450 new_mode->flags |= mandatory->flags;
3451 list_add_tail(&new_mode->head, &stereo_modes);
3456 list_splice_tail(&stereo_modes, &connector->probed_modes);
3461 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3463 struct drm_device *dev = connector->dev;
3464 struct drm_display_mode *newmode;
3466 if (!drm_valid_hdmi_vic(vic)) {
3467 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3471 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3475 drm_mode_probed_add(connector, newmode);
3480 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3481 const u8 *video_db, u8 video_len, u8 video_index)
3483 struct drm_display_mode *newmode;
3486 if (structure & (1 << 0)) {
3487 newmode = drm_display_mode_from_vic_index(connector, video_db,
3491 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3492 drm_mode_probed_add(connector, newmode);
3496 if (structure & (1 << 6)) {
3497 newmode = drm_display_mode_from_vic_index(connector, video_db,
3501 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3502 drm_mode_probed_add(connector, newmode);
3506 if (structure & (1 << 8)) {
3507 newmode = drm_display_mode_from_vic_index(connector, video_db,
3511 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3512 drm_mode_probed_add(connector, newmode);
3521 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3522 * @connector: connector corresponding to the HDMI sink
3523 * @db: start of the CEA vendor specific block
3524 * @len: length of the CEA block payload, ie. one can access up to db[len]
3526 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3527 * also adds the stereo 3d modes when applicable.
3530 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3531 const u8 *video_db, u8 video_len)
3533 struct drm_display_info *info = &connector->display_info;
3534 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3535 u8 vic_len, hdmi_3d_len = 0;
3542 /* no HDMI_Video_Present */
3543 if (!(db[8] & (1 << 5)))
3546 /* Latency_Fields_Present */
3547 if (db[8] & (1 << 7))
3550 /* I_Latency_Fields_Present */
3551 if (db[8] & (1 << 6))
3554 /* the declared length is not long enough for the 2 first bytes
3555 * of additional video format capabilities */
3556 if (len < (8 + offset + 2))
3561 if (db[8 + offset] & (1 << 7)) {
3562 modes += add_hdmi_mandatory_stereo_modes(connector);
3564 /* 3D_Multi_present */
3565 multi_present = (db[8 + offset] & 0x60) >> 5;
3569 vic_len = db[8 + offset] >> 5;
3570 hdmi_3d_len = db[8 + offset] & 0x1f;
3572 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3575 vic = db[9 + offset + i];
3576 modes += add_hdmi_mode(connector, vic);
3578 offset += 1 + vic_len;
3580 if (multi_present == 1)
3582 else if (multi_present == 2)
3587 if (len < (8 + offset + hdmi_3d_len - 1))
3590 if (hdmi_3d_len < multi_len)
3593 if (multi_present == 1 || multi_present == 2) {
3594 /* 3D_Structure_ALL */
3595 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3597 /* check if 3D_MASK is present */
3598 if (multi_present == 2)
3599 mask = (db[10 + offset] << 8) | db[11 + offset];
3603 for (i = 0; i < 16; i++) {
3604 if (mask & (1 << i))
3605 modes += add_3d_struct_modes(connector,
3612 offset += multi_len;
3614 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3616 struct drm_display_mode *newmode = NULL;
3617 unsigned int newflag = 0;
3618 bool detail_present;
3620 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3622 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3625 /* 2D_VIC_order_X */
3626 vic_index = db[8 + offset + i] >> 4;
3628 /* 3D_Structure_X */
3629 switch (db[8 + offset + i] & 0x0f) {
3631 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3634 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3638 if ((db[9 + offset + i] >> 4) == 1)
3639 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3644 newmode = drm_display_mode_from_vic_index(connector,
3650 newmode->flags |= newflag;
3651 drm_mode_probed_add(connector, newmode);
3662 info->has_hdmi_infoframe = true;
3667 cea_db_payload_len(const u8 *db)
3669 return db[0] & 0x1f;
3673 cea_db_extended_tag(const u8 *db)
3679 cea_db_tag(const u8 *db)
3685 cea_revision(const u8 *cea)
3691 cea_db_offsets(const u8 *cea, int *start, int *end)
3693 /* DisplayID CTA extension blocks and top-level CEA EDID
3694 * block header definitions differ in the following bytes:
3695 * 1) Byte 2 of the header specifies length differently,
3696 * 2) Byte 3 is only present in the CEA top level block.
3698 * The different definitions for byte 2 follow.
3700 * DisplayID CTA extension block defines byte 2 as:
3701 * Number of payload bytes
3703 * CEA EDID block defines byte 2 as:
3704 * Byte number (decimal) within this block where the 18-byte
3705 * DTDs begin. If no non-DTD data is present in this extension
3706 * block, the value should be set to 04h (the byte after next).
3707 * If set to 00h, there are no DTDs present in this block and
3710 if (cea[0] == DATA_BLOCK_CTA) {
3712 *end = *start + cea[2];
3713 } else if (cea[0] == CEA_EXT) {
3714 /* Data block offset in CEA extension block */
3719 if (*end < 4 || *end > 127)
3728 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3732 if (cea_db_tag(db) != VENDOR_BLOCK)
3735 if (cea_db_payload_len(db) < 5)
3738 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3740 return hdmi_id == HDMI_IEEE_OUI;
3743 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3747 if (cea_db_tag(db) != VENDOR_BLOCK)
3750 if (cea_db_payload_len(db) < 7)
3753 oui = db[3] << 16 | db[2] << 8 | db[1];
3755 return oui == HDMI_FORUM_IEEE_OUI;
3758 static bool cea_db_is_vcdb(const u8 *db)
3760 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3763 if (cea_db_payload_len(db) != 2)
3766 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
3772 static bool cea_db_is_y420cmdb(const u8 *db)
3774 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3777 if (!cea_db_payload_len(db))
3780 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3786 static bool cea_db_is_y420vdb(const u8 *db)
3788 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3791 if (!cea_db_payload_len(db))
3794 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3800 #define for_each_cea_db(cea, i, start, end) \
3801 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3803 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3806 struct drm_display_info *info = &connector->display_info;
3807 struct drm_hdmi_info *hdmi = &info->hdmi;
3808 u8 map_len = cea_db_payload_len(db) - 1;
3813 /* All CEA modes support ycbcr420 sampling also.*/
3814 hdmi->y420_cmdb_map = U64_MAX;
3815 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3820 * This map indicates which of the existing CEA block modes
3821 * from VDB can support YCBCR420 output too. So if bit=0 is
3822 * set, first mode from VDB can support YCBCR420 output too.
3823 * We will parse and keep this map, before parsing VDB itself
3824 * to avoid going through the same block again and again.
3826 * Spec is not clear about max possible size of this block.
3827 * Clamping max bitmap block size at 8 bytes. Every byte can
3828 * address 8 CEA modes, in this way this map can address
3829 * 8*8 = first 64 SVDs.
3831 if (WARN_ON_ONCE(map_len > 8))
3834 for (count = 0; count < map_len; count++)
3835 map |= (u64)db[2 + count] << (8 * count);
3838 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3840 hdmi->y420_cmdb_map = map;
3844 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3846 const u8 *cea = drm_find_cea_extension(edid);
3847 const u8 *db, *hdmi = NULL, *video = NULL;
3848 u8 dbl, hdmi_len, video_len = 0;
3851 if (cea && cea_revision(cea) >= 3) {
3854 if (cea_db_offsets(cea, &start, &end))
3857 for_each_cea_db(cea, i, start, end) {
3859 dbl = cea_db_payload_len(db);
3861 if (cea_db_tag(db) == VIDEO_BLOCK) {
3864 modes += do_cea_modes(connector, video, dbl);
3865 } else if (cea_db_is_hdmi_vsdb(db)) {
3868 } else if (cea_db_is_y420vdb(db)) {
3869 const u8 *vdb420 = &db[2];
3871 /* Add 4:2:0(only) modes present in EDID */
3872 modes += do_y420vdb_modes(connector,
3880 * We parse the HDMI VSDB after having added the cea modes as we will
3881 * be patching their flags when the sink supports stereo 3D.
3884 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3890 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3892 const struct drm_display_mode *cea_mode;
3893 int clock1, clock2, clock;
3898 * allow 5kHz clock difference either way to account for
3899 * the 10kHz clock resolution limit of detailed timings.
3901 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3902 if (drm_valid_cea_vic(vic)) {
3904 cea_mode = &edid_cea_modes[vic];
3905 clock1 = cea_mode->clock;
3906 clock2 = cea_mode_alternate_clock(cea_mode);
3908 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3909 if (drm_valid_hdmi_vic(vic)) {
3911 cea_mode = &edid_4k_modes[vic];
3912 clock1 = cea_mode->clock;
3913 clock2 = hdmi_mode_alternate_clock(cea_mode);
3919 /* pick whichever is closest */
3920 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3925 if (mode->clock == clock)
3928 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3929 type, vic, mode->clock, clock);
3930 mode->clock = clock;
3933 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
3935 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3938 if (db[1] != HDR_STATIC_METADATA_BLOCK)
3941 if (cea_db_payload_len(db) < 3)
3947 static uint8_t eotf_supported(const u8 *edid_ext)
3949 return edid_ext[2] &
3950 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
3951 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
3952 BIT(HDMI_EOTF_SMPTE_ST2084) |
3953 BIT(HDMI_EOTF_BT_2100_HLG));
3956 static uint8_t hdr_metadata_type(const u8 *edid_ext)
3958 return edid_ext[3] &
3959 BIT(HDMI_STATIC_METADATA_TYPE1);
3963 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
3967 len = cea_db_payload_len(db);
3969 connector->hdr_sink_metadata.hdmi_type1.eotf =
3971 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
3972 hdr_metadata_type(db);
3975 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
3977 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
3979 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
3983 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3985 u8 len = cea_db_payload_len(db);
3987 if (len >= 6 && (db[6] & (1 << 7)))
3988 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
3990 connector->latency_present[0] = db[8] >> 7;
3991 connector->latency_present[1] = (db[8] >> 6) & 1;
3994 connector->video_latency[0] = db[9];
3996 connector->audio_latency[0] = db[10];
3998 connector->video_latency[1] = db[11];
4000 connector->audio_latency[1] = db[12];
4002 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4003 "video latency %d %d, "
4004 "audio latency %d %d\n",
4005 connector->latency_present[0],
4006 connector->latency_present[1],
4007 connector->video_latency[0],
4008 connector->video_latency[1],
4009 connector->audio_latency[0],
4010 connector->audio_latency[1]);
4014 monitor_name(struct detailed_timing *t, void *data)
4016 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
4017 *(u8 **)data = t->data.other_data.data.str.str;
4020 static int get_monitor_name(struct edid *edid, char name[13])
4022 char *edid_name = NULL;
4028 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4029 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4030 if (edid_name[mnl] == 0x0a)
4033 name[mnl] = edid_name[mnl];
4040 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4041 * @edid: monitor EDID information
4042 * @name: pointer to a character array to hold the name of the monitor
4043 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4046 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4054 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4055 memcpy(name, buf, name_length);
4056 name[name_length] = '\0';
4058 EXPORT_SYMBOL(drm_edid_get_monitor_name);
4060 static void clear_eld(struct drm_connector *connector)
4062 memset(connector->eld, 0, sizeof(connector->eld));
4064 connector->latency_present[0] = false;
4065 connector->latency_present[1] = false;
4066 connector->video_latency[0] = 0;
4067 connector->audio_latency[0] = 0;
4068 connector->video_latency[1] = 0;
4069 connector->audio_latency[1] = 0;
4073 * drm_edid_to_eld - build ELD from EDID
4074 * @connector: connector corresponding to the HDMI/DP sink
4075 * @edid: EDID to parse
4077 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
4078 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
4080 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
4082 uint8_t *eld = connector->eld;
4085 int total_sad_count = 0;
4089 clear_eld(connector);
4094 cea = drm_find_cea_extension(edid);
4096 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4100 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4101 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
4103 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4104 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
4106 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
4108 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4109 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4110 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4111 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
4113 if (cea_revision(cea) >= 3) {
4116 if (cea_db_offsets(cea, &start, &end)) {
4121 for_each_cea_db(cea, i, start, end) {
4123 dbl = cea_db_payload_len(db);
4125 switch (cea_db_tag(db)) {
4129 /* Audio Data Block, contains SADs */
4130 sad_count = min(dbl / 3, 15 - total_sad_count);
4132 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
4133 &db[1], sad_count * 3);
4134 total_sad_count += sad_count;
4137 /* Speaker Allocation Data Block */
4139 eld[DRM_ELD_SPEAKER] = db[1];
4142 /* HDMI Vendor-Specific Data Block */
4143 if (cea_db_is_hdmi_vsdb(db))
4144 drm_parse_hdmi_vsdb_audio(connector, db);
4151 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4153 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4154 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4155 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4157 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4159 eld[DRM_ELD_BASELINE_ELD_LEN] =
4160 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4162 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4163 drm_eld_size(eld), total_sad_count);
4167 * drm_edid_to_sad - extracts SADs from EDID
4168 * @edid: EDID to parse
4169 * @sads: pointer that will be set to the extracted SADs
4171 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4173 * Note: The returned pointer needs to be freed using kfree().
4175 * Return: The number of found SADs or negative number on error.
4177 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4180 int i, start, end, dbl;
4183 cea = drm_find_cea_extension(edid);
4185 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4189 if (cea_revision(cea) < 3) {
4190 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4194 if (cea_db_offsets(cea, &start, &end)) {
4195 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4199 for_each_cea_db(cea, i, start, end) {
4202 if (cea_db_tag(db) == AUDIO_BLOCK) {
4204 dbl = cea_db_payload_len(db);
4206 count = dbl / 3; /* SAD is 3B */
4207 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4210 for (j = 0; j < count; j++) {
4211 u8 *sad = &db[1 + j * 3];
4213 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4214 (*sads)[j].channels = sad[0] & 0x7;
4215 (*sads)[j].freq = sad[1] & 0x7F;
4216 (*sads)[j].byte2 = sad[2];
4224 EXPORT_SYMBOL(drm_edid_to_sad);
4227 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4228 * @edid: EDID to parse
4229 * @sadb: pointer to the speaker block
4231 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4233 * Note: The returned pointer needs to be freed using kfree().
4235 * Return: The number of found Speaker Allocation Blocks or negative number on
4238 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4241 int i, start, end, dbl;
4244 cea = drm_find_cea_extension(edid);
4246 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4250 if (cea_revision(cea) < 3) {
4251 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4255 if (cea_db_offsets(cea, &start, &end)) {
4256 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4260 for_each_cea_db(cea, i, start, end) {
4261 const u8 *db = &cea[i];
4263 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4264 dbl = cea_db_payload_len(db);
4266 /* Speaker Allocation Data Block */
4268 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4279 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4282 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4283 * @connector: connector associated with the HDMI/DP sink
4284 * @mode: the display mode
4286 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4287 * the sink doesn't support audio or video.
4289 int drm_av_sync_delay(struct drm_connector *connector,
4290 const struct drm_display_mode *mode)
4292 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4295 if (!connector->latency_present[0])
4297 if (!connector->latency_present[1])
4300 a = connector->audio_latency[i];
4301 v = connector->video_latency[i];
4304 * HDMI/DP sink doesn't support audio or video?
4306 if (a == 255 || v == 255)
4310 * Convert raw EDID values to millisecond.
4311 * Treat unknown latency as 0ms.
4314 a = min(2 * (a - 1), 500);
4316 v = min(2 * (v - 1), 500);
4318 return max(v - a, 0);
4320 EXPORT_SYMBOL(drm_av_sync_delay);
4323 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4324 * @edid: monitor EDID information
4326 * Parse the CEA extension according to CEA-861-B.
4328 * Return: True if the monitor is HDMI, false if not or unknown.
4330 bool drm_detect_hdmi_monitor(struct edid *edid)
4334 int start_offset, end_offset;
4336 edid_ext = drm_find_cea_extension(edid);
4340 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4344 * Because HDMI identifier is in Vendor Specific Block,
4345 * search it from all data blocks of CEA extension.
4347 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4348 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4354 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4357 * drm_detect_monitor_audio - check monitor audio capability
4358 * @edid: EDID block to scan
4360 * Monitor should have CEA extension block.
4361 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4362 * audio' only. If there is any audio extension block and supported
4363 * audio format, assume at least 'basic audio' support, even if 'basic
4364 * audio' is not defined in EDID.
4366 * Return: True if the monitor supports audio, false otherwise.
4368 bool drm_detect_monitor_audio(struct edid *edid)
4372 bool has_audio = false;
4373 int start_offset, end_offset;
4375 edid_ext = drm_find_cea_extension(edid);
4379 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4382 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4386 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4389 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4390 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4392 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4393 DRM_DEBUG_KMS("CEA audio format %d\n",
4394 (edid_ext[i + j] >> 3) & 0xf);
4401 EXPORT_SYMBOL(drm_detect_monitor_audio);
4405 * drm_default_rgb_quant_range - default RGB quantization range
4406 * @mode: display mode
4408 * Determine the default RGB quantization range for the mode,
4409 * as specified in CEA-861.
4411 * Return: The default RGB quantization range for the mode
4413 enum hdmi_quantization_range
4414 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4416 /* All CEA modes other than VIC 1 use limited quantization range. */
4417 return drm_match_cea_mode(mode) > 1 ?
4418 HDMI_QUANTIZATION_RANGE_LIMITED :
4419 HDMI_QUANTIZATION_RANGE_FULL;
4421 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4423 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4425 struct drm_display_info *info = &connector->display_info;
4427 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4429 if (db[2] & EDID_CEA_VCDB_QS)
4430 info->rgb_quant_range_selectable = true;
4433 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4437 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4439 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4440 hdmi->y420_dc_modes = dc_mask;
4443 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4446 struct drm_display_info *display = &connector->display_info;
4447 struct drm_hdmi_info *hdmi = &display->hdmi;
4449 display->has_hdmi_infoframe = true;
4451 if (hf_vsdb[6] & 0x80) {
4452 hdmi->scdc.supported = true;
4453 if (hf_vsdb[6] & 0x40)
4454 hdmi->scdc.read_request = true;
4458 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4459 * And as per the spec, three factors confirm this:
4460 * * Availability of a HF-VSDB block in EDID (check)
4461 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4462 * * SCDC support available (let's check)
4463 * Lets check it out.
4467 /* max clock is 5000 KHz times block value */
4468 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4469 struct drm_scdc *scdc = &hdmi->scdc;
4471 if (max_tmds_clock > 340000) {
4472 display->max_tmds_clock = max_tmds_clock;
4473 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4474 display->max_tmds_clock);
4477 if (scdc->supported) {
4478 scdc->scrambling.supported = true;
4480 /* Few sinks support scrambling for cloks < 340M */
4481 if ((hf_vsdb[6] & 0x8))
4482 scdc->scrambling.low_rates = true;
4486 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4489 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4492 struct drm_display_info *info = &connector->display_info;
4493 unsigned int dc_bpc = 0;
4495 /* HDMI supports at least 8 bpc */
4498 if (cea_db_payload_len(hdmi) < 6)
4501 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4503 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4504 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4508 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4510 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4511 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4515 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4517 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4518 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4523 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4528 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4529 connector->name, dc_bpc);
4533 * Deep color support mandates RGB444 support for all video
4534 * modes and forbids YCRCB422 support for all video modes per
4537 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4539 /* YCRCB444 is optional according to spec. */
4540 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4541 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4542 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4547 * Spec says that if any deep color mode is supported at all,
4548 * then deep color 36 bit must be supported.
4550 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4551 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4557 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4559 struct drm_display_info *info = &connector->display_info;
4560 u8 len = cea_db_payload_len(db);
4563 info->dvi_dual = db[6] & 1;
4565 info->max_tmds_clock = db[7] * 5000;
4567 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4568 "max TMDS clock %d kHz\n",
4570 info->max_tmds_clock);
4572 drm_parse_hdmi_deep_color_info(connector, db);
4575 static void drm_parse_cea_ext(struct drm_connector *connector,
4576 const struct edid *edid)
4578 struct drm_display_info *info = &connector->display_info;
4582 edid_ext = drm_find_cea_extension(edid);
4586 info->cea_rev = edid_ext[1];
4588 /* The existence of a CEA block should imply RGB support */
4589 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4590 if (edid_ext[3] & EDID_CEA_YCRCB444)
4591 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4592 if (edid_ext[3] & EDID_CEA_YCRCB422)
4593 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4595 if (cea_db_offsets(edid_ext, &start, &end))
4598 for_each_cea_db(edid_ext, i, start, end) {
4599 const u8 *db = &edid_ext[i];
4601 if (cea_db_is_hdmi_vsdb(db))
4602 drm_parse_hdmi_vsdb_video(connector, db);
4603 if (cea_db_is_hdmi_forum_vsdb(db))
4604 drm_parse_hdmi_forum_vsdb(connector, db);
4605 if (cea_db_is_y420cmdb(db))
4606 drm_parse_y420cmdb_bitmap(connector, db);
4607 if (cea_db_is_vcdb(db))
4608 drm_parse_vcdb(connector, db);
4609 if (cea_db_is_hdmi_hdr_metadata_block(db))
4610 drm_parse_hdr_metadata_block(connector, db);
4614 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4615 * all of the values which would have been set from EDID
4618 drm_reset_display_info(struct drm_connector *connector)
4620 struct drm_display_info *info = &connector->display_info;
4623 info->height_mm = 0;
4626 info->color_formats = 0;
4628 info->max_tmds_clock = 0;
4629 info->dvi_dual = false;
4630 info->has_hdmi_infoframe = false;
4631 info->rgb_quant_range_selectable = false;
4632 memset(&info->hdmi, 0, sizeof(info->hdmi));
4634 info->non_desktop = 0;
4637 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4639 struct drm_display_info *info = &connector->display_info;
4641 u32 quirks = edid_get_quirks(edid);
4643 drm_reset_display_info(connector);
4645 info->width_mm = edid->width_cm * 10;
4646 info->height_mm = edid->height_cm * 10;
4648 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4650 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4652 if (edid->revision < 3)
4655 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4658 drm_parse_cea_ext(connector, edid);
4661 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4663 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4664 * tells us to assume 8 bpc color depth if the EDID doesn't have
4665 * extensions which tell otherwise.
4667 if (info->bpc == 0 && edid->revision == 3 &&
4668 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
4670 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4671 connector->name, info->bpc);
4674 /* Only defined for 1.4 with digital displays */
4675 if (edid->revision < 4)
4678 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4679 case DRM_EDID_DIGITAL_DEPTH_6:
4682 case DRM_EDID_DIGITAL_DEPTH_8:
4685 case DRM_EDID_DIGITAL_DEPTH_10:
4688 case DRM_EDID_DIGITAL_DEPTH_12:
4691 case DRM_EDID_DIGITAL_DEPTH_14:
4694 case DRM_EDID_DIGITAL_DEPTH_16:
4697 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4703 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4704 connector->name, info->bpc);
4706 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4707 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4708 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4709 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4710 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4714 static int validate_displayid(u8 *displayid, int length, int idx)
4718 struct displayid_hdr *base;
4720 base = (struct displayid_hdr *)&displayid[idx];
4722 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4723 base->rev, base->bytes, base->prod_id, base->ext_count);
4725 if (base->bytes + 5 > length - idx)
4727 for (i = idx; i <= base->bytes + 5; i++) {
4728 csum += displayid[i];
4731 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4737 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4738 struct displayid_detailed_timings_1 *timings)
4740 struct drm_display_mode *mode;
4741 unsigned pixel_clock = (timings->pixel_clock[0] |
4742 (timings->pixel_clock[1] << 8) |
4743 (timings->pixel_clock[2] << 16));
4744 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4745 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4746 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4747 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4748 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4749 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4750 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4751 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4752 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4753 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4754 mode = drm_mode_create(dev);
4758 mode->clock = pixel_clock * 10;
4759 mode->hdisplay = hactive;
4760 mode->hsync_start = mode->hdisplay + hsync;
4761 mode->hsync_end = mode->hsync_start + hsync_width;
4762 mode->htotal = mode->hdisplay + hblank;
4764 mode->vdisplay = vactive;
4765 mode->vsync_start = mode->vdisplay + vsync;
4766 mode->vsync_end = mode->vsync_start + vsync_width;
4767 mode->vtotal = mode->vdisplay + vblank;
4770 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4771 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4772 mode->type = DRM_MODE_TYPE_DRIVER;
4774 if (timings->flags & 0x80)
4775 mode->type |= DRM_MODE_TYPE_PREFERRED;
4776 mode->vrefresh = drm_mode_vrefresh(mode);
4777 drm_mode_set_name(mode);
4782 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4783 struct displayid_block *block)
4785 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4788 struct drm_display_mode *newmode;
4790 /* blocks must be multiple of 20 bytes length */
4791 if (block->num_bytes % 20)
4794 num_timings = block->num_bytes / 20;
4795 for (i = 0; i < num_timings; i++) {
4796 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4798 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4802 drm_mode_probed_add(connector, newmode);
4808 static int add_displayid_detailed_modes(struct drm_connector *connector,
4814 int length = EDID_LENGTH;
4815 struct displayid_block *block;
4818 displayid = drm_find_displayid_extension(edid);
4822 ret = validate_displayid(displayid, length, idx);
4826 idx += sizeof(struct displayid_hdr);
4827 for_each_displayid_db(displayid, block, idx, length) {
4828 switch (block->tag) {
4829 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4830 num_modes += add_displayid_detailed_1_modes(connector, block);
4838 * drm_add_edid_modes - add modes from EDID data, if available
4839 * @connector: connector we're probing
4842 * Add the specified modes to the connector's mode list. Also fills out the
4843 * &drm_display_info structure and ELD in @connector with any information which
4844 * can be derived from the edid.
4846 * Return: The number of modes added or 0 if we couldn't find any.
4848 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4854 clear_eld(connector);
4857 if (!drm_edid_is_valid(edid)) {
4858 clear_eld(connector);
4859 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4864 drm_edid_to_eld(connector, edid);
4867 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4868 * To avoid multiple parsing of same block, lets parse that map
4869 * from sink info, before parsing CEA modes.
4871 quirks = drm_add_display_info(connector, edid);
4874 * EDID spec says modes should be preferred in this order:
4875 * - preferred detailed mode
4876 * - other detailed modes from base block
4877 * - detailed modes from extension blocks
4878 * - CVT 3-byte code modes
4879 * - standard timing codes
4880 * - established timing codes
4881 * - modes inferred from GTF or CVT range information
4883 * We get this pretty much right.
4885 * XXX order for additional mode types in extension blocks?
4887 num_modes += add_detailed_modes(connector, edid, quirks);
4888 num_modes += add_cvt_modes(connector, edid);
4889 num_modes += add_standard_modes(connector, edid);
4890 num_modes += add_established_modes(connector, edid);
4891 num_modes += add_cea_modes(connector, edid);
4892 num_modes += add_alternate_cea_modes(connector, edid);
4893 num_modes += add_displayid_detailed_modes(connector, edid);
4894 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4895 num_modes += add_inferred_modes(connector, edid);
4897 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4898 edid_fixup_preferred(connector, quirks);
4900 if (quirks & EDID_QUIRK_FORCE_6BPC)
4901 connector->display_info.bpc = 6;
4903 if (quirks & EDID_QUIRK_FORCE_8BPC)
4904 connector->display_info.bpc = 8;
4906 if (quirks & EDID_QUIRK_FORCE_10BPC)
4907 connector->display_info.bpc = 10;
4909 if (quirks & EDID_QUIRK_FORCE_12BPC)
4910 connector->display_info.bpc = 12;
4914 EXPORT_SYMBOL(drm_add_edid_modes);
4917 * drm_add_modes_noedid - add modes for the connectors without EDID
4918 * @connector: connector we're probing
4919 * @hdisplay: the horizontal display limit
4920 * @vdisplay: the vertical display limit
4922 * Add the specified modes to the connector's mode list. Only when the
4923 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4925 * Return: The number of modes added or 0 if we couldn't find any.
4927 int drm_add_modes_noedid(struct drm_connector *connector,
4928 int hdisplay, int vdisplay)
4930 int i, count, num_modes = 0;
4931 struct drm_display_mode *mode;
4932 struct drm_device *dev = connector->dev;
4934 count = ARRAY_SIZE(drm_dmt_modes);
4940 for (i = 0; i < count; i++) {
4941 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4942 if (hdisplay && vdisplay) {
4944 * Only when two are valid, they will be used to check
4945 * whether the mode should be added to the mode list of
4948 if (ptr->hdisplay > hdisplay ||
4949 ptr->vdisplay > vdisplay)
4952 if (drm_mode_vrefresh(ptr) > 61)
4954 mode = drm_mode_duplicate(dev, ptr);
4956 drm_mode_probed_add(connector, mode);
4962 EXPORT_SYMBOL(drm_add_modes_noedid);
4965 * drm_set_preferred_mode - Sets the preferred mode of a connector
4966 * @connector: connector whose mode list should be processed
4967 * @hpref: horizontal resolution of preferred mode
4968 * @vpref: vertical resolution of preferred mode
4970 * Marks a mode as preferred if it matches the resolution specified by @hpref
4973 void drm_set_preferred_mode(struct drm_connector *connector,
4974 int hpref, int vpref)
4976 struct drm_display_mode *mode;
4978 list_for_each_entry(mode, &connector->probed_modes, head) {
4979 if (mode->hdisplay == hpref &&
4980 mode->vdisplay == vpref)
4981 mode->type |= DRM_MODE_TYPE_PREFERRED;
4984 EXPORT_SYMBOL(drm_set_preferred_mode);
4986 static bool is_hdmi2_sink(struct drm_connector *connector)
4989 * FIXME: sil-sii8620 doesn't have a connector around when
4990 * we need one, so we have to be prepared for a NULL connector.
4995 return connector->display_info.hdmi.scdc.supported ||
4996 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
4999 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5001 return sink_eotf & BIT(output_eotf);
5005 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5006 * HDR metadata from userspace
5007 * @frame: HDMI DRM infoframe
5008 * @conn_state: Connector state containing HDR metadata
5010 * Return: 0 on success or a negative error code on failure.
5013 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5014 const struct drm_connector_state *conn_state)
5016 struct drm_connector *connector;
5017 struct hdr_output_metadata *hdr_metadata;
5020 if (!frame || !conn_state)
5023 connector = conn_state->connector;
5025 if (!conn_state->hdr_output_metadata)
5028 hdr_metadata = conn_state->hdr_output_metadata->data;
5030 if (!hdr_metadata || !connector)
5033 /* Sink EOTF is Bit map while infoframe is absolute values */
5034 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5035 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5036 DRM_DEBUG_KMS("EOTF Not Supported\n");
5040 err = hdmi_drm_infoframe_init(frame);
5044 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5045 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5047 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5048 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5049 BUILD_BUG_ON(sizeof(frame->white_point) !=
5050 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5052 memcpy(&frame->display_primaries,
5053 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5054 sizeof(frame->display_primaries));
5056 memcpy(&frame->white_point,
5057 &hdr_metadata->hdmi_metadata_type1.white_point,
5058 sizeof(frame->white_point));
5060 frame->max_display_mastering_luminance =
5061 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5062 frame->min_display_mastering_luminance =
5063 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5064 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5065 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5069 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5072 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5073 * data from a DRM display mode
5074 * @frame: HDMI AVI infoframe
5075 * @connector: the connector
5076 * @mode: DRM display mode
5078 * Return: 0 on success or a negative error code on failure.
5081 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
5082 struct drm_connector *connector,
5083 const struct drm_display_mode *mode)
5085 enum hdmi_picture_aspect picture_aspect;
5088 if (!frame || !mode)
5091 err = hdmi_avi_infoframe_init(frame);
5095 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5096 frame->pixel_repeat = 1;
5098 frame->video_code = drm_match_cea_mode(mode);
5101 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5102 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5103 * have to make sure we dont break HDMI 1.4 sinks.
5105 if (!is_hdmi2_sink(connector) && frame->video_code > 64)
5106 frame->video_code = 0;
5109 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5110 * we should send its VIC in vendor infoframes, else send the
5111 * VIC in AVI infoframes. Lets check if this mode is present in
5112 * HDMI 1.4b 4K modes
5114 if (frame->video_code) {
5115 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
5116 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
5118 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
5119 frame->video_code = 0;
5122 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5125 * As some drivers don't support atomic, we can't use connector state.
5126 * So just initialize the frame with default values, just the same way
5127 * as it's done with other properties here.
5129 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5133 * Populate picture aspect ratio from either
5134 * user input (if specified) or from the CEA mode list.
5136 picture_aspect = mode->picture_aspect_ratio;
5137 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE)
5138 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code);
5141 * The infoframe can't convey anything but none, 4:3
5142 * and 16:9, so if the user has asked for anything else
5143 * we can only satisfy it by specifying the right VIC.
5145 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
5146 if (picture_aspect !=
5147 drm_get_cea_aspect_ratio(frame->video_code))
5149 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5152 frame->picture_aspect = picture_aspect;
5153 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
5154 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
5158 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
5160 /* HDMI Colorspace Spec Definitions */
5161 #define FULL_COLORIMETRY_MASK 0x1FF
5162 #define NORMAL_COLORIMETRY_MASK 0x3
5163 #define EXTENDED_COLORIMETRY_MASK 0x7
5164 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5166 #define C(x) ((x) << 0)
5167 #define EC(x) ((x) << 2)
5168 #define ACE(x) ((x) << 5)
5170 #define HDMI_COLORIMETRY_NO_DATA 0x0
5171 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5172 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5173 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5174 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5175 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5176 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5177 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5178 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5179 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5180 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5181 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5182 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5184 static const u32 hdmi_colorimetry_val[] = {
5185 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5186 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5187 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5188 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5189 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5190 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5191 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5192 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5193 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5194 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5195 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5203 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5204 * colorspace information
5205 * @frame: HDMI AVI infoframe
5206 * @conn_state: connector state
5209 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5210 const struct drm_connector_state *conn_state)
5212 u32 colorimetry_val;
5213 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5215 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5216 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5218 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5220 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5222 * ToDo: Extend it for ACE formats as well. Modify the infoframe
5223 * structure and extend it in drivers/video/hdmi
5225 frame->extended_colorimetry = (colorimetry_val >> 2) &
5226 EXTENDED_COLORIMETRY_MASK;
5228 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5231 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5232 * quantization range information
5233 * @frame: HDMI AVI infoframe
5234 * @connector: the connector
5235 * @mode: DRM display mode
5236 * @rgb_quant_range: RGB quantization range (Q)
5239 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
5240 struct drm_connector *connector,
5241 const struct drm_display_mode *mode,
5242 enum hdmi_quantization_range rgb_quant_range)
5244 const struct drm_display_info *info = &connector->display_info;
5248 * "A Source shall not send a non-zero Q value that does not correspond
5249 * to the default RGB Quantization Range for the transmitted Picture
5250 * unless the Sink indicates support for the Q bit in a Video
5251 * Capabilities Data Block."
5253 * HDMI 2.0 recommends sending non-zero Q when it does match the
5254 * default RGB quantization range for the mode, even when QS=0.
5256 if (info->rgb_quant_range_selectable ||
5257 rgb_quant_range == drm_default_rgb_quant_range(mode))
5258 frame->quantization_range = rgb_quant_range;
5260 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
5264 * "When transmitting any RGB colorimetry, the Source should set the
5265 * YQ-field to match the RGB Quantization Range being transmitted
5266 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5267 * set YQ=1) and the Sink shall ignore the YQ-field."
5269 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5270 * by non-zero YQ when receiving RGB. There doesn't seem to be any
5271 * good way to tell which version of CEA-861 the sink supports, so
5272 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5275 if (!is_hdmi2_sink(connector) ||
5276 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
5277 frame->ycc_quantization_range =
5278 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5280 frame->ycc_quantization_range =
5281 HDMI_YCC_QUANTIZATION_RANGE_FULL;
5283 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5285 static enum hdmi_3d_structure
5286 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5288 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5291 case DRM_MODE_FLAG_3D_FRAME_PACKING:
5292 return HDMI_3D_STRUCTURE_FRAME_PACKING;
5293 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5294 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5295 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5296 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5297 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5298 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5299 case DRM_MODE_FLAG_3D_L_DEPTH:
5300 return HDMI_3D_STRUCTURE_L_DEPTH;
5301 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5302 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5303 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5304 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5305 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5306 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5308 return HDMI_3D_STRUCTURE_INVALID;
5313 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5314 * data from a DRM display mode
5315 * @frame: HDMI vendor infoframe
5316 * @connector: the connector
5317 * @mode: DRM display mode
5319 * Note that there's is a need to send HDMI vendor infoframes only when using a
5320 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5321 * function will return -EINVAL, error that can be safely ignored.
5323 * Return: 0 on success or a negative error code on failure.
5326 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5327 struct drm_connector *connector,
5328 const struct drm_display_mode *mode)
5331 * FIXME: sil-sii8620 doesn't have a connector around when
5332 * we need one, so we have to be prepared for a NULL connector.
5334 bool has_hdmi_infoframe = connector ?
5335 connector->display_info.has_hdmi_infoframe : false;
5340 if (!frame || !mode)
5343 if (!has_hdmi_infoframe)
5346 vic = drm_match_hdmi_mode(mode);
5347 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
5350 * Even if it's not absolutely necessary to send the infoframe
5351 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5352 * know that the sink can handle it. This is based on a
5353 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5354 * have trouble realizing that they shuld switch from 3D to 2D
5355 * mode if the source simply stops sending the infoframe when
5356 * it wants to switch from 3D to 2D.
5359 if (vic && s3d_flags)
5362 err = hdmi_vendor_infoframe_init(frame);
5367 frame->s3d_struct = s3d_structure_from_display_mode(mode);
5371 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5373 static int drm_parse_tiled_block(struct drm_connector *connector,
5374 struct displayid_block *block)
5376 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5378 u8 tile_v_loc, tile_h_loc;
5379 u8 num_v_tile, num_h_tile;
5380 struct drm_tile_group *tg;
5382 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5383 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5385 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5386 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5387 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5388 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5390 connector->has_tile = true;
5391 if (tile->tile_cap & 0x80)
5392 connector->tile_is_single_monitor = true;
5394 connector->num_h_tile = num_h_tile + 1;
5395 connector->num_v_tile = num_v_tile + 1;
5396 connector->tile_h_loc = tile_h_loc;
5397 connector->tile_v_loc = tile_v_loc;
5398 connector->tile_h_size = w + 1;
5399 connector->tile_v_size = h + 1;
5401 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5402 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5403 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5404 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5405 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5407 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5409 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5414 if (connector->tile_group != tg) {
5415 /* if we haven't got a pointer,
5416 take the reference, drop ref to old tile group */
5417 if (connector->tile_group) {
5418 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5420 connector->tile_group = tg;
5422 /* if same tile group, then release the ref we just took. */
5423 drm_mode_put_tile_group(connector->dev, tg);
5427 static int drm_parse_display_id(struct drm_connector *connector,
5428 u8 *displayid, int length,
5429 bool is_edid_extension)
5431 /* if this is an EDID extension the first byte will be 0x70 */
5433 struct displayid_block *block;
5436 if (is_edid_extension)
5439 ret = validate_displayid(displayid, length, idx);
5443 idx += sizeof(struct displayid_hdr);
5444 for_each_displayid_db(displayid, block, idx, length) {
5445 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5446 block->tag, block->rev, block->num_bytes);
5448 switch (block->tag) {
5449 case DATA_BLOCK_TILED_DISPLAY:
5450 ret = drm_parse_tiled_block(connector, block);
5454 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5455 /* handled in mode gathering code. */
5457 case DATA_BLOCK_CTA:
5458 /* handled in the cea parser code. */
5461 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5468 static void drm_get_displayid(struct drm_connector *connector,
5471 void *displayid = NULL;
5473 connector->has_tile = false;
5474 displayid = drm_find_displayid_extension(edid);
5476 /* drop reference to any tile group we had */
5480 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5483 if (!connector->has_tile)
5487 if (connector->tile_group) {
5488 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5489 connector->tile_group = NULL;
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