drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "sdma0/sdma0_4_2_offset.h"
  34 #include "sdma0/sdma0_4_2_sh_mask.h"
  35 #include "sdma1/sdma1_4_2_offset.h"
  36 #include "sdma1/sdma1_4_2_sh_mask.h"
  37 #include "sdma2/sdma2_4_2_2_offset.h"
  38 #include "sdma2/sdma2_4_2_2_sh_mask.h"
  39 #include "sdma3/sdma3_4_2_2_offset.h"
  40 #include "sdma3/sdma3_4_2_2_sh_mask.h"
  41 #include "sdma4/sdma4_4_2_2_offset.h"
  42 #include "sdma4/sdma4_4_2_2_sh_mask.h"
  43 #include "sdma5/sdma5_4_2_2_offset.h"
  44 #include "sdma5/sdma5_4_2_2_sh_mask.h"
  45 #include "sdma6/sdma6_4_2_2_offset.h"
  46 #include "sdma6/sdma6_4_2_2_sh_mask.h"
  47 #include "sdma7/sdma7_4_2_2_offset.h"
  48 #include "sdma7/sdma7_4_2_2_sh_mask.h"
  49 #include "hdp/hdp_4_0_offset.h"
  50 #include "sdma0/sdma0_4_1_default.h"
  51
  52 #include "soc15_common.h"
  53 #include "soc15.h"
  54 #include "vega10_sdma_pkt_open.h"
  55
  56 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
  57 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
  58
  59 #include "amdgpu_ras.h"
  60
  61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
  62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
  63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
  64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
  65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
  66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
  67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
  68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
  69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
  70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin");
  71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin");
  72
  73 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
  74 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
  75
  76 #define WREG32_SDMA(instance, offset, value) \
  77         WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
  78 #define RREG32_SDMA(instance, offset) \
  79         RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
  80
  81 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
  82 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
  83 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  84 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  85
  86 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
  87         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
  88         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
  89         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
  90         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  91         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
  92         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  93         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
  94         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
  95         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  96         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
  97         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  98         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
  99         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
 100         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
 101         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
 102         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 103         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
 104         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 105         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
 106         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
 107         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 108         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
 109         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 110         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 111         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
 112 };
 113
 114 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
 115         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 116         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
 117         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 118         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 119         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)
 120 };
 121
 122 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
 123         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
 124         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
 125         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 126         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
 127         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001)
 128 };
 129
 130 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
 131         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 132         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 133         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
 134         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 135         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
 136         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
 137         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 138         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
 139         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 140         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 141         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
 142 };
 143
 144 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
 145         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 146 };
 147
 148 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
 149 {
 150         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 151         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 152         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 153         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 154         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 155         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 156         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 157         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 158         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003),
 159         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 160         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 161         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 162         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 163         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 164         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 165         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 166         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 167         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 168         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 169         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 170         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 171         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 172         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 173         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 174         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 175         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 176 };
 177
 178 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
 179         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 180         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
 181         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 182         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 183         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 184         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 185         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 186         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 187         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003),
 188         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 189         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 190         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 191         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 192         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 193         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 194         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 195         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 196         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 197         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 198         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 199         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 200         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 201         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 202         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 203         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 204         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 205 };
 206
 207 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
 208 {
 209         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
 210         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
 211 };
 212
 213 static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
 214 {
 215         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),
 216         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
 217 };
 218
 219 static const struct soc15_reg_golden golden_settings_sdma_arct[] =
 220 {
 221         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 222         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 223         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 224         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 225         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 226         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 227         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 228         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 229         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 230         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 231         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 232         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 233         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 234         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 235         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 236         SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 237         SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 238         SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 239         SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 240         SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 241         SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 242         SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 243         SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 244         SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002)
 245 };
 246
 247 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
 248         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 249         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 250         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
 251         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002),
 252         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 253         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
 254         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 255         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 256         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 257 };
 258
 259 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
 260                 u32 instance, u32 offset)
 261 {
 262         switch (instance) {
 263         case 0:
 264                 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
 265         case 1:
 266                 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset);
 267         case 2:
 268                 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
 269         case 3:
 270                 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
 271         case 4:
 272                 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
 273         case 5:
 274                 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
 275         case 6:
 276                 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
 277         case 7:
 278                 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
 279         default:
 280                 break;
 281         }
 282         return 0;
 283 }
 284
 285 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num)
 286 {
 287         switch (seq_num) {
 288         case 0:
 289                 return SOC15_IH_CLIENTID_SDMA0;
 290         case 1:
 291                 return SOC15_IH_CLIENTID_SDMA1;
 292         case 2:
 293                 return SOC15_IH_CLIENTID_SDMA2;
 294         case 3:
 295                 return SOC15_IH_CLIENTID_SDMA3;
 296         case 4:
 297                 return SOC15_IH_CLIENTID_SDMA4;
 298         case 5:
 299                 return SOC15_IH_CLIENTID_SDMA5;
 300         case 6:
 301                 return SOC15_IH_CLIENTID_SDMA6;
 302         case 7:
 303                 return SOC15_IH_CLIENTID_SDMA7;
 304         default:
 305                 break;
 306         }
 307         return -EINVAL;
 308 }
 309
 310 static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
 311 {
 312         switch (client_id) {
 313         case SOC15_IH_CLIENTID_SDMA0:
 314                 return 0;
 315         case SOC15_IH_CLIENTID_SDMA1:
 316                 return 1;
 317         case SOC15_IH_CLIENTID_SDMA2:
 318                 return 2;
 319         case SOC15_IH_CLIENTID_SDMA3:
 320                 return 3;
 321         case SOC15_IH_CLIENTID_SDMA4:
 322                 return 4;
 323         case SOC15_IH_CLIENTID_SDMA5:
 324                 return 5;
 325         case SOC15_IH_CLIENTID_SDMA6:
 326                 return 6;
 327         case SOC15_IH_CLIENTID_SDMA7:
 328                 return 7;
 329         default:
 330                 break;
 331         }
 332         return -EINVAL;
 333 }
 334
 335 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
 336 {
 337         switch (adev->asic_type) {
 338         case CHIP_VEGA10:
 339                 soc15_program_register_sequence(adev,
 340                                                 golden_settings_sdma_4,
 341                                                 ARRAY_SIZE(golden_settings_sdma_4));
 342                 soc15_program_register_sequence(adev,
 343                                                 golden_settings_sdma_vg10,
 344                                                 ARRAY_SIZE(golden_settings_sdma_vg10));
 345                 break;
 346         case CHIP_VEGA12:
 347                 soc15_program_register_sequence(adev,
 348                                                 golden_settings_sdma_4,
 349                                                 ARRAY_SIZE(golden_settings_sdma_4));
 350                 soc15_program_register_sequence(adev,
 351                                                 golden_settings_sdma_vg12,
 352                                                 ARRAY_SIZE(golden_settings_sdma_vg12));
 353                 break;
 354         case CHIP_VEGA20:
 355                 soc15_program_register_sequence(adev,
 356                                                 golden_settings_sdma0_4_2_init,
 357                                                 ARRAY_SIZE(golden_settings_sdma0_4_2_init));
 358                 soc15_program_register_sequence(adev,
 359                                                 golden_settings_sdma0_4_2,
 360                                                 ARRAY_SIZE(golden_settings_sdma0_4_2));
 361                 soc15_program_register_sequence(adev,
 362                                                 golden_settings_sdma1_4_2,
 363                                                 ARRAY_SIZE(golden_settings_sdma1_4_2));
 364                 break;
 365         case CHIP_ARCTURUS:
 366                 soc15_program_register_sequence(adev,
 367                                                 golden_settings_sdma_arct,
 368                                                 ARRAY_SIZE(golden_settings_sdma_arct));
 369                 break;
 370         case CHIP_RAVEN:
 371                 soc15_program_register_sequence(adev,
 372                                                 golden_settings_sdma_4_1,
 373                                                 ARRAY_SIZE(golden_settings_sdma_4_1));
 374                 if (adev->rev_id >= 8)
 375                         soc15_program_register_sequence(adev,
 376                                                         golden_settings_sdma_rv2,
 377                                                         ARRAY_SIZE(golden_settings_sdma_rv2));
 378                 else
 379                         soc15_program_register_sequence(adev,
 380                                                         golden_settings_sdma_rv1,
 381                                                         ARRAY_SIZE(golden_settings_sdma_rv1));
 382                 break;
 383         case CHIP_RENOIR:
 384                 soc15_program_register_sequence(adev,
 385                                                 golden_settings_sdma_4_3,
 386                                                 ARRAY_SIZE(golden_settings_sdma_4_3));
 387                 break;
 388         default:
 389                 break;
 390         }
 391 }
 392
 393 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
 394 {
 395         int err = 0;
 396         const struct sdma_firmware_header_v1_0 *hdr;
 397
 398         err = amdgpu_ucode_validate(sdma_inst->fw);
 399         if (err)
 400                 return err;
 401
 402         hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
 403         sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
 404         sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
 405
 406         if (sdma_inst->feature_version >= 20)
 407                 sdma_inst->burst_nop = true;
 408
 409         return 0;
 410 }
 411
 412 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
 413 {
 414         int i;
 415
 416         for (i = 0; i < adev->sdma.num_instances; i++) {
 417                 if (adev->sdma.instance[i].fw != NULL)
 418                         release_firmware(adev->sdma.instance[i].fw);
 419
 420                 /* arcturus shares the same FW memory across
 421                    all SDMA isntances */
 422                 if (adev->asic_type == CHIP_ARCTURUS)
 423                         break;
 424         }
 425
 426         memset((void*)adev->sdma.instance, 0,
 427                 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
 428 }
 429
 430 /**
 431  * sdma_v4_0_init_microcode - load ucode images from disk
 432  *
 433  * @adev: amdgpu_device pointer
 434  *
 435  * Use the firmware interface to load the ucode images into
 436  * the driver (not loaded into hw).
 437  * Returns 0 on success, error on failure.
 438  */
 439
 440 // emulation only, won't work on real chip
 441 // vega10 real chip need to use PSP to load firmware
 442 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
 443 {
 444         const char *chip_name;
 445         char fw_name[30];
 446         int err = 0, i;
 447         struct amdgpu_firmware_info *info = NULL;
 448         const struct common_firmware_header *header = NULL;
 449
 450         DRM_DEBUG("\n");
 451
 452         switch (adev->asic_type) {
 453         case CHIP_VEGA10:
 454                 chip_name = "vega10";
 455                 break;
 456         case CHIP_VEGA12:
 457                 chip_name = "vega12";
 458                 break;
 459         case CHIP_VEGA20:
 460                 chip_name = "vega20";
 461                 break;
 462         case CHIP_RAVEN:
 463                 if (adev->rev_id >= 8)
 464                         chip_name = "raven2";
 465                 else if (adev->pdev->device == 0x15d8)
 466                         chip_name = "picasso";
 467                 else
 468                         chip_name = "raven";
 469                 break;
 470         case CHIP_ARCTURUS:
 471                 chip_name = "arcturus";
 472                 break;
 473         case CHIP_RENOIR:
 474                 chip_name = "renoir";
 475                 break;
 476         default:
 477                 BUG();
 478         }
 479
 480         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 481
 482         err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
 483         if (err)
 484                 goto out;
 485
 486         err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]);
 487         if (err)
 488                 goto out;
 489
 490         for (i = 1; i < adev->sdma.num_instances; i++) {
 491                 if (adev->asic_type == CHIP_ARCTURUS) {
 492                         /* Acturus will leverage the same FW memory
 493                            for every SDMA instance */
 494                         memcpy((void*)&adev->sdma.instance[i],
 495                                (void*)&adev->sdma.instance[0],
 496                                sizeof(struct amdgpu_sdma_instance));
 497                 }
 498                 else {
 499                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
 500
 501                         err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 502                         if (err)
 503                                 goto out;
 504
 505                         err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]);
 506                         if (err)
 507                                 goto out;
 508                 }
 509         }
 510
 511         DRM_DEBUG("psp_load == '%s'\n",
 512                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 513
 514         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 515                 for (i = 0; i < adev->sdma.num_instances; i++) {
 516                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 517                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 518                         info->fw = adev->sdma.instance[i].fw;
 519                         header = (const struct common_firmware_header *)info->fw->data;
 520                         adev->firmware.fw_size +=
 521                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 522                 }
 523         }
 524
 525 out:
 526         if (err) {
 527                 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
 528                 sdma_v4_0_destroy_inst_ctx(adev);
 529         }
 530         return err;
 531 }
 532
 533 /**
 534  * sdma_v4_0_ring_get_rptr - get the current read pointer
 535  *
 536  * @ring: amdgpu ring pointer
 537  *
 538  * Get the current rptr from the hardware (VEGA10+).
 539  */
 540 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
 541 {
 542         u64 *rptr;
 543
 544         /* XXX check if swapping is necessary on BE */
 545         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 546
 547         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 548         return ((*rptr) >> 2);
 549 }
 550
 551 /**
 552  * sdma_v4_0_ring_get_wptr - get the current write pointer
 553  *
 554  * @ring: amdgpu ring pointer
 555  *
 556  * Get the current wptr from the hardware (VEGA10+).
 557  */
 558 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
 559 {
 560         struct amdgpu_device *adev = ring->adev;
 561         u64 wptr;
 562
 563         if (ring->use_doorbell) {
 564                 /* XXX check if swapping is necessary on BE */
 565                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 566                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 567         } else {
 568                 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
 569                 wptr = wptr << 32;
 570                 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
 571                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
 572                                 ring->me, wptr);
 573         }
 574
 575         return wptr >> 2;
 576 }
 577
 578 /**
 579  * sdma_v4_0_ring_set_wptr - commit the write pointer
 580  *
 581  * @ring: amdgpu ring pointer
 582  *
 583  * Write the wptr back to the hardware (VEGA10+).
 584  */
 585 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 586 {
 587         struct amdgpu_device *adev = ring->adev;
 588
 589         DRM_DEBUG("Setting write pointer\n");
 590         if (ring->use_doorbell) {
 591                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 592
 593                 DRM_DEBUG("Using doorbell -- "
 594                                 "wptr_offs == 0x%08x "
 595                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 596                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 597                                 ring->wptr_offs,
 598                                 lower_32_bits(ring->wptr << 2),
 599                                 upper_32_bits(ring->wptr << 2));
 600                 /* XXX check if swapping is necessary on BE */
 601                 WRITE_ONCE(*wb, (ring->wptr << 2));
 602                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 603                                 ring->doorbell_index, ring->wptr << 2);
 604                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 605         } else {
 606                 DRM_DEBUG("Not using doorbell -- "
 607                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 608                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 609                                 ring->me,
 610                                 lower_32_bits(ring->wptr << 2),
 611                                 ring->me,
 612                                 upper_32_bits(ring->wptr << 2));
 613                 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
 614                             lower_32_bits(ring->wptr << 2));
 615                 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
 616                             upper_32_bits(ring->wptr << 2));
 617         }
 618 }
 619
 620 /**
 621  * sdma_v4_0_page_ring_get_wptr - get the current write pointer
 622  *
 623  * @ring: amdgpu ring pointer
 624  *
 625  * Get the current wptr from the hardware (VEGA10+).
 626  */
 627 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
 628 {
 629         struct amdgpu_device *adev = ring->adev;
 630         u64 wptr;
 631
 632         if (ring->use_doorbell) {
 633                 /* XXX check if swapping is necessary on BE */
 634                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 635         } else {
 636                 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
 637                 wptr = wptr << 32;
 638                 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);
 639         }
 640
 641         return wptr >> 2;
 642 }
 643
 644 /**
 645  * sdma_v4_0_ring_set_wptr - commit the write pointer
 646  *
 647  * @ring: amdgpu ring pointer
 648  *
 649  * Write the wptr back to the hardware (VEGA10+).
 650  */
 651 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring)
 652 {
 653         struct amdgpu_device *adev = ring->adev;
 654
 655         if (ring->use_doorbell) {
 656                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 657
 658                 /* XXX check if swapping is necessary on BE */
 659                 WRITE_ONCE(*wb, (ring->wptr << 2));
 660                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 661         } else {
 662                 uint64_t wptr = ring->wptr << 2;
 663
 664                 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,
 665                             lower_32_bits(wptr));
 666                 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,
 667                             upper_32_bits(wptr));
 668         }
 669 }
 670
 671 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 672 {
 673         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 674         int i;
 675
 676         for (i = 0; i < count; i++)
 677                 if (sdma && sdma->burst_nop && (i == 0))
 678                         amdgpu_ring_write(ring, ring->funcs->nop |
 679                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 680                 else
 681                         amdgpu_ring_write(ring, ring->funcs->nop);
 682 }
 683
 684 /**
 685  * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
 686  *
 687  * @ring: amdgpu ring pointer
 688  * @ib: IB object to schedule
 689  *
 690  * Schedule an IB in the DMA ring (VEGA10).
 691  */
 692 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
 693                                    struct amdgpu_job *job,
 694                                    struct amdgpu_ib *ib,
 695                                    uint32_t flags)
 696 {
 697         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 698
 699         /* IB packet must end on a 8 DW boundary */
 700         sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 701
 702         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 703                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 704         /* base must be 32 byte aligned */
 705         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 706         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 707         amdgpu_ring_write(ring, ib->length_dw);
 708         amdgpu_ring_write(ring, 0);
 709         amdgpu_ring_write(ring, 0);
 710
 711 }
 712
 713 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
 714                                    int mem_space, int hdp,
 715                                    uint32_t addr0, uint32_t addr1,
 716                                    uint32_t ref, uint32_t mask,
 717                                    uint32_t inv)
 718 {
 719         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 720                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
 721                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
 722                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 723         if (mem_space) {
 724                 /* memory */
 725                 amdgpu_ring_write(ring, addr0);
 726                 amdgpu_ring_write(ring, addr1);
 727         } else {
 728                 /* registers */
 729                 amdgpu_ring_write(ring, addr0 << 2);
 730                 amdgpu_ring_write(ring, addr1 << 2);
 731         }
 732         amdgpu_ring_write(ring, ref); /* reference */
 733         amdgpu_ring_write(ring, mask); /* mask */
 734         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 735                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
 736 }
 737
 738 /**
 739  * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 740  *
 741  * @ring: amdgpu ring pointer
 742  *
 743  * Emit an hdp flush packet on the requested DMA ring.
 744  */
 745 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 746 {
 747         struct amdgpu_device *adev = ring->adev;
 748         u32 ref_and_mask = 0;
 749         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
 750
 751         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 752
 753         sdma_v4_0_wait_reg_mem(ring, 0, 1,
 754                                adev->nbio_funcs->get_hdp_flush_done_offset(adev),
 755                                adev->nbio_funcs->get_hdp_flush_req_offset(adev),
 756                                ref_and_mask, ref_and_mask, 10);
 757 }
 758
 759 /**
 760  * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
 761  *
 762  * @ring: amdgpu ring pointer
 763  * @fence: amdgpu fence object
 764  *
 765  * Add a DMA fence packet to the ring to write
 766  * the fence seq number and DMA trap packet to generate
 767  * an interrupt if needed (VEGA10).
 768  */
 769 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 770                                       unsigned flags)
 771 {
 772         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 773         /* write the fence */
 774         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 775         /* zero in first two bits */
 776         BUG_ON(addr & 0x3);
 777         amdgpu_ring_write(ring, lower_32_bits(addr));
 778         amdgpu_ring_write(ring, upper_32_bits(addr));
 779         amdgpu_ring_write(ring, lower_32_bits(seq));
 780
 781         /* optionally write high bits as well */
 782         if (write64bit) {
 783                 addr += 4;
 784                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 785                 /* zero in first two bits */
 786                 BUG_ON(addr & 0x3);
 787                 amdgpu_ring_write(ring, lower_32_bits(addr));
 788                 amdgpu_ring_write(ring, upper_32_bits(addr));
 789                 amdgpu_ring_write(ring, upper_32_bits(seq));
 790         }
 791
 792         /* generate an interrupt */
 793         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 794         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 795 }
 796
 797
 798 /**
 799  * sdma_v4_0_gfx_stop - stop the gfx async dma engines
 800  *
 801  * @adev: amdgpu_device pointer
 802  *
 803  * Stop the gfx async dma ring buffers (VEGA10).
 804  */
 805 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
 806 {
 807         struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
 808         u32 rb_cntl, ib_cntl;
 809         int i, unset = 0;
 810
 811         for (i = 0; i < adev->sdma.num_instances; i++) {
 812                 sdma[i] = &adev->sdma.instance[i].ring;
 813
 814                 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) {
 815                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
 816                         unset = 1;
 817                 }
 818
 819                 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
 820                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 821                 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
 822                 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
 823                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 824                 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
 825
 826                 sdma[i]->sched.ready = false;
 827         }
 828 }
 829
 830 /**
 831  * sdma_v4_0_rlc_stop - stop the compute async dma engines
 832  *
 833  * @adev: amdgpu_device pointer
 834  *
 835  * Stop the compute async dma queues (VEGA10).
 836  */
 837 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
 838 {
 839         /* XXX todo */
 840 }
 841
 842 /**
 843  * sdma_v4_0_page_stop - stop the page async dma engines
 844  *
 845  * @adev: amdgpu_device pointer
 846  *
 847  * Stop the page async dma ring buffers (VEGA10).
 848  */
 849 static void sdma_v4_0_page_stop(struct amdgpu_device *adev)
 850 {
 851         struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
 852         u32 rb_cntl, ib_cntl;
 853         int i;
 854         bool unset = false;
 855
 856         for (i = 0; i < adev->sdma.num_instances; i++) {
 857                 sdma[i] = &adev->sdma.instance[i].page;
 858
 859                 if ((adev->mman.buffer_funcs_ring == sdma[i]) &&
 860                         (unset == false)) {
 861                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
 862                         unset = true;
 863                 }
 864
 865                 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
 866                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
 867                                         RB_ENABLE, 0);
 868                 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
 869                 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
 870                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
 871                                         IB_ENABLE, 0);
 872                 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
 873
 874                 sdma[i]->sched.ready = false;
 875         }
 876 }
 877
 878 /**
 879  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 880  *
 881  * @adev: amdgpu_device pointer
 882  * @enable: enable/disable the DMA MEs context switch.
 883  *
 884  * Halt or unhalt the async dma engines context switch (VEGA10).
 885  */
 886 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 887 {
 888         u32 f32_cntl, phase_quantum = 0;
 889         int i;
 890
 891         if (amdgpu_sdma_phase_quantum) {
 892                 unsigned value = amdgpu_sdma_phase_quantum;
 893                 unsigned unit = 0;
 894
 895                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 896                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 897                         value = (value + 1) >> 1;
 898                         unit++;
 899                 }
 900                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 901                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 902                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 903                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 904                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 905                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 906                         WARN_ONCE(1,
 907                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 908                                   value << unit);
 909                 }
 910                 phase_quantum =
 911                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 912                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 913         }
 914
 915         for (i = 0; i < adev->sdma.num_instances; i++) {
 916                 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
 917                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 918                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 919                 if (enable && amdgpu_sdma_phase_quantum) {
 920                         WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
 921                         WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
 922                         WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
 923                 }
 924                 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
 925         }
 926
 927 }
 928
 929 /**
 930  * sdma_v4_0_enable - stop the async dma engines
 931  *
 932  * @adev: amdgpu_device pointer
 933  * @enable: enable/disable the DMA MEs.
 934  *
 935  * Halt or unhalt the async dma engines (VEGA10).
 936  */
 937 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
 938 {
 939         u32 f32_cntl;
 940         int i;
 941
 942         if (enable == false) {
 943                 sdma_v4_0_gfx_stop(adev);
 944                 sdma_v4_0_rlc_stop(adev);
 945                 if (adev->sdma.has_page_queue)
 946                         sdma_v4_0_page_stop(adev);
 947         }
 948
 949         for (i = 0; i < adev->sdma.num_instances; i++) {
 950                 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
 951                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 952                 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
 953         }
 954 }
 955
 956 /**
 957  * sdma_v4_0_rb_cntl - get parameters for rb_cntl
 958  */
 959 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
 960 {
 961         /* Set ring buffer size in dwords */
 962         uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
 963
 964         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 965 #ifdef __BIG_ENDIAN
 966         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 967         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 968                                 RPTR_WRITEBACK_SWAP_ENABLE, 1);
 969 #endif
 970         return rb_cntl;
 971 }
 972
 973 /**
 974  * sdma_v4_0_gfx_resume - setup and start the async dma engines
 975  *
 976  * @adev: amdgpu_device pointer
 977  * @i: instance to resume
 978  *
 979  * Set up the gfx DMA ring buffers and enable them (VEGA10).
 980  * Returns 0 for success, error for failure.
 981  */
 982 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
 983 {
 984         struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
 985         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 986         u32 wb_offset;
 987         u32 doorbell;
 988         u32 doorbell_offset;
 989         u64 wptr_gpu_addr;
 990
 991         wb_offset = (ring->rptr_offs * 4);
 992
 993         rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
 994         rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
 995         WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
 996
 997         /* Initialize the ring buffer's read and write pointers */
 998         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
 999         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);
1000         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
1001         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
1002
1003         /* set the wb address whether it's enabled or not */
1004         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
1005                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1006         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
1007                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1008
1009         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1010                                 RPTR_WRITEBACK_ENABLE, 1);
1011
1012         WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
1013         WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
1014
1015         ring->wptr = 0;
1016
1017         /* before programing wptr to a less value, need set minor_ptr_update first */
1018         WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);
1019
1020         doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);
1021         doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);
1022
1023         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,
1024                                  ring->use_doorbell);
1025         doorbell_offset = REG_SET_FIELD(doorbell_offset,
1026                                         SDMA0_GFX_DOORBELL_OFFSET,
1027                                         OFFSET, ring->doorbell_index);
1028         WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
1029         WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
1030
1031         sdma_v4_0_ring_set_wptr(ring);
1032
1033         /* set minor_ptr_update to 0 after wptr programed */
1034         WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
1035
1036         /* setup the wptr shadow polling */
1037         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1038         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
1039                     lower_32_bits(wptr_gpu_addr));
1040         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
1041                     upper_32_bits(wptr_gpu_addr));
1042         wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
1043         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1044                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
1045                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1046         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1047
1048         /* enable DMA RB */
1049         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
1050         WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1051
1052         ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
1053         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
1054 #ifdef __BIG_ENDIAN
1055         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
1056 #endif
1057         /* enable DMA IBs */
1058         WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1059
1060         ring->sched.ready = true;
1061 }
1062
1063 /**
1064  * sdma_v4_0_page_resume - setup and start the async dma engines
1065  *
1066  * @adev: amdgpu_device pointer
1067  * @i: instance to resume
1068  *
1069  * Set up the page DMA ring buffers and enable them (VEGA10).
1070  * Returns 0 for success, error for failure.
1071  */
1072 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
1073 {
1074         struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
1075         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1076         u32 wb_offset;
1077         u32 doorbell;
1078         u32 doorbell_offset;
1079         u64 wptr_gpu_addr;
1080
1081         wb_offset = (ring->rptr_offs * 4);
1082
1083         rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1084         rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1085         WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1086
1087         /* Initialize the ring buffer's read and write pointers */
1088         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0);
1089         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0);
1090         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0);
1091         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0);
1092
1093         /* set the wb address whether it's enabled or not */
1094         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,
1095                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1096         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,
1097                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1098
1099         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1100                                 RPTR_WRITEBACK_ENABLE, 1);
1101
1102         WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8);
1103         WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
1104
1105         ring->wptr = 0;
1106
1107         /* before programing wptr to a less value, need set minor_ptr_update first */
1108         WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1);
1109
1110         doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL);
1111         doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET);
1112
1113         doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,
1114                                  ring->use_doorbell);
1115         doorbell_offset = REG_SET_FIELD(doorbell_offset,
1116                                         SDMA0_PAGE_DOORBELL_OFFSET,
1117                                         OFFSET, ring->doorbell_index);
1118         WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
1119         WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
1120
1121         /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */
1122         sdma_v4_0_page_ring_set_wptr(ring);
1123
1124         /* set minor_ptr_update to 0 after wptr programed */
1125         WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
1126
1127         /* setup the wptr shadow polling */
1128         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1129         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,
1130                     lower_32_bits(wptr_gpu_addr));
1131         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,
1132                     upper_32_bits(wptr_gpu_addr));
1133         wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
1134         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1135                                        SDMA0_PAGE_RB_WPTR_POLL_CNTL,
1136                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1137         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1138
1139         /* enable DMA RB */
1140         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);
1141         WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1142
1143         ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1144         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);
1145 #ifdef __BIG_ENDIAN
1146         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
1147 #endif
1148         /* enable DMA IBs */
1149         WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1150
1151         ring->sched.ready = true;
1152 }
1153
1154 static void
1155 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
1156 {
1157         uint32_t def, data;
1158
1159         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
1160                 /* enable idle interrupt */
1161                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1162                 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1163
1164                 if (data != def)
1165                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1166         } else {
1167                 /* disable idle interrupt */
1168                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1169                 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1170                 if (data != def)
1171                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1172         }
1173 }
1174
1175 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
1176 {
1177         uint32_t def, data;
1178
1179         /* Enable HW based PG. */
1180         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1181         data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
1182         if (data != def)
1183                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1184
1185         /* enable interrupt */
1186         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1187         data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1188         if (data != def)
1189                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1190
1191         /* Configure hold time to filter in-valid power on/off request. Use default right now */
1192         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1193         data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
1194         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
1195         /* Configure switch time for hysteresis purpose. Use default right now */
1196         data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
1197         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
1198         if(data != def)
1199                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1200 }
1201
1202 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
1203 {
1204         if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
1205                 return;
1206
1207         switch (adev->asic_type) {
1208         case CHIP_RAVEN:
1209         case CHIP_RENOIR:
1210                 sdma_v4_1_init_power_gating(adev);
1211                 sdma_v4_1_update_power_gating(adev, true);
1212                 break;
1213         default:
1214                 break;
1215         }
1216 }
1217
1218 /**
1219  * sdma_v4_0_rlc_resume - setup and start the async dma engines
1220  *
1221  * @adev: amdgpu_device pointer
1222  *
1223  * Set up the compute DMA queues and enable them (VEGA10).
1224  * Returns 0 for success, error for failure.
1225  */
1226 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
1227 {
1228         sdma_v4_0_init_pg(adev);
1229
1230         return 0;
1231 }
1232
1233 /**
1234  * sdma_v4_0_load_microcode - load the sDMA ME ucode
1235  *
1236  * @adev: amdgpu_device pointer
1237  *
1238  * Loads the sDMA0/1 ucode.
1239  * Returns 0 for success, -EINVAL if the ucode is not available.
1240  */
1241 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
1242 {
1243         const struct sdma_firmware_header_v1_0 *hdr;
1244         const __le32 *fw_data;
1245         u32 fw_size;
1246         int i, j;
1247
1248         /* halt the MEs */
1249         sdma_v4_0_enable(adev, false);
1250
1251         for (i = 0; i < adev->sdma.num_instances; i++) {
1252                 if (!adev->sdma.instance[i].fw)
1253                         return -EINVAL;
1254
1255                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
1256                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
1257                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1258
1259                 fw_data = (const __le32 *)
1260                         (adev->sdma.instance[i].fw->data +
1261                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1262
1263                 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);
1264
1265                 for (j = 0; j < fw_size; j++)
1266                         WREG32_SDMA(i, mmSDMA0_UCODE_DATA,
1267                                     le32_to_cpup(fw_data++));
1268
1269                 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,
1270                             adev->sdma.instance[i].fw_version);
1271         }
1272
1273         return 0;
1274 }
1275
1276 /**
1277  * sdma_v4_0_start - setup and start the async dma engines
1278  *
1279  * @adev: amdgpu_device pointer
1280  *
1281  * Set up the DMA engines and enable them (VEGA10).
1282  * Returns 0 for success, error for failure.
1283  */
1284 static int sdma_v4_0_start(struct amdgpu_device *adev)
1285 {
1286         struct amdgpu_ring *ring;
1287         int i, r = 0;
1288
1289         if (amdgpu_sriov_vf(adev)) {
1290                 sdma_v4_0_ctx_switch_enable(adev, false);
1291                 sdma_v4_0_enable(adev, false);
1292         } else {
1293
1294                 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1295                         r = sdma_v4_0_load_microcode(adev);
1296                         if (r)
1297                                 return r;
1298                 }
1299
1300                 /* unhalt the MEs */
1301                 sdma_v4_0_enable(adev, true);
1302                 /* enable sdma ring preemption */
1303                 sdma_v4_0_ctx_switch_enable(adev, true);
1304         }
1305
1306         /* start the gfx rings and rlc compute queues */
1307         for (i = 0; i < adev->sdma.num_instances; i++) {
1308                 uint32_t temp;
1309
1310                 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
1311                 sdma_v4_0_gfx_resume(adev, i);
1312                 if (adev->sdma.has_page_queue)
1313                         sdma_v4_0_page_resume(adev, i);
1314
1315                 /* set utc l1 enable flag always to 1 */
1316                 temp = RREG32_SDMA(i, mmSDMA0_CNTL);
1317                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
1318                 WREG32_SDMA(i, mmSDMA0_CNTL, temp);
1319
1320                 if (!amdgpu_sriov_vf(adev)) {
1321                         /* unhalt engine */
1322                         temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1323                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
1324                         WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
1325                 }
1326         }
1327
1328         if (amdgpu_sriov_vf(adev)) {
1329                 sdma_v4_0_ctx_switch_enable(adev, true);
1330                 sdma_v4_0_enable(adev, true);
1331         } else {
1332                 r = sdma_v4_0_rlc_resume(adev);
1333                 if (r)
1334                         return r;
1335         }
1336
1337         for (i = 0; i < adev->sdma.num_instances; i++) {
1338                 ring = &adev->sdma.instance[i].ring;
1339
1340                 r = amdgpu_ring_test_helper(ring);
1341                 if (r)
1342                         return r;
1343
1344                 if (adev->sdma.has_page_queue) {
1345                         struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1346
1347                         r = amdgpu_ring_test_helper(page);
1348                         if (r)
1349                                 return r;
1350
1351                         if (adev->mman.buffer_funcs_ring == page)
1352                                 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1353                 }
1354
1355                 if (adev->mman.buffer_funcs_ring == ring)
1356                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
1357         }
1358
1359         return r;
1360 }
1361
1362 /**
1363  * sdma_v4_0_ring_test_ring - simple async dma engine test
1364  *
1365  * @ring: amdgpu_ring structure holding ring information
1366  *
1367  * Test the DMA engine by writing using it to write an
1368  * value to memory. (VEGA10).
1369  * Returns 0 for success, error for failure.
1370  */
1371 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
1372 {
1373         struct amdgpu_device *adev = ring->adev;
1374         unsigned i;
1375         unsigned index;
1376         int r;
1377         u32 tmp;
1378         u64 gpu_addr;
1379
1380         r = amdgpu_device_wb_get(adev, &index);
1381         if (r)
1382                 return r;
1383
1384         gpu_addr = adev->wb.gpu_addr + (index * 4);
1385         tmp = 0xCAFEDEAD;
1386         adev->wb.wb[index] = cpu_to_le32(tmp);
1387
1388         r = amdgpu_ring_alloc(ring, 5);
1389         if (r)
1390                 goto error_free_wb;
1391
1392         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1393                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1394         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1395         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1396         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1397         amdgpu_ring_write(ring, 0xDEADBEEF);
1398         amdgpu_ring_commit(ring);
1399
1400         for (i = 0; i < adev->usec_timeout; i++) {
1401                 tmp = le32_to_cpu(adev->wb.wb[index]);
1402                 if (tmp == 0xDEADBEEF)
1403                         break;
1404                 udelay(1);
1405         }
1406
1407         if (i >= adev->usec_timeout)
1408                 r = -ETIMEDOUT;
1409
1410 error_free_wb:
1411         amdgpu_device_wb_free(adev, index);
1412         return r;
1413 }
1414
1415 /**
1416  * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
1417  *
1418  * @ring: amdgpu_ring structure holding ring information
1419  *
1420  * Test a simple IB in the DMA ring (VEGA10).
1421  * Returns 0 on success, error on failure.
1422  */
1423 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1424 {
1425         struct amdgpu_device *adev = ring->adev;
1426         struct amdgpu_ib ib;
1427         struct dma_fence *f = NULL;
1428         unsigned index;
1429         long r;
1430         u32 tmp = 0;
1431         u64 gpu_addr;
1432
1433         r = amdgpu_device_wb_get(adev, &index);
1434         if (r)
1435                 return r;
1436
1437         gpu_addr = adev->wb.gpu_addr + (index * 4);
1438         tmp = 0xCAFEDEAD;
1439         adev->wb.wb[index] = cpu_to_le32(tmp);
1440         memset(&ib, 0, sizeof(ib));
1441         r = amdgpu_ib_get(adev, NULL, 256, &ib);
1442         if (r)
1443                 goto err0;
1444
1445         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1446                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1447         ib.ptr[1] = lower_32_bits(gpu_addr);
1448         ib.ptr[2] = upper_32_bits(gpu_addr);
1449         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1450         ib.ptr[4] = 0xDEADBEEF;
1451         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1452         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1453         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1454         ib.length_dw = 8;
1455
1456         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1457         if (r)
1458                 goto err1;
1459
1460         r = dma_fence_wait_timeout(f, false, timeout);
1461         if (r == 0) {
1462                 r = -ETIMEDOUT;
1463                 goto err1;
1464         } else if (r < 0) {
1465                 goto err1;
1466         }
1467         tmp = le32_to_cpu(adev->wb.wb[index]);
1468         if (tmp == 0xDEADBEEF)
1469                 r = 0;
1470         else
1471                 r = -EINVAL;
1472
1473 err1:
1474         amdgpu_ib_free(adev, &ib, NULL);
1475         dma_fence_put(f);
1476 err0:
1477         amdgpu_device_wb_free(adev, index);
1478         return r;
1479 }
1480
1481
1482 /**
1483  * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1484  *
1485  * @ib: indirect buffer to fill with commands
1486  * @pe: addr of the page entry
1487  * @src: src addr to copy from
1488  * @count: number of page entries to update
1489  *
1490  * Update PTEs by copying them from the GART using sDMA (VEGA10).
1491  */
1492 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1493                                   uint64_t pe, uint64_t src,
1494                                   unsigned count)
1495 {
1496         unsigned bytes = count * 8;
1497
1498         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1499                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1500         ib->ptr[ib->length_dw++] = bytes - 1;
1501         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1502         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1503         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1504         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1505         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1506
1507 }
1508
1509 /**
1510  * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1511  *
1512  * @ib: indirect buffer to fill with commands
1513  * @pe: addr of the page entry
1514  * @addr: dst addr to write into pe
1515  * @count: number of page entries to update
1516  * @incr: increase next addr by incr bytes
1517  * @flags: access flags
1518  *
1519  * Update PTEs by writing them manually using sDMA (VEGA10).
1520  */
1521 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1522                                    uint64_t value, unsigned count,
1523                                    uint32_t incr)
1524 {
1525         unsigned ndw = count * 2;
1526
1527         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1528                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1529         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1530         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1531         ib->ptr[ib->length_dw++] = ndw - 1;
1532         for (; ndw > 0; ndw -= 2) {
1533                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1534                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1535                 value += incr;
1536         }
1537 }
1538
1539 /**
1540  * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1541  *
1542  * @ib: indirect buffer to fill with commands
1543  * @pe: addr of the page entry
1544  * @addr: dst addr to write into pe
1545  * @count: number of page entries to update
1546  * @incr: increase next addr by incr bytes
1547  * @flags: access flags
1548  *
1549  * Update the page tables using sDMA (VEGA10).
1550  */
1551 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1552                                      uint64_t pe,
1553                                      uint64_t addr, unsigned count,
1554                                      uint32_t incr, uint64_t flags)
1555 {
1556         /* for physically contiguous pages (vram) */
1557         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1558         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1559         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1560         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1561         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1562         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1563         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1564         ib->ptr[ib->length_dw++] = incr; /* increment size */
1565         ib->ptr[ib->length_dw++] = 0;
1566         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1567 }
1568
1569 /**
1570  * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1571  *
1572  * @ib: indirect buffer to fill with padding
1573  *
1574  */
1575 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1576 {
1577         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1578         u32 pad_count;
1579         int i;
1580
1581         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1582         for (i = 0; i < pad_count; i++)
1583                 if (sdma && sdma->burst_nop && (i == 0))
1584                         ib->ptr[ib->length_dw++] =
1585                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1586                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1587                 else
1588                         ib->ptr[ib->length_dw++] =
1589                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1590 }
1591
1592
1593 /**
1594  * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1595  *
1596  * @ring: amdgpu_ring pointer
1597  *
1598  * Make sure all previous operations are completed (CIK).
1599  */
1600 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1601 {
1602         uint32_t seq = ring->fence_drv.sync_seq;
1603         uint64_t addr = ring->fence_drv.gpu_addr;
1604
1605         /* wait for idle */
1606         sdma_v4_0_wait_reg_mem(ring, 1, 0,
1607                                addr & 0xfffffffc,
1608                                upper_32_bits(addr) & 0xffffffff,
1609                                seq, 0xffffffff, 4);
1610 }
1611
1612
1613 /**
1614  * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1615  *
1616  * @ring: amdgpu_ring pointer
1617  * @vm: amdgpu_vm pointer
1618  *
1619  * Update the page table base and flush the VM TLB
1620  * using sDMA (VEGA10).
1621  */
1622 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1623                                          unsigned vmid, uint64_t pd_addr)
1624 {
1625         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1626 }
1627
1628 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1629                                      uint32_t reg, uint32_t val)
1630 {
1631         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1632                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1633         amdgpu_ring_write(ring, reg);
1634         amdgpu_ring_write(ring, val);
1635 }
1636
1637 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1638                                          uint32_t val, uint32_t mask)
1639 {
1640         sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1641 }
1642
1643 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
1644 {
1645         uint fw_version = adev->sdma.instance[0].fw_version;
1646
1647         switch (adev->asic_type) {
1648         case CHIP_VEGA10:
1649                 return fw_version >= 430;
1650         case CHIP_VEGA12:
1651                 /*return fw_version >= 31;*/
1652                 return false;
1653         case CHIP_VEGA20:
1654                 return fw_version >= 123;
1655         default:
1656                 return false;
1657         }
1658 }
1659
1660 static int sdma_v4_0_early_init(void *handle)
1661 {
1662         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1663         int r;
1664
1665         if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR)
1666                 adev->sdma.num_instances = 1;
1667         else if (adev->asic_type == CHIP_ARCTURUS)
1668                 adev->sdma.num_instances = 8;
1669         else
1670                 adev->sdma.num_instances = 2;
1671
1672         r = sdma_v4_0_init_microcode(adev);
1673         if (r) {
1674                 DRM_ERROR("Failed to load sdma firmware!\n");
1675                 return r;
1676         }
1677
1678         /* TODO: Page queue breaks driver reload under SRIOV */
1679         if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev)))
1680                 adev->sdma.has_page_queue = false;
1681         else if (sdma_v4_0_fw_support_paging_queue(adev))
1682                 adev->sdma.has_page_queue = true;
1683
1684         sdma_v4_0_set_ring_funcs(adev);
1685         sdma_v4_0_set_buffer_funcs(adev);
1686         sdma_v4_0_set_vm_pte_funcs(adev);
1687         sdma_v4_0_set_irq_funcs(adev);
1688
1689         return 0;
1690 }
1691
1692 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
1693                 struct ras_err_data *err_data,
1694                 struct amdgpu_iv_entry *entry);
1695
1696 static int sdma_v4_0_late_init(void *handle)
1697 {
1698         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1699         struct ras_common_if **ras_if = &adev->sdma.ras_if;
1700         struct ras_ih_if ih_info = {
1701                 .cb = sdma_v4_0_process_ras_data_cb,
1702         };
1703         struct ras_fs_if fs_info = {
1704                 .sysfs_name = "sdma_err_count",
1705                 .debugfs_name = "sdma_err_inject",
1706         };
1707         struct ras_common_if ras_block = {
1708                 .block = AMDGPU_RAS_BLOCK__SDMA,
1709                 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
1710                 .sub_block_index = 0,
1711                 .name = "sdma",
1712         };
1713         int r, i;
1714
1715         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
1716                 amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0);
1717                 return 0;
1718         }
1719
1720         /* handle resume path. */
1721         if (*ras_if) {
1722                 /* resend ras TA enable cmd during resume.
1723                  * prepare to handle failure.
1724                  */
1725                 ih_info.head = **ras_if;
1726                 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
1727                 if (r) {
1728                         if (r == -EAGAIN) {
1729                                 /* request a gpu reset. will run again. */
1730                                 amdgpu_ras_request_reset_on_boot(adev,
1731                                                 AMDGPU_RAS_BLOCK__SDMA);
1732                                 return 0;
1733                         }
1734                         /* fail to enable ras, cleanup all. */
1735                         goto irq;
1736                 }
1737                 /* enable successfully. continue. */
1738                 goto resume;
1739         }
1740
1741         *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
1742         if (!*ras_if)
1743                 return -ENOMEM;
1744
1745         **ras_if = ras_block;
1746
1747         r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
1748         if (r) {
1749                 if (r == -EAGAIN) {
1750                         amdgpu_ras_request_reset_on_boot(adev,
1751                                         AMDGPU_RAS_BLOCK__SDMA);
1752                         r = 0;
1753                 }
1754                 goto feature;
1755         }
1756
1757         ih_info.head = **ras_if;
1758         fs_info.head = **ras_if;
1759
1760         r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
1761         if (r)
1762                 goto interrupt;
1763
1764         amdgpu_ras_debugfs_create(adev, &fs_info);
1765
1766         r = amdgpu_ras_sysfs_create(adev, &fs_info);
1767         if (r)
1768                 goto sysfs;
1769 resume:
1770         for (i = 0; i < adev->sdma.num_instances; i++) {
1771                 r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq,
1772                                    AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1773                 if (r)
1774                         goto irq;
1775         }
1776
1777         return 0;
1778 irq:
1779         amdgpu_ras_sysfs_remove(adev, *ras_if);
1780 sysfs:
1781         amdgpu_ras_debugfs_remove(adev, *ras_if);
1782         amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
1783 interrupt:
1784         amdgpu_ras_feature_enable(adev, *ras_if, 0);
1785 feature:
1786         kfree(*ras_if);
1787         *ras_if = NULL;
1788         return r;
1789 }
1790
1791 static int sdma_v4_0_sw_init(void *handle)
1792 {
1793         struct amdgpu_ring *ring;
1794         int r, i;
1795         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1796
1797         /* SDMA trap event */
1798         for (i = 0; i < adev->sdma.num_instances; i++) {
1799                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1800                                       SDMA0_4_0__SRCID__SDMA_TRAP,
1801                                       &adev->sdma.trap_irq);
1802                 if (r)
1803                         return r;
1804         }
1805
1806         /* SDMA SRAM ECC event */
1807         for (i = 0; i < adev->sdma.num_instances; i++) {
1808                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1809                                       SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1810                                       &adev->sdma.ecc_irq);
1811                 if (r)
1812                         return r;
1813         }
1814
1815         for (i = 0; i < adev->sdma.num_instances; i++) {
1816                 ring = &adev->sdma.instance[i].ring;
1817                 ring->ring_obj = NULL;
1818                 ring->use_doorbell = true;
1819
1820                 DRM_INFO("use_doorbell being set to: [%s]\n",
1821                                 ring->use_doorbell?"true":"false");
1822
1823                 /* doorbell size is 2 dwords, get DWORD offset */
1824                 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1825
1826                 sprintf(ring->name, "sdma%d", i);
1827                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1828                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1829                 if (r)
1830                         return r;
1831
1832                 if (adev->sdma.has_page_queue) {
1833                         ring = &adev->sdma.instance[i].page;
1834                         ring->ring_obj = NULL;
1835                         ring->use_doorbell = true;
1836
1837                         /* paging queue use same doorbell index/routing as gfx queue
1838                          * with 0x400 (4096 dwords) offset on second doorbell page
1839                          */
1840                         ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1841                         ring->doorbell_index += 0x400;
1842
1843                         sprintf(ring->name, "page%d", i);
1844                         r = amdgpu_ring_init(adev, ring, 1024,
1845                                              &adev->sdma.trap_irq,
1846                                              AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1847                         if (r)
1848                                 return r;
1849                 }
1850         }
1851
1852         return r;
1853 }
1854
1855 static int sdma_v4_0_sw_fini(void *handle)
1856 {
1857         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1858         int i;
1859
1860         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA) &&
1861                         adev->sdma.ras_if) {
1862                 struct ras_common_if *ras_if = adev->sdma.ras_if;
1863                 struct ras_ih_if ih_info = {
1864                         .head = *ras_if,
1865                 };
1866
1867                 /*remove fs first*/
1868                 amdgpu_ras_debugfs_remove(adev, ras_if);
1869                 amdgpu_ras_sysfs_remove(adev, ras_if);
1870                 /*remove the IH*/
1871                 amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
1872                 amdgpu_ras_feature_enable(adev, ras_if, 0);
1873                 kfree(ras_if);
1874         }
1875
1876         for (i = 0; i < adev->sdma.num_instances; i++) {
1877                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1878                 if (adev->sdma.has_page_queue)
1879                         amdgpu_ring_fini(&adev->sdma.instance[i].page);
1880         }
1881
1882         sdma_v4_0_destroy_inst_ctx(adev);
1883
1884         return 0;
1885 }
1886
1887 static int sdma_v4_0_hw_init(void *handle)
1888 {
1889         int r;
1890         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1891
1892         if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs &&
1893                         adev->powerplay.pp_funcs->set_powergating_by_smu)
1894                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
1895
1896         if (!amdgpu_sriov_vf(adev))
1897                 sdma_v4_0_init_golden_registers(adev);
1898
1899         r = sdma_v4_0_start(adev);
1900
1901         return r;
1902 }
1903
1904 static int sdma_v4_0_hw_fini(void *handle)
1905 {
1906         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1907         int i;
1908
1909         if (amdgpu_sriov_vf(adev))
1910                 return 0;
1911
1912         for (i = 0; i < adev->sdma.num_instances; i++) {
1913                 amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1914                                AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1915         }
1916
1917         sdma_v4_0_ctx_switch_enable(adev, false);
1918         sdma_v4_0_enable(adev, false);
1919
1920         if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs
1921                         && adev->powerplay.pp_funcs->set_powergating_by_smu)
1922                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
1923
1924         return 0;
1925 }
1926
1927 static int sdma_v4_0_suspend(void *handle)
1928 {
1929         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1930
1931         return sdma_v4_0_hw_fini(adev);
1932 }
1933
1934 static int sdma_v4_0_resume(void *handle)
1935 {
1936         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1937
1938         return sdma_v4_0_hw_init(adev);
1939 }
1940
1941 static bool sdma_v4_0_is_idle(void *handle)
1942 {
1943         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1944         u32 i;
1945
1946         for (i = 0; i < adev->sdma.num_instances; i++) {
1947                 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
1948
1949                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1950                         return false;
1951         }
1952
1953         return true;
1954 }
1955
1956 static int sdma_v4_0_wait_for_idle(void *handle)
1957 {
1958         unsigned i, j;
1959         u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
1960         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1961
1962         for (i = 0; i < adev->usec_timeout; i++) {
1963                 for (j = 0; j < adev->sdma.num_instances; j++) {
1964                         sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG);
1965                         if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK))
1966                                 break;
1967                 }
1968                 if (j == adev->sdma.num_instances)
1969                         return 0;
1970                 udelay(1);
1971         }
1972         return -ETIMEDOUT;
1973 }
1974
1975 static int sdma_v4_0_soft_reset(void *handle)
1976 {
1977         /* todo */
1978
1979         return 0;
1980 }
1981
1982 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
1983                                         struct amdgpu_irq_src *source,
1984                                         unsigned type,
1985                                         enum amdgpu_interrupt_state state)
1986 {
1987         u32 sdma_cntl;
1988
1989         sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL);
1990         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1991                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1992         WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl);
1993
1994         return 0;
1995 }
1996
1997 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
1998                                       struct amdgpu_irq_src *source,
1999                                       struct amdgpu_iv_entry *entry)
2000 {
2001         uint32_t instance;
2002
2003         DRM_DEBUG("IH: SDMA trap\n");
2004         instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2005         switch (entry->ring_id) {
2006         case 0:
2007                 amdgpu_fence_process(&adev->sdma.instance[instance].ring);
2008                 break;
2009         case 1:
2010                 if (adev->asic_type == CHIP_VEGA20)
2011                         amdgpu_fence_process(&adev->sdma.instance[instance].page);
2012                 break;
2013         case 2:
2014                 /* XXX compute */
2015                 break;
2016         case 3:
2017                 if (adev->asic_type != CHIP_VEGA20)
2018                         amdgpu_fence_process(&adev->sdma.instance[instance].page);
2019                 break;
2020         }
2021         return 0;
2022 }
2023
2024 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
2025                 struct ras_err_data *err_data,
2026                 struct amdgpu_iv_entry *entry)
2027 {
2028         uint32_t err_source;
2029         int instance;
2030
2031         instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2032         if (instance < 0)
2033                 return 0;
2034
2035         switch (entry->src_id) {
2036         case SDMA0_4_0__SRCID__SDMA_SRAM_ECC:
2037                 err_source = 0;
2038                 break;
2039         case SDMA0_4_0__SRCID__SDMA_ECC:
2040                 err_source = 1;
2041                 break;
2042         default:
2043                 return 0;
2044         }
2045
2046         kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
2047
2048         amdgpu_ras_reset_gpu(adev, 0);
2049
2050         return AMDGPU_RAS_SUCCESS;
2051 }
2052
2053 static int sdma_v4_0_process_ecc_irq(struct amdgpu_device *adev,
2054                                       struct amdgpu_irq_src *source,
2055                                       struct amdgpu_iv_entry *entry)
2056 {
2057         struct ras_common_if *ras_if = adev->sdma.ras_if;
2058         struct ras_dispatch_if ih_data = {
2059                 .entry = entry,
2060         };
2061
2062         if (!ras_if)
2063                 return 0;
2064
2065         ih_data.head = *ras_if;
2066
2067         amdgpu_ras_interrupt_dispatch(adev, &ih_data);
2068         return 0;
2069 }
2070
2071 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
2072                                               struct amdgpu_irq_src *source,
2073                                               struct amdgpu_iv_entry *entry)
2074 {
2075         int instance;
2076
2077         DRM_ERROR("Illegal instruction in SDMA command stream\n");
2078
2079         instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2080         if (instance < 0)
2081                 return 0;
2082
2083         switch (entry->ring_id) {
2084         case 0:
2085                 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
2086                 break;
2087         }
2088         return 0;
2089 }
2090
2091 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev,
2092                                         struct amdgpu_irq_src *source,
2093                                         unsigned type,
2094                                         enum amdgpu_interrupt_state state)
2095 {
2096         u32 sdma_edc_config;
2097
2098         sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG);
2099         sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,
2100                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2101         WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config);
2102
2103         return 0;
2104 }
2105
2106 static void sdma_v4_0_update_medium_grain_clock_gating(
2107                 struct amdgpu_device *adev,
2108                 bool enable)
2109 {
2110         uint32_t data, def;
2111         int i;
2112
2113         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
2114                 for (i = 0; i < adev->sdma.num_instances; i++) {
2115                         def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2116                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2117                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2118                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2119                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2120                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2121                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2122                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2123                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2124                         if (def != data)
2125                                 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2126                 }
2127         } else {
2128                 for (i = 0; i < adev->sdma.num_instances; i++) {
2129                         def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2130                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2131                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2132                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2133                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2134                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2135                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2136                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2137                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2138                         if (def != data)
2139                                 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2140                 }
2141         }
2142 }
2143
2144
2145 static void sdma_v4_0_update_medium_grain_light_sleep(
2146                 struct amdgpu_device *adev,
2147                 bool enable)
2148 {
2149         uint32_t data, def;
2150         int i;
2151
2152         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
2153                 for (i = 0; i < adev->sdma.num_instances; i++) {
2154                         /* 1-not override: enable sdma mem light sleep */
2155                         def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2156                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2157                         if (def != data)
2158                                 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2159                 }
2160         } else {
2161                 for (i = 0; i < adev->sdma.num_instances; i++) {
2162                 /* 0-override:disable sdma mem light sleep */
2163                         def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2164                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2165                         if (def != data)
2166                                 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2167                 }
2168         }
2169 }
2170
2171 static int sdma_v4_0_set_clockgating_state(void *handle,
2172                                           enum amd_clockgating_state state)
2173 {
2174         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2175
2176         if (amdgpu_sriov_vf(adev))
2177                 return 0;
2178
2179         switch (adev->asic_type) {
2180         case CHIP_VEGA10:
2181         case CHIP_VEGA12:
2182         case CHIP_VEGA20:
2183         case CHIP_RAVEN:
2184         case CHIP_ARCTURUS:
2185         case CHIP_RENOIR:
2186                 sdma_v4_0_update_medium_grain_clock_gating(adev,
2187                                 state == AMD_CG_STATE_GATE ? true : false);
2188                 sdma_v4_0_update_medium_grain_light_sleep(adev,
2189                                 state == AMD_CG_STATE_GATE ? true : false);
2190                 break;
2191         default:
2192                 break;
2193         }
2194         return 0;
2195 }
2196
2197 static int sdma_v4_0_set_powergating_state(void *handle,
2198                                           enum amd_powergating_state state)
2199 {
2200         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2201
2202         switch (adev->asic_type) {
2203         case CHIP_RAVEN:
2204                 sdma_v4_1_update_power_gating(adev,
2205                                 state == AMD_PG_STATE_GATE ? true : false);
2206                 break;
2207         default:
2208                 break;
2209         }
2210
2211         return 0;
2212 }
2213
2214 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
2215 {
2216         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2217         int data;
2218
2219         if (amdgpu_sriov_vf(adev))
2220                 *flags = 0;
2221
2222         /* AMD_CG_SUPPORT_SDMA_MGCG */
2223         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
2224         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
2225                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
2226
2227         /* AMD_CG_SUPPORT_SDMA_LS */
2228         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
2229         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
2230                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
2231 }
2232
2233 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
2234         .name = "sdma_v4_0",
2235         .early_init = sdma_v4_0_early_init,
2236         .late_init = sdma_v4_0_late_init,
2237         .sw_init = sdma_v4_0_sw_init,
2238         .sw_fini = sdma_v4_0_sw_fini,
2239         .hw_init = sdma_v4_0_hw_init,
2240         .hw_fini = sdma_v4_0_hw_fini,
2241         .suspend = sdma_v4_0_suspend,
2242         .resume = sdma_v4_0_resume,
2243         .is_idle = sdma_v4_0_is_idle,
2244         .wait_for_idle = sdma_v4_0_wait_for_idle,
2245         .soft_reset = sdma_v4_0_soft_reset,
2246         .set_clockgating_state = sdma_v4_0_set_clockgating_state,
2247         .set_powergating_state = sdma_v4_0_set_powergating_state,
2248         .get_clockgating_state = sdma_v4_0_get_clockgating_state,
2249 };
2250
2251 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
2252         .type = AMDGPU_RING_TYPE_SDMA,
2253         .align_mask = 0xf,
2254         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2255         .support_64bit_ptrs = true,
2256         .vmhub = AMDGPU_MMHUB_0,
2257         .get_rptr = sdma_v4_0_ring_get_rptr,
2258         .get_wptr = sdma_v4_0_ring_get_wptr,
2259         .set_wptr = sdma_v4_0_ring_set_wptr,
2260         .emit_frame_size =
2261                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2262                 3 + /* hdp invalidate */
2263                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2264                 /* sdma_v4_0_ring_emit_vm_flush */
2265                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2266                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2267                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2268         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2269         .emit_ib = sdma_v4_0_ring_emit_ib,
2270         .emit_fence = sdma_v4_0_ring_emit_fence,
2271         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2272         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2273         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2274         .test_ring = sdma_v4_0_ring_test_ring,
2275         .test_ib = sdma_v4_0_ring_test_ib,
2276         .insert_nop = sdma_v4_0_ring_insert_nop,
2277         .pad_ib = sdma_v4_0_ring_pad_ib,
2278         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2279         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2280         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2281 };
2282
2283 /*
2284  * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1).
2285  * So create a individual constant ring_funcs for those instances.
2286  */
2287 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = {
2288         .type = AMDGPU_RING_TYPE_SDMA,
2289         .align_mask = 0xf,
2290         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2291         .support_64bit_ptrs = true,
2292         .vmhub = AMDGPU_MMHUB_1,
2293         .get_rptr = sdma_v4_0_ring_get_rptr,
2294         .get_wptr = sdma_v4_0_ring_get_wptr,
2295         .set_wptr = sdma_v4_0_ring_set_wptr,
2296         .emit_frame_size =
2297                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2298                 3 + /* hdp invalidate */
2299                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2300                 /* sdma_v4_0_ring_emit_vm_flush */
2301                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2302                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2303                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2304         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2305         .emit_ib = sdma_v4_0_ring_emit_ib,
2306         .emit_fence = sdma_v4_0_ring_emit_fence,
2307         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2308         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2309         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2310         .test_ring = sdma_v4_0_ring_test_ring,
2311         .test_ib = sdma_v4_0_ring_test_ib,
2312         .insert_nop = sdma_v4_0_ring_insert_nop,
2313         .pad_ib = sdma_v4_0_ring_pad_ib,
2314         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2315         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2316         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2317 };
2318
2319 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
2320         .type = AMDGPU_RING_TYPE_SDMA,
2321         .align_mask = 0xf,
2322         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2323         .support_64bit_ptrs = true,
2324         .vmhub = AMDGPU_MMHUB_0,
2325         .get_rptr = sdma_v4_0_ring_get_rptr,
2326         .get_wptr = sdma_v4_0_page_ring_get_wptr,
2327         .set_wptr = sdma_v4_0_page_ring_set_wptr,
2328         .emit_frame_size =
2329                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2330                 3 + /* hdp invalidate */
2331                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2332                 /* sdma_v4_0_ring_emit_vm_flush */
2333                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2334                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2335                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2336         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2337         .emit_ib = sdma_v4_0_ring_emit_ib,
2338         .emit_fence = sdma_v4_0_ring_emit_fence,
2339         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2340         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2341         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2342         .test_ring = sdma_v4_0_ring_test_ring,
2343         .test_ib = sdma_v4_0_ring_test_ib,
2344         .insert_nop = sdma_v4_0_ring_insert_nop,
2345         .pad_ib = sdma_v4_0_ring_pad_ib,
2346         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2347         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2348         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2349 };
2350
2351 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = {
2352         .type = AMDGPU_RING_TYPE_SDMA,
2353         .align_mask = 0xf,
2354         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2355         .support_64bit_ptrs = true,
2356         .vmhub = AMDGPU_MMHUB_1,
2357         .get_rptr = sdma_v4_0_ring_get_rptr,
2358         .get_wptr = sdma_v4_0_page_ring_get_wptr,
2359         .set_wptr = sdma_v4_0_page_ring_set_wptr,
2360         .emit_frame_size =
2361                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2362                 3 + /* hdp invalidate */
2363                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2364                 /* sdma_v4_0_ring_emit_vm_flush */
2365                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2366                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2367                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2368         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2369         .emit_ib = sdma_v4_0_ring_emit_ib,
2370         .emit_fence = sdma_v4_0_ring_emit_fence,
2371         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2372         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2373         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2374         .test_ring = sdma_v4_0_ring_test_ring,
2375         .test_ib = sdma_v4_0_ring_test_ib,
2376         .insert_nop = sdma_v4_0_ring_insert_nop,
2377         .pad_ib = sdma_v4_0_ring_pad_ib,
2378         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2379         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2380         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2381 };
2382
2383 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
2384 {
2385         int i;
2386
2387         for (i = 0; i < adev->sdma.num_instances; i++) {
2388                 if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
2389                         adev->sdma.instance[i].ring.funcs =
2390                                         &sdma_v4_0_ring_funcs_2nd_mmhub;
2391                 else
2392                         adev->sdma.instance[i].ring.funcs =
2393                                         &sdma_v4_0_ring_funcs;
2394                 adev->sdma.instance[i].ring.me = i;
2395                 if (adev->sdma.has_page_queue) {
2396                         if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
2397                                 adev->sdma.instance[i].page.funcs =
2398                                         &sdma_v4_0_page_ring_funcs_2nd_mmhub;
2399                         else
2400                                 adev->sdma.instance[i].page.funcs =
2401                                         &sdma_v4_0_page_ring_funcs;
2402                         adev->sdma.instance[i].page.me = i;
2403                 }
2404         }
2405 }
2406
2407 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
2408         .set = sdma_v4_0_set_trap_irq_state,
2409         .process = sdma_v4_0_process_trap_irq,
2410 };
2411
2412 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
2413         .process = sdma_v4_0_process_illegal_inst_irq,
2414 };
2415
2416 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = {
2417         .set = sdma_v4_0_set_ecc_irq_state,
2418         .process = sdma_v4_0_process_ecc_irq,
2419 };
2420
2421
2422
2423 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2424 {
2425         switch (adev->sdma.num_instances) {
2426         case 1:
2427                 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
2428                 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
2429                 break;
2430         case 8:
2431                 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2432                 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2433                 break;
2434         case 2:
2435         default:
2436                 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
2437                 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
2438                 break;
2439         }
2440         adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
2441         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
2442         adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;
2443 }
2444
2445 /**
2446  * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
2447  *
2448  * @ring: amdgpu_ring structure holding ring information
2449  * @src_offset: src GPU address
2450  * @dst_offset: dst GPU address
2451  * @byte_count: number of bytes to xfer
2452  *
2453  * Copy GPU buffers using the DMA engine (VEGA10/12).
2454  * Used by the amdgpu ttm implementation to move pages if
2455  * registered as the asic copy callback.
2456  */
2457 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
2458                                        uint64_t src_offset,
2459                                        uint64_t dst_offset,
2460                                        uint32_t byte_count)
2461 {
2462         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2463                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
2464         ib->ptr[ib->length_dw++] = byte_count - 1;
2465         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2466         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2467         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2468         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2469         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2470 }
2471
2472 /**
2473  * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
2474  *
2475  * @ring: amdgpu_ring structure holding ring information
2476  * @src_data: value to write to buffer
2477  * @dst_offset: dst GPU address
2478  * @byte_count: number of bytes to xfer
2479  *
2480  * Fill GPU buffers using the DMA engine (VEGA10/12).
2481  */
2482 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
2483                                        uint32_t src_data,
2484                                        uint64_t dst_offset,
2485                                        uint32_t byte_count)
2486 {
2487         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2488         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2489         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2490         ib->ptr[ib->length_dw++] = src_data;
2491         ib->ptr[ib->length_dw++] = byte_count - 1;
2492 }
2493
2494 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
2495         .copy_max_bytes = 0x400000,
2496         .copy_num_dw = 7,
2497         .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
2498
2499         .fill_max_bytes = 0x400000,
2500         .fill_num_dw = 5,
2501         .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
2502 };
2503
2504 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
2505 {
2506         adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
2507         if (adev->sdma.has_page_queue)
2508                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2509         else
2510                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2511 }
2512
2513 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
2514         .copy_pte_num_dw = 7,
2515         .copy_pte = sdma_v4_0_vm_copy_pte,
2516
2517         .write_pte = sdma_v4_0_vm_write_pte,
2518         .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
2519 };
2520
2521 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
2522 {
2523         struct drm_gpu_scheduler *sched;
2524         unsigned i;
2525
2526         adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
2527         for (i = 0; i < adev->sdma.num_instances; i++) {
2528                 if (adev->sdma.has_page_queue)
2529                         sched = &adev->sdma.instance[i].page.sched;
2530                 else
2531                         sched = &adev->sdma.instance[i].ring.sched;
2532                 adev->vm_manager.vm_pte_rqs[i] =
2533                         &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
2534         }
2535         adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
2536 }
2537
2538 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
2539         .type = AMD_IP_BLOCK_TYPE_SDMA,
2540         .major = 4,
2541         .minor = 0,
2542         .rev = 0,
2543         .funcs = &sdma_v4_0_ip_funcs,
2544 };