drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_psp.h"
  28 #include "amdgpu_ucode.h"
  29 #include "soc15_common.h"
  30 #include "psp_v11_0.h"
  31
  32 #include "mp/mp_11_0_offset.h"
  33 #include "mp/mp_11_0_sh_mask.h"
  34 #include "gc/gc_9_0_offset.h"
  35 #include "sdma0/sdma0_4_0_offset.h"
  36 #include "nbio/nbio_7_4_offset.h"
  37
  38 #include "oss/osssys_4_0_offset.h"
  39 #include "oss/osssys_4_0_sh_mask.h"
  40
  41 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
  42 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
  43 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
  44 MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
  45 MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
  46 MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
  47 MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
  48 MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
  49 MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
  50 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
  51 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
  52
  53 /* address block */
  54 #define smnMP1_FIRMWARE_FLAGS           0x3010024
  55 /* navi10 reg offset define */
  56 #define mmRLC_GPM_UCODE_ADDR_NV10       0x5b61
  57 #define mmRLC_GPM_UCODE_DATA_NV10       0x5b62
  58 #define mmSDMA0_UCODE_ADDR_NV10         0x5880
  59 #define mmSDMA0_UCODE_DATA_NV10         0x5881
  60
  61 static int psp_v11_0_init_microcode(struct psp_context *psp)
  62 {
  63         struct amdgpu_device *adev = psp->adev;
  64         const char *chip_name;
  65         char fw_name[30];
  66         int err = 0;
  67         const struct psp_firmware_header_v1_0 *sos_hdr;
  68         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
  69         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
  70         const struct psp_firmware_header_v1_0 *asd_hdr;
  71         const struct ta_firmware_header_v1_0 *ta_hdr;
  72
  73         DRM_DEBUG("\n");
  74
  75         switch (adev->asic_type) {
  76         case CHIP_VEGA20:
  77                 chip_name = "vega20";
  78                 break;
  79         case CHIP_NAVI10:
  80                 chip_name = "navi10";
  81                 break;
  82         case CHIP_NAVI14:
  83                 chip_name = "navi14";
  84                 break;
  85         case CHIP_NAVI12:
  86                 chip_name = "navi12";
  87                 break;
  88         case CHIP_ARCTURUS:
  89                 chip_name = "arcturus";
  90                 break;
  91         default:
  92                 BUG();
  93         }
  94
  95         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
  96         err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
  97         if (err)
  98                 goto out;
  99
 100         err = amdgpu_ucode_validate(adev->psp.sos_fw);
 101         if (err)
 102                 goto out;
 103
 104         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
 105         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
 106
 107         switch (sos_hdr->header.header_version_major) {
 108         case 1:
 109                 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
 110                 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
 111                 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
 112                 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes);
 113                 adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
 114                                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
 115                 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 116                                 le32_to_cpu(sos_hdr->sos_offset_bytes);
 117                 if (sos_hdr->header.header_version_minor == 1) {
 118                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
 119                         adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
 120                         adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 121                                         le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
 122                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
 123                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 124                                         le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
 125                 }
 126                 if (sos_hdr->header.header_version_minor == 2) {
 127                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
 128                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);
 129                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 130                                                     le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);
 131                 }
 132                 break;
 133         default:
 134                 dev_err(adev->dev,
 135                         "Unsupported psp sos firmware\n");
 136                 err = -EINVAL;
 137                 goto out;
 138         }
 139
 140         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
 141         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
 142         if (err)
 143                 goto out1;
 144
 145         err = amdgpu_ucode_validate(adev->psp.asd_fw);
 146         if (err)
 147                 goto out1;
 148
 149         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
 150         adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
 151         adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
 152         adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
 153         adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
 154                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
 155
 156         switch (adev->asic_type) {
 157         case CHIP_VEGA20:
 158                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
 159                 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
 160                 if (err) {
 161                         release_firmware(adev->psp.ta_fw);
 162                         adev->psp.ta_fw = NULL;
 163                         dev_info(adev->dev,
 164                                  "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 165                 } else {
 166                         err = amdgpu_ucode_validate(adev->psp.ta_fw);
 167                         if (err)
 168                                 goto out2;
 169
 170                         ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
 171                         adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
 172                         adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
 173                         adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
 174                                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
 175                         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
 176                         adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version);
 177                         adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes);
 178                         adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr +
 179                                 le32_to_cpu(ta_hdr->ta_ras_offset_bytes);
 180                 }
 181                 break;
 182         case CHIP_NAVI10:
 183         case CHIP_NAVI14:
 184         case CHIP_NAVI12:
 185         case CHIP_ARCTURUS:
 186                 break;
 187         default:
 188                 BUG();
 189         }
 190
 191         return 0;
 192
 193 out2:
 194         release_firmware(adev->psp.ta_fw);
 195         adev->psp.ta_fw = NULL;
 196 out1:
 197         release_firmware(adev->psp.asd_fw);
 198         adev->psp.asd_fw = NULL;
 199 out:
 200         dev_err(adev->dev,
 201                 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 202         release_firmware(adev->psp.sos_fw);
 203         adev->psp.sos_fw = NULL;
 204
 205         return err;
 206 }
 207
 208 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
 209 {
 210         int ret;
 211         uint32_t psp_gfxdrv_command_reg = 0;
 212         struct amdgpu_device *adev = psp->adev;
 213         uint32_t sol_reg;
 214
 215         /* Check tOS sign of life register to confirm sys driver and sOS
 216          * are already been loaded.
 217          */
 218         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 219         if (sol_reg) {
 220                 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
 221                 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
 222                 return 0;
 223         }
 224
 225         /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 226         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 227                            0x80000000, 0x80000000, false);
 228         if (ret)
 229                 return ret;
 230
 231         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 232
 233         /* Copy PSP KDB binary to memory */
 234         memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size);
 235
 236         /* Provide the sys driver to bootloader */
 237         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 238                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 239         psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
 240         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 241                psp_gfxdrv_command_reg);
 242
 243         /* Wait for bootloader to signify that is ready having  bit 31 of C2PMSG_35 set to 1*/
 244         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 245                            0x80000000, 0x80000000, false);
 246
 247         return ret;
 248 }
 249
 250 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
 251 {
 252         int ret;
 253         uint32_t psp_gfxdrv_command_reg = 0;
 254         struct amdgpu_device *adev = psp->adev;
 255         uint32_t sol_reg;
 256
 257         /* Check sOS sign of life register to confirm sys driver and sOS
 258          * are already been loaded.
 259          */
 260         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 261         if (sol_reg) {
 262                 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
 263                 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
 264                 return 0;
 265         }
 266
 267         /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 268         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 269                            0x80000000, 0x80000000, false);
 270         if (ret)
 271                 return ret;
 272
 273         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 274
 275         /* Copy PSP System Driver binary to memory */
 276         memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
 277
 278         /* Provide the sys driver to bootloader */
 279         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 280                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 281         psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
 282         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 283                psp_gfxdrv_command_reg);
 284
 285         /* there might be handshake issue with hardware which needs delay */
 286         mdelay(20);
 287
 288         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 289                            0x80000000, 0x80000000, false);
 290
 291         return ret;
 292 }
 293
 294 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
 295 {
 296         int ret;
 297         unsigned int psp_gfxdrv_command_reg = 0;
 298         struct amdgpu_device *adev = psp->adev;
 299         uint32_t sol_reg;
 300
 301         /* Check sOS sign of life register to confirm sys driver and sOS
 302          * are already been loaded.
 303          */
 304         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 305         if (sol_reg)
 306                 return 0;
 307
 308         /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 309         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 310                            0x80000000, 0x80000000, false);
 311         if (ret)
 312                 return ret;
 313
 314         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 315
 316         /* Copy Secure OS binary to PSP memory */
 317         memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
 318
 319         /* Provide the PSP secure OS to bootloader */
 320         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 321                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 322         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 323         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 324                psp_gfxdrv_command_reg);
 325
 326         /* there might be handshake issue with hardware which needs delay */
 327         mdelay(20);
 328         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
 329                            RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
 330                            0, true);
 331
 332         return ret;
 333 }
 334
 335 static void psp_v11_0_reroute_ih(struct psp_context *psp)
 336 {
 337         struct amdgpu_device *adev = psp->adev;
 338         uint32_t tmp;
 339
 340         /* Change IH ring for VMC */
 341         tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
 342         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
 343         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 344
 345         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
 346         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 347         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 348
 349         mdelay(20);
 350         psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 351                      0x80000000, 0x8000FFFF, false);
 352
 353         /* Change IH ring for UMC */
 354         tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
 355         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 356
 357         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
 358         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 359         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 360
 361         mdelay(20);
 362         psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 363                      0x80000000, 0x8000FFFF, false);
 364 }
 365
 366 static int psp_v11_0_ring_init(struct psp_context *psp,
 367                               enum psp_ring_type ring_type)
 368 {
 369         int ret = 0;
 370         struct psp_ring *ring;
 371         struct amdgpu_device *adev = psp->adev;
 372
 373         psp_v11_0_reroute_ih(psp);
 374
 375         ring = &psp->km_ring;
 376
 377         ring->ring_type = ring_type;
 378
 379         /* allocate 4k Page of Local Frame Buffer memory for ring */
 380         ring->ring_size = 0x1000;
 381         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 382                                       AMDGPU_GEM_DOMAIN_VRAM,
 383                                       &adev->firmware.rbuf,
 384                                       &ring->ring_mem_mc_addr,
 385                                       (void **)&ring->ring_mem);
 386         if (ret) {
 387                 ring->ring_size = 0;
 388                 return ret;
 389         }
 390
 391         return 0;
 392 }
 393
 394 static bool psp_v11_0_support_vmr_ring(struct psp_context *psp)
 395 {
 396         if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
 397                 return true;
 398         return false;
 399 }
 400
 401 static int psp_v11_0_ring_create(struct psp_context *psp,
 402                                 enum psp_ring_type ring_type)
 403 {
 404         int ret = 0;
 405         unsigned int psp_ring_reg = 0;
 406         struct psp_ring *ring = &psp->km_ring;
 407         struct amdgpu_device *adev = psp->adev;
 408
 409         if (psp_v11_0_support_vmr_ring(psp)) {
 410                 /* Write low address of the ring to C2PMSG_102 */
 411                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 412                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
 413                 /* Write high address of the ring to C2PMSG_103 */
 414                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 415                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
 416
 417                 /* Write the ring initialization command to C2PMSG_101 */
 418                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 419                                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 420
 421                 /* there might be handshake issue with hardware which needs delay */
 422                 mdelay(20);
 423
 424                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 425                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 426                                    0x80000000, 0x8000FFFF, false);
 427
 428         } else {
 429                 /* Write low address of the ring to C2PMSG_69 */
 430                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 431                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 432                 /* Write high address of the ring to C2PMSG_70 */
 433                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 434                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 435                 /* Write size of ring to C2PMSG_71 */
 436                 psp_ring_reg = ring->ring_size;
 437                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 438                 /* Write the ring initialization command to C2PMSG_64 */
 439                 psp_ring_reg = ring_type;
 440                 psp_ring_reg = psp_ring_reg << 16;
 441                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 442
 443                 /* there might be handshake issue with hardware which needs delay */
 444                 mdelay(20);
 445
 446                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 447                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 448                                    0x80000000, 0x8000FFFF, false);
 449         }
 450
 451         return ret;
 452 }
 453
 454 static int psp_v11_0_ring_stop(struct psp_context *psp,
 455                               enum psp_ring_type ring_type)
 456 {
 457         int ret = 0;
 458         struct amdgpu_device *adev = psp->adev;
 459
 460         /* Write the ring destroy command*/
 461         if (psp_v11_0_support_vmr_ring(psp))
 462                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 463                                      GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 464         else
 465                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
 466                                      GFX_CTRL_CMD_ID_DESTROY_RINGS);
 467
 468         /* there might be handshake issue with hardware which needs delay */
 469         mdelay(20);
 470
 471         /* Wait for response flag (bit 31) */
 472         if (psp_v11_0_support_vmr_ring(psp))
 473                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 474                                    0x80000000, 0x80000000, false);
 475         else
 476                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 477                                    0x80000000, 0x80000000, false);
 478
 479         return ret;
 480 }
 481
 482 static int psp_v11_0_ring_destroy(struct psp_context *psp,
 483                                  enum psp_ring_type ring_type)
 484 {
 485         int ret = 0;
 486         struct psp_ring *ring = &psp->km_ring;
 487         struct amdgpu_device *adev = psp->adev;
 488
 489         ret = psp_v11_0_ring_stop(psp, ring_type);
 490         if (ret)
 491                 DRM_ERROR("Fail to stop psp ring\n");
 492
 493         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 494                               &ring->ring_mem_mc_addr,
 495                               (void **)&ring->ring_mem);
 496
 497         return ret;
 498 }
 499
 500 static int psp_v11_0_cmd_submit(struct psp_context *psp,
 501                                uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
 502                                int index)
 503 {
 504         unsigned int psp_write_ptr_reg = 0;
 505         struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
 506         struct psp_ring *ring = &psp->km_ring;
 507         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
 508         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
 509                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
 510         struct amdgpu_device *adev = psp->adev;
 511         uint32_t ring_size_dw = ring->ring_size / 4;
 512         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
 513
 514         /* KM (GPCOM) prepare write pointer */
 515         if (psp_v11_0_support_vmr_ring(psp))
 516                 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
 517         else
 518                 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 519
 520         /* Update KM RB frame pointer to new frame */
 521         /* write_frame ptr increments by size of rb_frame in bytes */
 522         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
 523         if ((psp_write_ptr_reg % ring_size_dw) == 0)
 524                 write_frame = ring_buffer_start;
 525         else
 526                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
 527         /* Check invalid write_frame ptr address */
 528         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
 529                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
 530                           ring_buffer_start, ring_buffer_end, write_frame);
 531                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
 532                 return -EINVAL;
 533         }
 534
 535         /* Initialize KM RB frame */
 536         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
 537
 538         /* Update KM RB frame */
 539         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
 540         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
 541         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
 542         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
 543         write_frame->fence_value = index;
 544
 545         /* Update the write Pointer in DWORDs */
 546         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
 547         if (psp_v11_0_support_vmr_ring(psp)) {
 548                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
 549                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
 550         } else
 551                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
 552
 553         return 0;
 554 }
 555
 556 static int
 557 psp_v11_0_sram_map(struct amdgpu_device *adev,
 558                   unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
 559                   unsigned int *sram_data_reg_offset,
 560                   enum AMDGPU_UCODE_ID ucode_id)
 561 {
 562         int ret = 0;
 563
 564         switch (ucode_id) {
 565 /* TODO: needs to confirm */
 566 #if 0
 567         case AMDGPU_UCODE_ID_SMC:
 568                 *sram_offset = 0;
 569                 *sram_addr_reg_offset = 0;
 570                 *sram_data_reg_offset = 0;
 571                 break;
 572 #endif
 573
 574         case AMDGPU_UCODE_ID_CP_CE:
 575                 *sram_offset = 0x0;
 576                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
 577                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
 578                 break;
 579
 580         case AMDGPU_UCODE_ID_CP_PFP:
 581                 *sram_offset = 0x0;
 582                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
 583                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
 584                 break;
 585
 586         case AMDGPU_UCODE_ID_CP_ME:
 587                 *sram_offset = 0x0;
 588                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
 589                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
 590                 break;
 591
 592         case AMDGPU_UCODE_ID_CP_MEC1:
 593                 *sram_offset = 0x10000;
 594                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
 595                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
 596                 break;
 597
 598         case AMDGPU_UCODE_ID_CP_MEC2:
 599                 *sram_offset = 0x10000;
 600                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
 601                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
 602                 break;
 603
 604         case AMDGPU_UCODE_ID_RLC_G:
 605                 *sram_offset = 0x2000;
 606                 if (adev->asic_type < CHIP_NAVI10) {
 607                         *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
 608                         *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
 609                 } else {
 610                         *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10;
 611                         *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10;
 612                 }
 613                 break;
 614
 615         case AMDGPU_UCODE_ID_SDMA0:
 616                 *sram_offset = 0x0;
 617                 if (adev->asic_type < CHIP_NAVI10) {
 618                         *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
 619                         *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
 620                 } else {
 621                         *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10;
 622                         *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10;
 623                 }
 624                 break;
 625
 626 /* TODO: needs to confirm */
 627 #if 0
 628         case AMDGPU_UCODE_ID_SDMA1:
 629                 *sram_offset = ;
 630                 *sram_addr_reg_offset = ;
 631                 break;
 632
 633         case AMDGPU_UCODE_ID_UVD:
 634                 *sram_offset = ;
 635                 *sram_addr_reg_offset = ;
 636                 break;
 637
 638         case AMDGPU_UCODE_ID_VCE:
 639                 *sram_offset = ;
 640                 *sram_addr_reg_offset = ;
 641                 break;
 642 #endif
 643
 644         case AMDGPU_UCODE_ID_MAXIMUM:
 645         default:
 646                 ret = -EINVAL;
 647                 break;
 648         }
 649
 650         return ret;
 651 }
 652
 653 static bool psp_v11_0_compare_sram_data(struct psp_context *psp,
 654                                        struct amdgpu_firmware_info *ucode,
 655                                        enum AMDGPU_UCODE_ID ucode_type)
 656 {
 657         int err = 0;
 658         unsigned int fw_sram_reg_val = 0;
 659         unsigned int fw_sram_addr_reg_offset = 0;
 660         unsigned int fw_sram_data_reg_offset = 0;
 661         unsigned int ucode_size;
 662         uint32_t *ucode_mem = NULL;
 663         struct amdgpu_device *adev = psp->adev;
 664
 665         err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
 666                                 &fw_sram_data_reg_offset, ucode_type);
 667         if (err)
 668                 return false;
 669
 670         WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
 671
 672         ucode_size = ucode->ucode_size;
 673         ucode_mem = (uint32_t *)ucode->kaddr;
 674         while (ucode_size) {
 675                 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
 676
 677                 if (*ucode_mem != fw_sram_reg_val)
 678                         return false;
 679
 680                 ucode_mem++;
 681                 /* 4 bytes */
 682                 ucode_size -= 4;
 683         }
 684
 685         return true;
 686 }
 687
 688 static int psp_v11_0_mode1_reset(struct psp_context *psp)
 689 {
 690         int ret;
 691         uint32_t offset;
 692         struct amdgpu_device *adev = psp->adev;
 693
 694         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
 695
 696         ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
 697
 698         if (ret) {
 699                 DRM_INFO("psp is not working correctly before mode1 reset!\n");
 700                 return -EINVAL;
 701         }
 702
 703         /*send the mode 1 reset command*/
 704         WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
 705
 706         msleep(500);
 707
 708         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
 709
 710         ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
 711
 712         if (ret) {
 713                 DRM_INFO("psp mode 1 reset failed!\n");
 714                 return -EINVAL;
 715         }
 716
 717         DRM_INFO("psp mode1 reset succeed \n");
 718
 719         return 0;
 720 }
 721
 722 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready.
 723  * For now, return success and hack the hive_id so high level code can
 724  * start testing
 725  */
 726 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp,
 727         int number_devices, struct psp_xgmi_topology_info *topology)
 728 {
 729         struct ta_xgmi_shared_memory *xgmi_cmd;
 730         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 731         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
 732         int i;
 733         int ret;
 734
 735         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 736                 return -EINVAL;
 737
 738         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 739         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 740
 741         /* Fill in the shared memory with topology information as input */
 742         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 743         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
 744         topology_info_input->num_nodes = number_devices;
 745
 746         for (i = 0; i < topology_info_input->num_nodes; i++) {
 747                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 748                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 749                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
 750                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 751         }
 752
 753         /* Invoke xgmi ta to get the topology information */
 754         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
 755         if (ret)
 756                 return ret;
 757
 758         /* Read the output topology information from the shared memory */
 759         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
 760         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
 761         for (i = 0; i < topology->num_nodes; i++) {
 762                 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
 763                 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
 764                 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
 765                 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
 766         }
 767
 768         return 0;
 769 }
 770
 771 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp,
 772         int number_devices, struct psp_xgmi_topology_info *topology)
 773 {
 774         struct ta_xgmi_shared_memory *xgmi_cmd;
 775         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 776         int i;
 777
 778         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 779                 return -EINVAL;
 780
 781         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 782         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 783
 784         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 785         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
 786         topology_info_input->num_nodes = number_devices;
 787
 788         for (i = 0; i < topology_info_input->num_nodes; i++) {
 789                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 790                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 791                 topology_info_input->nodes[i].is_sharing_enabled = 1;
 792                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 793         }
 794
 795         /* Invoke xgmi ta to set topology information */
 796         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
 797 }
 798
 799 static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
 800 {
 801         struct ta_xgmi_shared_memory *xgmi_cmd;
 802         int ret;
 803
 804         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 805         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 806
 807         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
 808
 809         /* Invoke xgmi ta to get hive id */
 810         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 811         if (ret)
 812                 return ret;
 813
 814         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
 815
 816         return 0;
 817 }
 818
 819 static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
 820 {
 821         struct ta_xgmi_shared_memory *xgmi_cmd;
 822         int ret;
 823
 824         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 825         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 826
 827         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
 828
 829         /* Invoke xgmi ta to get the node id */
 830         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 831         if (ret)
 832                 return ret;
 833
 834         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
 835
 836         return 0;
 837 }
 838
 839 static int psp_v11_0_ras_trigger_error(struct psp_context *psp,
 840                 struct ta_ras_trigger_error_input *info)
 841 {
 842         struct ta_ras_shared_memory *ras_cmd;
 843         int ret;
 844
 845         if (!psp->ras.ras_initialized)
 846                 return -EINVAL;
 847
 848         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 849         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 850
 851         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
 852         ras_cmd->ras_in_message.trigger_error = *info;
 853
 854         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 855         if (ret)
 856                 return -EINVAL;
 857
 858         return ras_cmd->ras_status;
 859 }
 860
 861 static int psp_v11_0_ras_cure_posion(struct psp_context *psp, uint64_t *mode_ptr)
 862 {
 863 #if 0
 864         // not support yet.
 865         struct ta_ras_shared_memory *ras_cmd;
 866         int ret;
 867
 868         if (!psp->ras.ras_initialized)
 869                 return -EINVAL;
 870
 871         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 872         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 873
 874         ras_cmd->cmd_id = TA_RAS_COMMAND__CURE_POISON;
 875         ras_cmd->ras_in_message.cure_poison.mode_ptr = mode_ptr;
 876
 877         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 878         if (ret)
 879                 return -EINVAL;
 880
 881         return ras_cmd->ras_status;
 882 #else
 883         return -EINVAL;
 884 #endif
 885 }
 886
 887 static int psp_v11_0_rlc_autoload_start(struct psp_context *psp)
 888 {
 889         return psp_rlc_autoload_start(psp);
 890 }
 891
 892 static const struct psp_funcs psp_v11_0_funcs = {
 893         .init_microcode = psp_v11_0_init_microcode,
 894         .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
 895         .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
 896         .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
 897         .ring_init = psp_v11_0_ring_init,
 898         .ring_create = psp_v11_0_ring_create,
 899         .ring_stop = psp_v11_0_ring_stop,
 900         .ring_destroy = psp_v11_0_ring_destroy,
 901         .cmd_submit = psp_v11_0_cmd_submit,
 902         .compare_sram_data = psp_v11_0_compare_sram_data,
 903         .mode1_reset = psp_v11_0_mode1_reset,
 904         .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
 905         .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
 906         .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
 907         .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id,
 908         .support_vmr_ring = psp_v11_0_support_vmr_ring,
 909         .ras_trigger_error = psp_v11_0_ras_trigger_error,
 910         .ras_cure_posion = psp_v11_0_ras_cure_posion,
 911         .rlc_autoload_start = psp_v11_0_rlc_autoload_start,
 912 };
 913
 914 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
 915 {
 916         psp->funcs = &psp_v11_0_funcs;
 917 }