drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_psp.h"
  35 #include "amdgpu_smu.h"
  36 #include "atom.h"
  37 #include "amd_pcie.h"
  38
  39 #include "gc/gc_10_1_0_offset.h"
  40 #include "gc/gc_10_1_0_sh_mask.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "hdp/hdp_5_0_0_sh_mask.h"
  43
  44 #include "soc15.h"
  45 #include "soc15_common.h"
  46 #include "gmc_v10_0.h"
  47 #include "gfxhub_v2_0.h"
  48 #include "mmhub_v2_0.h"
  49 #include "nv.h"
  50 #include "navi10_ih.h"
  51 #include "gfx_v10_0.h"
  52 #include "sdma_v5_0.h"
  53 #include "vcn_v2_0.h"
  54 #include "dce_virtual.h"
  55 #include "mes_v10_1.h"
  56
  57 static const struct amd_ip_funcs nv_common_ip_funcs;
  58
  59 /*
  60  * Indirect registers accessor
  61  */
  62 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  63 {
  64         unsigned long flags, address, data;
  65         u32 r;
  66         address = adev->nbio_funcs->get_pcie_index_offset(adev);
  67         data = adev->nbio_funcs->get_pcie_data_offset(adev);
  68
  69         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  70         WREG32(address, reg);
  71         (void)RREG32(address);
  72         r = RREG32(data);
  73         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  74         return r;
  75 }
  76
  77 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  78 {
  79         unsigned long flags, address, data;
  80
  81         address = adev->nbio_funcs->get_pcie_index_offset(adev);
  82         data = adev->nbio_funcs->get_pcie_data_offset(adev);
  83
  84         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  85         WREG32(address, reg);
  86         (void)RREG32(address);
  87         WREG32(data, v);
  88         (void)RREG32(data);
  89         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  90 }
  91
  92 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
  93 {
  94         unsigned long flags, address, data;
  95         u32 r;
  96
  97         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
  98         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
  99
 100         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 101         WREG32(address, (reg));
 102         r = RREG32(data);
 103         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 104         return r;
 105 }
 106
 107 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 108 {
 109         unsigned long flags, address, data;
 110
 111         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 112         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 113
 114         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 115         WREG32(address, (reg));
 116         WREG32(data, (v));
 117         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 118 }
 119
 120 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 121 {
 122         return adev->nbio_funcs->get_memsize(adev);
 123 }
 124
 125 static u32 nv_get_xclk(struct amdgpu_device *adev)
 126 {
 127         return adev->clock.spll.reference_freq;
 128 }
 129
 130
 131 void nv_grbm_select(struct amdgpu_device *adev,
 132                      u32 me, u32 pipe, u32 queue, u32 vmid)
 133 {
 134         u32 grbm_gfx_cntl = 0;
 135         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 136         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 137         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 138         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 139
 140         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 141 }
 142
 143 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
 144 {
 145         /* todo */
 146 }
 147
 148 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 149 {
 150         /* todo */
 151         return false;
 152 }
 153
 154 static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
 155                                   u8 *bios, u32 length_bytes)
 156 {
 157         /* TODO: will implement it when SMU header is available */
 158         return false;
 159 }
 160
 161 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 162         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 163         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 164         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 165         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 166         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 167         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 168 #if 0   /* TODO: will set it when SDMA header is available */
 169         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 170         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 171 #endif
 172         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 173         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 174         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 175         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 176         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 177         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 178         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 179         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 180         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 181         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 182 };
 183
 184 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 185                                          u32 sh_num, u32 reg_offset)
 186 {
 187         uint32_t val;
 188
 189         mutex_lock(&adev->grbm_idx_mutex);
 190         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 191                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 192
 193         val = RREG32(reg_offset);
 194
 195         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 196                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 197         mutex_unlock(&adev->grbm_idx_mutex);
 198         return val;
 199 }
 200
 201 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 202                                       bool indexed, u32 se_num,
 203                                       u32 sh_num, u32 reg_offset)
 204 {
 205         if (indexed) {
 206                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 207         } else {
 208                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 209                         return adev->gfx.config.gb_addr_config;
 210                 return RREG32(reg_offset);
 211         }
 212 }
 213
 214 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 215                             u32 sh_num, u32 reg_offset, u32 *value)
 216 {
 217         uint32_t i;
 218         struct soc15_allowed_register_entry  *en;
 219
 220         *value = 0;
 221         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 222                 en = &nv_allowed_read_registers[i];
 223                 if (reg_offset !=
 224                     (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 225                         continue;
 226
 227                 *value = nv_get_register_value(adev,
 228                                                nv_allowed_read_registers[i].grbm_indexed,
 229                                                se_num, sh_num, reg_offset);
 230                 return 0;
 231         }
 232         return -EINVAL;
 233 }
 234
 235 #if 0
 236 static void nv_gpu_pci_config_reset(struct amdgpu_device *adev)
 237 {
 238         u32 i;
 239
 240         dev_info(adev->dev, "GPU pci config reset\n");
 241
 242         /* disable BM */
 243         pci_clear_master(adev->pdev);
 244         /* reset */
 245         amdgpu_pci_config_reset(adev);
 246
 247         udelay(100);
 248
 249         /* wait for asic to come out of reset */
 250         for (i = 0; i < adev->usec_timeout; i++) {
 251                 u32 memsize = nbio_v2_3_get_memsize(adev);
 252                 if (memsize != 0xffffffff)
 253                         break;
 254                 udelay(1);
 255         }
 256
 257 }
 258 #endif
 259
 260 static int nv_asic_mode1_reset(struct amdgpu_device *adev)
 261 {
 262         u32 i;
 263         int ret = 0;
 264
 265         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 266
 267         dev_info(adev->dev, "GPU mode1 reset\n");
 268
 269         /* disable BM */
 270         pci_clear_master(adev->pdev);
 271
 272         pci_save_state(adev->pdev);
 273
 274         ret = psp_gpu_reset(adev);
 275         if (ret)
 276                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 277
 278         pci_restore_state(adev->pdev);
 279
 280         /* wait for asic to come out of reset */
 281         for (i = 0; i < adev->usec_timeout; i++) {
 282                 u32 memsize = adev->nbio_funcs->get_memsize(adev);
 283
 284                 if (memsize != 0xffffffff)
 285                         break;
 286                 udelay(1);
 287         }
 288
 289         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 290
 291         return ret;
 292 }
 293
 294 static enum amd_reset_method
 295 nv_asic_reset_method(struct amdgpu_device *adev)
 296 {
 297         struct smu_context *smu = &adev->smu;
 298
 299         if (smu_baco_is_support(smu))
 300                 return AMD_RESET_METHOD_BACO;
 301         else
 302                 return AMD_RESET_METHOD_MODE1;
 303 }
 304
 305 static int nv_asic_reset(struct amdgpu_device *adev)
 306 {
 307
 308         /* FIXME: it doesn't work since vega10 */
 309 #if 0
 310         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 311
 312         nv_gpu_pci_config_reset(adev);
 313
 314         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 315 #endif
 316         int ret = 0;
 317         struct smu_context *smu = &adev->smu;
 318
 319         if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
 320                 amdgpu_inc_vram_lost(adev);
 321                 ret = smu_baco_reset(smu);
 322         } else {
 323                 amdgpu_inc_vram_lost(adev);
 324                 ret = nv_asic_mode1_reset(adev);
 325         }
 326
 327         return ret;
 328 }
 329
 330 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 331 {
 332         /* todo */
 333         return 0;
 334 }
 335
 336 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 337 {
 338         /* todo */
 339         return 0;
 340 }
 341
 342 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 343 {
 344         if (pci_is_root_bus(adev->pdev->bus))
 345                 return;
 346
 347         if (amdgpu_pcie_gen2 == 0)
 348                 return;
 349
 350         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 351                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 352                 return;
 353
 354         /* todo */
 355 }
 356
 357 static void nv_program_aspm(struct amdgpu_device *adev)
 358 {
 359
 360         if (amdgpu_aspm == 0)
 361                 return;
 362
 363         /* todo */
 364 }
 365
 366 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
 367                                         bool enable)
 368 {
 369         adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
 370         adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
 371 }
 372
 373 static const struct amdgpu_ip_block_version nv_common_ip_block =
 374 {
 375         .type = AMD_IP_BLOCK_TYPE_COMMON,
 376         .major = 1,
 377         .minor = 0,
 378         .rev = 0,
 379         .funcs = &nv_common_ip_funcs,
 380 };
 381
 382 static int nv_reg_base_init(struct amdgpu_device *adev)
 383 {
 384         int r;
 385
 386         if (amdgpu_discovery) {
 387                 r = amdgpu_discovery_reg_base_init(adev);
 388                 if (r) {
 389                         DRM_WARN("failed to init reg base from ip discovery table, "
 390                                         "fallback to legacy init method\n");
 391                         goto legacy_init;
 392                 }
 393
 394                 return 0;
 395         }
 396
 397 legacy_init:
 398         switch (adev->asic_type) {
 399         case CHIP_NAVI10:
 400                 navi10_reg_base_init(adev);
 401                 break;
 402         case CHIP_NAVI14:
 403                 navi14_reg_base_init(adev);
 404                 break;
 405         case CHIP_NAVI12:
 406                 navi12_reg_base_init(adev);
 407                 break;
 408         default:
 409                 return -EINVAL;
 410         }
 411
 412         return 0;
 413 }
 414
 415 int nv_set_ip_blocks(struct amdgpu_device *adev)
 416 {
 417         int r;
 418
 419         /* Set IP register base before any HW register access */
 420         r = nv_reg_base_init(adev);
 421         if (r)
 422                 return r;
 423
 424         adev->nbio_funcs = &nbio_v2_3_funcs;
 425
 426         adev->nbio_funcs->detect_hw_virt(adev);
 427
 428         switch (adev->asic_type) {
 429         case CHIP_NAVI10:
 430         case CHIP_NAVI14:
 431                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 432                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 433                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 434                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 435                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 436                     is_support_sw_smu(adev))
 437                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 438                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 439                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 440 #if defined(CONFIG_DRM_AMD_DC)
 441                 else if (amdgpu_device_has_dc_support(adev))
 442                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 443 #endif
 444                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 445                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 446                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 447                     is_support_sw_smu(adev))
 448                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 449                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 450                 if (adev->enable_mes)
 451                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 452                 break;
 453         case CHIP_NAVI12:
 454                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 455                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 456                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 457                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 458                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 459                     is_support_sw_smu(adev))
 460                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 461                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 462                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 463 #if defined(CONFIG_DRM_AMD_DC)
 464                 else if (amdgpu_device_has_dc_support(adev))
 465                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 466 #endif
 467                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 468                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 469                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 470                     is_support_sw_smu(adev))
 471                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 472                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 473                 break;
 474         default:
 475                 return -EINVAL;
 476         }
 477
 478         return 0;
 479 }
 480
 481 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
 482 {
 483         return adev->nbio_funcs->get_rev_id(adev);
 484 }
 485
 486 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 487 {
 488         adev->nbio_funcs->hdp_flush(adev, ring);
 489 }
 490
 491 static void nv_invalidate_hdp(struct amdgpu_device *adev,
 492                                 struct amdgpu_ring *ring)
 493 {
 494         if (!ring || !ring->funcs->emit_wreg) {
 495                 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 496         } else {
 497                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 498                                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 499         }
 500 }
 501
 502 static bool nv_need_full_reset(struct amdgpu_device *adev)
 503 {
 504         return true;
 505 }
 506
 507 static void nv_get_pcie_usage(struct amdgpu_device *adev,
 508                               uint64_t *count0,
 509                               uint64_t *count1)
 510 {
 511         /*TODO*/
 512 }
 513
 514 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 515 {
 516 #if 0
 517         u32 sol_reg;
 518
 519         if (adev->flags & AMD_IS_APU)
 520                 return false;
 521
 522         /* Check sOS sign of life register to confirm sys driver and sOS
 523          * are already been loaded.
 524          */
 525         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 526         if (sol_reg)
 527                 return true;
 528 #endif
 529         /* TODO: re-enable it when mode1 reset is functional */
 530         return false;
 531 }
 532
 533 static void nv_init_doorbell_index(struct amdgpu_device *adev)
 534 {
 535         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 536         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 537         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 538         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 539         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 540         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 541         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 542         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 543         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 544         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 545         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 546         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 547         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 548         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 549         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 550         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 551         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 552         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 553         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 554         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 555         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 556         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 557
 558         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 559         adev->doorbell_index.sdma_doorbell_range = 20;
 560 }
 561
 562 static const struct amdgpu_asic_funcs nv_asic_funcs =
 563 {
 564         .read_disabled_bios = &nv_read_disabled_bios,
 565         .read_bios_from_rom = &nv_read_bios_from_rom,
 566         .read_register = &nv_read_register,
 567         .reset = &nv_asic_reset,
 568         .reset_method = &nv_asic_reset_method,
 569         .set_vga_state = &nv_vga_set_state,
 570         .get_xclk = &nv_get_xclk,
 571         .set_uvd_clocks = &nv_set_uvd_clocks,
 572         .set_vce_clocks = &nv_set_vce_clocks,
 573         .get_config_memsize = &nv_get_config_memsize,
 574         .flush_hdp = &nv_flush_hdp,
 575         .invalidate_hdp = &nv_invalidate_hdp,
 576         .init_doorbell_index = &nv_init_doorbell_index,
 577         .need_full_reset = &nv_need_full_reset,
 578         .get_pcie_usage = &nv_get_pcie_usage,
 579         .need_reset_on_init = &nv_need_reset_on_init,
 580 };
 581
 582 static int nv_common_early_init(void *handle)
 583 {
 584         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 585
 586         adev->smc_rreg = NULL;
 587         adev->smc_wreg = NULL;
 588         adev->pcie_rreg = &nv_pcie_rreg;
 589         adev->pcie_wreg = &nv_pcie_wreg;
 590
 591         /* TODO: will add them during VCN v2 implementation */
 592         adev->uvd_ctx_rreg = NULL;
 593         adev->uvd_ctx_wreg = NULL;
 594
 595         adev->didt_rreg = &nv_didt_rreg;
 596         adev->didt_wreg = &nv_didt_wreg;
 597
 598         adev->asic_funcs = &nv_asic_funcs;
 599
 600         adev->rev_id = nv_get_rev_id(adev);
 601         adev->external_rev_id = 0xff;
 602         switch (adev->asic_type) {
 603         case CHIP_NAVI10:
 604                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 605                         AMD_CG_SUPPORT_GFX_CGCG |
 606                         AMD_CG_SUPPORT_IH_CG |
 607                         AMD_CG_SUPPORT_HDP_MGCG |
 608                         AMD_CG_SUPPORT_HDP_LS |
 609                         AMD_CG_SUPPORT_SDMA_MGCG |
 610                         AMD_CG_SUPPORT_SDMA_LS |
 611                         AMD_CG_SUPPORT_MC_MGCG |
 612                         AMD_CG_SUPPORT_MC_LS |
 613                         AMD_CG_SUPPORT_ATHUB_MGCG |
 614                         AMD_CG_SUPPORT_ATHUB_LS |
 615                         AMD_CG_SUPPORT_VCN_MGCG |
 616                         AMD_CG_SUPPORT_BIF_MGCG |
 617                         AMD_CG_SUPPORT_BIF_LS;
 618                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 619                         AMD_PG_SUPPORT_VCN_DPG |
 620                         AMD_PG_SUPPORT_ATHUB;
 621                 adev->external_rev_id = adev->rev_id + 0x1;
 622                 break;
 623         case CHIP_NAVI14:
 624                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 625                         AMD_CG_SUPPORT_GFX_CGCG |
 626                         AMD_CG_SUPPORT_IH_CG |
 627                         AMD_CG_SUPPORT_HDP_MGCG |
 628                         AMD_CG_SUPPORT_HDP_LS |
 629                         AMD_CG_SUPPORT_SDMA_MGCG |
 630                         AMD_CG_SUPPORT_SDMA_LS |
 631                         AMD_CG_SUPPORT_MC_MGCG |
 632                         AMD_CG_SUPPORT_MC_LS |
 633                         AMD_CG_SUPPORT_ATHUB_MGCG |
 634                         AMD_CG_SUPPORT_ATHUB_LS |
 635                         AMD_CG_SUPPORT_VCN_MGCG |
 636                         AMD_CG_SUPPORT_BIF_MGCG |
 637                         AMD_CG_SUPPORT_BIF_LS;
 638                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 639                         AMD_PG_SUPPORT_VCN_DPG;
 640                 adev->external_rev_id = adev->rev_id + 20;
 641                 break;
 642         case CHIP_NAVI12:
 643                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 644                         AMD_CG_SUPPORT_GFX_MGLS |
 645                         AMD_CG_SUPPORT_GFX_CGCG |
 646                         AMD_CG_SUPPORT_GFX_CP_LS |
 647                         AMD_CG_SUPPORT_GFX_RLC_LS |
 648                         AMD_CG_SUPPORT_IH_CG |
 649                         AMD_CG_SUPPORT_HDP_MGCG |
 650                         AMD_CG_SUPPORT_HDP_LS |
 651                         AMD_CG_SUPPORT_SDMA_MGCG |
 652                         AMD_CG_SUPPORT_SDMA_LS |
 653                         AMD_CG_SUPPORT_MC_MGCG |
 654                         AMD_CG_SUPPORT_MC_LS |
 655                         AMD_CG_SUPPORT_ATHUB_MGCG |
 656                         AMD_CG_SUPPORT_ATHUB_LS |
 657                         AMD_CG_SUPPORT_VCN_MGCG;
 658                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 659                         AMD_PG_SUPPORT_VCN_DPG |
 660                         AMD_PG_SUPPORT_ATHUB;
 661                 adev->external_rev_id = adev->rev_id + 0xa;
 662                 break;
 663         default:
 664                 /* FIXME: not supported yet */
 665                 return -EINVAL;
 666         }
 667
 668         return 0;
 669 }
 670
 671 static int nv_common_late_init(void *handle)
 672 {
 673         return 0;
 674 }
 675
 676 static int nv_common_sw_init(void *handle)
 677 {
 678         return 0;
 679 }
 680
 681 static int nv_common_sw_fini(void *handle)
 682 {
 683         return 0;
 684 }
 685
 686 static int nv_common_hw_init(void *handle)
 687 {
 688         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 689
 690         /* enable pcie gen2/3 link */
 691         nv_pcie_gen3_enable(adev);
 692         /* enable aspm */
 693         nv_program_aspm(adev);
 694         /* setup nbio registers */
 695         adev->nbio_funcs->init_registers(adev);
 696         /* enable the doorbell aperture */
 697         nv_enable_doorbell_aperture(adev, true);
 698
 699         return 0;
 700 }
 701
 702 static int nv_common_hw_fini(void *handle)
 703 {
 704         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 705
 706         /* disable the doorbell aperture */
 707         nv_enable_doorbell_aperture(adev, false);
 708
 709         return 0;
 710 }
 711
 712 static int nv_common_suspend(void *handle)
 713 {
 714         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 715
 716         return nv_common_hw_fini(adev);
 717 }
 718
 719 static int nv_common_resume(void *handle)
 720 {
 721         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 722
 723         return nv_common_hw_init(adev);
 724 }
 725
 726 static bool nv_common_is_idle(void *handle)
 727 {
 728         return true;
 729 }
 730
 731 static int nv_common_wait_for_idle(void *handle)
 732 {
 733         return 0;
 734 }
 735
 736 static int nv_common_soft_reset(void *handle)
 737 {
 738         return 0;
 739 }
 740
 741 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev,
 742                                            bool enable)
 743 {
 744         uint32_t hdp_clk_cntl, hdp_clk_cntl1;
 745         uint32_t hdp_mem_pwr_cntl;
 746
 747         if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
 748                                 AMD_CG_SUPPORT_HDP_DS |
 749                                 AMD_CG_SUPPORT_HDP_SD)))
 750                 return;
 751
 752         hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
 753         hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
 754
 755         /* Before doing clock/power mode switch,
 756          * forced on IPH & RC clock */
 757         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
 758                                      IPH_MEM_CLK_SOFT_OVERRIDE, 1);
 759         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
 760                                      RC_MEM_CLK_SOFT_OVERRIDE, 1);
 761         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
 762
 763         /* HDP 5.0 doesn't support dynamic power mode switch,
 764          * disable clock and power gating before any changing */
 765         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 766                                          IPH_MEM_POWER_CTRL_EN, 0);
 767         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 768                                          IPH_MEM_POWER_LS_EN, 0);
 769         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 770                                          IPH_MEM_POWER_DS_EN, 0);
 771         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 772                                          IPH_MEM_POWER_SD_EN, 0);
 773         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 774                                          RC_MEM_POWER_CTRL_EN, 0);
 775         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 776                                          RC_MEM_POWER_LS_EN, 0);
 777         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 778                                          RC_MEM_POWER_DS_EN, 0);
 779         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 780                                          RC_MEM_POWER_SD_EN, 0);
 781         WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
 782
 783         /* only one clock gating mode (LS/DS/SD) can be enabled */
 784         if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
 785                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 786                                                  HDP_MEM_POWER_CTRL,
 787                                                  IPH_MEM_POWER_LS_EN, enable);
 788                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 789                                                  HDP_MEM_POWER_CTRL,
 790                                                  RC_MEM_POWER_LS_EN, enable);
 791         } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
 792                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 793                                                  HDP_MEM_POWER_CTRL,
 794                                                  IPH_MEM_POWER_DS_EN, enable);
 795                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 796                                                  HDP_MEM_POWER_CTRL,
 797                                                  RC_MEM_POWER_DS_EN, enable);
 798         } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
 799                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 800                                                  HDP_MEM_POWER_CTRL,
 801                                                  IPH_MEM_POWER_SD_EN, enable);
 802                 /* RC should not use shut down mode, fallback to ds */
 803                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 804                                                  HDP_MEM_POWER_CTRL,
 805                                                  RC_MEM_POWER_DS_EN, enable);
 806         }
 807
 808         WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
 809
 810         /* restore IPH & RC clock override after clock/power mode changing */
 811         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1);
 812 }
 813
 814 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev,
 815                                        bool enable)
 816 {
 817         uint32_t hdp_clk_cntl;
 818
 819         if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
 820                 return;
 821
 822         hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
 823
 824         if (enable) {
 825                 hdp_clk_cntl &=
 826                         ~(uint32_t)
 827                           (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
 828                            HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
 829                            HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
 830                            HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
 831                            HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
 832                            HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);
 833         } else {
 834                 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
 835                         HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
 836                         HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
 837                         HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
 838                         HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
 839                         HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;
 840         }
 841
 842         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
 843 }
 844
 845 static int nv_common_set_clockgating_state(void *handle,
 846                                            enum amd_clockgating_state state)
 847 {
 848         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 849
 850         if (amdgpu_sriov_vf(adev))
 851                 return 0;
 852
 853         switch (adev->asic_type) {
 854         case CHIP_NAVI10:
 855         case CHIP_NAVI14:
 856         case CHIP_NAVI12:
 857                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
 858                                 state == AMD_CG_STATE_GATE ? true : false);
 859                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
 860                                 state == AMD_CG_STATE_GATE ? true : false);
 861                 nv_update_hdp_mem_power_gating(adev,
 862                                    state == AMD_CG_STATE_GATE ? true : false);
 863                 nv_update_hdp_clock_gating(adev,
 864                                 state == AMD_CG_STATE_GATE ? true : false);
 865                 break;
 866         default:
 867                 break;
 868         }
 869         return 0;
 870 }
 871
 872 static int nv_common_set_powergating_state(void *handle,
 873                                            enum amd_powergating_state state)
 874 {
 875         /* TODO */
 876         return 0;
 877 }
 878
 879 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
 880 {
 881         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 882         uint32_t tmp;
 883
 884         if (amdgpu_sriov_vf(adev))
 885                 *flags = 0;
 886
 887         adev->nbio_funcs->get_clockgating_state(adev, flags);
 888
 889         /* AMD_CG_SUPPORT_HDP_MGCG */
 890         tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
 891         if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
 892                      HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
 893                      HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
 894                      HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
 895                      HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
 896                      HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))
 897                 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
 898
 899         /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
 900         tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
 901         if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK)
 902                 *flags |= AMD_CG_SUPPORT_HDP_LS;
 903         else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK)
 904                 *flags |= AMD_CG_SUPPORT_HDP_DS;
 905         else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK)
 906                 *flags |= AMD_CG_SUPPORT_HDP_SD;
 907
 908         return;
 909 }
 910
 911 static const struct amd_ip_funcs nv_common_ip_funcs = {
 912         .name = "nv_common",
 913         .early_init = nv_common_early_init,
 914         .late_init = nv_common_late_init,
 915         .sw_init = nv_common_sw_init,
 916         .sw_fini = nv_common_sw_fini,
 917         .hw_init = nv_common_hw_init,
 918         .hw_fini = nv_common_hw_fini,
 919         .suspend = nv_common_suspend,
 920         .resume = nv_common_resume,
 921         .is_idle = nv_common_is_idle,
 922         .wait_for_idle = nv_common_wait_for_idle,
 923         .soft_reset = nv_common_soft_reset,
 924         .set_clockgating_state = nv_common_set_clockgating_state,
 925         .set_powergating_state = nv_common_set_powergating_state,
 926         .get_clockgating_state = nv_common_get_clockgating_state,
 927 };