drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <drm/drm_cache.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_trace.h"
  39 #include "amdgpu_amdkfd.h"
  40
  41 static bool amdgpu_need_backup(struct amdgpu_device *adev)
  42 {
  43         if (adev->flags & AMD_IS_APU)
  44                 return false;
  45
  46         if (amdgpu_gpu_recovery == 0 ||
  47             (amdgpu_gpu_recovery == -1  && !amdgpu_sriov_vf(adev)))
  48                 return false;
  49
  50         return true;
  51 }
  52
  53 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  54 {
  55         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
  56         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
  57
  58         if (bo->kfd_bo)
  59                 amdgpu_amdkfd_unreserve_system_memory_limit(bo);
  60
  61         amdgpu_bo_kunmap(bo);
  62
  63         if (bo->gem_base.import_attach)
  64                 drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg);
  65         drm_gem_object_release(&bo->gem_base);
  66         amdgpu_bo_unref(&bo->parent);
  67         if (!list_empty(&bo->shadow_list)) {
  68                 mutex_lock(&adev->shadow_list_lock);
  69                 list_del_init(&bo->shadow_list);
  70                 mutex_unlock(&adev->shadow_list_lock);
  71         }
  72         kfree(bo->metadata);
  73         kfree(bo);
  74 }
  75
  76 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
  77 {
  78         if (bo->destroy == &amdgpu_ttm_bo_destroy)
  79                 return true;
  80         return false;
  81 }
  82
  83 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
  84 {
  85         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
  86         struct ttm_placement *placement = &abo->placement;
  87         struct ttm_place *places = abo->placements;
  88         u64 flags = abo->flags;
  89         u32 c = 0;
  90
  91         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
  92                 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
  93
  94                 places[c].fpfn = 0;
  95                 places[c].lpfn = 0;
  96                 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  97                         TTM_PL_FLAG_VRAM;
  98
  99                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
 100                         places[c].lpfn = visible_pfn;
 101                 else
 102                         places[c].flags |= TTM_PL_FLAG_TOPDOWN;
 103
 104                 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
 105                         places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
 106                 c++;
 107         }
 108
 109         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 110                 places[c].fpfn = 0;
 111                 if (flags & AMDGPU_GEM_CREATE_SHADOW)
 112                         places[c].lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 113                 else
 114                         places[c].lpfn = 0;
 115                 places[c].flags = TTM_PL_FLAG_TT;
 116                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 117                         places[c].flags |= TTM_PL_FLAG_WC |
 118                                 TTM_PL_FLAG_UNCACHED;
 119                 else
 120                         places[c].flags |= TTM_PL_FLAG_CACHED;
 121                 c++;
 122         }
 123
 124         if (domain & AMDGPU_GEM_DOMAIN_CPU) {
 125                 places[c].fpfn = 0;
 126                 places[c].lpfn = 0;
 127                 places[c].flags = TTM_PL_FLAG_SYSTEM;
 128                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 129                         places[c].flags |= TTM_PL_FLAG_WC |
 130                                 TTM_PL_FLAG_UNCACHED;
 131                 else
 132                         places[c].flags |= TTM_PL_FLAG_CACHED;
 133                 c++;
 134         }
 135
 136         if (domain & AMDGPU_GEM_DOMAIN_GDS) {
 137                 places[c].fpfn = 0;
 138                 places[c].lpfn = 0;
 139                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
 140                 c++;
 141         }
 142
 143         if (domain & AMDGPU_GEM_DOMAIN_GWS) {
 144                 places[c].fpfn = 0;
 145                 places[c].lpfn = 0;
 146                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
 147                 c++;
 148         }
 149
 150         if (domain & AMDGPU_GEM_DOMAIN_OA) {
 151                 places[c].fpfn = 0;
 152                 places[c].lpfn = 0;
 153                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
 154                 c++;
 155         }
 156
 157         if (!c) {
 158                 places[c].fpfn = 0;
 159                 places[c].lpfn = 0;
 160                 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 161                 c++;
 162         }
 163
 164         placement->num_placement = c;
 165         placement->placement = places;
 166
 167         placement->num_busy_placement = c;
 168         placement->busy_placement = places;
 169 }
 170
 171 /**
 172  * amdgpu_bo_create_reserved - create reserved BO for kernel use
 173  *
 174  * @adev: amdgpu device object
 175  * @size: size for the new BO
 176  * @align: alignment for the new BO
 177  * @domain: where to place it
 178  * @bo_ptr: used to initialize BOs in structures
 179  * @gpu_addr: GPU addr of the pinned BO
 180  * @cpu_addr: optional CPU address mapping
 181  *
 182  * Allocates and pins a BO for kernel internal use, and returns it still
 183  * reserved.
 184  *
 185  * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
 186  *
 187  * Returns 0 on success, negative error code otherwise.
 188  */
 189 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
 190                               unsigned long size, int align,
 191                               u32 domain, struct amdgpu_bo **bo_ptr,
 192                               u64 *gpu_addr, void **cpu_addr)
 193 {
 194         bool free = false;
 195         int r;
 196
 197         if (!*bo_ptr) {
 198                 r = amdgpu_bo_create(adev, size, align, domain,
 199                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 200                                      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 201                                      ttm_bo_type_kernel, NULL, bo_ptr);
 202                 if (r) {
 203                         dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
 204                                 r);
 205                         return r;
 206                 }
 207                 free = true;
 208         }
 209
 210         r = amdgpu_bo_reserve(*bo_ptr, false);
 211         if (r) {
 212                 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
 213                 goto error_free;
 214         }
 215
 216         r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
 217         if (r) {
 218                 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
 219                 goto error_unreserve;
 220         }
 221
 222         if (cpu_addr) {
 223                 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
 224                 if (r) {
 225                         dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
 226                         goto error_unreserve;
 227                 }
 228         }
 229
 230         return 0;
 231
 232 error_unreserve:
 233         amdgpu_bo_unreserve(*bo_ptr);
 234
 235 error_free:
 236         if (free)
 237                 amdgpu_bo_unref(bo_ptr);
 238
 239         return r;
 240 }
 241
 242 /**
 243  * amdgpu_bo_create_kernel - create BO for kernel use
 244  *
 245  * @adev: amdgpu device object
 246  * @size: size for the new BO
 247  * @align: alignment for the new BO
 248  * @domain: where to place it
 249  * @bo_ptr:  used to initialize BOs in structures
 250  * @gpu_addr: GPU addr of the pinned BO
 251  * @cpu_addr: optional CPU address mapping
 252  *
 253  * Allocates and pins a BO for kernel internal use.
 254  *
 255  * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
 256  *
 257  * Returns 0 on success, negative error code otherwise.
 258  */
 259 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 260                             unsigned long size, int align,
 261                             u32 domain, struct amdgpu_bo **bo_ptr,
 262                             u64 *gpu_addr, void **cpu_addr)
 263 {
 264         int r;
 265
 266         r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
 267                                       gpu_addr, cpu_addr);
 268
 269         if (r)
 270                 return r;
 271
 272         amdgpu_bo_unreserve(*bo_ptr);
 273
 274         return 0;
 275 }
 276
 277 /**
 278  * amdgpu_bo_free_kernel - free BO for kernel use
 279  *
 280  * @bo: amdgpu BO to free
 281  *
 282  * unmaps and unpin a BO for kernel internal use.
 283  */
 284 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 285                            void **cpu_addr)
 286 {
 287         if (*bo == NULL)
 288                 return;
 289
 290         if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
 291                 if (cpu_addr)
 292                         amdgpu_bo_kunmap(*bo);
 293
 294                 amdgpu_bo_unpin(*bo);
 295                 amdgpu_bo_unreserve(*bo);
 296         }
 297         amdgpu_bo_unref(bo);
 298
 299         if (gpu_addr)
 300                 *gpu_addr = 0;
 301
 302         if (cpu_addr)
 303                 *cpu_addr = NULL;
 304 }
 305
 306 /* Validate bo size is bit bigger then the request domain */
 307 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
 308                                           unsigned long size, u32 domain)
 309 {
 310         struct ttm_mem_type_manager *man = NULL;
 311
 312         /*
 313          * If GTT is part of requested domains the check must succeed to
 314          * allow fall back to GTT
 315          */
 316         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 317                 man = &adev->mman.bdev.man[TTM_PL_TT];
 318
 319                 if (size < (man->size << PAGE_SHIFT))
 320                         return true;
 321                 else
 322                         goto fail;
 323         }
 324
 325         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
 326                 man = &adev->mman.bdev.man[TTM_PL_VRAM];
 327
 328                 if (size < (man->size << PAGE_SHIFT))
 329                         return true;
 330                 else
 331                         goto fail;
 332         }
 333
 334
 335         /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
 336         return true;
 337
 338 fail:
 339         DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
 340                   man->size << PAGE_SHIFT);
 341         return false;
 342 }
 343
 344 static int amdgpu_bo_do_create(struct amdgpu_device *adev, unsigned long size,
 345                                int byte_align, u32 domain,
 346                                u64 flags, enum ttm_bo_type type,
 347                                struct reservation_object *resv,
 348                                struct amdgpu_bo **bo_ptr)
 349 {
 350         struct ttm_operation_ctx ctx = {
 351                 .interruptible = (type != ttm_bo_type_kernel),
 352                 .no_wait_gpu = false,
 353                 .resv = resv,
 354                 .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
 355         };
 356         struct amdgpu_bo *bo;
 357         unsigned long page_align;
 358         size_t acc_size;
 359         u32 domains;
 360         int r;
 361
 362         page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 363         size = ALIGN(size, PAGE_SIZE);
 364
 365         if (!amdgpu_bo_validate_size(adev, size, domain))
 366                 return -ENOMEM;
 367
 368         *bo_ptr = NULL;
 369
 370         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 371                                        sizeof(struct amdgpu_bo));
 372
 373         bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
 374         if (bo == NULL)
 375                 return -ENOMEM;
 376         drm_gem_private_object_init(adev->ddev, &bo->gem_base, size);
 377         INIT_LIST_HEAD(&bo->shadow_list);
 378         INIT_LIST_HEAD(&bo->va);
 379         bo->preferred_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
 380                                          AMDGPU_GEM_DOMAIN_GTT |
 381                                          AMDGPU_GEM_DOMAIN_CPU |
 382                                          AMDGPU_GEM_DOMAIN_GDS |
 383                                          AMDGPU_GEM_DOMAIN_GWS |
 384                                          AMDGPU_GEM_DOMAIN_OA);
 385         bo->allowed_domains = bo->preferred_domains;
 386         if (type != ttm_bo_type_kernel &&
 387             bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 388                 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 389
 390         bo->flags = flags;
 391
 392 #ifdef CONFIG_X86_32
 393         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 394          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 395          */
 396         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 397 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 398         /* Don't try to enable write-combining when it can't work, or things
 399          * may be slow
 400          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 401          */
 402
 403 #ifndef CONFIG_COMPILE_TEST
 404 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 405          thanks to write-combining
 406 #endif
 407
 408         if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 409                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 410                               "better performance thanks to write-combining\n");
 411         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 412 #else
 413         /* For architectures that don't support WC memory,
 414          * mask out the WC flag from the BO
 415          */
 416         if (!drm_arch_can_wc_memory())
 417                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 418 #endif
 419
 420         bo->tbo.bdev = &adev->mman.bdev;
 421         domains = bo->preferred_domains;
 422 retry:
 423         amdgpu_ttm_placement_from_domain(bo, domains);
 424         r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
 425                                  &bo->placement, page_align, &ctx, acc_size,
 426                                  NULL, resv, &amdgpu_ttm_bo_destroy);
 427
 428         if (unlikely(r && r != -ERESTARTSYS)) {
 429                 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
 430                         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 431                         goto retry;
 432                 } else if (domains != bo->preferred_domains) {
 433                         domains = bo->allowed_domains;
 434                         goto retry;
 435                 }
 436         }
 437         if (unlikely(r))
 438                 return r;
 439
 440         if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
 441             bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 442             bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
 443                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
 444                                              ctx.bytes_moved);
 445         else
 446                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
 447
 448         if (type == ttm_bo_type_kernel)
 449                 bo->tbo.priority = 1;
 450
 451         if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
 452             bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
 453                 struct dma_fence *fence;
 454
 455                 r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
 456                 if (unlikely(r))
 457                         goto fail_unreserve;
 458
 459                 amdgpu_bo_fence(bo, fence, false);
 460                 dma_fence_put(bo->tbo.moving);
 461                 bo->tbo.moving = dma_fence_get(fence);
 462                 dma_fence_put(fence);
 463         }
 464         if (!resv)
 465                 amdgpu_bo_unreserve(bo);
 466         *bo_ptr = bo;
 467
 468         trace_amdgpu_bo_create(bo);
 469
 470         /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
 471         if (type == ttm_bo_type_device)
 472                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 473
 474         return 0;
 475
 476 fail_unreserve:
 477         if (!resv)
 478                 ww_mutex_unlock(&bo->tbo.resv->lock);
 479         amdgpu_bo_unref(&bo);
 480         return r;
 481 }
 482
 483 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
 484                                    unsigned long size, int byte_align,
 485                                    struct amdgpu_bo *bo)
 486 {
 487         int r;
 488
 489         if (bo->shadow)
 490                 return 0;
 491
 492         r = amdgpu_bo_do_create(adev, size, byte_align, AMDGPU_GEM_DOMAIN_GTT,
 493                                 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 494                                 AMDGPU_GEM_CREATE_SHADOW,
 495                                 ttm_bo_type_kernel,
 496                                 bo->tbo.resv, &bo->shadow);
 497         if (!r) {
 498                 bo->shadow->parent = amdgpu_bo_ref(bo);
 499                 mutex_lock(&adev->shadow_list_lock);
 500                 list_add_tail(&bo->shadow_list, &adev->shadow_list);
 501                 mutex_unlock(&adev->shadow_list_lock);
 502         }
 503
 504         return r;
 505 }
 506
 507 int amdgpu_bo_create(struct amdgpu_device *adev, unsigned long size,
 508                      int byte_align, u32 domain,
 509                      u64 flags, enum ttm_bo_type type,
 510                      struct reservation_object *resv,
 511                      struct amdgpu_bo **bo_ptr)
 512 {
 513         uint64_t parent_flags = flags & ~AMDGPU_GEM_CREATE_SHADOW;
 514         int r;
 515
 516         r = amdgpu_bo_do_create(adev, size, byte_align, domain,
 517                                 parent_flags, type, resv, bo_ptr);
 518         if (r)
 519                 return r;
 520
 521         if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) {
 522                 if (!resv)
 523                         WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv,
 524                                                         NULL));
 525
 526                 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
 527
 528                 if (!resv)
 529                         reservation_object_unlock((*bo_ptr)->tbo.resv);
 530
 531                 if (r)
 532                         amdgpu_bo_unref(bo_ptr);
 533         }
 534
 535         return r;
 536 }
 537
 538 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
 539                                struct amdgpu_ring *ring,
 540                                struct amdgpu_bo *bo,
 541                                struct reservation_object *resv,
 542                                struct dma_fence **fence,
 543                                bool direct)
 544
 545 {
 546         struct amdgpu_bo *shadow = bo->shadow;
 547         uint64_t bo_addr, shadow_addr;
 548         int r;
 549
 550         if (!shadow)
 551                 return -EINVAL;
 552
 553         bo_addr = amdgpu_bo_gpu_offset(bo);
 554         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 555
 556         r = reservation_object_reserve_shared(bo->tbo.resv);
 557         if (r)
 558                 goto err;
 559
 560         r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
 561                                amdgpu_bo_size(bo), resv, fence,
 562                                direct, false);
 563         if (!r)
 564                 amdgpu_bo_fence(bo, *fence, true);
 565
 566 err:
 567         return r;
 568 }
 569
 570 int amdgpu_bo_validate(struct amdgpu_bo *bo)
 571 {
 572         struct ttm_operation_ctx ctx = { false, false };
 573         uint32_t domain;
 574         int r;
 575
 576         if (bo->pin_count)
 577                 return 0;
 578
 579         domain = bo->preferred_domains;
 580
 581 retry:
 582         amdgpu_ttm_placement_from_domain(bo, domain);
 583         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 584         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 585                 domain = bo->allowed_domains;
 586                 goto retry;
 587         }
 588
 589         return r;
 590 }
 591
 592 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
 593                                   struct amdgpu_ring *ring,
 594                                   struct amdgpu_bo *bo,
 595                                   struct reservation_object *resv,
 596                                   struct dma_fence **fence,
 597                                   bool direct)
 598
 599 {
 600         struct amdgpu_bo *shadow = bo->shadow;
 601         uint64_t bo_addr, shadow_addr;
 602         int r;
 603
 604         if (!shadow)
 605                 return -EINVAL;
 606
 607         bo_addr = amdgpu_bo_gpu_offset(bo);
 608         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 609
 610         r = reservation_object_reserve_shared(bo->tbo.resv);
 611         if (r)
 612                 goto err;
 613
 614         r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
 615                                amdgpu_bo_size(bo), resv, fence,
 616                                direct, false);
 617         if (!r)
 618                 amdgpu_bo_fence(bo, *fence, true);
 619
 620 err:
 621         return r;
 622 }
 623
 624 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 625 {
 626         void *kptr;
 627         long r;
 628
 629         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 630                 return -EPERM;
 631
 632         kptr = amdgpu_bo_kptr(bo);
 633         if (kptr) {
 634                 if (ptr)
 635                         *ptr = kptr;
 636                 return 0;
 637         }
 638
 639         r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
 640                                                 MAX_SCHEDULE_TIMEOUT);
 641         if (r < 0)
 642                 return r;
 643
 644         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 645         if (r)
 646                 return r;
 647
 648         if (ptr)
 649                 *ptr = amdgpu_bo_kptr(bo);
 650
 651         return 0;
 652 }
 653
 654 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
 655 {
 656         bool is_iomem;
 657
 658         return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 659 }
 660
 661 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
 662 {
 663         if (bo->kmap.bo)
 664                 ttm_bo_kunmap(&bo->kmap);
 665 }
 666
 667 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 668 {
 669         if (bo == NULL)
 670                 return NULL;
 671
 672         ttm_bo_reference(&bo->tbo);
 673         return bo;
 674 }
 675
 676 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 677 {
 678         struct ttm_buffer_object *tbo;
 679
 680         if ((*bo) == NULL)
 681                 return;
 682
 683         tbo = &((*bo)->tbo);
 684         ttm_bo_unref(&tbo);
 685         if (tbo == NULL)
 686                 *bo = NULL;
 687 }
 688
 689 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 690                              u64 min_offset, u64 max_offset,
 691                              u64 *gpu_addr)
 692 {
 693         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 694         struct ttm_operation_ctx ctx = { false, false };
 695         int r, i;
 696
 697         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 698                 return -EPERM;
 699
 700         if (WARN_ON_ONCE(min_offset > max_offset))
 701                 return -EINVAL;
 702
 703         /* A shared bo cannot be migrated to VRAM */
 704         if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM))
 705                 return -EINVAL;
 706
 707         if (bo->pin_count) {
 708                 uint32_t mem_type = bo->tbo.mem.mem_type;
 709
 710                 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
 711                         return -EINVAL;
 712
 713                 bo->pin_count++;
 714                 if (gpu_addr)
 715                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 716
 717                 if (max_offset != 0) {
 718                         u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
 719                         WARN_ON_ONCE(max_offset <
 720                                      (amdgpu_bo_gpu_offset(bo) - domain_start));
 721                 }
 722
 723                 return 0;
 724         }
 725
 726         bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 727         /* force to pin into visible video ram */
 728         if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
 729                 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 730         amdgpu_ttm_placement_from_domain(bo, domain);
 731         for (i = 0; i < bo->placement.num_placement; i++) {
 732                 unsigned fpfn, lpfn;
 733
 734                 fpfn = min_offset >> PAGE_SHIFT;
 735                 lpfn = max_offset >> PAGE_SHIFT;
 736
 737                 if (fpfn > bo->placements[i].fpfn)
 738                         bo->placements[i].fpfn = fpfn;
 739                 if (!bo->placements[i].lpfn ||
 740                     (lpfn && lpfn < bo->placements[i].lpfn))
 741                         bo->placements[i].lpfn = lpfn;
 742                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 743         }
 744
 745         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 746         if (unlikely(r)) {
 747                 dev_err(adev->dev, "%p pin failed\n", bo);
 748                 goto error;
 749         }
 750
 751         r = amdgpu_ttm_alloc_gart(&bo->tbo);
 752         if (unlikely(r)) {
 753                 dev_err(adev->dev, "%p bind failed\n", bo);
 754                 goto error;
 755         }
 756
 757         bo->pin_count = 1;
 758         if (gpu_addr != NULL)
 759                 *gpu_addr = amdgpu_bo_gpu_offset(bo);
 760
 761         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 762         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
 763                 adev->vram_pin_size += amdgpu_bo_size(bo);
 764                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 765                         adev->invisible_pin_size += amdgpu_bo_size(bo);
 766         } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
 767                 adev->gart_pin_size += amdgpu_bo_size(bo);
 768         }
 769
 770 error:
 771         return r;
 772 }
 773
 774 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
 775 {
 776         return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
 777 }
 778
 779 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 780 {
 781         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 782         struct ttm_operation_ctx ctx = { false, false };
 783         int r, i;
 784
 785         if (!bo->pin_count) {
 786                 dev_warn(adev->dev, "%p unpin not necessary\n", bo);
 787                 return 0;
 788         }
 789         bo->pin_count--;
 790         if (bo->pin_count)
 791                 return 0;
 792         for (i = 0; i < bo->placement.num_placement; i++) {
 793                 bo->placements[i].lpfn = 0;
 794                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 795         }
 796         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 797         if (unlikely(r)) {
 798                 dev_err(adev->dev, "%p validate failed for unpin\n", bo);
 799                 goto error;
 800         }
 801
 802         if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
 803                 adev->vram_pin_size -= amdgpu_bo_size(bo);
 804                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 805                         adev->invisible_pin_size -= amdgpu_bo_size(bo);
 806         } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
 807                 adev->gart_pin_size -= amdgpu_bo_size(bo);
 808         }
 809
 810 error:
 811         return r;
 812 }
 813
 814 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
 815 {
 816         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 817         if (0 && (adev->flags & AMD_IS_APU)) {
 818                 /* Useless to evict on IGP chips */
 819                 return 0;
 820         }
 821         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 822 }
 823
 824 static const char *amdgpu_vram_names[] = {
 825         "UNKNOWN",
 826         "GDDR1",
 827         "DDR2",
 828         "GDDR3",
 829         "GDDR4",
 830         "GDDR5",
 831         "HBM",
 832         "DDR3",
 833         "DDR4",
 834 };
 835
 836 int amdgpu_bo_init(struct amdgpu_device *adev)
 837 {
 838         /* reserve PAT memory space to WC for VRAM */
 839         arch_io_reserve_memtype_wc(adev->gmc.aper_base,
 840                                    adev->gmc.aper_size);
 841
 842         /* Add an MTRR for the VRAM */
 843         adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
 844                                               adev->gmc.aper_size);
 845         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 846                  adev->gmc.mc_vram_size >> 20,
 847                  (unsigned long long)adev->gmc.aper_size >> 20);
 848         DRM_INFO("RAM width %dbits %s\n",
 849                  adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
 850         return amdgpu_ttm_init(adev);
 851 }
 852
 853 void amdgpu_bo_fini(struct amdgpu_device *adev)
 854 {
 855         amdgpu_ttm_fini(adev);
 856         arch_phys_wc_del(adev->gmc.vram_mtrr);
 857         arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
 858 }
 859
 860 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 861                              struct vm_area_struct *vma)
 862 {
 863         return ttm_fbdev_mmap(vma, &bo->tbo);
 864 }
 865
 866 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 867 {
 868         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 869
 870         if (adev->family <= AMDGPU_FAMILY_CZ &&
 871             AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
 872                 return -EINVAL;
 873
 874         bo->tiling_flags = tiling_flags;
 875         return 0;
 876 }
 877
 878 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
 879 {
 880         lockdep_assert_held(&bo->tbo.resv->lock.base);
 881
 882         if (tiling_flags)
 883                 *tiling_flags = bo->tiling_flags;
 884 }
 885
 886 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 887                             uint32_t metadata_size, uint64_t flags)
 888 {
 889         void *buffer;
 890
 891         if (!metadata_size) {
 892                 if (bo->metadata_size) {
 893                         kfree(bo->metadata);
 894                         bo->metadata = NULL;
 895                         bo->metadata_size = 0;
 896                 }
 897                 return 0;
 898         }
 899
 900         if (metadata == NULL)
 901                 return -EINVAL;
 902
 903         buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
 904         if (buffer == NULL)
 905                 return -ENOMEM;
 906
 907         kfree(bo->metadata);
 908         bo->metadata_flags = flags;
 909         bo->metadata = buffer;
 910         bo->metadata_size = metadata_size;
 911
 912         return 0;
 913 }
 914
 915 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 916                            size_t buffer_size, uint32_t *metadata_size,
 917                            uint64_t *flags)
 918 {
 919         if (!buffer && !metadata_size)
 920                 return -EINVAL;
 921
 922         if (buffer) {
 923                 if (buffer_size < bo->metadata_size)
 924                         return -EINVAL;
 925
 926                 if (bo->metadata_size)
 927                         memcpy(buffer, bo->metadata, bo->metadata_size);
 928         }
 929
 930         if (metadata_size)
 931                 *metadata_size = bo->metadata_size;
 932         if (flags)
 933                 *flags = bo->metadata_flags;
 934
 935         return 0;
 936 }
 937
 938 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 939                            bool evict,
 940                            struct ttm_mem_reg *new_mem)
 941 {
 942         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 943         struct amdgpu_bo *abo;
 944         struct ttm_mem_reg *old_mem = &bo->mem;
 945
 946         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 947                 return;
 948
 949         abo = ttm_to_amdgpu_bo(bo);
 950         amdgpu_vm_bo_invalidate(adev, abo, evict);
 951
 952         amdgpu_bo_kunmap(abo);
 953
 954         /* remember the eviction */
 955         if (evict)
 956                 atomic64_inc(&adev->num_evictions);
 957
 958         /* update statistics */
 959         if (!new_mem)
 960                 return;
 961
 962         /* move_notify is called before move happens */
 963         trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 964 }
 965
 966 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 967 {
 968         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 969         struct ttm_operation_ctx ctx = { false, false };
 970         struct amdgpu_bo *abo;
 971         unsigned long offset, size;
 972         int r;
 973
 974         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 975                 return 0;
 976
 977         abo = ttm_to_amdgpu_bo(bo);
 978
 979         /* Remember that this BO was accessed by the CPU */
 980         abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 981
 982         if (bo->mem.mem_type != TTM_PL_VRAM)
 983                 return 0;
 984
 985         size = bo->mem.num_pages << PAGE_SHIFT;
 986         offset = bo->mem.start << PAGE_SHIFT;
 987         if ((offset + size) <= adev->gmc.visible_vram_size)
 988                 return 0;
 989
 990         /* Can't move a pinned BO to visible VRAM */
 991         if (abo->pin_count > 0)
 992                 return -EINVAL;
 993
 994         /* hurrah the memory is not visible ! */
 995         atomic64_inc(&adev->num_vram_cpu_page_faults);
 996         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 997                                          AMDGPU_GEM_DOMAIN_GTT);
 998
 999         /* Avoid costly evictions; only set GTT as a busy placement */
1000         abo->placement.num_busy_placement = 1;
1001         abo->placement.busy_placement = &abo->placements[1];
1002
1003         r = ttm_bo_validate(bo, &abo->placement, &ctx);
1004         if (unlikely(r != 0))
1005                 return r;
1006
1007         offset = bo->mem.start << PAGE_SHIFT;
1008         /* this should never happen */
1009         if (bo->mem.mem_type == TTM_PL_VRAM &&
1010             (offset + size) > adev->gmc.visible_vram_size)
1011                 return -EINVAL;
1012
1013         return 0;
1014 }
1015
1016 /**
1017  * amdgpu_bo_fence - add fence to buffer object
1018  *
1019  * @bo: buffer object in question
1020  * @fence: fence to add
1021  * @shared: true if fence should be added shared
1022  *
1023  */
1024 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1025                      bool shared)
1026 {
1027         struct reservation_object *resv = bo->tbo.resv;
1028
1029         if (shared)
1030                 reservation_object_add_shared_fence(resv, fence);
1031         else
1032                 reservation_object_add_excl_fence(resv, fence);
1033 }
1034
1035 /**
1036  * amdgpu_bo_gpu_offset - return GPU offset of bo
1037  * @bo: amdgpu object for which we query the offset
1038  *
1039  * Returns current GPU offset of the object.
1040  *
1041  * Note: object should either be pinned or reserved when calling this
1042  * function, it might be useful to add check for this for debugging.
1043  */
1044 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1045 {
1046         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
1047         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
1048                      !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem));
1049         WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
1050                      !bo->pin_count);
1051         WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
1052         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
1053                      !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1054
1055         return bo->tbo.offset;
1056 }