drivers/phy/rockchip/phy-rockchip-emmc.c

   1 /*
   2  * Rockchip emmc PHY driver
   3  *
   4  * Copyright (C) 2016 Shawn Lin <[email protected]>
   5  * Copyright (C) 2016 ROCKCHIP, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/phy/phy.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/regmap.h>
  26
  27 /*
  28  * The higher 16-bit of this register is used for write protection
  29  * only if BIT(x + 16) set to 1 the BIT(x) can be written.
  30  */
  31 #define HIWORD_UPDATE(val, mask, shift) \
  32                 ((val) << (shift) | (mask) << ((shift) + 16))
  33
  34 /* Register definition */
  35 #define GRF_EMMCPHY_CON0                0x0
  36 #define GRF_EMMCPHY_CON1                0x4
  37 #define GRF_EMMCPHY_CON2                0x8
  38 #define GRF_EMMCPHY_CON3                0xc
  39 #define GRF_EMMCPHY_CON4                0x10
  40 #define GRF_EMMCPHY_CON5                0x14
  41 #define GRF_EMMCPHY_CON6                0x18
  42 #define GRF_EMMCPHY_STATUS              0x20
  43
  44 #define PHYCTRL_PDB_MASK                0x1
  45 #define PHYCTRL_PDB_SHIFT               0x0
  46 #define PHYCTRL_PDB_PWR_ON              0x1
  47 #define PHYCTRL_PDB_PWR_OFF             0x0
  48 #define PHYCTRL_ENDLL_MASK              0x1
  49 #define PHYCTRL_ENDLL_SHIFT             0x1
  50 #define PHYCTRL_ENDLL_ENABLE            0x1
  51 #define PHYCTRL_ENDLL_DISABLE           0x0
  52 #define PHYCTRL_CALDONE_MASK            0x1
  53 #define PHYCTRL_CALDONE_SHIFT           0x6
  54 #define PHYCTRL_CALDONE_DONE            0x1
  55 #define PHYCTRL_CALDONE_GOING           0x0
  56 #define PHYCTRL_DLLRDY_MASK             0x1
  57 #define PHYCTRL_DLLRDY_SHIFT            0x5
  58 #define PHYCTRL_DLLRDY_DONE             0x1
  59 #define PHYCTRL_DLLRDY_GOING            0x0
  60 #define PHYCTRL_FREQSEL_200M            0x0
  61 #define PHYCTRL_FREQSEL_50M             0x1
  62 #define PHYCTRL_FREQSEL_100M            0x2
  63 #define PHYCTRL_FREQSEL_150M            0x3
  64 #define PHYCTRL_FREQSEL_MASK            0x3
  65 #define PHYCTRL_FREQSEL_SHIFT           0xc
  66 #define PHYCTRL_DR_MASK                 0x7
  67 #define PHYCTRL_DR_SHIFT                0x4
  68 #define PHYCTRL_DR_50OHM                0x0
  69 #define PHYCTRL_DR_33OHM                0x1
  70 #define PHYCTRL_DR_66OHM                0x2
  71 #define PHYCTRL_DR_100OHM               0x3
  72 #define PHYCTRL_DR_40OHM                0x4
  73 #define PHYCTRL_OTAPDLYENA              0x1
  74 #define PHYCTRL_OTAPDLYENA_MASK         0x1
  75 #define PHYCTRL_OTAPDLYENA_SHIFT        0xb
  76 #define PHYCTRL_OTAPDLYSEL_MASK         0xf
  77 #define PHYCTRL_OTAPDLYSEL_SHIFT        0x7
  78
  79 #define PHYCTRL_IS_CALDONE(x) \
  80         ((((x) >> PHYCTRL_CALDONE_SHIFT) & \
  81           PHYCTRL_CALDONE_MASK) == PHYCTRL_CALDONE_DONE)
  82 #define PHYCTRL_IS_DLLRDY(x) \
  83         ((((x) >> PHYCTRL_DLLRDY_SHIFT) & \
  84           PHYCTRL_DLLRDY_MASK) == PHYCTRL_DLLRDY_DONE)
  85
  86 struct rockchip_emmc_phy {
  87         unsigned int    reg_offset;
  88         struct regmap   *reg_base;
  89         struct clk      *emmcclk;
  90         unsigned int drive_impedance;
  91 };
  92
  93 static int rockchip_emmc_phy_power(struct phy *phy, bool on_off)
  94 {
  95         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
  96         unsigned int caldone;
  97         unsigned int dllrdy;
  98         unsigned int freqsel = PHYCTRL_FREQSEL_200M;
  99         unsigned long rate;
 100         int ret;
 101
 102         /*
 103          * Keep phyctrl_pdb and phyctrl_endll low to allow
 104          * initialization of CALIO state M/C DFFs
 105          */
 106         regmap_write(rk_phy->reg_base,
 107                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 108                      HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
 109                                    PHYCTRL_PDB_MASK,
 110                                    PHYCTRL_PDB_SHIFT));
 111         regmap_write(rk_phy->reg_base,
 112                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 113                      HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
 114                                    PHYCTRL_ENDLL_MASK,
 115                                    PHYCTRL_ENDLL_SHIFT));
 116
 117         /* Already finish power_off above */
 118         if (on_off == PHYCTRL_PDB_PWR_OFF)
 119                 return 0;
 120
 121         rate = clk_get_rate(rk_phy->emmcclk);
 122
 123         if (rate != 0) {
 124                 unsigned long ideal_rate;
 125                 unsigned long diff;
 126
 127                 switch (rate) {
 128                 case 1 ... 74999999:
 129                         ideal_rate = 50000000;
 130                         freqsel = PHYCTRL_FREQSEL_50M;
 131                         break;
 132                 case 75000000 ... 124999999:
 133                         ideal_rate = 100000000;
 134                         freqsel = PHYCTRL_FREQSEL_100M;
 135                         break;
 136                 case 125000000 ... 174999999:
 137                         ideal_rate = 150000000;
 138                         freqsel = PHYCTRL_FREQSEL_150M;
 139                         break;
 140                 default:
 141                         ideal_rate = 200000000;
 142                         break;
 143                 }
 144
 145                 diff = (rate > ideal_rate) ?
 146                         rate - ideal_rate : ideal_rate - rate;
 147
 148                 /*
 149                  * In order for tuning delays to be accurate we need to be
 150                  * pretty spot on for the DLL range, so warn if we're too
 151                  * far off.  Also warn if we're above the 200 MHz max.  Don't
 152                  * warn for really slow rates since we won't be tuning then.
 153                  */
 154                 if ((rate > 50000000 && diff > 15000000) || (rate > 200000000))
 155                         dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);
 156         }
 157
 158         /*
 159          * According to the user manual, calpad calibration
 160          * cycle takes more than 2us without the minimal recommended
 161          * value, so we may need a little margin here
 162          */
 163         udelay(3);
 164         regmap_write(rk_phy->reg_base,
 165                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 166                      HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
 167                                    PHYCTRL_PDB_MASK,
 168                                    PHYCTRL_PDB_SHIFT));
 169
 170         /*
 171          * According to the user manual, it asks driver to wait 5us for
 172          * calpad busy trimming. However it is documented that this value is
 173          * PVT(A.K.A process,voltage and temperature) relevant, so some
 174          * failure cases are found which indicates we should be more tolerant
 175          * to calpad busy trimming.
 176          */
 177         ret = regmap_read_poll_timeout(rk_phy->reg_base,
 178                                        rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
 179                                        caldone, PHYCTRL_IS_CALDONE(caldone),
 180                                        0, 50);
 181         if (ret) {
 182                 pr_err("%s: caldone failed, ret=%d\n", __func__, ret);
 183                 return ret;
 184         }
 185
 186         /* Set the frequency of the DLL operation */
 187         regmap_write(rk_phy->reg_base,
 188                      rk_phy->reg_offset + GRF_EMMCPHY_CON0,
 189                      HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK,
 190                                    PHYCTRL_FREQSEL_SHIFT));
 191
 192         /* Turn on the DLL */
 193         regmap_write(rk_phy->reg_base,
 194                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 195                      HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
 196                                    PHYCTRL_ENDLL_MASK,
 197                                    PHYCTRL_ENDLL_SHIFT));
 198
 199         /*
 200          * We turned on the DLL even though the rate was 0 because we the
 201          * clock might be turned on later.  ...but we can't wait for the DLL
 202          * to lock when the rate is 0 because it will never lock with no
 203          * input clock.
 204          *
 205          * Technically we should be checking the lock later when the clock
 206          * is turned on, but for now we won't.
 207          */
 208         if (rate == 0)
 209                 return 0;
 210
 211         /*
 212          * After enabling analog DLL circuits docs say that we need 10.2 us if
 213          * our source clock is at 50 MHz and that lock time scales linearly
 214          * with clock speed.  If we are powering on the PHY and the card clock
 215          * is super slow (like 100 kHZ) this could take as long as 5.1 ms as
 216          * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
 217          * Hopefully we won't be running at 100 kHz, but we should still make
 218          * sure we wait long enough.
 219          *
 220          * NOTE: There appear to be corner cases where the DLL seems to take
 221          * extra long to lock for reasons that aren't understood.  In some
 222          * extreme cases we've seen it take up to over 10ms (!).  We'll be
 223          * generous and give it 50ms.
 224          */
 225         ret = regmap_read_poll_timeout(rk_phy->reg_base,
 226                                        rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
 227                                        dllrdy, PHYCTRL_IS_DLLRDY(dllrdy),
 228                                        0, 50 * USEC_PER_MSEC);
 229         if (ret) {
 230                 pr_err("%s: dllrdy failed. ret=%d\n", __func__, ret);
 231                 return ret;
 232         }
 233
 234         return 0;
 235 }
 236
 237 static int rockchip_emmc_phy_init(struct phy *phy)
 238 {
 239         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
 240         int ret = 0;
 241
 242         /*
 243          * We purposely get the clock here and not in probe to avoid the
 244          * circular dependency problem.  We expect:
 245          * - PHY driver to probe
 246          * - SDHCI driver to start probe
 247          * - SDHCI driver to register it's clock
 248          * - SDHCI driver to get the PHY
 249          * - SDHCI driver to init the PHY
 250          *
 251          * The clock is optional, so upon any error we just set to NULL.
 252          *
 253          * NOTE: we don't do anything special for EPROBE_DEFER here.  Given the
 254          * above expected use case, EPROBE_DEFER isn't sensible to expect, so
 255          * it's just like any other error.
 256          */
 257         rk_phy->emmcclk = clk_get(&phy->dev, "emmcclk");
 258         if (IS_ERR(rk_phy->emmcclk)) {
 259                 dev_dbg(&phy->dev, "Error getting emmcclk: %d\n", ret);
 260                 rk_phy->emmcclk = NULL;
 261         }
 262
 263         return ret;
 264 }
 265
 266 static int rockchip_emmc_phy_exit(struct phy *phy)
 267 {
 268         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
 269
 270         clk_put(rk_phy->emmcclk);
 271
 272         return 0;
 273 }
 274
 275 static int rockchip_emmc_phy_power_off(struct phy *phy)
 276 {
 277         /* Power down emmc phy analog blocks */
 278         return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_OFF);
 279 }
 280
 281 static int rockchip_emmc_phy_power_on(struct phy *phy)
 282 {
 283         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
 284
 285         /* Drive impedance: from DTS */
 286         regmap_write(rk_phy->reg_base,
 287                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 288                      HIWORD_UPDATE(rk_phy->drive_impedance,
 289                                    PHYCTRL_DR_MASK,
 290                                    PHYCTRL_DR_SHIFT));
 291
 292         /* Output tap delay: enable */
 293         regmap_write(rk_phy->reg_base,
 294                      rk_phy->reg_offset + GRF_EMMCPHY_CON0,
 295                      HIWORD_UPDATE(PHYCTRL_OTAPDLYENA,
 296                                    PHYCTRL_OTAPDLYENA_MASK,
 297                                    PHYCTRL_OTAPDLYENA_SHIFT));
 298
 299         /* Output tap delay */
 300         regmap_write(rk_phy->reg_base,
 301                      rk_phy->reg_offset + GRF_EMMCPHY_CON0,
 302                      HIWORD_UPDATE(4,
 303                                    PHYCTRL_OTAPDLYSEL_MASK,
 304                                    PHYCTRL_OTAPDLYSEL_SHIFT));
 305
 306         /* Power up emmc phy analog blocks */
 307         return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_ON);
 308 }
 309
 310 static const struct phy_ops ops = {
 311         .init           = rockchip_emmc_phy_init,
 312         .exit           = rockchip_emmc_phy_exit,
 313         .power_on       = rockchip_emmc_phy_power_on,
 314         .power_off      = rockchip_emmc_phy_power_off,
 315         .owner          = THIS_MODULE,
 316 };
 317
 318 static u32 convert_drive_impedance_ohm(struct platform_device *pdev, u32 dr_ohm)
 319 {
 320         switch (dr_ohm) {
 321         case 100:
 322                 return PHYCTRL_DR_100OHM;
 323         case 66:
 324                 return PHYCTRL_DR_66OHM;
 325         case 50:
 326                 return PHYCTRL_DR_50OHM;
 327         case 40:
 328                 return PHYCTRL_DR_40OHM;
 329         case 33:
 330                 return PHYCTRL_DR_33OHM;
 331         }
 332
 333         dev_warn(&pdev->dev, "Invalid value %u for drive-impedance-ohm.\n",
 334                  dr_ohm);
 335         return PHYCTRL_DR_50OHM;
 336 }
 337
 338 static int rockchip_emmc_phy_probe(struct platform_device *pdev)
 339 {
 340         struct device *dev = &pdev->dev;
 341         struct rockchip_emmc_phy *rk_phy;
 342         struct phy *generic_phy;
 343         struct phy_provider *phy_provider;
 344         struct regmap *grf;
 345         unsigned int reg_offset;
 346         u32 val;
 347
 348         if (!dev->parent || !dev->parent->of_node)
 349                 return -ENODEV;
 350
 351         grf = syscon_node_to_regmap(dev->parent->of_node);
 352         if (IS_ERR(grf)) {
 353                 dev_err(dev, "Missing rockchip,grf property\n");
 354                 return PTR_ERR(grf);
 355         }
 356
 357         rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
 358         if (!rk_phy)
 359                 return -ENOMEM;
 360
 361         if (of_property_read_u32(dev->of_node, "reg", &reg_offset)) {
 362                 dev_err(dev, "missing reg property in node %pOFn\n",
 363                         dev->of_node);
 364                 return -EINVAL;
 365         }
 366
 367         rk_phy->reg_offset = reg_offset;
 368         rk_phy->reg_base = grf;
 369         rk_phy->drive_impedance = PHYCTRL_DR_50OHM;
 370
 371         if (!of_property_read_u32(dev->of_node, "drive-impedance-ohm", &val))
 372                 rk_phy->drive_impedance = convert_drive_impedance_ohm(pdev, val);
 373
 374         generic_phy = devm_phy_create(dev, dev->of_node, &ops);
 375         if (IS_ERR(generic_phy)) {
 376                 dev_err(dev, "failed to create PHY\n");
 377                 return PTR_ERR(generic_phy);
 378         }
 379
 380         phy_set_drvdata(generic_phy, rk_phy);
 381         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 382
 383         return PTR_ERR_OR_ZERO(phy_provider);
 384 }
 385
 386 static const struct of_device_id rockchip_emmc_phy_dt_ids[] = {
 387         { .compatible = "rockchip,rk3399-emmc-phy" },
 388         {}
 389 };
 390
 391 MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids);
 392
 393 static struct platform_driver rockchip_emmc_driver = {
 394         .probe          = rockchip_emmc_phy_probe,
 395         .driver         = {
 396                 .name   = "rockchip-emmc-phy",
 397                 .of_match_table = rockchip_emmc_phy_dt_ids,
 398         },
 399 };
 400
 401 module_platform_driver(rockchip_emmc_driver);
 402
 403 MODULE_AUTHOR("Shawn Lin <[email protected]>");
 404 MODULE_DESCRIPTION("Rockchip EMMC PHY driver");
 405 MODULE_LICENSE("GPL v2");