drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27 #include <linux/list_sort.h>
  28 #include <drm/drmP.h>
  29 #include <drm/amdgpu_drm.h>
  30 #include "amdgpu.h"
  31 #include "amdgpu_trace.h"
  32
  33 #define AMDGPU_CS_MAX_PRIORITY          32u
  34 #define AMDGPU_CS_NUM_BUCKETS           (AMDGPU_CS_MAX_PRIORITY + 1)
  35
  36 /* This is based on the bucket sort with O(n) time complexity.
  37  * An item with priority "i" is added to bucket[i]. The lists are then
  38  * concatenated in descending order.
  39  */
  40 struct amdgpu_cs_buckets {
  41         struct list_head bucket[AMDGPU_CS_NUM_BUCKETS];
  42 };
  43
  44 static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b)
  45 {
  46         unsigned i;
  47
  48         for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++)
  49                 INIT_LIST_HEAD(&b->bucket[i]);
  50 }
  51
  52 static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b,
  53                                   struct list_head *item, unsigned priority)
  54 {
  55         /* Since buffers which appear sooner in the relocation list are
  56          * likely to be used more often than buffers which appear later
  57          * in the list, the sort mustn't change the ordering of buffers
  58          * with the same priority, i.e. it must be stable.
  59          */
  60         list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]);
  61 }
  62
  63 static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b,
  64                                        struct list_head *out_list)
  65 {
  66         unsigned i;
  67
  68         /* Connect the sorted buckets in the output list. */
  69         for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) {
  70                 list_splice(&b->bucket[i], out_list);
  71         }
  72 }
  73
  74 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
  75                        u32 ip_instance, u32 ring,
  76                        struct amdgpu_ring **out_ring)
  77 {
  78         /* Right now all IPs have only one instance - multiple rings. */
  79         if (ip_instance != 0) {
  80                 DRM_ERROR("invalid ip instance: %d\n", ip_instance);
  81                 return -EINVAL;
  82         }
  83
  84         switch (ip_type) {
  85         default:
  86                 DRM_ERROR("unknown ip type: %d\n", ip_type);
  87                 return -EINVAL;
  88         case AMDGPU_HW_IP_GFX:
  89                 if (ring < adev->gfx.num_gfx_rings) {
  90                         *out_ring = &adev->gfx.gfx_ring[ring];
  91                 } else {
  92                         DRM_ERROR("only %d gfx rings are supported now\n",
  93                                   adev->gfx.num_gfx_rings);
  94                         return -EINVAL;
  95                 }
  96                 break;
  97         case AMDGPU_HW_IP_COMPUTE:
  98                 if (ring < adev->gfx.num_compute_rings) {
  99                         *out_ring = &adev->gfx.compute_ring[ring];
 100                 } else {
 101                         DRM_ERROR("only %d compute rings are supported now\n",
 102                                   adev->gfx.num_compute_rings);
 103                         return -EINVAL;
 104                 }
 105                 break;
 106         case AMDGPU_HW_IP_DMA:
 107                 if (ring < 2) {
 108                         *out_ring = &adev->sdma[ring].ring;
 109                 } else {
 110                         DRM_ERROR("only two SDMA rings are supported\n");
 111                         return -EINVAL;
 112                 }
 113                 break;
 114         case AMDGPU_HW_IP_UVD:
 115                 *out_ring = &adev->uvd.ring;
 116                 break;
 117         case AMDGPU_HW_IP_VCE:
 118                 if (ring < 2){
 119                         *out_ring = &adev->vce.ring[ring];
 120                 } else {
 121                         DRM_ERROR("only two VCE rings are supported\n");
 122                         return -EINVAL;
 123                 }
 124                 break;
 125         }
 126         return 0;
 127 }
 128
 129 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
 130 {
 131         union drm_amdgpu_cs *cs = data;
 132         uint64_t *chunk_array_user;
 133         uint64_t *chunk_array = NULL;
 134         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 135         unsigned size, i;
 136         int r = 0;
 137
 138         if (!cs->in.num_chunks)
 139                 goto out;
 140
 141         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 142         if (!p->ctx) {
 143                 r = -EINVAL;
 144                 goto out;
 145         }
 146         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 147
 148         /* get chunks */
 149         INIT_LIST_HEAD(&p->validated);
 150         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 151         if (chunk_array == NULL) {
 152                 r = -ENOMEM;
 153                 goto out;
 154         }
 155
 156         chunk_array_user = (uint64_t __user *)(cs->in.chunks);
 157         if (copy_from_user(chunk_array, chunk_array_user,
 158                            sizeof(uint64_t)*cs->in.num_chunks)) {
 159                 r = -EFAULT;
 160                 goto out;
 161         }
 162
 163         p->nchunks = cs->in.num_chunks;
 164         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 165                             GFP_KERNEL);
 166         if (p->chunks == NULL) {
 167                 r = -ENOMEM;
 168                 goto out;
 169         }
 170
 171         for (i = 0; i < p->nchunks; i++) {
 172                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 173                 struct drm_amdgpu_cs_chunk user_chunk;
 174                 uint32_t __user *cdata;
 175
 176                 chunk_ptr = (void __user *)chunk_array[i];
 177                 if (copy_from_user(&user_chunk, chunk_ptr,
 178                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 179                         r = -EFAULT;
 180                         goto out;
 181                 }
 182                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 183                 p->chunks[i].length_dw = user_chunk.length_dw;
 184
 185                 size = p->chunks[i].length_dw;
 186                 cdata = (void __user *)user_chunk.chunk_data;
 187                 p->chunks[i].user_ptr = cdata;
 188
 189                 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
 190                 if (p->chunks[i].kdata == NULL) {
 191                         r = -ENOMEM;
 192                         goto out;
 193                 }
 194                 size *= sizeof(uint32_t);
 195                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 196                         r = -EFAULT;
 197                         goto out;
 198                 }
 199
 200                 switch (p->chunks[i].chunk_id) {
 201                 case AMDGPU_CHUNK_ID_IB:
 202                         p->num_ibs++;
 203                         break;
 204
 205                 case AMDGPU_CHUNK_ID_FENCE:
 206                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 207                         if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) {
 208                                 uint32_t handle;
 209                                 struct drm_gem_object *gobj;
 210                                 struct drm_amdgpu_cs_chunk_fence *fence_data;
 211
 212                                 fence_data = (void *)p->chunks[i].kdata;
 213                                 handle = fence_data->handle;
 214                                 gobj = drm_gem_object_lookup(p->adev->ddev,
 215                                                              p->filp, handle);
 216                                 if (gobj == NULL) {
 217                                         r = -EINVAL;
 218                                         goto out;
 219                                 }
 220
 221                                 p->uf.bo = gem_to_amdgpu_bo(gobj);
 222                                 p->uf.offset = fence_data->offset;
 223                         } else {
 224                                 r = -EINVAL;
 225                                 goto out;
 226                         }
 227                         break;
 228
 229                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 230                         break;
 231
 232                 default:
 233                         r = -EINVAL;
 234                         goto out;
 235                 }
 236         }
 237
 238
 239         p->ibs = kmalloc_array(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL);
 240         if (!p->ibs)
 241                 r = -ENOMEM;
 242
 243 out:
 244         kfree(chunk_array);
 245         return r;
 246 }
 247
 248 /* Returns how many bytes TTM can move per IB.
 249  */
 250 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
 251 {
 252         u64 real_vram_size = adev->mc.real_vram_size;
 253         u64 vram_usage = atomic64_read(&adev->vram_usage);
 254
 255         /* This function is based on the current VRAM usage.
 256          *
 257          * - If all of VRAM is free, allow relocating the number of bytes that
 258          *   is equal to 1/4 of the size of VRAM for this IB.
 259
 260          * - If more than one half of VRAM is occupied, only allow relocating
 261          *   1 MB of data for this IB.
 262          *
 263          * - From 0 to one half of used VRAM, the threshold decreases
 264          *   linearly.
 265          *         __________________
 266          * 1/4 of -|\               |
 267          * VRAM    | \              |
 268          *         |  \             |
 269          *         |   \            |
 270          *         |    \           |
 271          *         |     \          |
 272          *         |      \         |
 273          *         |       \________|1 MB
 274          *         |----------------|
 275          *    VRAM 0 %             100 %
 276          *         used            used
 277          *
 278          * Note: It's a threshold, not a limit. The threshold must be crossed
 279          * for buffer relocations to stop, so any buffer of an arbitrary size
 280          * can be moved as long as the threshold isn't crossed before
 281          * the relocation takes place. We don't want to disable buffer
 282          * relocations completely.
 283          *
 284          * The idea is that buffers should be placed in VRAM at creation time
 285          * and TTM should only do a minimum number of relocations during
 286          * command submission. In practice, you need to submit at least
 287          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 288          *
 289          * Also, things can get pretty crazy under memory pressure and actual
 290          * VRAM usage can change a lot, so playing safe even at 50% does
 291          * consistently increase performance.
 292          */
 293
 294         u64 half_vram = real_vram_size >> 1;
 295         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 296         u64 bytes_moved_threshold = half_free_vram >> 1;
 297         return max(bytes_moved_threshold, 1024*1024ull);
 298 }
 299
 300 int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p)
 301 {
 302         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 303         struct amdgpu_vm *vm = &fpriv->vm;
 304         struct amdgpu_device *adev = p->adev;
 305         struct amdgpu_bo_list_entry *lobj;
 306         struct list_head duplicates;
 307         struct amdgpu_bo *bo;
 308         u64 bytes_moved = 0, initial_bytes_moved;
 309         u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev);
 310         int r;
 311
 312         INIT_LIST_HEAD(&duplicates);
 313         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);
 314         if (unlikely(r != 0)) {
 315                 return r;
 316         }
 317
 318         list_for_each_entry(lobj, &p->validated, tv.head) {
 319                 bo = lobj->robj;
 320                 if (!bo->pin_count) {
 321                         u32 domain = lobj->prefered_domains;
 322                         u32 current_domain =
 323                                 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 324
 325                         /* Check if this buffer will be moved and don't move it
 326                          * if we have moved too many buffers for this IB already.
 327                          *
 328                          * Note that this allows moving at least one buffer of
 329                          * any size, because it doesn't take the current "bo"
 330                          * into account. We don't want to disallow buffer moves
 331                          * completely.
 332                          */
 333                         if (current_domain != AMDGPU_GEM_DOMAIN_CPU &&
 334                             (domain & current_domain) == 0 && /* will be moved */
 335                             bytes_moved > bytes_moved_threshold) {
 336                                 /* don't move it */
 337                                 domain = current_domain;
 338                         }
 339
 340                 retry:
 341                         amdgpu_ttm_placement_from_domain(bo, domain);
 342                         initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 343                         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 344                         bytes_moved += atomic64_read(&adev->num_bytes_moved) -
 345                                        initial_bytes_moved;
 346
 347                         if (unlikely(r)) {
 348                                 if (r != -ERESTARTSYS && domain != lobj->allowed_domains) {
 349                                         domain = lobj->allowed_domains;
 350                                         goto retry;
 351                                 }
 352                                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 353                                 return r;
 354                         }
 355                 }
 356                 lobj->bo_va = amdgpu_vm_bo_find(vm, bo);
 357         }
 358         return 0;
 359 }
 360
 361 static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
 362 {
 363         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 364         struct amdgpu_cs_buckets buckets;
 365         bool need_mmap_lock = false;
 366         int i, r;
 367
 368         if (p->bo_list) {
 369                 need_mmap_lock = p->bo_list->has_userptr;
 370                 amdgpu_cs_buckets_init(&buckets);
 371                 for (i = 0; i < p->bo_list->num_entries; i++)
 372                         amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
 373                                                                   p->bo_list->array[i].priority);
 374
 375                 amdgpu_cs_buckets_get_list(&buckets, &p->validated);
 376         }
 377
 378         p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
 379                                       &p->validated);
 380
 381         if (need_mmap_lock)
 382                 down_read(&current->mm->mmap_sem);
 383
 384         r = amdgpu_cs_list_validate(p);
 385
 386         if (need_mmap_lock)
 387                 up_read(&current->mm->mmap_sem);
 388
 389         return r;
 390 }
 391
 392 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 393 {
 394         struct amdgpu_bo_list_entry *e;
 395         int r;
 396
 397         list_for_each_entry(e, &p->validated, tv.head) {
 398                 struct reservation_object *resv = e->robj->tbo.resv;
 399                 r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp);
 400
 401                 if (r)
 402                         return r;
 403         }
 404         return 0;
 405 }
 406
 407 static int cmp_size_smaller_first(void *priv, struct list_head *a,
 408                                   struct list_head *b)
 409 {
 410         struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head);
 411         struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head);
 412
 413         /* Sort A before B if A is smaller. */
 414         return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
 415 }
 416
 417 /**
 418  * cs_parser_fini() - clean parser states
 419  * @parser:     parser structure holding parsing context.
 420  * @error:      error number
 421  *
 422  * If error is set than unvalidate buffer, otherwise just free memory
 423  * used by parsing context.
 424  **/
 425 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
 426 {
 427         unsigned i;
 428
 429         if (!error) {
 430                 /* Sort the buffer list from the smallest to largest buffer,
 431                  * which affects the order of buffers in the LRU list.
 432                  * This assures that the smallest buffers are added first
 433                  * to the LRU list, so they are likely to be later evicted
 434                  * first, instead of large buffers whose eviction is more
 435                  * expensive.
 436                  *
 437                  * This slightly lowers the number of bytes moved by TTM
 438                  * per frame under memory pressure.
 439                  */
 440                 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
 441
 442                 ttm_eu_fence_buffer_objects(&parser->ticket,
 443                                 &parser->validated,
 444                                 &parser->ibs[parser->num_ibs-1].fence->base);
 445         } else if (backoff) {
 446                 ttm_eu_backoff_reservation(&parser->ticket,
 447                                            &parser->validated);
 448         }
 449
 450         if (parser->ctx)
 451                 amdgpu_ctx_put(parser->ctx);
 452         if (parser->bo_list)
 453                 amdgpu_bo_list_put(parser->bo_list);
 454         drm_free_large(parser->vm_bos);
 455         for (i = 0; i < parser->nchunks; i++)
 456                 drm_free_large(parser->chunks[i].kdata);
 457         kfree(parser->chunks);
 458         if (parser->ibs)
 459                 for (i = 0; i < parser->num_ibs; i++)
 460                         amdgpu_ib_free(parser->adev, &parser->ibs[i]);
 461         kfree(parser->ibs);
 462         if (parser->uf.bo)
 463                 drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base);
 464 }
 465
 466 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
 467                                    struct amdgpu_vm *vm)
 468 {
 469         struct amdgpu_device *adev = p->adev;
 470         struct amdgpu_bo_va *bo_va;
 471         struct amdgpu_bo *bo;
 472         int i, r;
 473
 474         r = amdgpu_vm_update_page_directory(adev, vm);
 475         if (r)
 476                 return r;
 477
 478         r = amdgpu_vm_clear_freed(adev, vm);
 479         if (r)
 480                 return r;
 481
 482         if (p->bo_list) {
 483                 for (i = 0; i < p->bo_list->num_entries; i++) {
 484                         struct fence *f;
 485
 486                         /* ignore duplicates */
 487                         bo = p->bo_list->array[i].robj;
 488                         if (!bo)
 489                                 continue;
 490
 491                         bo_va = p->bo_list->array[i].bo_va;
 492                         if (bo_va == NULL)
 493                                 continue;
 494
 495                         r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
 496                         if (r)
 497                                 return r;
 498
 499                         f = &bo_va->last_pt_update->base;
 500                         r = amdgpu_sync_fence(adev, &p->ibs[0].sync, f);
 501                         if (r)
 502                                 return r;
 503                 }
 504         }
 505
 506         return amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync);
 507 }
 508
 509 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 510                                  struct amdgpu_cs_parser *parser)
 511 {
 512         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 513         struct amdgpu_vm *vm = &fpriv->vm;
 514         struct amdgpu_ring *ring;
 515         int i, r;
 516
 517         if (parser->num_ibs == 0)
 518                 return 0;
 519
 520         /* Only for UVD/VCE VM emulation */
 521         for (i = 0; i < parser->num_ibs; i++) {
 522                 ring = parser->ibs[i].ring;
 523                 if (ring->funcs->parse_cs) {
 524                         r = amdgpu_ring_parse_cs(ring, parser, i);
 525                         if (r)
 526                                 return r;
 527                 }
 528         }
 529
 530         mutex_lock(&vm->mutex);
 531         r = amdgpu_bo_vm_update_pte(parser, vm);
 532         if (r) {
 533                 goto out;
 534         }
 535         amdgpu_cs_sync_rings(parser);
 536
 537         r = amdgpu_ib_schedule(adev, parser->num_ibs, parser->ibs,
 538                                parser->filp);
 539
 540 out:
 541         mutex_unlock(&vm->mutex);
 542         return r;
 543 }
 544
 545 static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
 546 {
 547         if (r == -EDEADLK) {
 548                 r = amdgpu_gpu_reset(adev);
 549                 if (!r)
 550                         r = -EAGAIN;
 551         }
 552         return r;
 553 }
 554
 555 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 556                              struct amdgpu_cs_parser *parser)
 557 {
 558         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 559         struct amdgpu_vm *vm = &fpriv->vm;
 560         int i, j;
 561         int r;
 562
 563         for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) {
 564                 struct amdgpu_cs_chunk *chunk;
 565                 struct amdgpu_ib *ib;
 566                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 567                 struct amdgpu_ring *ring;
 568
 569                 chunk = &parser->chunks[i];
 570                 ib = &parser->ibs[j];
 571                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 572
 573                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 574                         continue;
 575
 576                 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
 577                                        chunk_ib->ip_instance, chunk_ib->ring,
 578                                        &ring);
 579                 if (r)
 580                         return r;
 581
 582                 if (ring->funcs->parse_cs) {
 583                         struct amdgpu_bo_va_mapping *m;
 584                         struct amdgpu_bo *aobj = NULL;
 585                         uint64_t offset;
 586                         uint8_t *kptr;
 587
 588                         m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
 589                                                    &aobj);
 590                         if (!aobj) {
 591                                 DRM_ERROR("IB va_start is invalid\n");
 592                                 return -EINVAL;
 593                         }
 594
 595                         if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
 596                             (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 597                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 598                                 return -EINVAL;
 599                         }
 600
 601                         /* the IB should be reserved at this point */
 602                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 603                         if (r) {
 604                                 return r;
 605                         }
 606
 607                         offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
 608                         kptr += chunk_ib->va_start - offset;
 609
 610                         r =  amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib);
 611                         if (r) {
 612                                 DRM_ERROR("Failed to get ib !\n");
 613                                 return r;
 614                         }
 615
 616                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 617                         amdgpu_bo_kunmap(aobj);
 618                 } else {
 619                         r =  amdgpu_ib_get(ring, vm, 0, ib);
 620                         if (r) {
 621                                 DRM_ERROR("Failed to get ib !\n");
 622                                 return r;
 623                         }
 624
 625                         ib->gpu_addr = chunk_ib->va_start;
 626                 }
 627
 628                 ib->length_dw = chunk_ib->ib_bytes / 4;
 629                 ib->flags = chunk_ib->flags;
 630                 ib->ctx = parser->ctx;
 631                 j++;
 632         }
 633
 634         if (!parser->num_ibs)
 635                 return 0;
 636
 637         /* add GDS resources to first IB */
 638         if (parser->bo_list) {
 639                 struct amdgpu_bo *gds = parser->bo_list->gds_obj;
 640                 struct amdgpu_bo *gws = parser->bo_list->gws_obj;
 641                 struct amdgpu_bo *oa = parser->bo_list->oa_obj;
 642                 struct amdgpu_ib *ib = &parser->ibs[0];
 643
 644                 if (gds) {
 645                         ib->gds_base = amdgpu_bo_gpu_offset(gds);
 646                         ib->gds_size = amdgpu_bo_size(gds);
 647                 }
 648                 if (gws) {
 649                         ib->gws_base = amdgpu_bo_gpu_offset(gws);
 650                         ib->gws_size = amdgpu_bo_size(gws);
 651                 }
 652                 if (oa) {
 653                         ib->oa_base = amdgpu_bo_gpu_offset(oa);
 654                         ib->oa_size = amdgpu_bo_size(oa);
 655                 }
 656         }
 657
 658         /* wrap the last IB with user fence */
 659         if (parser->uf.bo) {
 660                 struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1];
 661
 662                 /* UVD & VCE fw doesn't support user fences */
 663                 if (ib->ring->type == AMDGPU_RING_TYPE_UVD ||
 664                     ib->ring->type == AMDGPU_RING_TYPE_VCE)
 665                         return -EINVAL;
 666
 667                 ib->user = &parser->uf;
 668         }
 669
 670         return 0;
 671 }
 672
 673 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
 674                                   struct amdgpu_cs_parser *p)
 675 {
 676         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 677         struct amdgpu_ib *ib;
 678         int i, j, r;
 679
 680         if (!p->num_ibs)
 681                 return 0;
 682
 683         /* Add dependencies to first IB */
 684         ib = &p->ibs[0];
 685         for (i = 0; i < p->nchunks; ++i) {
 686                 struct drm_amdgpu_cs_chunk_dep *deps;
 687                 struct amdgpu_cs_chunk *chunk;
 688                 unsigned num_deps;
 689
 690                 chunk = &p->chunks[i];
 691
 692                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
 693                         continue;
 694
 695                 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
 696                 num_deps = chunk->length_dw * 4 /
 697                         sizeof(struct drm_amdgpu_cs_chunk_dep);
 698
 699                 for (j = 0; j < num_deps; ++j) {
 700                         struct amdgpu_ring *ring;
 701                         struct amdgpu_ctx *ctx;
 702                         struct fence *fence;
 703
 704                         r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
 705                                                deps[j].ip_instance,
 706                                                deps[j].ring, &ring);
 707                         if (r)
 708                                 return r;
 709
 710                         ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
 711                         if (ctx == NULL)
 712                                 return -EINVAL;
 713
 714                         fence = amdgpu_ctx_get_fence(ctx, ring,
 715                                                      deps[j].handle);
 716                         if (IS_ERR(fence)) {
 717                                 r = PTR_ERR(fence);
 718                                 amdgpu_ctx_put(ctx);
 719                                 return r;
 720
 721                         } else if (fence) {
 722                                 r = amdgpu_sync_fence(adev, &ib->sync, fence);
 723                                 fence_put(fence);
 724                                 amdgpu_ctx_put(ctx);
 725                                 if (r)
 726                                         return r;
 727                         }
 728                 }
 729         }
 730
 731         return 0;
 732 }
 733
 734 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 735 {
 736         struct amdgpu_device *adev = dev->dev_private;
 737         union drm_amdgpu_cs *cs = data;
 738         struct amdgpu_cs_parser parser;
 739         int r, i;
 740         bool reserved_buffers = false;
 741
 742         down_read(&adev->exclusive_lock);
 743         if (!adev->accel_working) {
 744                 up_read(&adev->exclusive_lock);
 745                 return -EBUSY;
 746         }
 747         /* initialize parser */
 748         memset(&parser, 0, sizeof(struct amdgpu_cs_parser));
 749         parser.filp = filp;
 750         parser.adev = adev;
 751         r = amdgpu_cs_parser_init(&parser, data);
 752         if (r) {
 753                 DRM_ERROR("Failed to initialize parser !\n");
 754                 amdgpu_cs_parser_fini(&parser, r, false);
 755                 up_read(&adev->exclusive_lock);
 756                 r = amdgpu_cs_handle_lockup(adev, r);
 757                 return r;
 758         }
 759
 760         r = amdgpu_cs_parser_relocs(&parser);
 761         if (r) {
 762                 if (r != -ERESTARTSYS) {
 763                         if (r == -ENOMEM)
 764                                 DRM_ERROR("Not enough memory for command submission!\n");
 765                         else
 766                                 DRM_ERROR("Failed to process the buffer list %d!\n", r);
 767                 }
 768         }
 769
 770         if (!r) {
 771                 reserved_buffers = true;
 772                 r = amdgpu_cs_ib_fill(adev, &parser);
 773         }
 774
 775         if (!r) {
 776                 r = amdgpu_cs_dependencies(adev, &parser);
 777                 if (r)
 778                         DRM_ERROR("Failed in the dependencies handling %d!\n", r);
 779         }
 780
 781         if (r) {
 782                 amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
 783                 up_read(&adev->exclusive_lock);
 784                 r = amdgpu_cs_handle_lockup(adev, r);
 785                 return r;
 786         }
 787
 788         for (i = 0; i < parser.num_ibs; i++)
 789                 trace_amdgpu_cs(&parser, i);
 790
 791         r = amdgpu_cs_ib_vm_chunk(adev, &parser);
 792         if (r) {
 793                 goto out;
 794         }
 795
 796         cs->out.handle = parser.ibs[parser.num_ibs - 1].sequence;
 797 out:
 798         amdgpu_cs_parser_fini(&parser, r, true);
 799         up_read(&adev->exclusive_lock);
 800         r = amdgpu_cs_handle_lockup(adev, r);
 801         return r;
 802 }
 803
 804 /**
 805  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
 806  *
 807  * @dev: drm device
 808  * @data: data from userspace
 809  * @filp: file private
 810  *
 811  * Wait for the command submission identified by handle to finish.
 812  */
 813 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
 814                          struct drm_file *filp)
 815 {
 816         union drm_amdgpu_wait_cs *wait = data;
 817         struct amdgpu_device *adev = dev->dev_private;
 818         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
 819         struct amdgpu_ring *ring = NULL;
 820         struct amdgpu_ctx *ctx;
 821         struct fence *fence;
 822         long r;
 823
 824         r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
 825                                wait->in.ring, &ring);
 826         if (r)
 827                 return r;
 828
 829         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
 830         if (ctx == NULL)
 831                 return -EINVAL;
 832
 833         fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
 834         if (IS_ERR(fence))
 835                 r = PTR_ERR(fence);
 836
 837         else if (fence) {
 838                 r = fence_wait_timeout(fence, true, timeout);
 839                 fence_put(fence);
 840
 841         } else
 842                 r = 1;
 843
 844         amdgpu_ctx_put(ctx);
 845         if (r < 0)
 846                 return r;
 847
 848         memset(wait, 0, sizeof(*wait));
 849         wait->out.status = (r == 0);
 850
 851         return 0;
 852 }
 853
 854 /**
 855  * amdgpu_cs_find_bo_va - find bo_va for VM address
 856  *
 857  * @parser: command submission parser context
 858  * @addr: VM address
 859  * @bo: resulting BO of the mapping found
 860  *
 861  * Search the buffer objects in the command submission context for a certain
 862  * virtual memory address. Returns allocation structure when found, NULL
 863  * otherwise.
 864  */
 865 struct amdgpu_bo_va_mapping *
 866 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
 867                        uint64_t addr, struct amdgpu_bo **bo)
 868 {
 869         struct amdgpu_bo_list_entry *reloc;
 870         struct amdgpu_bo_va_mapping *mapping;
 871
 872         addr /= AMDGPU_GPU_PAGE_SIZE;
 873
 874         list_for_each_entry(reloc, &parser->validated, tv.head) {
 875                 if (!reloc->bo_va)
 876                         continue;
 877
 878                 list_for_each_entry(mapping, &reloc->bo_va->mappings, list) {
 879                         if (mapping->it.start > addr ||
 880                             addr > mapping->it.last)
 881                                 continue;
 882
 883                         *bo = reloc->bo_va->bo;
 884                         return mapping;
 885                 }
 886         }
 887
 888         return NULL;
 889 }