drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/slab.h>
  26 #include <linux/module.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_ucode.h"
  30
  31 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
  32 {
  33         DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
  34         DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
  35         DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
  36         DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
  37         DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
  38         DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
  39         DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
  40         DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
  41         DRM_DEBUG("ucode_array_offset_bytes: %u\n",
  42                   le32_to_cpu(hdr->ucode_array_offset_bytes));
  43         DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
  44 }
  45
  46 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
  47 {
  48         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
  49         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
  50
  51         DRM_DEBUG("MC\n");
  52         amdgpu_ucode_print_common_hdr(hdr);
  53
  54         if (version_major == 1) {
  55                 const struct mc_firmware_header_v1_0 *mc_hdr =
  56                         container_of(hdr, struct mc_firmware_header_v1_0, header);
  57
  58                 DRM_DEBUG("io_debug_size_bytes: %u\n",
  59                           le32_to_cpu(mc_hdr->io_debug_size_bytes));
  60                 DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
  61                           le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
  62         } else {
  63                 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
  64         }
  65 }
  66
  67 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
  68 {
  69         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
  70         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
  71
  72         DRM_DEBUG("SMC\n");
  73         amdgpu_ucode_print_common_hdr(hdr);
  74
  75         if (version_major == 1) {
  76                 const struct smc_firmware_header_v1_0 *smc_hdr =
  77                         container_of(hdr, struct smc_firmware_header_v1_0, header);
  78
  79                 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr));
  80         } else if (version_major == 2) {
  81                 const struct smc_firmware_header_v1_0 *v1_hdr =
  82                         container_of(hdr, struct smc_firmware_header_v1_0, header);
  83                 const struct smc_firmware_header_v2_0 *v2_hdr =
  84                         container_of(v1_hdr, struct smc_firmware_header_v2_0, v1_0);
  85
  86                 DRM_INFO("ppt_offset_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_offset_bytes));
  87                 DRM_INFO("ppt_size_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_size_bytes));
  88         } else {
  89                 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
  90         }
  91 }
  92
  93 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
  94 {
  95         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
  96         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
  97
  98         DRM_DEBUG("GFX\n");
  99         amdgpu_ucode_print_common_hdr(hdr);
 100
 101         if (version_major == 1) {
 102                 const struct gfx_firmware_header_v1_0 *gfx_hdr =
 103                         container_of(hdr, struct gfx_firmware_header_v1_0, header);
 104
 105                 DRM_DEBUG("ucode_feature_version: %u\n",
 106                           le32_to_cpu(gfx_hdr->ucode_feature_version));
 107                 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
 108                 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
 109         } else {
 110                 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
 111         }
 112 }
 113
 114 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
 115 {
 116         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 117         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 118
 119         DRM_DEBUG("RLC\n");
 120         amdgpu_ucode_print_common_hdr(hdr);
 121
 122         if (version_major == 1) {
 123                 const struct rlc_firmware_header_v1_0 *rlc_hdr =
 124                         container_of(hdr, struct rlc_firmware_header_v1_0, header);
 125
 126                 DRM_DEBUG("ucode_feature_version: %u\n",
 127                           le32_to_cpu(rlc_hdr->ucode_feature_version));
 128                 DRM_DEBUG("save_and_restore_offset: %u\n",
 129                           le32_to_cpu(rlc_hdr->save_and_restore_offset));
 130                 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
 131                           le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
 132                 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
 133                           le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
 134                 DRM_DEBUG("master_pkt_description_offset: %u\n",
 135                           le32_to_cpu(rlc_hdr->master_pkt_description_offset));
 136         } else if (version_major == 2) {
 137                 const struct rlc_firmware_header_v2_0 *rlc_hdr =
 138                         container_of(hdr, struct rlc_firmware_header_v2_0, header);
 139
 140                 DRM_DEBUG("ucode_feature_version: %u\n",
 141                           le32_to_cpu(rlc_hdr->ucode_feature_version));
 142                 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
 143                 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
 144                 DRM_DEBUG("save_and_restore_offset: %u\n",
 145                           le32_to_cpu(rlc_hdr->save_and_restore_offset));
 146                 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
 147                           le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
 148                 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
 149                           le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
 150                 DRM_DEBUG("reg_restore_list_size: %u\n",
 151                           le32_to_cpu(rlc_hdr->reg_restore_list_size));
 152                 DRM_DEBUG("reg_list_format_start: %u\n",
 153                           le32_to_cpu(rlc_hdr->reg_list_format_start));
 154                 DRM_DEBUG("reg_list_format_separate_start: %u\n",
 155                           le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
 156                 DRM_DEBUG("starting_offsets_start: %u\n",
 157                           le32_to_cpu(rlc_hdr->starting_offsets_start));
 158                 DRM_DEBUG("reg_list_format_size_bytes: %u\n",
 159                           le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
 160                 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
 161                           le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 162                 DRM_DEBUG("reg_list_size_bytes: %u\n",
 163                           le32_to_cpu(rlc_hdr->reg_list_size_bytes));
 164                 DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
 165                           le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 166                 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
 167                           le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
 168                 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
 169                           le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
 170                 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
 171                           le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
 172                 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
 173                           le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
 174                 if (version_minor == 1) {
 175                         const struct rlc_firmware_header_v2_1 *v2_1 =
 176                                 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
 177                         DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
 178                                   le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length));
 179                         DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
 180                                   le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver));
 181                         DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
 182                                   le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver));
 183                         DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
 184                                   le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes));
 185                         DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
 186                                   le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes));
 187                         DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
 188                                   le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver));
 189                         DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
 190                                   le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver));
 191                         DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
 192                                   le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes));
 193                         DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
 194                                   le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes));
 195                         DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
 196                                   le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver));
 197                         DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
 198                                   le32_to_cpu(v2_1->save_restore_list_srm_feature_ver));
 199                         DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
 200                                   le32_to_cpu(v2_1->save_restore_list_srm_size_bytes));
 201                         DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
 202                                   le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes));
 203                 }
 204         } else {
 205                 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
 206         }
 207 }
 208
 209 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
 210 {
 211         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 212         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 213
 214         DRM_DEBUG("SDMA\n");
 215         amdgpu_ucode_print_common_hdr(hdr);
 216
 217         if (version_major == 1) {
 218                 const struct sdma_firmware_header_v1_0 *sdma_hdr =
 219                         container_of(hdr, struct sdma_firmware_header_v1_0, header);
 220
 221                 DRM_DEBUG("ucode_feature_version: %u\n",
 222                           le32_to_cpu(sdma_hdr->ucode_feature_version));
 223                 DRM_DEBUG("ucode_change_version: %u\n",
 224                           le32_to_cpu(sdma_hdr->ucode_change_version));
 225                 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
 226                 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
 227                 if (version_minor >= 1) {
 228                         const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
 229                                 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
 230                         DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
 231                 }
 232         } else {
 233                 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
 234                           version_major, version_minor);
 235         }
 236 }
 237
 238 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
 239 {
 240         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 241         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 242
 243         DRM_DEBUG("PSP\n");
 244         amdgpu_ucode_print_common_hdr(hdr);
 245
 246         if (version_major == 1) {
 247                 const struct psp_firmware_header_v1_0 *psp_hdr =
 248                         container_of(hdr, struct psp_firmware_header_v1_0, header);
 249
 250                 DRM_DEBUG("ucode_feature_version: %u\n",
 251                           le32_to_cpu(psp_hdr->ucode_feature_version));
 252                 DRM_DEBUG("sos_offset_bytes: %u\n",
 253                           le32_to_cpu(psp_hdr->sos_offset_bytes));
 254                 DRM_DEBUG("sos_size_bytes: %u\n",
 255                           le32_to_cpu(psp_hdr->sos_size_bytes));
 256                 if (version_minor == 1) {
 257                         const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
 258                                 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
 259                         DRM_DEBUG("toc_header_version: %u\n",
 260                                   le32_to_cpu(psp_hdr_v1_1->toc_header_version));
 261                         DRM_DEBUG("toc_offset_bytes: %u\n",
 262                                   le32_to_cpu(psp_hdr_v1_1->toc_offset_bytes));
 263                         DRM_DEBUG("toc_size_bytes: %u\n",
 264                                   le32_to_cpu(psp_hdr_v1_1->toc_size_bytes));
 265                 }
 266         } else {
 267                 DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
 268                           version_major, version_minor);
 269         }
 270 }
 271
 272 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
 273 {
 274         uint16_t version_major = le16_to_cpu(hdr->header_version_major);
 275         uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
 276
 277         DRM_DEBUG("GPU_INFO\n");
 278         amdgpu_ucode_print_common_hdr(hdr);
 279
 280         if (version_major == 1) {
 281                 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
 282                         container_of(hdr, struct gpu_info_firmware_header_v1_0, header);
 283
 284                 DRM_DEBUG("version_major: %u\n",
 285                           le16_to_cpu(gpu_info_hdr->version_major));
 286                 DRM_DEBUG("version_minor: %u\n",
 287                           le16_to_cpu(gpu_info_hdr->version_minor));
 288         } else {
 289                 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
 290         }
 291 }
 292
 293 int amdgpu_ucode_validate(const struct firmware *fw)
 294 {
 295         const struct common_firmware_header *hdr =
 296                 (const struct common_firmware_header *)fw->data;
 297
 298         if (fw->size == le32_to_cpu(hdr->size_bytes))
 299                 return 0;
 300
 301         return -EINVAL;
 302 }
 303
 304 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
 305                                 uint16_t hdr_major, uint16_t hdr_minor)
 306 {
 307         if ((hdr->common.header_version_major == hdr_major) &&
 308                 (hdr->common.header_version_minor == hdr_minor))
 309                 return false;
 310         return true;
 311 }
 312
 313 enum amdgpu_firmware_load_type
 314 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
 315 {
 316         switch (adev->asic_type) {
 317 #ifdef CONFIG_DRM_AMDGPU_SI
 318         case CHIP_TAHITI:
 319         case CHIP_PITCAIRN:
 320         case CHIP_VERDE:
 321         case CHIP_OLAND:
 322         case CHIP_HAINAN:
 323                 return AMDGPU_FW_LOAD_DIRECT;
 324 #endif
 325 #ifdef CONFIG_DRM_AMDGPU_CIK
 326         case CHIP_BONAIRE:
 327         case CHIP_KAVERI:
 328         case CHIP_KABINI:
 329         case CHIP_HAWAII:
 330         case CHIP_MULLINS:
 331                 return AMDGPU_FW_LOAD_DIRECT;
 332 #endif
 333         case CHIP_TOPAZ:
 334         case CHIP_TONGA:
 335         case CHIP_FIJI:
 336         case CHIP_CARRIZO:
 337         case CHIP_STONEY:
 338         case CHIP_POLARIS10:
 339         case CHIP_POLARIS11:
 340         case CHIP_POLARIS12:
 341         case CHIP_VEGAM:
 342                 return AMDGPU_FW_LOAD_SMU;
 343         case CHIP_VEGA10:
 344         case CHIP_RAVEN:
 345         case CHIP_VEGA12:
 346         case CHIP_VEGA20:
 347         case CHIP_NAVI10:
 348                 if (!load_type)
 349                         return AMDGPU_FW_LOAD_DIRECT;
 350                 else
 351                         return AMDGPU_FW_LOAD_PSP;
 352         default:
 353                 DRM_ERROR("Unknown firmware load type\n");
 354         }
 355
 356         return AMDGPU_FW_LOAD_DIRECT;
 357 }
 358
 359 #define FW_VERSION_ATTR(name, mode, field)                              \
 360 static ssize_t show_##name(struct device *dev,                          \
 361                           struct device_attribute *attr,                \
 362                           char *buf)                                    \
 363 {                                                                       \
 364         struct drm_device *ddev = dev_get_drvdata(dev);                 \
 365         struct amdgpu_device *adev = ddev->dev_private;                 \
 366                                                                         \
 367         return snprintf(buf, PAGE_SIZE, "0x%08x\n", adev->field);       \
 368 }                                                                       \
 369 static DEVICE_ATTR(name, mode, show_##name, NULL)
 370
 371 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
 372 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
 373 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version);
 374 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
 375 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
 376 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
 377 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
 378 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
 379 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
 380 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
 381 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
 382 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
 383 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos_fw_version);
 384 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_fw_version);
 385 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ta_fw_version);
 386 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.ta_fw_version);
 387 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version);
 388 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version);
 389 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version);
 390 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);
 391 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version);
 392
 393 static struct attribute *fw_attrs[] = {
 394         &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr,
 395         &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr,
 396         &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr,
 397         &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr,
 398         &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr,
 399         &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr,
 400         &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr,
 401         &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,
 402         &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,
 403         &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,
 404         &dev_attr_dmcu_fw_version.attr, NULL
 405 };
 406
 407 static const struct attribute_group fw_attr_group = {
 408         .name = "fw_version",
 409         .attrs = fw_attrs
 410 };
 411
 412 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
 413 {
 414         return sysfs_create_group(&adev->dev->kobj, &fw_attr_group);
 415 }
 416
 417 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev)
 418 {
 419         sysfs_remove_group(&adev->dev->kobj, &fw_attr_group);
 420 }
 421
 422 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
 423                                        struct amdgpu_firmware_info *ucode,
 424                                        uint64_t mc_addr, void *kptr)
 425 {
 426         const struct common_firmware_header *header = NULL;
 427         const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
 428         const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
 429
 430         if (NULL == ucode->fw)
 431                 return 0;
 432
 433         ucode->mc_addr = mc_addr;
 434         ucode->kaddr = kptr;
 435
 436         if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
 437                 return 0;
 438
 439         header = (const struct common_firmware_header *)ucode->fw->data;
 440         cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
 441         dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
 442
 443         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
 444             (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
 445              ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&
 446              ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&
 447              ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&
 448              ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&
 449              ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
 450              ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&
 451                  ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM &&
 452                  ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV)) {
 453                 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
 454
 455                 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
 456                                               le32_to_cpu(header->ucode_array_offset_bytes)),
 457                        ucode->ucode_size);
 458         } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 ||
 459                    ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) {
 460                 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
 461                         le32_to_cpu(cp_hdr->jt_size) * 4;
 462
 463                 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
 464                                               le32_to_cpu(header->ucode_array_offset_bytes)),
 465                        ucode->ucode_size);
 466         } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
 467                    ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) {
 468                 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
 469
 470                 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
 471                                               le32_to_cpu(header->ucode_array_offset_bytes) +
 472                                               le32_to_cpu(cp_hdr->jt_offset) * 4),
 473                        ucode->ucode_size);
 474         } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) {
 475                 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
 476                                 le32_to_cpu(dmcu_hdr->intv_size_bytes);
 477
 478                 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
 479                                               le32_to_cpu(header->ucode_array_offset_bytes)),
 480                        ucode->ucode_size);
 481         } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) {
 482                 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
 483
 484                 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
 485                                               le32_to_cpu(header->ucode_array_offset_bytes) +
 486                                               le32_to_cpu(dmcu_hdr->intv_offset_bytes)),
 487                        ucode->ucode_size);
 488         } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {
 489                 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
 490                 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,
 491                        ucode->ucode_size);
 492         } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) {
 493                 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
 494                 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm,
 495                        ucode->ucode_size);
 496         } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
 497                 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
 498                 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,
 499                        ucode->ucode_size);
 500         }
 501
 502         return 0;
 503 }
 504
 505 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
 506                                 uint64_t mc_addr, void *kptr)
 507 {
 508         const struct gfx_firmware_header_v1_0 *header = NULL;
 509         const struct common_firmware_header *comm_hdr = NULL;
 510         uint8_t* src_addr = NULL;
 511         uint8_t* dst_addr = NULL;
 512
 513         if (NULL == ucode->fw)
 514                 return 0;
 515
 516         comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
 517         header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
 518         dst_addr = ucode->kaddr +
 519                            ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
 520                            PAGE_SIZE);
 521         src_addr = (uint8_t *)ucode->fw->data +
 522                            le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
 523                            (le32_to_cpu(header->jt_offset) * 4);
 524         memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
 525
 526         return 0;
 527 }
 528
 529 int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
 530 {
 531         if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
 532                 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
 533                         amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
 534                         &adev->firmware.fw_buf,
 535                         &adev->firmware.fw_buf_mc,
 536                         &adev->firmware.fw_buf_ptr);
 537                 if (!adev->firmware.fw_buf) {
 538                         dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
 539                         return -ENOMEM;
 540                 } else if (amdgpu_sriov_vf(adev)) {
 541                         memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
 542                 }
 543         }
 544         return 0;
 545 }
 546
 547 void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
 548 {
 549         if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT)
 550                 amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
 551                 &adev->firmware.fw_buf_mc,
 552                 &adev->firmware.fw_buf_ptr);
 553 }
 554
 555 int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
 556 {
 557         uint64_t fw_offset = 0;
 558         int i;
 559         struct amdgpu_firmware_info *ucode = NULL;
 560
 561  /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
 562         if (!amdgpu_sriov_vf(adev) && (adev->in_gpu_reset || adev->in_suspend))
 563                 return 0;
 564         /*
 565          * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
 566          * ucode info here
 567          */
 568         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 569                 if (amdgpu_sriov_vf(adev))
 570                         adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
 571                 else
 572                         adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
 573         } else {
 574                 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
 575         }
 576
 577         for (i = 0; i < adev->firmware.max_ucodes; i++) {
 578                 ucode = &adev->firmware.ucode[i];
 579                 if (ucode->fw) {
 580                         amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
 581                                                     adev->firmware.fw_buf_ptr + fw_offset);
 582                         if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
 583                             adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 584                                 const struct gfx_firmware_header_v1_0 *cp_hdr;
 585                                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
 586                                 amdgpu_ucode_patch_jt(ucode,  adev->firmware.fw_buf_mc + fw_offset,
 587                                                     adev->firmware.fw_buf_ptr + fw_offset);
 588                                 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
 589                         }
 590                         fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
 591                 }
 592         }
 593         return 0;
 594 }