drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/seq_file.h>
  39 #include <linux/slab.h>
  40 #include <linux/swap.h>
  41 #include <linux/swiotlb.h>
  42
  43 #include <drm/ttm/ttm_bo_api.h>
  44 #include <drm/ttm/ttm_bo_driver.h>
  45 #include <drm/ttm/ttm_placement.h>
  46 #include <drm/ttm/ttm_module.h>
  47 #include <drm/ttm/ttm_page_alloc.h>
  48
  49 #include <drm/drm_debugfs.h>
  50 #include <drm/amdgpu_drm.h>
  51
  52 #include "amdgpu.h"
  53 #include "amdgpu_object.h"
  54 #include "amdgpu_trace.h"
  55 #include "amdgpu_amdkfd.h"
  56 #include "amdgpu_sdma.h"
  57 #include "bif/bif_4_1_d.h"
  58
  59 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  60                              struct ttm_mem_reg *mem, unsigned num_pages,
  61                              uint64_t offset, unsigned window,
  62                              struct amdgpu_ring *ring,
  63                              uint64_t *addr);
  64
  65 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  66 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  67
  68 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  69 {
  70         return 0;
  71 }
  72
  73 /**
  74  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
  75  * memory request.
  76  *
  77  * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
  78  * @type: The type of memory requested
  79  * @man: The memory type manager for each domain
  80  *
  81  * This is called by ttm_bo_init_mm() when a buffer object is being
  82  * initialized.
  83  */
  84 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  85                                 struct ttm_mem_type_manager *man)
  86 {
  87         struct amdgpu_device *adev;
  88
  89         adev = amdgpu_ttm_adev(bdev);
  90
  91         switch (type) {
  92         case TTM_PL_SYSTEM:
  93                 /* System memory */
  94                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  95                 man->available_caching = TTM_PL_MASK_CACHING;
  96                 man->default_caching = TTM_PL_FLAG_CACHED;
  97                 break;
  98         case TTM_PL_TT:
  99                 /* GTT memory  */
 100                 man->func = &amdgpu_gtt_mgr_func;
 101                 man->gpu_offset = adev->gmc.gart_start;
 102                 man->available_caching = TTM_PL_MASK_CACHING;
 103                 man->default_caching = TTM_PL_FLAG_CACHED;
 104                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 105                 break;
 106         case TTM_PL_VRAM:
 107                 /* "On-card" video ram */
 108                 man->func = &amdgpu_vram_mgr_func;
 109                 man->gpu_offset = adev->gmc.vram_start;
 110                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 111                              TTM_MEMTYPE_FLAG_MAPPABLE;
 112                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 113                 man->default_caching = TTM_PL_FLAG_WC;
 114                 break;
 115         case AMDGPU_PL_GDS:
 116         case AMDGPU_PL_GWS:
 117         case AMDGPU_PL_OA:
 118                 /* On-chip GDS memory*/
 119                 man->func = &ttm_bo_manager_func;
 120                 man->gpu_offset = 0;
 121                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 122                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 123                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 124                 break;
 125         default:
 126                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 127                 return -EINVAL;
 128         }
 129         return 0;
 130 }
 131
 132 /**
 133  * amdgpu_evict_flags - Compute placement flags
 134  *
 135  * @bo: The buffer object to evict
 136  * @placement: Possible destination(s) for evicted BO
 137  *
 138  * Fill in placement data when ttm_bo_evict() is called
 139  */
 140 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 141                                 struct ttm_placement *placement)
 142 {
 143         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 144         struct amdgpu_bo *abo;
 145         static const struct ttm_place placements = {
 146                 .fpfn = 0,
 147                 .lpfn = 0,
 148                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 149         };
 150
 151         /* Don't handle scatter gather BOs */
 152         if (bo->type == ttm_bo_type_sg) {
 153                 placement->num_placement = 0;
 154                 placement->num_busy_placement = 0;
 155                 return;
 156         }
 157
 158         /* Object isn't an AMDGPU object so ignore */
 159         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 160                 placement->placement = &placements;
 161                 placement->busy_placement = &placements;
 162                 placement->num_placement = 1;
 163                 placement->num_busy_placement = 1;
 164                 return;
 165         }
 166
 167         abo = ttm_to_amdgpu_bo(bo);
 168         switch (bo->mem.mem_type) {
 169         case AMDGPU_PL_GDS:
 170         case AMDGPU_PL_GWS:
 171         case AMDGPU_PL_OA:
 172                 placement->num_placement = 0;
 173                 placement->num_busy_placement = 0;
 174                 return;
 175
 176         case TTM_PL_VRAM:
 177                 if (!adev->mman.buffer_funcs_enabled) {
 178                         /* Move to system memory */
 179                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 180                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 181                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 182                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 183
 184                         /* Try evicting to the CPU inaccessible part of VRAM
 185                          * first, but only set GTT as busy placement, so this
 186                          * BO will be evicted to GTT rather than causing other
 187                          * BOs to be evicted from VRAM
 188                          */
 189                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 190                                                          AMDGPU_GEM_DOMAIN_GTT);
 191                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 192                         abo->placements[0].lpfn = 0;
 193                         abo->placement.busy_placement = &abo->placements[1];
 194                         abo->placement.num_busy_placement = 1;
 195                 } else {
 196                         /* Move to GTT memory */
 197                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 198                 }
 199                 break;
 200         case TTM_PL_TT:
 201         default:
 202                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 203                 break;
 204         }
 205         *placement = abo->placement;
 206 }
 207
 208 /**
 209  * amdgpu_verify_access - Verify access for a mmap call
 210  *
 211  * @bo: The buffer object to map
 212  * @filp: The file pointer from the process performing the mmap
 213  *
 214  * This is called by ttm_bo_mmap() to verify whether a process
 215  * has the right to mmap a BO to their process space.
 216  */
 217 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 218 {
 219         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 220
 221         /*
 222          * Don't verify access for KFD BOs. They don't have a GEM
 223          * object associated with them.
 224          */
 225         if (abo->kfd_bo)
 226                 return 0;
 227
 228         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 229                 return -EPERM;
 230         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 231                                           filp->private_data);
 232 }
 233
 234 /**
 235  * amdgpu_move_null - Register memory for a buffer object
 236  *
 237  * @bo: The bo to assign the memory to
 238  * @new_mem: The memory to be assigned.
 239  *
 240  * Assign the memory from new_mem to the memory of the buffer object bo.
 241  */
 242 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 243                              struct ttm_mem_reg *new_mem)
 244 {
 245         struct ttm_mem_reg *old_mem = &bo->mem;
 246
 247         BUG_ON(old_mem->mm_node != NULL);
 248         *old_mem = *new_mem;
 249         new_mem->mm_node = NULL;
 250 }
 251
 252 /**
 253  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 254  *
 255  * @bo: The bo to assign the memory to.
 256  * @mm_node: Memory manager node for drm allocator.
 257  * @mem: The region where the bo resides.
 258  *
 259  */
 260 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 261                                     struct drm_mm_node *mm_node,
 262                                     struct ttm_mem_reg *mem)
 263 {
 264         uint64_t addr = 0;
 265
 266         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 267                 addr = mm_node->start << PAGE_SHIFT;
 268                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 269         }
 270         return addr;
 271 }
 272
 273 /**
 274  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 275  * @offset. It also modifies the offset to be within the drm_mm_node returned
 276  *
 277  * @mem: The region where the bo resides.
 278  * @offset: The offset that drm_mm_node is used for finding.
 279  *
 280  */
 281 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 282                                                unsigned long *offset)
 283 {
 284         struct drm_mm_node *mm_node = mem->mm_node;
 285
 286         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 287                 *offset -= (mm_node->size << PAGE_SHIFT);
 288                 ++mm_node;
 289         }
 290         return mm_node;
 291 }
 292
 293 /**
 294  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 295  *
 296  * The function copies @size bytes from {src->mem + src->offset} to
 297  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 298  * move and different for a BO to BO copy.
 299  *
 300  * @f: Returns the last fence if multiple jobs are submitted.
 301  */
 302 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 303                                struct amdgpu_copy_mem *src,
 304                                struct amdgpu_copy_mem *dst,
 305                                uint64_t size,
 306                                struct reservation_object *resv,
 307                                struct dma_fence **f)
 308 {
 309         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 310         struct drm_mm_node *src_mm, *dst_mm;
 311         uint64_t src_node_start, dst_node_start, src_node_size,
 312                  dst_node_size, src_page_offset, dst_page_offset;
 313         struct dma_fence *fence = NULL;
 314         int r = 0;
 315         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 316                                         AMDGPU_GPU_PAGE_SIZE);
 317
 318         if (!adev->mman.buffer_funcs_enabled) {
 319                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 320                 return -EINVAL;
 321         }
 322
 323         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 324         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 325                                              src->offset;
 326         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 327         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 328
 329         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 330         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 331                                              dst->offset;
 332         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 333         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 334
 335         mutex_lock(&adev->mman.gtt_window_lock);
 336
 337         while (size) {
 338                 unsigned long cur_size;
 339                 uint64_t from = src_node_start, to = dst_node_start;
 340                 struct dma_fence *next;
 341
 342                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 343                  * begins at an offset, then adjust the size accordingly
 344                  */
 345                 cur_size = min3(min(src_node_size, dst_node_size), size,
 346                                 GTT_MAX_BYTES);
 347                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 348                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 349                         cur_size -= max(src_page_offset, dst_page_offset);
 350
 351                 /* Map only what needs to be accessed. Map src to window 0 and
 352                  * dst to window 1
 353                  */
 354                 if (src->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 355                         r = amdgpu_map_buffer(src->bo, src->mem,
 356                                         PFN_UP(cur_size + src_page_offset),
 357                                         src_node_start, 0, ring,
 358                                         &from);
 359                         if (r)
 360                                 goto error;
 361                         /* Adjust the offset because amdgpu_map_buffer returns
 362                          * start of mapped page
 363                          */
 364                         from += src_page_offset;
 365                 }
 366
 367                 if (dst->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 368                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 369                                         PFN_UP(cur_size + dst_page_offset),
 370                                         dst_node_start, 1, ring,
 371                                         &to);
 372                         if (r)
 373                                 goto error;
 374                         to += dst_page_offset;
 375                 }
 376
 377                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 378                                        resv, &next, false, true);
 379                 if (r)
 380                         goto error;
 381
 382                 dma_fence_put(fence);
 383                 fence = next;
 384
 385                 size -= cur_size;
 386                 if (!size)
 387                         break;
 388
 389                 src_node_size -= cur_size;
 390                 if (!src_node_size) {
 391                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 392                                                              src->mem);
 393                         src_node_size = (src_mm->size << PAGE_SHIFT);
 394                 } else {
 395                         src_node_start += cur_size;
 396                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 397                 }
 398                 dst_node_size -= cur_size;
 399                 if (!dst_node_size) {
 400                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 401                                                              dst->mem);
 402                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 403                 } else {
 404                         dst_node_start += cur_size;
 405                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 406                 }
 407         }
 408 error:
 409         mutex_unlock(&adev->mman.gtt_window_lock);
 410         if (f)
 411                 *f = dma_fence_get(fence);
 412         dma_fence_put(fence);
 413         return r;
 414 }
 415
 416 /**
 417  * amdgpu_move_blit - Copy an entire buffer to another buffer
 418  *
 419  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 420  * help move buffers to and from VRAM.
 421  */
 422 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 423                             bool evict, bool no_wait_gpu,
 424                             struct ttm_mem_reg *new_mem,
 425                             struct ttm_mem_reg *old_mem)
 426 {
 427         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 428         struct amdgpu_copy_mem src, dst;
 429         struct dma_fence *fence = NULL;
 430         int r;
 431
 432         src.bo = bo;
 433         dst.bo = bo;
 434         src.mem = old_mem;
 435         dst.mem = new_mem;
 436         src.offset = 0;
 437         dst.offset = 0;
 438
 439         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 440                                        new_mem->num_pages << PAGE_SHIFT,
 441                                        bo->resv, &fence);
 442         if (r)
 443                 goto error;
 444
 445         /* Always block for VM page tables before committing the new location */
 446         if (bo->type == ttm_bo_type_kernel)
 447                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 448         else
 449                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 450         dma_fence_put(fence);
 451         return r;
 452
 453 error:
 454         if (fence)
 455                 dma_fence_wait(fence, false);
 456         dma_fence_put(fence);
 457         return r;
 458 }
 459
 460 /**
 461  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 462  *
 463  * Called by amdgpu_bo_move().
 464  */
 465 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 466                                 struct ttm_operation_ctx *ctx,
 467                                 struct ttm_mem_reg *new_mem)
 468 {
 469         struct amdgpu_device *adev;
 470         struct ttm_mem_reg *old_mem = &bo->mem;
 471         struct ttm_mem_reg tmp_mem;
 472         struct ttm_place placements;
 473         struct ttm_placement placement;
 474         int r;
 475
 476         adev = amdgpu_ttm_adev(bo->bdev);
 477
 478         /* create space/pages for new_mem in GTT space */
 479         tmp_mem = *new_mem;
 480         tmp_mem.mm_node = NULL;
 481         placement.num_placement = 1;
 482         placement.placement = &placements;
 483         placement.num_busy_placement = 1;
 484         placement.busy_placement = &placements;
 485         placements.fpfn = 0;
 486         placements.lpfn = 0;
 487         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 488         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 489         if (unlikely(r)) {
 490                 return r;
 491         }
 492
 493         /* set caching flags */
 494         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 495         if (unlikely(r)) {
 496                 goto out_cleanup;
 497         }
 498
 499         /* Bind the memory to the GTT space */
 500         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 501         if (unlikely(r)) {
 502                 goto out_cleanup;
 503         }
 504
 505         /* blit VRAM to GTT */
 506         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 507         if (unlikely(r)) {
 508                 goto out_cleanup;
 509         }
 510
 511         /* move BO (in tmp_mem) to new_mem */
 512         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 513 out_cleanup:
 514         ttm_bo_mem_put(bo, &tmp_mem);
 515         return r;
 516 }
 517
 518 /**
 519  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 520  *
 521  * Called by amdgpu_bo_move().
 522  */
 523 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 524                                 struct ttm_operation_ctx *ctx,
 525                                 struct ttm_mem_reg *new_mem)
 526 {
 527         struct amdgpu_device *adev;
 528         struct ttm_mem_reg *old_mem = &bo->mem;
 529         struct ttm_mem_reg tmp_mem;
 530         struct ttm_placement placement;
 531         struct ttm_place placements;
 532         int r;
 533
 534         adev = amdgpu_ttm_adev(bo->bdev);
 535
 536         /* make space in GTT for old_mem buffer */
 537         tmp_mem = *new_mem;
 538         tmp_mem.mm_node = NULL;
 539         placement.num_placement = 1;
 540         placement.placement = &placements;
 541         placement.num_busy_placement = 1;
 542         placement.busy_placement = &placements;
 543         placements.fpfn = 0;
 544         placements.lpfn = 0;
 545         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 546         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 547         if (unlikely(r)) {
 548                 return r;
 549         }
 550
 551         /* move/bind old memory to GTT space */
 552         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 553         if (unlikely(r)) {
 554                 goto out_cleanup;
 555         }
 556
 557         /* copy to VRAM */
 558         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 559         if (unlikely(r)) {
 560                 goto out_cleanup;
 561         }
 562 out_cleanup:
 563         ttm_bo_mem_put(bo, &tmp_mem);
 564         return r;
 565 }
 566
 567 /**
 568  * amdgpu_bo_move - Move a buffer object to a new memory location
 569  *
 570  * Called by ttm_bo_handle_move_mem()
 571  */
 572 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 573                           struct ttm_operation_ctx *ctx,
 574                           struct ttm_mem_reg *new_mem)
 575 {
 576         struct amdgpu_device *adev;
 577         struct amdgpu_bo *abo;
 578         struct ttm_mem_reg *old_mem = &bo->mem;
 579         int r;
 580
 581         /* Can't move a pinned BO */
 582         abo = ttm_to_amdgpu_bo(bo);
 583         if (WARN_ON_ONCE(abo->pin_count > 0))
 584                 return -EINVAL;
 585
 586         adev = amdgpu_ttm_adev(bo->bdev);
 587
 588         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 589                 amdgpu_move_null(bo, new_mem);
 590                 return 0;
 591         }
 592         if ((old_mem->mem_type == TTM_PL_TT &&
 593              new_mem->mem_type == TTM_PL_SYSTEM) ||
 594             (old_mem->mem_type == TTM_PL_SYSTEM &&
 595              new_mem->mem_type == TTM_PL_TT)) {
 596                 /* bind is enough */
 597                 amdgpu_move_null(bo, new_mem);
 598                 return 0;
 599         }
 600         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 601             old_mem->mem_type == AMDGPU_PL_GWS ||
 602             old_mem->mem_type == AMDGPU_PL_OA ||
 603             new_mem->mem_type == AMDGPU_PL_GDS ||
 604             new_mem->mem_type == AMDGPU_PL_GWS ||
 605             new_mem->mem_type == AMDGPU_PL_OA) {
 606                 /* Nothing to save here */
 607                 amdgpu_move_null(bo, new_mem);
 608                 return 0;
 609         }
 610
 611         if (!adev->mman.buffer_funcs_enabled)
 612                 goto memcpy;
 613
 614         if (old_mem->mem_type == TTM_PL_VRAM &&
 615             new_mem->mem_type == TTM_PL_SYSTEM) {
 616                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 617         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 618                    new_mem->mem_type == TTM_PL_VRAM) {
 619                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 620         } else {
 621                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 622                                      new_mem, old_mem);
 623         }
 624
 625         if (r) {
 626 memcpy:
 627                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 628                 if (r) {
 629                         return r;
 630                 }
 631         }
 632
 633         if (bo->type == ttm_bo_type_device &&
 634             new_mem->mem_type == TTM_PL_VRAM &&
 635             old_mem->mem_type != TTM_PL_VRAM) {
 636                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 637                  * accesses the BO after it's moved.
 638                  */
 639                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 640         }
 641
 642         /* update statistics */
 643         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 644         return 0;
 645 }
 646
 647 /**
 648  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 649  *
 650  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 651  */
 652 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 653 {
 654         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 655         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 656         struct drm_mm_node *mm_node = mem->mm_node;
 657
 658         mem->bus.addr = NULL;
 659         mem->bus.offset = 0;
 660         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 661         mem->bus.base = 0;
 662         mem->bus.is_iomem = false;
 663         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 664                 return -EINVAL;
 665         switch (mem->mem_type) {
 666         case TTM_PL_SYSTEM:
 667                 /* system memory */
 668                 return 0;
 669         case TTM_PL_TT:
 670                 break;
 671         case TTM_PL_VRAM:
 672                 mem->bus.offset = mem->start << PAGE_SHIFT;
 673                 /* check if it's visible */
 674                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 675                         return -EINVAL;
 676                 /* Only physically contiguous buffers apply. In a contiguous
 677                  * buffer, size of the first mm_node would match the number of
 678                  * pages in ttm_mem_reg.
 679                  */
 680                 if (adev->mman.aper_base_kaddr &&
 681                     (mm_node->size == mem->num_pages))
 682                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 683                                         mem->bus.offset;
 684
 685                 mem->bus.base = adev->gmc.aper_base;
 686                 mem->bus.is_iomem = true;
 687                 break;
 688         default:
 689                 return -EINVAL;
 690         }
 691         return 0;
 692 }
 693
 694 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 695 {
 696 }
 697
 698 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 699                                            unsigned long page_offset)
 700 {
 701         struct drm_mm_node *mm;
 702         unsigned long offset = (page_offset << PAGE_SHIFT);
 703
 704         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 705         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 706                 (offset >> PAGE_SHIFT);
 707 }
 708
 709 /*
 710  * TTM backend functions.
 711  */
 712 struct amdgpu_ttm_tt {
 713         struct ttm_dma_tt       ttm;
 714         u64                     offset;
 715         uint64_t                userptr;
 716         struct task_struct      *usertask;
 717         uint32_t                userflags;
 718 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 719         struct hmm_range        *range;
 720 #endif
 721 };
 722
 723 /**
 724  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 725  * memory and start HMM tracking CPU page table update
 726  *
 727  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 728  * once afterwards to stop HMM tracking
 729  */
 730 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 731
 732 #define MAX_RETRY_HMM_RANGE_FAULT       16
 733
 734 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 735 {
 736         struct hmm_mirror *mirror = bo->mn ? &bo->mn->mirror : NULL;
 737         struct ttm_tt *ttm = bo->tbo.ttm;
 738         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 739         struct mm_struct *mm = gtt->usertask->mm;
 740         unsigned long start = gtt->userptr;
 741         struct vm_area_struct *vma;
 742         struct hmm_range *range;
 743         unsigned long i;
 744         uint64_t *pfns;
 745         int retry = 0;
 746         int r = 0;
 747
 748         if (!mm) /* Happens during process shutdown */
 749                 return -ESRCH;
 750
 751         if (unlikely(!mirror)) {
 752                 DRM_DEBUG_DRIVER("Failed to get hmm_mirror\n");
 753                 r = -EFAULT;
 754                 goto out;
 755         }
 756
 757         vma = find_vma(mm, start);
 758         if (unlikely(!vma || start < vma->vm_start)) {
 759                 r = -EFAULT;
 760                 goto out;
 761         }
 762         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 763                 vma->vm_file)) {
 764                 r = -EPERM;
 765                 goto out;
 766         }
 767
 768         range = kzalloc(sizeof(*range), GFP_KERNEL);
 769         if (unlikely(!range)) {
 770                 r = -ENOMEM;
 771                 goto out;
 772         }
 773
 774         pfns = kvmalloc_array(ttm->num_pages, sizeof(*pfns), GFP_KERNEL);
 775         if (unlikely(!pfns)) {
 776                 r = -ENOMEM;
 777                 goto out_free_ranges;
 778         }
 779
 780         amdgpu_hmm_init_range(range);
 781         range->default_flags = range->flags[HMM_PFN_VALID];
 782         range->default_flags |= amdgpu_ttm_tt_is_readonly(ttm) ?
 783                                 0 : range->flags[HMM_PFN_WRITE];
 784         range->pfn_flags_mask = 0;
 785         range->pfns = pfns;
 786         hmm_range_register(range, mm, start,
 787                            start + ttm->num_pages * PAGE_SIZE, PAGE_SHIFT);
 788
 789 retry:
 790         /*
 791          * Just wait for range to be valid, safe to ignore return value as we
 792          * will use the return value of hmm_range_fault() below under the
 793          * mmap_sem to ascertain the validity of the range.
 794          */
 795         hmm_range_wait_until_valid(range, HMM_RANGE_DEFAULT_TIMEOUT);
 796
 797         down_read(&mm->mmap_sem);
 798
 799         r = hmm_range_fault(range, true);
 800         if (unlikely(r < 0)) {
 801                 if (likely(r == -EAGAIN)) {
 802                         /*
 803                          * return -EAGAIN, mmap_sem is dropped
 804                          */
 805                         if (retry++ < MAX_RETRY_HMM_RANGE_FAULT)
 806                                 goto retry;
 807                         else
 808                                 pr_err("Retry hmm fault too many times\n");
 809                 }
 810
 811                 goto out_up_read;
 812         }
 813
 814         up_read(&mm->mmap_sem);
 815
 816         for (i = 0; i < ttm->num_pages; i++) {
 817                 pages[i] = hmm_device_entry_to_page(range, pfns[i]);
 818                 if (unlikely(!pages[i])) {
 819                         pr_err("Page fault failed for pfn[%lu] = 0x%llx\n",
 820                                i, pfns[i]);
 821                         r = -ENOMEM;
 822
 823                         goto out_free_pfns;
 824                 }
 825         }
 826
 827         gtt->range = range;
 828
 829         return 0;
 830
 831 out_up_read:
 832         if (likely(r != -EAGAIN))
 833                 up_read(&mm->mmap_sem);
 834 out_free_pfns:
 835         hmm_range_unregister(range);
 836         kvfree(pfns);
 837 out_free_ranges:
 838         kfree(range);
 839 out:
 840         return r;
 841 }
 842
 843 /**
 844  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 845  * Check if the pages backing this ttm range have been invalidated
 846  *
 847  * Returns: true if pages are still valid
 848  */
 849 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 850 {
 851         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 852         bool r = false;
 853
 854         if (!gtt || !gtt->userptr)
 855                 return false;
 856
 857         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
 858                 gtt->userptr, ttm->num_pages);
 859
 860         WARN_ONCE(!gtt->range || !gtt->range->pfns,
 861                 "No user pages to check\n");
 862
 863         if (gtt->range) {
 864                 r = hmm_range_valid(gtt->range);
 865                 hmm_range_unregister(gtt->range);
 866
 867                 kvfree(gtt->range->pfns);
 868                 kfree(gtt->range);
 869                 gtt->range = NULL;
 870         }
 871
 872         return r;
 873 }
 874 #endif
 875
 876 /**
 877  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 878  *
 879  * Called by amdgpu_cs_list_validate(). This creates the page list
 880  * that backs user memory and will ultimately be mapped into the device
 881  * address space.
 882  */
 883 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 884 {
 885         unsigned long i;
 886
 887         for (i = 0; i < ttm->num_pages; ++i)
 888                 ttm->pages[i] = pages ? pages[i] : NULL;
 889 }
 890
 891 /**
 892  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
 893  *
 894  * Called by amdgpu_ttm_backend_bind()
 895  **/
 896 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 897 {
 898         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 899         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 900         unsigned nents;
 901         int r;
 902
 903         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 904         enum dma_data_direction direction = write ?
 905                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 906
 907         /* Allocate an SG array and squash pages into it */
 908         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 909                                       ttm->num_pages << PAGE_SHIFT,
 910                                       GFP_KERNEL);
 911         if (r)
 912                 goto release_sg;
 913
 914         /* Map SG to device */
 915         r = -ENOMEM;
 916         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 917         if (nents != ttm->sg->nents)
 918                 goto release_sg;
 919
 920         /* convert SG to linear array of pages and dma addresses */
 921         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 922                                          gtt->ttm.dma_address, ttm->num_pages);
 923
 924         return 0;
 925
 926 release_sg:
 927         kfree(ttm->sg);
 928         return r;
 929 }
 930
 931 /**
 932  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 933  */
 934 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 935 {
 936         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 937         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 938
 939         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 940         enum dma_data_direction direction = write ?
 941                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 942
 943         /* double check that we don't free the table twice */
 944         if (!ttm->sg->sgl)
 945                 return;
 946
 947         /* unmap the pages mapped to the device */
 948         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 949
 950         sg_free_table(ttm->sg);
 951
 952 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 953         if (gtt->range &&
 954             ttm->pages[0] == hmm_device_entry_to_page(gtt->range,
 955                                                       gtt->range->pfns[0]))
 956                 WARN_ONCE(1, "Missing get_user_page_done\n");
 957 #endif
 958 }
 959
 960 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 961                                 struct ttm_buffer_object *tbo,
 962                                 uint64_t flags)
 963 {
 964         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 965         struct ttm_tt *ttm = tbo->ttm;
 966         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 967         int r;
 968
 969         if (abo->flags & AMDGPU_GEM_CREATE_MQD_GFX9) {
 970                 uint64_t page_idx = 1;
 971
 972                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 973                                 ttm->pages, gtt->ttm.dma_address, flags);
 974                 if (r)
 975                         goto gart_bind_fail;
 976
 977                 /* Patch mtype of the second part BO */
 978                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
 979                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
 980
 981                 r = amdgpu_gart_bind(adev,
 982                                 gtt->offset + (page_idx << PAGE_SHIFT),
 983                                 ttm->num_pages - page_idx,
 984                                 &ttm->pages[page_idx],
 985                                 &(gtt->ttm.dma_address[page_idx]), flags);
 986         } else {
 987                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 988                                      ttm->pages, gtt->ttm.dma_address, flags);
 989         }
 990
 991 gart_bind_fail:
 992         if (r)
 993                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 994                           ttm->num_pages, gtt->offset);
 995
 996         return r;
 997 }
 998
 999 /**
1000  * amdgpu_ttm_backend_bind - Bind GTT memory
1001  *
1002  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1003  * This handles binding GTT memory to the device address space.
1004  */
1005 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1006                                    struct ttm_mem_reg *bo_mem)
1007 {
1008         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1009         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1010         uint64_t flags;
1011         int r = 0;
1012
1013         if (gtt->userptr) {
1014                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1015                 if (r) {
1016                         DRM_ERROR("failed to pin userptr\n");
1017                         return r;
1018                 }
1019         }
1020         if (!ttm->num_pages) {
1021                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1022                      ttm->num_pages, bo_mem, ttm);
1023         }
1024
1025         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1026             bo_mem->mem_type == AMDGPU_PL_GWS ||
1027             bo_mem->mem_type == AMDGPU_PL_OA)
1028                 return -EINVAL;
1029
1030         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1031                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1032                 return 0;
1033         }
1034
1035         /* compute PTE flags relevant to this BO memory */
1036         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1037
1038         /* bind pages into GART page tables */
1039         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1040         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1041                 ttm->pages, gtt->ttm.dma_address, flags);
1042
1043         if (r)
1044                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1045                           ttm->num_pages, gtt->offset);
1046         return r;
1047 }
1048
1049 /**
1050  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1051  */
1052 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1053 {
1054         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1055         struct ttm_operation_ctx ctx = { false, false };
1056         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1057         struct ttm_mem_reg tmp;
1058         struct ttm_placement placement;
1059         struct ttm_place placements;
1060         uint64_t addr, flags;
1061         int r;
1062
1063         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1064                 return 0;
1065
1066         addr = amdgpu_gmc_agp_addr(bo);
1067         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1068                 bo->mem.start = addr >> PAGE_SHIFT;
1069         } else {
1070
1071                 /* allocate GART space */
1072                 tmp = bo->mem;
1073                 tmp.mm_node = NULL;
1074                 placement.num_placement = 1;
1075                 placement.placement = &placements;
1076                 placement.num_busy_placement = 1;
1077                 placement.busy_placement = &placements;
1078                 placements.fpfn = 0;
1079                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1080                 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1081                         TTM_PL_FLAG_TT;
1082
1083                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1084                 if (unlikely(r))
1085                         return r;
1086
1087                 /* compute PTE flags for this buffer object */
1088                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1089
1090                 /* Bind pages */
1091                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1092                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1093                 if (unlikely(r)) {
1094                         ttm_bo_mem_put(bo, &tmp);
1095                         return r;
1096                 }
1097
1098                 ttm_bo_mem_put(bo, &bo->mem);
1099                 bo->mem = tmp;
1100         }
1101
1102         bo->offset = (bo->mem.start << PAGE_SHIFT) +
1103                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
1104
1105         return 0;
1106 }
1107
1108 /**
1109  * amdgpu_ttm_recover_gart - Rebind GTT pages
1110  *
1111  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1112  * rebind GTT pages during a GPU reset.
1113  */
1114 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1115 {
1116         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1117         uint64_t flags;
1118         int r;
1119
1120         if (!tbo->ttm)
1121                 return 0;
1122
1123         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1124         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1125
1126         return r;
1127 }
1128
1129 /**
1130  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1131  *
1132  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1133  * ttm_tt_destroy().
1134  */
1135 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1136 {
1137         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1138         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1139         int r;
1140
1141         /* if the pages have userptr pinning then clear that first */
1142         if (gtt->userptr)
1143                 amdgpu_ttm_tt_unpin_userptr(ttm);
1144
1145         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1146                 return 0;
1147
1148         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1149         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1150         if (r)
1151                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1152                           gtt->ttm.ttm.num_pages, gtt->offset);
1153         return r;
1154 }
1155
1156 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1157 {
1158         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1159
1160         if (gtt->usertask)
1161                 put_task_struct(gtt->usertask);
1162
1163         ttm_dma_tt_fini(&gtt->ttm);
1164         kfree(gtt);
1165 }
1166
1167 static struct ttm_backend_func amdgpu_backend_func = {
1168         .bind = &amdgpu_ttm_backend_bind,
1169         .unbind = &amdgpu_ttm_backend_unbind,
1170         .destroy = &amdgpu_ttm_backend_destroy,
1171 };
1172
1173 /**
1174  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1175  *
1176  * @bo: The buffer object to create a GTT ttm_tt object around
1177  *
1178  * Called by ttm_tt_create().
1179  */
1180 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1181                                            uint32_t page_flags)
1182 {
1183         struct amdgpu_device *adev;
1184         struct amdgpu_ttm_tt *gtt;
1185
1186         adev = amdgpu_ttm_adev(bo->bdev);
1187
1188         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1189         if (gtt == NULL) {
1190                 return NULL;
1191         }
1192         gtt->ttm.ttm.func = &amdgpu_backend_func;
1193
1194         /* allocate space for the uninitialized page entries */
1195         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1196                 kfree(gtt);
1197                 return NULL;
1198         }
1199         return &gtt->ttm.ttm;
1200 }
1201
1202 /**
1203  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1204  *
1205  * Map the pages of a ttm_tt object to an address space visible
1206  * to the underlying device.
1207  */
1208 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1209                         struct ttm_operation_ctx *ctx)
1210 {
1211         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1212         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1213         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1214
1215         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1216         if (gtt && gtt->userptr) {
1217                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1218                 if (!ttm->sg)
1219                         return -ENOMEM;
1220
1221                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1222                 ttm->state = tt_unbound;
1223                 return 0;
1224         }
1225
1226         if (slave && ttm->sg) {
1227                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1228                                                  gtt->ttm.dma_address,
1229                                                  ttm->num_pages);
1230                 ttm->state = tt_unbound;
1231                 return 0;
1232         }
1233
1234 #ifdef CONFIG_SWIOTLB
1235         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1236                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1237         }
1238 #endif
1239
1240         /* fall back to generic helper to populate the page array
1241          * and map them to the device */
1242         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1243 }
1244
1245 /**
1246  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1247  *
1248  * Unmaps pages of a ttm_tt object from the device address space and
1249  * unpopulates the page array backing it.
1250  */
1251 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1252 {
1253         struct amdgpu_device *adev;
1254         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1255         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1256
1257         if (gtt && gtt->userptr) {
1258                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1259                 kfree(ttm->sg);
1260                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1261                 return;
1262         }
1263
1264         if (slave)
1265                 return;
1266
1267         adev = amdgpu_ttm_adev(ttm->bdev);
1268
1269 #ifdef CONFIG_SWIOTLB
1270         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1271                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1272                 return;
1273         }
1274 #endif
1275
1276         /* fall back to generic helper to unmap and unpopulate array */
1277         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1278 }
1279
1280 /**
1281  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1282  * task
1283  *
1284  * @ttm: The ttm_tt object to bind this userptr object to
1285  * @addr:  The address in the current tasks VM space to use
1286  * @flags: Requirements of userptr object.
1287  *
1288  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1289  * to current task
1290  */
1291 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1292                               uint32_t flags)
1293 {
1294         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1295
1296         if (gtt == NULL)
1297                 return -EINVAL;
1298
1299         gtt->userptr = addr;
1300         gtt->userflags = flags;
1301
1302         if (gtt->usertask)
1303                 put_task_struct(gtt->usertask);
1304         gtt->usertask = current->group_leader;
1305         get_task_struct(gtt->usertask);
1306
1307         return 0;
1308 }
1309
1310 /**
1311  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1312  */
1313 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1314 {
1315         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1316
1317         if (gtt == NULL)
1318                 return NULL;
1319
1320         if (gtt->usertask == NULL)
1321                 return NULL;
1322
1323         return gtt->usertask->mm;
1324 }
1325
1326 /**
1327  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1328  * address range for the current task.
1329  *
1330  */
1331 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1332                                   unsigned long end)
1333 {
1334         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1335         unsigned long size;
1336
1337         if (gtt == NULL || !gtt->userptr)
1338                 return false;
1339
1340         /* Return false if no part of the ttm_tt object lies within
1341          * the range
1342          */
1343         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1344         if (gtt->userptr > end || gtt->userptr + size <= start)
1345                 return false;
1346
1347         return true;
1348 }
1349
1350 /**
1351  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1352  */
1353 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1354 {
1355         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1356
1357         if (gtt == NULL || !gtt->userptr)
1358                 return false;
1359
1360         return true;
1361 }
1362
1363 /**
1364  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1365  */
1366 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1367 {
1368         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1369
1370         if (gtt == NULL)
1371                 return false;
1372
1373         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1374 }
1375
1376 /**
1377  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1378  *
1379  * @ttm: The ttm_tt object to compute the flags for
1380  * @mem: The memory registry backing this ttm_tt object
1381  *
1382  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1383  */
1384 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1385 {
1386         uint64_t flags = 0;
1387
1388         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1389                 flags |= AMDGPU_PTE_VALID;
1390
1391         if (mem && mem->mem_type == TTM_PL_TT) {
1392                 flags |= AMDGPU_PTE_SYSTEM;
1393
1394                 if (ttm->caching_state == tt_cached)
1395                         flags |= AMDGPU_PTE_SNOOPED;
1396         }
1397
1398         return flags;
1399 }
1400
1401 /**
1402  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1403  *
1404  * @ttm: The ttm_tt object to compute the flags for
1405  * @mem: The memory registry backing this ttm_tt object
1406
1407  * Figure out the flags to use for a VM PTE (Page Table Entry).
1408  */
1409 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1410                                  struct ttm_mem_reg *mem)
1411 {
1412         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1413
1414         flags |= adev->gart.gart_pte_flags;
1415         flags |= AMDGPU_PTE_READABLE;
1416
1417         if (!amdgpu_ttm_tt_is_readonly(ttm))
1418                 flags |= AMDGPU_PTE_WRITEABLE;
1419
1420         return flags;
1421 }
1422
1423 /**
1424  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1425  * object.
1426  *
1427  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1428  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1429  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1430  * used to clean out a memory space.
1431  */
1432 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1433                                             const struct ttm_place *place)
1434 {
1435         unsigned long num_pages = bo->mem.num_pages;
1436         struct drm_mm_node *node = bo->mem.mm_node;
1437         struct reservation_object_list *flist;
1438         struct dma_fence *f;
1439         int i;
1440
1441         /* Don't evict VM page tables while they are busy, otherwise we can't
1442          * cleanly handle page faults.
1443          */
1444         if (bo->type == ttm_bo_type_kernel &&
1445             !reservation_object_test_signaled_rcu(bo->resv, true))
1446                 return false;
1447
1448         /* If bo is a KFD BO, check if the bo belongs to the current process.
1449          * If true, then return false as any KFD process needs all its BOs to
1450          * be resident to run successfully
1451          */
1452         flist = reservation_object_get_list(bo->resv);
1453         if (flist) {
1454                 for (i = 0; i < flist->shared_count; ++i) {
1455                         f = rcu_dereference_protected(flist->shared[i],
1456                                 reservation_object_held(bo->resv));
1457                         if (amdkfd_fence_check_mm(f, current->mm))
1458                                 return false;
1459                 }
1460         }
1461
1462         switch (bo->mem.mem_type) {
1463         case TTM_PL_TT:
1464                 return true;
1465
1466         case TTM_PL_VRAM:
1467                 /* Check each drm MM node individually */
1468                 while (num_pages) {
1469                         if (place->fpfn < (node->start + node->size) &&
1470                             !(place->lpfn && place->lpfn <= node->start))
1471                                 return true;
1472
1473                         num_pages -= node->size;
1474                         ++node;
1475                 }
1476                 return false;
1477
1478         default:
1479                 break;
1480         }
1481
1482         return ttm_bo_eviction_valuable(bo, place);
1483 }
1484
1485 /**
1486  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1487  *
1488  * @bo:  The buffer object to read/write
1489  * @offset:  Offset into buffer object
1490  * @buf:  Secondary buffer to write/read from
1491  * @len: Length in bytes of access
1492  * @write:  true if writing
1493  *
1494  * This is used to access VRAM that backs a buffer object via MMIO
1495  * access for debugging purposes.
1496  */
1497 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1498                                     unsigned long offset,
1499                                     void *buf, int len, int write)
1500 {
1501         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1502         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1503         struct drm_mm_node *nodes;
1504         uint32_t value = 0;
1505         int ret = 0;
1506         uint64_t pos;
1507         unsigned long flags;
1508
1509         if (bo->mem.mem_type != TTM_PL_VRAM)
1510                 return -EIO;
1511
1512         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1513         pos = (nodes->start << PAGE_SHIFT) + offset;
1514
1515         while (len && pos < adev->gmc.mc_vram_size) {
1516                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1517                 uint32_t bytes = 4 - (pos & 3);
1518                 uint32_t shift = (pos & 3) * 8;
1519                 uint32_t mask = 0xffffffff << shift;
1520
1521                 if (len < bytes) {
1522                         mask &= 0xffffffff >> (bytes - len) * 8;
1523                         bytes = len;
1524                 }
1525
1526                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1527                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1528                 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1529                 if (!write || mask != 0xffffffff)
1530                         value = RREG32_NO_KIQ(mmMM_DATA);
1531                 if (write) {
1532                         value &= ~mask;
1533                         value |= (*(uint32_t *)buf << shift) & mask;
1534                         WREG32_NO_KIQ(mmMM_DATA, value);
1535                 }
1536                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1537                 if (!write) {
1538                         value = (value & mask) >> shift;
1539                         memcpy(buf, &value, bytes);
1540                 }
1541
1542                 ret += bytes;
1543                 buf = (uint8_t *)buf + bytes;
1544                 pos += bytes;
1545                 len -= bytes;
1546                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1547                         ++nodes;
1548                         pos = (nodes->start << PAGE_SHIFT);
1549                 }
1550         }
1551
1552         return ret;
1553 }
1554
1555 static struct ttm_bo_driver amdgpu_bo_driver = {
1556         .ttm_tt_create = &amdgpu_ttm_tt_create,
1557         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1558         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1559         .invalidate_caches = &amdgpu_invalidate_caches,
1560         .init_mem_type = &amdgpu_init_mem_type,
1561         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1562         .evict_flags = &amdgpu_evict_flags,
1563         .move = &amdgpu_bo_move,
1564         .verify_access = &amdgpu_verify_access,
1565         .move_notify = &amdgpu_bo_move_notify,
1566         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1567         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1568         .io_mem_free = &amdgpu_ttm_io_mem_free,
1569         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1570         .access_memory = &amdgpu_ttm_access_memory,
1571         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1572 };
1573
1574 /*
1575  * Firmware Reservation functions
1576  */
1577 /**
1578  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1579  *
1580  * @adev: amdgpu_device pointer
1581  *
1582  * free fw reserved vram if it has been reserved.
1583  */
1584 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1585 {
1586         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1587                 NULL, &adev->fw_vram_usage.va);
1588 }
1589
1590 /**
1591  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1592  *
1593  * @adev: amdgpu_device pointer
1594  *
1595  * create bo vram reservation from fw.
1596  */
1597 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1598 {
1599         struct ttm_operation_ctx ctx = { false, false };
1600         struct amdgpu_bo_param bp;
1601         int r = 0;
1602         int i;
1603         u64 vram_size = adev->gmc.visible_vram_size;
1604         u64 offset = adev->fw_vram_usage.start_offset;
1605         u64 size = adev->fw_vram_usage.size;
1606         struct amdgpu_bo *bo;
1607
1608         memset(&bp, 0, sizeof(bp));
1609         bp.size = adev->fw_vram_usage.size;
1610         bp.byte_align = PAGE_SIZE;
1611         bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
1612         bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1613                 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1614         bp.type = ttm_bo_type_kernel;
1615         bp.resv = NULL;
1616         adev->fw_vram_usage.va = NULL;
1617         adev->fw_vram_usage.reserved_bo = NULL;
1618
1619         if (adev->fw_vram_usage.size > 0 &&
1620                 adev->fw_vram_usage.size <= vram_size) {
1621
1622                 r = amdgpu_bo_create(adev, &bp,
1623                                      &adev->fw_vram_usage.reserved_bo);
1624                 if (r)
1625                         goto error_create;
1626
1627                 r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
1628                 if (r)
1629                         goto error_reserve;
1630
1631                 /* remove the original mem node and create a new one at the
1632                  * request position
1633                  */
1634                 bo = adev->fw_vram_usage.reserved_bo;
1635                 offset = ALIGN(offset, PAGE_SIZE);
1636                 for (i = 0; i < bo->placement.num_placement; ++i) {
1637                         bo->placements[i].fpfn = offset >> PAGE_SHIFT;
1638                         bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
1639                 }
1640
1641                 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
1642                 r = ttm_bo_mem_space(&bo->tbo, &bo->placement,
1643                                      &bo->tbo.mem, &ctx);
1644                 if (r)
1645                         goto error_pin;
1646
1647                 r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
1648                         AMDGPU_GEM_DOMAIN_VRAM,
1649                         adev->fw_vram_usage.start_offset,
1650                         (adev->fw_vram_usage.start_offset +
1651                         adev->fw_vram_usage.size));
1652                 if (r)
1653                         goto error_pin;
1654                 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
1655                         &adev->fw_vram_usage.va);
1656                 if (r)
1657                         goto error_kmap;
1658
1659                 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1660         }
1661         return r;
1662
1663 error_kmap:
1664         amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
1665 error_pin:
1666         amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1667 error_reserve:
1668         amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
1669 error_create:
1670         adev->fw_vram_usage.va = NULL;
1671         adev->fw_vram_usage.reserved_bo = NULL;
1672         return r;
1673 }
1674 /**
1675  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1676  * gtt/vram related fields.
1677  *
1678  * This initializes all of the memory space pools that the TTM layer
1679  * will need such as the GTT space (system memory mapped to the device),
1680  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1681  * can be mapped per VMID.
1682  */
1683 int amdgpu_ttm_init(struct amdgpu_device *adev)
1684 {
1685         uint64_t gtt_size;
1686         int r;
1687         u64 vis_vram_limit;
1688
1689         mutex_init(&adev->mman.gtt_window_lock);
1690
1691         /* No others user of address space so set it to 0 */
1692         r = ttm_bo_device_init(&adev->mman.bdev,
1693                                &amdgpu_bo_driver,
1694                                adev->ddev->anon_inode->i_mapping,
1695                                adev->need_dma32);
1696         if (r) {
1697                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1698                 return r;
1699         }
1700         adev->mman.initialized = true;
1701
1702         /* We opt to avoid OOM on system pages allocations */
1703         adev->mman.bdev.no_retry = true;
1704
1705         /* Initialize VRAM pool with all of VRAM divided into pages */
1706         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1707                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1708         if (r) {
1709                 DRM_ERROR("Failed initializing VRAM heap.\n");
1710                 return r;
1711         }
1712
1713         /* Reduce size of CPU-visible VRAM if requested */
1714         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1715         if (amdgpu_vis_vram_limit > 0 &&
1716             vis_vram_limit <= adev->gmc.visible_vram_size)
1717                 adev->gmc.visible_vram_size = vis_vram_limit;
1718
1719         /* Change the size here instead of the init above so only lpfn is affected */
1720         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1721 #ifdef CONFIG_64BIT
1722         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1723                                                 adev->gmc.visible_vram_size);
1724 #endif
1725
1726         /*
1727          *The reserved vram for firmware must be pinned to the specified
1728          *place on the VRAM, so reserve it early.
1729          */
1730         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1731         if (r) {
1732                 return r;
1733         }
1734
1735         /* allocate memory as required for VGA
1736          * This is used for VGA emulation and pre-OS scanout buffers to
1737          * avoid display artifacts while transitioning between pre-OS
1738          * and driver.  */
1739         r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1740                                     AMDGPU_GEM_DOMAIN_VRAM,
1741                                     &adev->stolen_vga_memory,
1742                                     NULL, NULL);
1743         if (r)
1744                 return r;
1745         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1746                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1747
1748         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1749          * or whatever the user passed on module init */
1750         if (amdgpu_gtt_size == -1) {
1751                 struct sysinfo si;
1752
1753                 si_meminfo(&si);
1754                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1755                                adev->gmc.mc_vram_size),
1756                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1757         }
1758         else
1759                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1760
1761         /* Initialize GTT memory pool */
1762         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1763         if (r) {
1764                 DRM_ERROR("Failed initializing GTT heap.\n");
1765                 return r;
1766         }
1767         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1768                  (unsigned)(gtt_size / (1024 * 1024)));
1769
1770         /* Initialize various on-chip memory pools */
1771         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1772                            adev->gds.gds_size);
1773         if (r) {
1774                 DRM_ERROR("Failed initializing GDS heap.\n");
1775                 return r;
1776         }
1777
1778         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1779                            adev->gds.gws_size);
1780         if (r) {
1781                 DRM_ERROR("Failed initializing gws heap.\n");
1782                 return r;
1783         }
1784
1785         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1786                            adev->gds.oa_size);
1787         if (r) {
1788                 DRM_ERROR("Failed initializing oa heap.\n");
1789                 return r;
1790         }
1791
1792         /* Register debugfs entries for amdgpu_ttm */
1793         r = amdgpu_ttm_debugfs_init(adev);
1794         if (r) {
1795                 DRM_ERROR("Failed to init debugfs\n");
1796                 return r;
1797         }
1798         return 0;
1799 }
1800
1801 /**
1802  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1803  */
1804 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1805 {
1806         /* return the VGA stolen memory (if any) back to VRAM */
1807         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1808 }
1809
1810 /**
1811  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1812  */
1813 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1814 {
1815         if (!adev->mman.initialized)
1816                 return;
1817
1818         amdgpu_ttm_debugfs_fini(adev);
1819         amdgpu_ttm_fw_reserve_vram_fini(adev);
1820         if (adev->mman.aper_base_kaddr)
1821                 iounmap(adev->mman.aper_base_kaddr);
1822         adev->mman.aper_base_kaddr = NULL;
1823
1824         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1825         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1826         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1827         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1828         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1829         ttm_bo_device_release(&adev->mman.bdev);
1830         adev->mman.initialized = false;
1831         DRM_INFO("amdgpu: ttm finalized\n");
1832 }
1833
1834 /**
1835  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1836  *
1837  * @adev: amdgpu_device pointer
1838  * @enable: true when we can use buffer functions.
1839  *
1840  * Enable/disable use of buffer functions during suspend/resume. This should
1841  * only be called at bootup or when userspace isn't running.
1842  */
1843 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1844 {
1845         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
1846         uint64_t size;
1847         int r;
1848
1849         if (!adev->mman.initialized || adev->in_gpu_reset ||
1850             adev->mman.buffer_funcs_enabled == enable)
1851                 return;
1852
1853         if (enable) {
1854                 struct amdgpu_ring *ring;
1855                 struct drm_sched_rq *rq;
1856
1857                 ring = adev->mman.buffer_funcs_ring;
1858                 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
1859                 r = drm_sched_entity_init(&adev->mman.entity, &rq, 1, NULL);
1860                 if (r) {
1861                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1862                                   r);
1863                         return;
1864                 }
1865         } else {
1866                 drm_sched_entity_destroy(&adev->mman.entity);
1867                 dma_fence_put(man->move);
1868                 man->move = NULL;
1869         }
1870
1871         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1872         if (enable)
1873                 size = adev->gmc.real_vram_size;
1874         else
1875                 size = adev->gmc.visible_vram_size;
1876         man->size = size >> PAGE_SHIFT;
1877         adev->mman.buffer_funcs_enabled = enable;
1878 }
1879
1880 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1881 {
1882         struct drm_file *file_priv = filp->private_data;
1883         struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
1884
1885         if (adev == NULL)
1886                 return -EINVAL;
1887
1888         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1889 }
1890
1891 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1892                              struct ttm_mem_reg *mem, unsigned num_pages,
1893                              uint64_t offset, unsigned window,
1894                              struct amdgpu_ring *ring,
1895                              uint64_t *addr)
1896 {
1897         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1898         struct amdgpu_device *adev = ring->adev;
1899         struct ttm_tt *ttm = bo->ttm;
1900         struct amdgpu_job *job;
1901         unsigned num_dw, num_bytes;
1902         dma_addr_t *dma_address;
1903         struct dma_fence *fence;
1904         uint64_t src_addr, dst_addr;
1905         uint64_t flags;
1906         int r;
1907
1908         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1909                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1910
1911         *addr = adev->gmc.gart_start;
1912         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1913                 AMDGPU_GPU_PAGE_SIZE;
1914
1915         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1916         while (num_dw & 0x7)
1917                 num_dw++;
1918
1919         num_bytes = num_pages * 8;
1920
1921         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1922         if (r)
1923                 return r;
1924
1925         src_addr = num_dw * 4;
1926         src_addr += job->ibs[0].gpu_addr;
1927
1928         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
1929         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1930         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1931                                 dst_addr, num_bytes);
1932
1933         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1934         WARN_ON(job->ibs[0].length_dw > num_dw);
1935
1936         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
1937         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
1938         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
1939                             &job->ibs[0].ptr[num_dw]);
1940         if (r)
1941                 goto error_free;
1942
1943         r = amdgpu_job_submit(job, &adev->mman.entity,
1944                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1945         if (r)
1946                 goto error_free;
1947
1948         dma_fence_put(fence);
1949
1950         return r;
1951
1952 error_free:
1953         amdgpu_job_free(job);
1954         return r;
1955 }
1956
1957 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1958                        uint64_t dst_offset, uint32_t byte_count,
1959                        struct reservation_object *resv,
1960                        struct dma_fence **fence, bool direct_submit,
1961                        bool vm_needs_flush)
1962 {
1963         struct amdgpu_device *adev = ring->adev;
1964         struct amdgpu_job *job;
1965
1966         uint32_t max_bytes;
1967         unsigned num_loops, num_dw;
1968         unsigned i;
1969         int r;
1970
1971         if (direct_submit && !ring->sched.ready) {
1972                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1973                 return -EINVAL;
1974         }
1975
1976         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1977         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1978         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1979
1980         /* for IB padding */
1981         while (num_dw & 0x7)
1982                 num_dw++;
1983
1984         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1985         if (r)
1986                 return r;
1987
1988         if (vm_needs_flush) {
1989                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
1990                 job->vm_needs_flush = true;
1991         }
1992         if (resv) {
1993                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1994                                      AMDGPU_FENCE_OWNER_UNDEFINED,
1995                                      false);
1996                 if (r) {
1997                         DRM_ERROR("sync failed (%d).\n", r);
1998                         goto error_free;
1999                 }
2000         }
2001
2002         for (i = 0; i < num_loops; i++) {
2003                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2004
2005                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2006                                         dst_offset, cur_size_in_bytes);
2007
2008                 src_offset += cur_size_in_bytes;
2009                 dst_offset += cur_size_in_bytes;
2010                 byte_count -= cur_size_in_bytes;
2011         }
2012
2013         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2014         WARN_ON(job->ibs[0].length_dw > num_dw);
2015         if (direct_submit)
2016                 r = amdgpu_job_submit_direct(job, ring, fence);
2017         else
2018                 r = amdgpu_job_submit(job, &adev->mman.entity,
2019                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2020         if (r)
2021                 goto error_free;
2022
2023         return r;
2024
2025 error_free:
2026         amdgpu_job_free(job);
2027         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2028         return r;
2029 }
2030
2031 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2032                        uint32_t src_data,
2033                        struct reservation_object *resv,
2034                        struct dma_fence **fence)
2035 {
2036         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2037         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2038         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2039
2040         struct drm_mm_node *mm_node;
2041         unsigned long num_pages;
2042         unsigned int num_loops, num_dw;
2043
2044         struct amdgpu_job *job;
2045         int r;
2046
2047         if (!adev->mman.buffer_funcs_enabled) {
2048                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2049                 return -EINVAL;
2050         }
2051
2052         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2053                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2054                 if (r)
2055                         return r;
2056         }
2057
2058         num_pages = bo->tbo.num_pages;
2059         mm_node = bo->tbo.mem.mm_node;
2060         num_loops = 0;
2061         while (num_pages) {
2062                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
2063
2064                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
2065                 num_pages -= mm_node->size;
2066                 ++mm_node;
2067         }
2068         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2069
2070         /* for IB padding */
2071         num_dw += 64;
2072
2073         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2074         if (r)
2075                 return r;
2076
2077         if (resv) {
2078                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2079                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
2080                 if (r) {
2081                         DRM_ERROR("sync failed (%d).\n", r);
2082                         goto error_free;
2083                 }
2084         }
2085
2086         num_pages = bo->tbo.num_pages;
2087         mm_node = bo->tbo.mem.mm_node;
2088
2089         while (num_pages) {
2090                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
2091                 uint64_t dst_addr;
2092
2093                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2094                 while (byte_count) {
2095                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2096
2097                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2098                                                 dst_addr, cur_size_in_bytes);
2099
2100                         dst_addr += cur_size_in_bytes;
2101                         byte_count -= cur_size_in_bytes;
2102                 }
2103
2104                 num_pages -= mm_node->size;
2105                 ++mm_node;
2106         }
2107
2108         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2109         WARN_ON(job->ibs[0].length_dw > num_dw);
2110         r = amdgpu_job_submit(job, &adev->mman.entity,
2111                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2112         if (r)
2113                 goto error_free;
2114
2115         return 0;
2116
2117 error_free:
2118         amdgpu_job_free(job);
2119         return r;
2120 }
2121
2122 #if defined(CONFIG_DEBUG_FS)
2123
2124 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2125 {
2126         struct drm_info_node *node = (struct drm_info_node *)m->private;
2127         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2128         struct drm_device *dev = node->minor->dev;
2129         struct amdgpu_device *adev = dev->dev_private;
2130         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2131         struct drm_printer p = drm_seq_file_printer(m);
2132
2133         man->func->debug(man, &p);
2134         return 0;
2135 }
2136
2137 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2138         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2139         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2140         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2141         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2142         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2143         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2144 #ifdef CONFIG_SWIOTLB
2145         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2146 #endif
2147 };
2148
2149 /**
2150  * amdgpu_ttm_vram_read - Linear read access to VRAM
2151  *
2152  * Accesses VRAM via MMIO for debugging purposes.
2153  */
2154 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2155                                     size_t size, loff_t *pos)
2156 {
2157         struct amdgpu_device *adev = file_inode(f)->i_private;
2158         ssize_t result = 0;
2159         int r;
2160
2161         if (size & 0x3 || *pos & 0x3)
2162                 return -EINVAL;
2163
2164         if (*pos >= adev->gmc.mc_vram_size)
2165                 return -ENXIO;
2166
2167         while (size) {
2168                 unsigned long flags;
2169                 uint32_t value;
2170
2171                 if (*pos >= adev->gmc.mc_vram_size)
2172                         return result;
2173
2174                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2175                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2176                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2177                 value = RREG32_NO_KIQ(mmMM_DATA);
2178                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2179
2180                 r = put_user(value, (uint32_t *)buf);
2181                 if (r)
2182                         return r;
2183
2184                 result += 4;
2185                 buf += 4;
2186                 *pos += 4;
2187                 size -= 4;
2188         }
2189
2190         return result;
2191 }
2192
2193 /**
2194  * amdgpu_ttm_vram_write - Linear write access to VRAM
2195  *
2196  * Accesses VRAM via MMIO for debugging purposes.
2197  */
2198 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2199                                     size_t size, loff_t *pos)
2200 {
2201         struct amdgpu_device *adev = file_inode(f)->i_private;
2202         ssize_t result = 0;
2203         int r;
2204
2205         if (size & 0x3 || *pos & 0x3)
2206                 return -EINVAL;
2207
2208         if (*pos >= adev->gmc.mc_vram_size)
2209                 return -ENXIO;
2210
2211         while (size) {
2212                 unsigned long flags;
2213                 uint32_t value;
2214
2215                 if (*pos >= adev->gmc.mc_vram_size)
2216                         return result;
2217
2218                 r = get_user(value, (uint32_t *)buf);
2219                 if (r)
2220                         return r;
2221
2222                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2223                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2224                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2225                 WREG32_NO_KIQ(mmMM_DATA, value);
2226                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2227
2228                 result += 4;
2229                 buf += 4;
2230                 *pos += 4;
2231                 size -= 4;
2232         }
2233
2234         return result;
2235 }
2236
2237 static const struct file_operations amdgpu_ttm_vram_fops = {
2238         .owner = THIS_MODULE,
2239         .read = amdgpu_ttm_vram_read,
2240         .write = amdgpu_ttm_vram_write,
2241         .llseek = default_llseek,
2242 };
2243
2244 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2245
2246 /**
2247  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2248  */
2249 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2250                                    size_t size, loff_t *pos)
2251 {
2252         struct amdgpu_device *adev = file_inode(f)->i_private;
2253         ssize_t result = 0;
2254         int r;
2255
2256         while (size) {
2257                 loff_t p = *pos / PAGE_SIZE;
2258                 unsigned off = *pos & ~PAGE_MASK;
2259                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2260                 struct page *page;
2261                 void *ptr;
2262
2263                 if (p >= adev->gart.num_cpu_pages)
2264                         return result;
2265
2266                 page = adev->gart.pages[p];
2267                 if (page) {
2268                         ptr = kmap(page);
2269                         ptr += off;
2270
2271                         r = copy_to_user(buf, ptr, cur_size);
2272                         kunmap(adev->gart.pages[p]);
2273                 } else
2274                         r = clear_user(buf, cur_size);
2275
2276                 if (r)
2277                         return -EFAULT;
2278
2279                 result += cur_size;
2280                 buf += cur_size;
2281                 *pos += cur_size;
2282                 size -= cur_size;
2283         }
2284
2285         return result;
2286 }
2287
2288 static const struct file_operations amdgpu_ttm_gtt_fops = {
2289         .owner = THIS_MODULE,
2290         .read = amdgpu_ttm_gtt_read,
2291         .llseek = default_llseek
2292 };
2293
2294 #endif
2295
2296 /**
2297  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2298  *
2299  * This function is used to read memory that has been mapped to the
2300  * GPU and the known addresses are not physical addresses but instead
2301  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2302  */
2303 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2304                                  size_t size, loff_t *pos)
2305 {
2306         struct amdgpu_device *adev = file_inode(f)->i_private;
2307         struct iommu_domain *dom;
2308         ssize_t result = 0;
2309         int r;
2310
2311         /* retrieve the IOMMU domain if any for this device */
2312         dom = iommu_get_domain_for_dev(adev->dev);
2313
2314         while (size) {
2315                 phys_addr_t addr = *pos & PAGE_MASK;
2316                 loff_t off = *pos & ~PAGE_MASK;
2317                 size_t bytes = PAGE_SIZE - off;
2318                 unsigned long pfn;
2319                 struct page *p;
2320                 void *ptr;
2321
2322                 bytes = bytes < size ? bytes : size;
2323
2324                 /* Translate the bus address to a physical address.  If
2325                  * the domain is NULL it means there is no IOMMU active
2326                  * and the address translation is the identity
2327                  */
2328                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2329
2330                 pfn = addr >> PAGE_SHIFT;
2331                 if (!pfn_valid(pfn))
2332                         return -EPERM;
2333
2334                 p = pfn_to_page(pfn);
2335                 if (p->mapping != adev->mman.bdev.dev_mapping)
2336                         return -EPERM;
2337
2338                 ptr = kmap(p);
2339                 r = copy_to_user(buf, ptr + off, bytes);
2340                 kunmap(p);
2341                 if (r)
2342                         return -EFAULT;
2343
2344                 size -= bytes;
2345                 *pos += bytes;
2346                 result += bytes;
2347         }
2348
2349         return result;
2350 }
2351
2352 /**
2353  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2354  *
2355  * This function is used to write memory that has been mapped to the
2356  * GPU and the known addresses are not physical addresses but instead
2357  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2358  */
2359 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2360                                  size_t size, loff_t *pos)
2361 {
2362         struct amdgpu_device *adev = file_inode(f)->i_private;
2363         struct iommu_domain *dom;
2364         ssize_t result = 0;
2365         int r;
2366
2367         dom = iommu_get_domain_for_dev(adev->dev);
2368
2369         while (size) {
2370                 phys_addr_t addr = *pos & PAGE_MASK;
2371                 loff_t off = *pos & ~PAGE_MASK;
2372                 size_t bytes = PAGE_SIZE - off;
2373                 unsigned long pfn;
2374                 struct page *p;
2375                 void *ptr;
2376
2377                 bytes = bytes < size ? bytes : size;
2378
2379                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2380
2381                 pfn = addr >> PAGE_SHIFT;
2382                 if (!pfn_valid(pfn))
2383                         return -EPERM;
2384
2385                 p = pfn_to_page(pfn);
2386                 if (p->mapping != adev->mman.bdev.dev_mapping)
2387                         return -EPERM;
2388
2389                 ptr = kmap(p);
2390                 r = copy_from_user(ptr + off, buf, bytes);
2391                 kunmap(p);
2392                 if (r)
2393                         return -EFAULT;
2394
2395                 size -= bytes;
2396                 *pos += bytes;
2397                 result += bytes;
2398         }
2399
2400         return result;
2401 }
2402
2403 static const struct file_operations amdgpu_ttm_iomem_fops = {
2404         .owner = THIS_MODULE,
2405         .read = amdgpu_iomem_read,
2406         .write = amdgpu_iomem_write,
2407         .llseek = default_llseek
2408 };
2409
2410 static const struct {
2411         char *name;
2412         const struct file_operations *fops;
2413         int domain;
2414 } ttm_debugfs_entries[] = {
2415         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2416 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2417         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2418 #endif
2419         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2420 };
2421
2422 #endif
2423
2424 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2425 {
2426 #if defined(CONFIG_DEBUG_FS)
2427         unsigned count;
2428
2429         struct drm_minor *minor = adev->ddev->primary;
2430         struct dentry *ent, *root = minor->debugfs_root;
2431
2432         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2433                 ent = debugfs_create_file(
2434                                 ttm_debugfs_entries[count].name,
2435                                 S_IFREG | S_IRUGO, root,
2436                                 adev,
2437                                 ttm_debugfs_entries[count].fops);
2438                 if (IS_ERR(ent))
2439                         return PTR_ERR(ent);
2440                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2441                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2442                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2443                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2444                 adev->mman.debugfs_entries[count] = ent;
2445         }
2446
2447         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2448
2449 #ifdef CONFIG_SWIOTLB
2450         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2451                 --count;
2452 #endif
2453
2454         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2455 #else
2456         return 0;
2457 #endif
2458 }
2459
2460 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
2461 {
2462 #if defined(CONFIG_DEBUG_FS)
2463         unsigned i;
2464
2465         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
2466                 debugfs_remove(adev->mman.debugfs_entries[i]);
2467 #endif
2468 }