drivers/gpu/drm/amd/amdgpu/soc21.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_psp.h"
  35 #include "amdgpu_smu.h"
  36 #include "atom.h"
  37 #include "amd_pcie.h"
  38
  39 #include "gc/gc_11_0_0_offset.h"
  40 #include "gc/gc_11_0_0_sh_mask.h"
  41 #include "mp/mp_13_0_0_offset.h"
  42
  43 #include "soc15.h"
  44 #include "soc15_common.h"
  45 #include "soc21.h"
  46 #include "mxgpu_nv.h"
  47
  48 static const struct amd_ip_funcs soc21_common_ip_funcs;
  49
  50 /* SOC21 */
  51 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] =
  52 {
  53         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
  54         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
  55         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
  56 };
  57
  58 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] =
  59 {
  60         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
  61         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
  62 };
  63
  64 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 =
  65 {
  66         .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0),
  67         .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0,
  68 };
  69
  70 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 =
  71 {
  72         .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1),
  73         .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1,
  74 };
  75
  76 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] =
  77 {
  78         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
  79         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
  80         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
  81         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
  82         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
  83 };
  84
  85 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] =
  86 {
  87         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
  88         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
  89         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
  90         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
  91 };
  92
  93 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 =
  94 {
  95         .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0),
  96         .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0,
  97 };
  98
  99 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 =
 100 {
 101         .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1),
 102         .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1,
 103 };
 104
 105 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
 106                                  const struct amdgpu_video_codecs **codecs)
 107 {
 108         if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
 109                 return -EINVAL;
 110
 111         switch (adev->ip_versions[UVD_HWIP][0]) {
 112         case IP_VERSION(4, 0, 0):
 113         case IP_VERSION(4, 0, 2):
 114                 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
 115                         if (encode)
 116                                 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
 117                         else
 118                                 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
 119                 } else {
 120                         if (encode)
 121                                 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
 122                         else
 123                                 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
 124                 }
 125                 return 0;
 126         default:
 127                 return -EINVAL;
 128         }
 129 }
 130 /*
 131  * Indirect registers accessor
 132  */
 133 static u32 soc21_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 134 {
 135         unsigned long address, data;
 136         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 137         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 138
 139         return amdgpu_device_indirect_rreg(adev, address, data, reg);
 140 }
 141
 142 static void soc21_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 143 {
 144         unsigned long address, data;
 145
 146         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 147         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 148
 149         amdgpu_device_indirect_wreg(adev, address, data, reg, v);
 150 }
 151
 152 static u64 soc21_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 153 {
 154         unsigned long address, data;
 155         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 156         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 157
 158         return amdgpu_device_indirect_rreg64(adev, address, data, reg);
 159 }
 160
 161 static void soc21_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 162 {
 163         unsigned long address, data;
 164
 165         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 166         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 167
 168         amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
 169 }
 170
 171 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg)
 172 {
 173         unsigned long flags, address, data;
 174         u32 r;
 175
 176         address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
 177         data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
 178
 179         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 180         WREG32(address, (reg));
 181         r = RREG32(data);
 182         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 183         return r;
 184 }
 185
 186 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 187 {
 188         unsigned long flags, address, data;
 189
 190         address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
 191         data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
 192
 193         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 194         WREG32(address, (reg));
 195         WREG32(data, (v));
 196         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 197 }
 198
 199 static u32 soc21_get_config_memsize(struct amdgpu_device *adev)
 200 {
 201         return adev->nbio.funcs->get_memsize(adev);
 202 }
 203
 204 static u32 soc21_get_xclk(struct amdgpu_device *adev)
 205 {
 206         return adev->clock.spll.reference_freq;
 207 }
 208
 209
 210 void soc21_grbm_select(struct amdgpu_device *adev,
 211                      u32 me, u32 pipe, u32 queue, u32 vmid)
 212 {
 213         u32 grbm_gfx_cntl = 0;
 214         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 215         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 216         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 217         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 218
 219         WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl);
 220 }
 221
 222 static void soc21_vga_set_state(struct amdgpu_device *adev, bool state)
 223 {
 224         /* todo */
 225 }
 226
 227 static bool soc21_read_disabled_bios(struct amdgpu_device *adev)
 228 {
 229         /* todo */
 230         return false;
 231 }
 232
 233 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = {
 234         { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
 235         { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
 236         { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
 237         { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
 238         { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
 239         { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
 240         { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
 241         { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},
 242         { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
 243         { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
 244         { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)},
 245         { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},
 246         { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)},
 247         { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)},
 248         { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
 249         { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)},
 250         { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},
 251         { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
 252         { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
 253 };
 254
 255 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 256                                          u32 sh_num, u32 reg_offset)
 257 {
 258         uint32_t val;
 259
 260         mutex_lock(&adev->grbm_idx_mutex);
 261         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 262                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 263
 264         val = RREG32(reg_offset);
 265
 266         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 267                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 268         mutex_unlock(&adev->grbm_idx_mutex);
 269         return val;
 270 }
 271
 272 static uint32_t soc21_get_register_value(struct amdgpu_device *adev,
 273                                       bool indexed, u32 se_num,
 274                                       u32 sh_num, u32 reg_offset)
 275 {
 276         if (indexed) {
 277                 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset);
 278         } else {
 279                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config)
 280                         return adev->gfx.config.gb_addr_config;
 281                 return RREG32(reg_offset);
 282         }
 283 }
 284
 285 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
 286                             u32 sh_num, u32 reg_offset, u32 *value)
 287 {
 288         uint32_t i;
 289         struct soc15_allowed_register_entry  *en;
 290
 291         *value = 0;
 292         for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
 293                 en = &soc21_allowed_read_registers[i];
 294                 if (adev->reg_offset[en->hwip][en->inst] &&
 295                     reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 296                                    + en->reg_offset))
 297                         continue;
 298
 299                 *value = soc21_get_register_value(adev,
 300                                                soc21_allowed_read_registers[i].grbm_indexed,
 301                                                se_num, sh_num, reg_offset);
 302                 return 0;
 303         }
 304         return -EINVAL;
 305 }
 306
 307 #if 0
 308 static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
 309 {
 310         u32 i;
 311         int ret = 0;
 312
 313         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 314
 315         /* disable BM */
 316         pci_clear_master(adev->pdev);
 317
 318         amdgpu_device_cache_pci_state(adev->pdev);
 319
 320         if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
 321                 dev_info(adev->dev, "GPU smu mode1 reset\n");
 322                 ret = amdgpu_dpm_mode1_reset(adev);
 323         } else {
 324                 dev_info(adev->dev, "GPU psp mode1 reset\n");
 325                 ret = psp_gpu_reset(adev);
 326         }
 327
 328         if (ret)
 329                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 330         amdgpu_device_load_pci_state(adev->pdev);
 331
 332         /* wait for asic to come out of reset */
 333         for (i = 0; i < adev->usec_timeout; i++) {
 334                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 335
 336                 if (memsize != 0xffffffff)
 337                         break;
 338                 udelay(1);
 339         }
 340
 341         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 342
 343         return ret;
 344 }
 345 #endif
 346
 347 static enum amd_reset_method
 348 soc21_asic_reset_method(struct amdgpu_device *adev)
 349 {
 350         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 351             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 352             amdgpu_reset_method == AMD_RESET_METHOD_BACO)
 353                 return amdgpu_reset_method;
 354
 355         if (amdgpu_reset_method != -1)
 356                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 357                                   amdgpu_reset_method);
 358
 359         switch (adev->ip_versions[MP1_HWIP][0]) {
 360         case IP_VERSION(13, 0, 0):
 361         case IP_VERSION(13, 0, 7):
 362         case IP_VERSION(13, 0, 10):
 363                 return AMD_RESET_METHOD_MODE1;
 364         case IP_VERSION(13, 0, 4):
 365         case IP_VERSION(13, 0, 11):
 366                 return AMD_RESET_METHOD_MODE2;
 367         default:
 368                 if (amdgpu_dpm_is_baco_supported(adev))
 369                         return AMD_RESET_METHOD_BACO;
 370                 else
 371                         return AMD_RESET_METHOD_MODE1;
 372         }
 373 }
 374
 375 static int soc21_asic_reset(struct amdgpu_device *adev)
 376 {
 377         int ret = 0;
 378
 379         switch (soc21_asic_reset_method(adev)) {
 380         case AMD_RESET_METHOD_PCI:
 381                 dev_info(adev->dev, "PCI reset\n");
 382                 ret = amdgpu_device_pci_reset(adev);
 383                 break;
 384         case AMD_RESET_METHOD_BACO:
 385                 dev_info(adev->dev, "BACO reset\n");
 386                 ret = amdgpu_dpm_baco_reset(adev);
 387                 break;
 388         case AMD_RESET_METHOD_MODE2:
 389                 dev_info(adev->dev, "MODE2 reset\n");
 390                 ret = amdgpu_dpm_mode2_reset(adev);
 391                 break;
 392         default:
 393                 dev_info(adev->dev, "MODE1 reset\n");
 394                 ret = amdgpu_device_mode1_reset(adev);
 395                 break;
 396         }
 397
 398         return ret;
 399 }
 400
 401 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 402 {
 403         /* todo */
 404         return 0;
 405 }
 406
 407 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 408 {
 409         /* todo */
 410         return 0;
 411 }
 412
 413 static void soc21_pcie_gen3_enable(struct amdgpu_device *adev)
 414 {
 415         if (pci_is_root_bus(adev->pdev->bus))
 416                 return;
 417
 418         if (amdgpu_pcie_gen2 == 0)
 419                 return;
 420
 421         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 422                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 423                 return;
 424
 425         /* todo */
 426 }
 427
 428 static void soc21_program_aspm(struct amdgpu_device *adev)
 429 {
 430         if (!amdgpu_device_should_use_aspm(adev))
 431                 return;
 432
 433         if (!(adev->flags & AMD_IS_APU) &&
 434             (adev->nbio.funcs->program_aspm))
 435                 adev->nbio.funcs->program_aspm(adev);
 436 }
 437
 438 static void soc21_enable_doorbell_aperture(struct amdgpu_device *adev,
 439                                         bool enable)
 440 {
 441         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 442         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 443 }
 444
 445 const struct amdgpu_ip_block_version soc21_common_ip_block =
 446 {
 447         .type = AMD_IP_BLOCK_TYPE_COMMON,
 448         .major = 1,
 449         .minor = 0,
 450         .rev = 0,
 451         .funcs = &soc21_common_ip_funcs,
 452 };
 453
 454 static uint32_t soc21_get_rev_id(struct amdgpu_device *adev)
 455 {
 456         return adev->nbio.funcs->get_rev_id(adev);
 457 }
 458
 459 static bool soc21_need_full_reset(struct amdgpu_device *adev)
 460 {
 461         switch (adev->ip_versions[GC_HWIP][0]) {
 462         case IP_VERSION(11, 0, 0):
 463                 return amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC);
 464         case IP_VERSION(11, 0, 2):
 465         case IP_VERSION(11, 0, 3):
 466                 return false;
 467         default:
 468                 return true;
 469         }
 470 }
 471
 472 static bool soc21_need_reset_on_init(struct amdgpu_device *adev)
 473 {
 474         u32 sol_reg;
 475
 476         if (adev->flags & AMD_IS_APU)
 477                 return false;
 478
 479         /* Check sOS sign of life register to confirm sys driver and sOS
 480          * are already been loaded.
 481          */
 482         sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
 483         if (sol_reg)
 484                 return true;
 485
 486         return false;
 487 }
 488
 489 static uint64_t soc21_get_pcie_replay_count(struct amdgpu_device *adev)
 490 {
 491
 492         /* TODO
 493          * dummy implement for pcie_replay_count sysfs interface
 494          * */
 495
 496         return 0;
 497 }
 498
 499 static void soc21_init_doorbell_index(struct amdgpu_device *adev)
 500 {
 501         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 502         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 503         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 504         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 505         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 506         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 507         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 508         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 509         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 510         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 511         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 512         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 513         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 514         adev->doorbell_index.gfx_userqueue_start =
 515                 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
 516         adev->doorbell_index.gfx_userqueue_end =
 517                 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
 518         adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
 519         adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
 520         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 521         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 522         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 523         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 524         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 525         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 526         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 527         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 528         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 529
 530         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 531         adev->doorbell_index.sdma_doorbell_range = 20;
 532 }
 533
 534 static void soc21_pre_asic_init(struct amdgpu_device *adev)
 535 {
 536 }
 537
 538 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev,
 539                                           bool enter)
 540 {
 541         if (enter)
 542                 amdgpu_gfx_rlc_enter_safe_mode(adev);
 543         else
 544                 amdgpu_gfx_rlc_exit_safe_mode(adev);
 545
 546         if (adev->gfx.funcs->update_perfmon_mgcg)
 547                 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
 548
 549         return 0;
 550 }
 551
 552 static const struct amdgpu_asic_funcs soc21_asic_funcs =
 553 {
 554         .read_disabled_bios = &soc21_read_disabled_bios,
 555         .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
 556         .read_register = &soc21_read_register,
 557         .reset = &soc21_asic_reset,
 558         .reset_method = &soc21_asic_reset_method,
 559         .set_vga_state = &soc21_vga_set_state,
 560         .get_xclk = &soc21_get_xclk,
 561         .set_uvd_clocks = &soc21_set_uvd_clocks,
 562         .set_vce_clocks = &soc21_set_vce_clocks,
 563         .get_config_memsize = &soc21_get_config_memsize,
 564         .init_doorbell_index = &soc21_init_doorbell_index,
 565         .need_full_reset = &soc21_need_full_reset,
 566         .need_reset_on_init = &soc21_need_reset_on_init,
 567         .get_pcie_replay_count = &soc21_get_pcie_replay_count,
 568         .supports_baco = &amdgpu_dpm_is_baco_supported,
 569         .pre_asic_init = &soc21_pre_asic_init,
 570         .query_video_codecs = &soc21_query_video_codecs,
 571         .update_umd_stable_pstate = &soc21_update_umd_stable_pstate,
 572 };
 573
 574 static int soc21_common_early_init(void *handle)
 575 {
 576 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 577         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 578
 579         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 580         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 581         adev->smc_rreg = NULL;
 582         adev->smc_wreg = NULL;
 583         adev->pcie_rreg = &soc21_pcie_rreg;
 584         adev->pcie_wreg = &soc21_pcie_wreg;
 585         adev->pcie_rreg64 = &soc21_pcie_rreg64;
 586         adev->pcie_wreg64 = &soc21_pcie_wreg64;
 587         adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
 588         adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
 589
 590         /* TODO: will add them during VCN v2 implementation */
 591         adev->uvd_ctx_rreg = NULL;
 592         adev->uvd_ctx_wreg = NULL;
 593
 594         adev->didt_rreg = &soc21_didt_rreg;
 595         adev->didt_wreg = &soc21_didt_wreg;
 596
 597         adev->asic_funcs = &soc21_asic_funcs;
 598
 599         adev->rev_id = soc21_get_rev_id(adev);
 600         adev->external_rev_id = 0xff;
 601         switch (adev->ip_versions[GC_HWIP][0]) {
 602         case IP_VERSION(11, 0, 0):
 603                 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
 604                         AMD_CG_SUPPORT_GFX_CGLS |
 605 #if 0
 606                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 607                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 608 #endif
 609                         AMD_CG_SUPPORT_GFX_MGCG |
 610                         AMD_CG_SUPPORT_REPEATER_FGCG |
 611                         AMD_CG_SUPPORT_GFX_FGCG |
 612                         AMD_CG_SUPPORT_GFX_PERF_CLK |
 613                         AMD_CG_SUPPORT_VCN_MGCG |
 614                         AMD_CG_SUPPORT_JPEG_MGCG |
 615                         AMD_CG_SUPPORT_ATHUB_MGCG |
 616                         AMD_CG_SUPPORT_ATHUB_LS |
 617                         AMD_CG_SUPPORT_MC_MGCG |
 618                         AMD_CG_SUPPORT_MC_LS |
 619                         AMD_CG_SUPPORT_IH_CG |
 620                         AMD_CG_SUPPORT_HDP_SD;
 621                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 622                         AMD_PG_SUPPORT_VCN_DPG |
 623                         AMD_PG_SUPPORT_JPEG |
 624                         AMD_PG_SUPPORT_ATHUB |
 625                         AMD_PG_SUPPORT_MMHUB;
 626                 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update
 627                 break;
 628         case IP_VERSION(11, 0, 2):
 629                 adev->cg_flags =
 630                         AMD_CG_SUPPORT_GFX_CGCG |
 631                         AMD_CG_SUPPORT_GFX_CGLS |
 632                         AMD_CG_SUPPORT_REPEATER_FGCG |
 633                         AMD_CG_SUPPORT_VCN_MGCG |
 634                         AMD_CG_SUPPORT_JPEG_MGCG |
 635                         AMD_CG_SUPPORT_ATHUB_MGCG |
 636                         AMD_CG_SUPPORT_ATHUB_LS |
 637                         AMD_CG_SUPPORT_IH_CG |
 638                         AMD_CG_SUPPORT_HDP_SD;
 639                 adev->pg_flags =
 640                         AMD_PG_SUPPORT_VCN |
 641                         AMD_PG_SUPPORT_VCN_DPG |
 642                         AMD_PG_SUPPORT_JPEG |
 643                         AMD_PG_SUPPORT_ATHUB |
 644                         AMD_PG_SUPPORT_MMHUB;
 645                 adev->external_rev_id = adev->rev_id + 0x10;
 646                 break;
 647         case IP_VERSION(11, 0, 1):
 648                 adev->cg_flags =
 649                         AMD_CG_SUPPORT_GFX_CGCG |
 650                         AMD_CG_SUPPORT_GFX_CGLS |
 651                         AMD_CG_SUPPORT_GFX_MGCG |
 652                         AMD_CG_SUPPORT_GFX_FGCG |
 653                         AMD_CG_SUPPORT_REPEATER_FGCG |
 654                         AMD_CG_SUPPORT_GFX_PERF_CLK |
 655                         AMD_CG_SUPPORT_MC_MGCG |
 656                         AMD_CG_SUPPORT_MC_LS |
 657                         AMD_CG_SUPPORT_HDP_MGCG |
 658                         AMD_CG_SUPPORT_HDP_LS |
 659                         AMD_CG_SUPPORT_ATHUB_MGCG |
 660                         AMD_CG_SUPPORT_ATHUB_LS |
 661                         AMD_CG_SUPPORT_IH_CG |
 662                         AMD_CG_SUPPORT_BIF_MGCG |
 663                         AMD_CG_SUPPORT_BIF_LS |
 664                         AMD_CG_SUPPORT_VCN_MGCG |
 665                         AMD_CG_SUPPORT_JPEG_MGCG;
 666                 adev->pg_flags =
 667                         AMD_PG_SUPPORT_GFX_PG |
 668                         AMD_PG_SUPPORT_VCN |
 669                         AMD_PG_SUPPORT_VCN_DPG |
 670                         AMD_PG_SUPPORT_JPEG;
 671                 adev->external_rev_id = adev->rev_id + 0x1;
 672                 break;
 673         case IP_VERSION(11, 0, 3):
 674                 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
 675                         AMD_CG_SUPPORT_JPEG_MGCG |
 676                         AMD_CG_SUPPORT_GFX_CGCG |
 677                         AMD_CG_SUPPORT_GFX_CGLS |
 678                         AMD_CG_SUPPORT_REPEATER_FGCG |
 679                         AMD_CG_SUPPORT_GFX_MGCG |
 680                         AMD_CG_SUPPORT_HDP_SD |
 681                         AMD_CG_SUPPORT_ATHUB_MGCG |
 682                         AMD_CG_SUPPORT_ATHUB_LS;
 683                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 684                         AMD_PG_SUPPORT_VCN_DPG |
 685                         AMD_PG_SUPPORT_JPEG;
 686                 adev->external_rev_id = adev->rev_id + 0x20;
 687                 break;
 688         case IP_VERSION(11, 0, 4):
 689                 adev->cg_flags =
 690                         AMD_CG_SUPPORT_GFX_CGCG |
 691                         AMD_CG_SUPPORT_GFX_CGLS |
 692                         AMD_CG_SUPPORT_GFX_MGCG |
 693                         AMD_CG_SUPPORT_GFX_FGCG |
 694                         AMD_CG_SUPPORT_REPEATER_FGCG |
 695                         AMD_CG_SUPPORT_GFX_PERF_CLK |
 696                         AMD_CG_SUPPORT_MC_MGCG |
 697                         AMD_CG_SUPPORT_MC_LS |
 698                         AMD_CG_SUPPORT_HDP_MGCG |
 699                         AMD_CG_SUPPORT_HDP_LS |
 700                         AMD_CG_SUPPORT_ATHUB_MGCG |
 701                         AMD_CG_SUPPORT_ATHUB_LS |
 702                         AMD_CG_SUPPORT_IH_CG |
 703                         AMD_CG_SUPPORT_BIF_MGCG |
 704                         AMD_CG_SUPPORT_BIF_LS |
 705                         AMD_CG_SUPPORT_VCN_MGCG |
 706                         AMD_CG_SUPPORT_JPEG_MGCG;
 707                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 708                         AMD_PG_SUPPORT_VCN_DPG |
 709                         AMD_PG_SUPPORT_GFX_PG |
 710                         AMD_PG_SUPPORT_JPEG;
 711                 adev->external_rev_id = adev->rev_id + 0x1;
 712                 break;
 713
 714         default:
 715                 /* FIXME: not supported yet */
 716                 return -EINVAL;
 717         }
 718
 719         if (amdgpu_sriov_vf(adev)) {
 720                 amdgpu_virt_init_setting(adev);
 721                 xgpu_nv_mailbox_set_irq_funcs(adev);
 722         }
 723
 724         return 0;
 725 }
 726
 727 static int soc21_common_late_init(void *handle)
 728 {
 729         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 730
 731         if (amdgpu_sriov_vf(adev))
 732                 xgpu_nv_mailbox_get_irq(adev);
 733
 734         return 0;
 735 }
 736
 737 static int soc21_common_sw_init(void *handle)
 738 {
 739         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 740
 741         if (amdgpu_sriov_vf(adev))
 742                 xgpu_nv_mailbox_add_irq_id(adev);
 743
 744         return 0;
 745 }
 746
 747 static int soc21_common_sw_fini(void *handle)
 748 {
 749         return 0;
 750 }
 751
 752 static int soc21_common_hw_init(void *handle)
 753 {
 754         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 755
 756         /* enable pcie gen2/3 link */
 757         soc21_pcie_gen3_enable(adev);
 758         /* enable aspm */
 759         soc21_program_aspm(adev);
 760         /* setup nbio registers */
 761         adev->nbio.funcs->init_registers(adev);
 762         /* remap HDP registers to a hole in mmio space,
 763          * for the purpose of expose those registers
 764          * to process space
 765          */
 766         if (adev->nbio.funcs->remap_hdp_registers)
 767                 adev->nbio.funcs->remap_hdp_registers(adev);
 768         /* enable the doorbell aperture */
 769         soc21_enable_doorbell_aperture(adev, true);
 770
 771         return 0;
 772 }
 773
 774 static int soc21_common_hw_fini(void *handle)
 775 {
 776         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 777
 778         /* disable the doorbell aperture */
 779         soc21_enable_doorbell_aperture(adev, false);
 780
 781         if (amdgpu_sriov_vf(adev))
 782                 xgpu_nv_mailbox_put_irq(adev);
 783
 784         return 0;
 785 }
 786
 787 static int soc21_common_suspend(void *handle)
 788 {
 789         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 790
 791         return soc21_common_hw_fini(adev);
 792 }
 793
 794 static int soc21_common_resume(void *handle)
 795 {
 796         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 797
 798         return soc21_common_hw_init(adev);
 799 }
 800
 801 static bool soc21_common_is_idle(void *handle)
 802 {
 803         return true;
 804 }
 805
 806 static int soc21_common_wait_for_idle(void *handle)
 807 {
 808         return 0;
 809 }
 810
 811 static int soc21_common_soft_reset(void *handle)
 812 {
 813         return 0;
 814 }
 815
 816 static int soc21_common_set_clockgating_state(void *handle,
 817                                            enum amd_clockgating_state state)
 818 {
 819         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 820
 821         switch (adev->ip_versions[NBIO_HWIP][0]) {
 822         case IP_VERSION(4, 3, 0):
 823         case IP_VERSION(4, 3, 1):
 824         case IP_VERSION(7, 7, 0):
 825                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
 826                                 state == AMD_CG_STATE_GATE);
 827                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
 828                                 state == AMD_CG_STATE_GATE);
 829                 adev->hdp.funcs->update_clock_gating(adev,
 830                                 state == AMD_CG_STATE_GATE);
 831                 break;
 832         default:
 833                 break;
 834         }
 835         return 0;
 836 }
 837
 838 static int soc21_common_set_powergating_state(void *handle,
 839                                            enum amd_powergating_state state)
 840 {
 841         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 842
 843         switch (adev->ip_versions[LSDMA_HWIP][0]) {
 844         case IP_VERSION(6, 0, 0):
 845         case IP_VERSION(6, 0, 2):
 846                 adev->lsdma.funcs->update_memory_power_gating(adev,
 847                                 state == AMD_PG_STATE_GATE);
 848                 break;
 849         default:
 850                 break;
 851         }
 852
 853         return 0;
 854 }
 855
 856 static void soc21_common_get_clockgating_state(void *handle, u64 *flags)
 857 {
 858         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 859
 860         adev->nbio.funcs->get_clockgating_state(adev, flags);
 861
 862         adev->hdp.funcs->get_clock_gating_state(adev, flags);
 863
 864         return;
 865 }
 866
 867 static const struct amd_ip_funcs soc21_common_ip_funcs = {
 868         .name = "soc21_common",
 869         .early_init = soc21_common_early_init,
 870         .late_init = soc21_common_late_init,
 871         .sw_init = soc21_common_sw_init,
 872         .sw_fini = soc21_common_sw_fini,
 873         .hw_init = soc21_common_hw_init,
 874         .hw_fini = soc21_common_hw_fini,
 875         .suspend = soc21_common_suspend,
 876         .resume = soc21_common_resume,
 877         .is_idle = soc21_common_is_idle,
 878         .wait_for_idle = soc21_common_wait_for_idle,
 879         .soft_reset = soc21_common_soft_reset,
 880         .set_clockgating_state = soc21_common_set_clockgating_state,
 881         .set_powergating_state = soc21_common_set_powergating_state,
 882         .get_clockgating_state = soc21_common_get_clockgating_state,
 883 };