drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drm_drv.h>
  24 #include <linux/vmalloc.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_psp.h"
  27 #include "amdgpu_ucode.h"
  28 #include "soc15_common.h"
  29 #include "psp_v13_0.h"
  30
  31 #include "mp/mp_13_0_2_offset.h"
  32 #include "mp/mp_13_0_2_sh_mask.h"
  33
  34 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
  35 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
  36 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
  37 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
  38 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
  39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
  40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
  41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
  42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
  43 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
  44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
  45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
  46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
  47 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
  48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin");
  49 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin");
  50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");
  51
  52 /* For large FW files the time to complete can be very long */
  53 #define USBC_PD_POLLING_LIMIT_S 240
  54
  55 /* Read USB-PD from LFB */
  56 #define GFX_CMD_USB_PD_USE_LFB 0x480
  57
  58 /* VBIOS gfl defines */
  59 #define MBOX_READY_MASK 0x80000000
  60 #define MBOX_STATUS_MASK 0x0000FFFF
  61 #define MBOX_COMMAND_MASK 0x00FF0000
  62 #define MBOX_READY_FLAG 0x80000000
  63 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
  64 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
  65 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
  66
  67 /* memory training timeout define */
  68 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US   3000000
  69
  70 static int psp_v13_0_init_microcode(struct psp_context *psp)
  71 {
  72         struct amdgpu_device *adev = psp->adev;
  73         char ucode_prefix[30];
  74         int err = 0;
  75
  76         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
  77
  78         switch (adev->ip_versions[MP0_HWIP][0]) {
  79         case IP_VERSION(13, 0, 2):
  80                 err = psp_init_sos_microcode(psp, ucode_prefix);
  81                 if (err)
  82                         return err;
  83                 /* It's not necessary to load ras ta on Guest side */
  84                 if (!amdgpu_sriov_vf(adev)) {
  85                         err = psp_init_ta_microcode(psp, ucode_prefix);
  86                         if (err)
  87                                 return err;
  88                 }
  89                 break;
  90         case IP_VERSION(13, 0, 1):
  91         case IP_VERSION(13, 0, 3):
  92         case IP_VERSION(13, 0, 5):
  93         case IP_VERSION(13, 0, 8):
  94         case IP_VERSION(13, 0, 11):
  95                 err = psp_init_toc_microcode(psp, ucode_prefix);
  96                 if (err)
  97                         return err;
  98                 err = psp_init_ta_microcode(psp, ucode_prefix);
  99                 if (err)
 100                         return err;
 101                 break;
 102         case IP_VERSION(13, 0, 0):
 103         case IP_VERSION(13, 0, 7):
 104         case IP_VERSION(13, 0, 10):
 105                 err = psp_init_sos_microcode(psp, ucode_prefix);
 106                 if (err)
 107                         return err;
 108                 /* It's not necessary to load ras ta on Guest side */
 109                 err = psp_init_ta_microcode(psp, ucode_prefix);
 110                 if (err)
 111                         return err;
 112                 break;
 113         default:
 114                 BUG();
 115         }
 116
 117         return 0;
 118 }
 119
 120 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
 121 {
 122         struct amdgpu_device *adev = psp->adev;
 123         uint32_t sol_reg;
 124
 125         sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
 126
 127         return sol_reg != 0x0;
 128 }
 129
 130 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
 131 {
 132         struct amdgpu_device *adev = psp->adev;
 133
 134         int ret;
 135         int retry_loop;
 136
 137         for (retry_loop = 0; retry_loop < 10; retry_loop++) {
 138                 /* Wait for bootloader to signify that is
 139                     ready having bit 31 of C2PMSG_35 set to 1 */
 140                 ret = psp_wait_for(psp,
 141                                    SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 142                                    0x80000000,
 143                                    0x80000000,
 144                                    false);
 145
 146                 if (ret == 0)
 147                         return 0;
 148         }
 149
 150         return ret;
 151 }
 152
 153 static int psp_v13_0_bootloader_load_component(struct psp_context       *psp,
 154                                                struct psp_bin_desc      *bin_desc,
 155                                                enum psp_bootloader_cmd  bl_cmd)
 156 {
 157         int ret;
 158         uint32_t psp_gfxdrv_command_reg = 0;
 159         struct amdgpu_device *adev = psp->adev;
 160
 161         /* Check tOS sign of life register to confirm sys driver and sOS
 162          * are already been loaded.
 163          */
 164         if (psp_v13_0_is_sos_alive(psp))
 165                 return 0;
 166
 167         ret = psp_v13_0_wait_for_bootloader(psp);
 168         if (ret)
 169                 return ret;
 170
 171         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 172
 173         /* Copy PSP KDB binary to memory */
 174         memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
 175
 176         /* Provide the PSP KDB to bootloader */
 177         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 178                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 179         psp_gfxdrv_command_reg = bl_cmd;
 180         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 181                psp_gfxdrv_command_reg);
 182
 183         ret = psp_v13_0_wait_for_bootloader(psp);
 184
 185         return ret;
 186 }
 187
 188 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
 189 {
 190         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
 191 }
 192
 193 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
 194 {
 195         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
 196 }
 197
 198 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
 199 {
 200         return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
 201 }
 202
 203 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
 204 {
 205         return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
 206 }
 207
 208 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
 209 {
 210         return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
 211 }
 212
 213 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
 214 {
 215         return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
 216 }
 217
 218 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp)
 219 {
 220         return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
 221 }
 222
 223
 224 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
 225 {
 226         int ret;
 227         unsigned int psp_gfxdrv_command_reg = 0;
 228         struct amdgpu_device *adev = psp->adev;
 229
 230         /* Check sOS sign of life register to confirm sys driver and sOS
 231          * are already been loaded.
 232          */
 233         if (psp_v13_0_is_sos_alive(psp))
 234                 return 0;
 235
 236         ret = psp_v13_0_wait_for_bootloader(psp);
 237         if (ret)
 238                 return ret;
 239
 240         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 241
 242         /* Copy Secure OS binary to PSP memory */
 243         memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
 244
 245         /* Provide the PSP secure OS to bootloader */
 246         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 247                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 248         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 249         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 250                psp_gfxdrv_command_reg);
 251
 252         /* there might be handshake issue with hardware which needs delay */
 253         mdelay(20);
 254         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
 255                            RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
 256                            0, true);
 257
 258         return ret;
 259 }
 260
 261 static int psp_v13_0_ring_stop(struct psp_context *psp,
 262                                enum psp_ring_type ring_type)
 263 {
 264         int ret = 0;
 265         struct amdgpu_device *adev = psp->adev;
 266
 267         if (amdgpu_sriov_vf(adev)) {
 268                 /* Write the ring destroy command*/
 269                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 270                              GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 271                 /* there might be handshake issue with hardware which needs delay */
 272                 mdelay(20);
 273                 /* Wait for response flag (bit 31) */
 274                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 275                                    0x80000000, 0x80000000, false);
 276         } else {
 277                 /* Write the ring destroy command*/
 278                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
 279                              GFX_CTRL_CMD_ID_DESTROY_RINGS);
 280                 /* there might be handshake issue with hardware which needs delay */
 281                 mdelay(20);
 282                 /* Wait for response flag (bit 31) */
 283                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 284                                    0x80000000, 0x80000000, false);
 285         }
 286
 287         return ret;
 288 }
 289
 290 static int psp_v13_0_ring_create(struct psp_context *psp,
 291                                  enum psp_ring_type ring_type)
 292 {
 293         int ret = 0;
 294         unsigned int psp_ring_reg = 0;
 295         struct psp_ring *ring = &psp->km_ring;
 296         struct amdgpu_device *adev = psp->adev;
 297
 298         if (amdgpu_sriov_vf(adev)) {
 299                 ret = psp_v13_0_ring_stop(psp, ring_type);
 300                 if (ret) {
 301                         DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
 302                         return ret;
 303                 }
 304
 305                 /* Write low address of the ring to C2PMSG_102 */
 306                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 307                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
 308                 /* Write high address of the ring to C2PMSG_103 */
 309                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 310                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
 311
 312                 /* Write the ring initialization command to C2PMSG_101 */
 313                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 314                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 315
 316                 /* there might be handshake issue with hardware which needs delay */
 317                 mdelay(20);
 318
 319                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 320                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 321                                    0x80000000, 0x8000FFFF, false);
 322
 323         } else {
 324                 /* Wait for sOS ready for ring creation */
 325                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 326                                    0x80000000, 0x80000000, false);
 327                 if (ret) {
 328                         DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
 329                         return ret;
 330                 }
 331
 332                 /* Write low address of the ring to C2PMSG_69 */
 333                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 334                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
 335                 /* Write high address of the ring to C2PMSG_70 */
 336                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 337                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
 338                 /* Write size of ring to C2PMSG_71 */
 339                 psp_ring_reg = ring->ring_size;
 340                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
 341                 /* Write the ring initialization command to C2PMSG_64 */
 342                 psp_ring_reg = ring_type;
 343                 psp_ring_reg = psp_ring_reg << 16;
 344                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
 345
 346                 /* there might be handshake issue with hardware which needs delay */
 347                 mdelay(20);
 348
 349                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 350                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 351                                    0x80000000, 0x8000FFFF, false);
 352         }
 353
 354         return ret;
 355 }
 356
 357 static int psp_v13_0_ring_destroy(struct psp_context *psp,
 358                                   enum psp_ring_type ring_type)
 359 {
 360         int ret = 0;
 361         struct psp_ring *ring = &psp->km_ring;
 362         struct amdgpu_device *adev = psp->adev;
 363
 364         ret = psp_v13_0_ring_stop(psp, ring_type);
 365         if (ret)
 366                 DRM_ERROR("Fail to stop psp ring\n");
 367
 368         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 369                               &ring->ring_mem_mc_addr,
 370                               (void **)&ring->ring_mem);
 371
 372         return ret;
 373 }
 374
 375 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
 376 {
 377         uint32_t data;
 378         struct amdgpu_device *adev = psp->adev;
 379
 380         if (amdgpu_sriov_vf(adev))
 381                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
 382         else
 383                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
 384
 385         return data;
 386 }
 387
 388 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
 389 {
 390         struct amdgpu_device *adev = psp->adev;
 391
 392         if (amdgpu_sriov_vf(adev)) {
 393                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
 394                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 395                              GFX_CTRL_CMD_ID_CONSUME_CMD);
 396         } else
 397                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
 398 }
 399
 400 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
 401 {
 402         int ret;
 403         int i;
 404         uint32_t data_32;
 405         int max_wait;
 406         struct amdgpu_device *adev = psp->adev;
 407
 408         data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
 409         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
 410         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
 411
 412         max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
 413         for (i = 0; i < max_wait; i++) {
 414                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 415                                    0x80000000, 0x80000000, false);
 416                 if (ret == 0)
 417                         break;
 418         }
 419         if (i < max_wait)
 420                 ret = 0;
 421         else
 422                 ret = -ETIME;
 423
 424         dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
 425                   (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
 426                   (ret == 0) ? "succeed" : "failed",
 427                   i, adev->usec_timeout/1000);
 428         return ret;
 429 }
 430
 431
 432 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
 433 {
 434         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 435         uint32_t *pcache = (uint32_t *)ctx->sys_cache;
 436         struct amdgpu_device *adev = psp->adev;
 437         uint32_t p2c_header[4];
 438         uint32_t sz;
 439         void *buf;
 440         int ret, idx;
 441
 442         if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
 443                 dev_dbg(adev->dev, "Memory training is not supported.\n");
 444                 return 0;
 445         } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
 446                 dev_err(adev->dev, "Memory training initialization failure.\n");
 447                 return -EINVAL;
 448         }
 449
 450         if (psp_v13_0_is_sos_alive(psp)) {
 451                 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
 452                 return 0;
 453         }
 454
 455         amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
 456         dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
 457                   pcache[0], pcache[1], pcache[2], pcache[3],
 458                   p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
 459
 460         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 461                 dev_dbg(adev->dev, "Short training depends on restore.\n");
 462                 ops |= PSP_MEM_TRAIN_RESTORE;
 463         }
 464
 465         if ((ops & PSP_MEM_TRAIN_RESTORE) &&
 466             pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 467                 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
 468                 ops |= PSP_MEM_TRAIN_SAVE;
 469         }
 470
 471         if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 472             !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 473               pcache[3] == p2c_header[3])) {
 474                 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
 475                 ops |= PSP_MEM_TRAIN_SAVE;
 476         }
 477
 478         if ((ops & PSP_MEM_TRAIN_SAVE) &&
 479             p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 480                 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
 481                 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
 482         }
 483
 484         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 485                 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
 486                 ops |= PSP_MEM_TRAIN_SAVE;
 487         }
 488
 489         dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
 490
 491         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 492                 /*
 493                  * Long training will encroach a certain amount on the bottom of VRAM;
 494                  * save the content from the bottom of VRAM to system memory
 495                  * before training, and restore it after training to avoid
 496                  * VRAM corruption.
 497                  */
 498                 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
 499
 500                 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
 501                         dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
 502                                   adev->gmc.visible_vram_size,
 503                                   adev->mman.aper_base_kaddr);
 504                         return -EINVAL;
 505                 }
 506
 507                 buf = vmalloc(sz);
 508                 if (!buf) {
 509                         dev_err(adev->dev, "failed to allocate system memory.\n");
 510                         return -ENOMEM;
 511                 }
 512
 513                 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 514                         memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
 515                         ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
 516                         if (ret) {
 517                                 DRM_ERROR("Send long training msg failed.\n");
 518                                 vfree(buf);
 519                                 drm_dev_exit(idx);
 520                                 return ret;
 521                         }
 522
 523                         memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
 524                         adev->hdp.funcs->flush_hdp(adev, NULL);
 525                         vfree(buf);
 526                         drm_dev_exit(idx);
 527                 } else {
 528                         vfree(buf);
 529                         return -ENODEV;
 530                 }
 531         }
 532
 533         if (ops & PSP_MEM_TRAIN_SAVE) {
 534                 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
 535         }
 536
 537         if (ops & PSP_MEM_TRAIN_RESTORE) {
 538                 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
 539         }
 540
 541         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 542                 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
 543                                                          PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
 544                 if (ret) {
 545                         dev_err(adev->dev, "send training msg failed.\n");
 546                         return ret;
 547                 }
 548         }
 549         ctx->training_cnt++;
 550         return 0;
 551 }
 552
 553 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
 554 {
 555         struct amdgpu_device *adev = psp->adev;
 556         uint32_t reg_status;
 557         int ret, i = 0;
 558
 559         /*
 560          * LFB address which is aligned to 1MB address and has to be
 561          * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
 562          * register
 563          */
 564         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
 565
 566         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 567                              0x80000000, 0x80000000, false);
 568         if (ret)
 569                 return ret;
 570
 571         /* Fireup interrupt so PSP can pick up the address */
 572         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
 573
 574         /* FW load takes very long time */
 575         do {
 576                 msleep(1000);
 577                 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
 578
 579                 if (reg_status & 0x80000000)
 580                         goto done;
 581
 582         } while (++i < USBC_PD_POLLING_LIMIT_S);
 583
 584         return -ETIME;
 585 done:
 586
 587         if ((reg_status & 0xFFFF) != 0) {
 588                 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
 589                                 reg_status & 0xFFFF);
 590                 return -EIO;
 591         }
 592
 593         return 0;
 594 }
 595
 596 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
 597 {
 598         struct amdgpu_device *adev = psp->adev;
 599         int ret;
 600
 601         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 602
 603         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 604                                      0x80000000, 0x80000000, false);
 605         if (!ret)
 606                 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
 607
 608         return ret;
 609 }
 610
 611 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
 612 {
 613         uint32_t reg_status = 0, reg_val = 0;
 614         struct amdgpu_device *adev = psp->adev;
 615         int ret;
 616
 617         /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
 618         reg_val |= (cmd << 16);
 619         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115,  reg_val);
 620
 621         /* Ring the doorbell */
 622         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
 623
 624         if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
 625                 return 0;
 626
 627         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 628                                 MBOX_READY_FLAG, MBOX_READY_MASK, false);
 629         if (ret) {
 630                 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
 631                 return ret;
 632         }
 633
 634         reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 635         if ((reg_status & 0xFFFF) != 0) {
 636                 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
 637                                 cmd, reg_status & 0xFFFF);
 638                 return -EIO;
 639         }
 640
 641         return 0;
 642 }
 643
 644 static int psp_v13_0_update_spirom(struct psp_context *psp,
 645                                    uint64_t fw_pri_mc_addr)
 646 {
 647         struct amdgpu_device *adev = psp->adev;
 648         int ret;
 649
 650         /* Confirm PSP is ready to start */
 651         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 652                            MBOX_READY_FLAG, MBOX_READY_MASK, false);
 653         if (ret) {
 654                 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
 655                 return ret;
 656         }
 657
 658         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
 659
 660         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
 661         if (ret)
 662                 return ret;
 663
 664         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
 665
 666         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
 667         if (ret)
 668                 return ret;
 669
 670         psp->vbflash_done = true;
 671
 672         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
 673         if (ret)
 674                 return ret;
 675
 676         return 0;
 677 }
 678
 679 static int psp_v13_0_vbflash_status(struct psp_context *psp)
 680 {
 681         struct amdgpu_device *adev = psp->adev;
 682
 683         return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 684 }
 685
 686 static const struct psp_funcs psp_v13_0_funcs = {
 687         .init_microcode = psp_v13_0_init_microcode,
 688         .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
 689         .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
 690         .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
 691         .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
 692         .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
 693         .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
 694         .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv,
 695         .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
 696         .ring_create = psp_v13_0_ring_create,
 697         .ring_stop = psp_v13_0_ring_stop,
 698         .ring_destroy = psp_v13_0_ring_destroy,
 699         .ring_get_wptr = psp_v13_0_ring_get_wptr,
 700         .ring_set_wptr = psp_v13_0_ring_set_wptr,
 701         .mem_training = psp_v13_0_memory_training,
 702         .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
 703         .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
 704         .update_spirom = psp_v13_0_update_spirom,
 705         .vbflash_stat = psp_v13_0_vbflash_status
 706 };
 707
 708 void psp_v13_0_set_psp_funcs(struct psp_context *psp)
 709 {
 710         psp->funcs = &psp_v13_0_funcs;
 711 }