drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "gfxhub_v3_0.h"
  26
  27 #include "gc/gc_11_0_0_offset.h"
  28 #include "gc/gc_11_0_0_sh_mask.h"
  29 #include "gc/gc_11_0_0_default.h"
  30 #include "navi10_enum.h"
  31 #include "soc15_common.h"
  32
  33 static const char *gfxhub_client_ids[] = {
  34         "CB/DB",
  35         "Reserved",
  36         "GE1",
  37         "GE2",
  38         "CPF",
  39         "CPC",
  40         "CPG",
  41         "RLC",
  42         "TCP",
  43         "SQC (inst)",
  44         "SQC (data)",
  45         "SQG",
  46         "Reserved",
  47         "SDMA0",
  48         "SDMA1",
  49         "GCR",
  50         "SDMA2",
  51         "SDMA3",
  52 };
  53
  54 static uint32_t gfxhub_v3_0_get_invalidate_req(unsigned int vmid,
  55                                                uint32_t flush_type)
  56 {
  57         u32 req = 0;
  58
  59         /* invalidate using legacy mode on vmid*/
  60         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
  61                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
  62         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
  63         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
  64         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
  65         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
  66         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
  67         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
  68         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
  69                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
  70
  71         return req;
  72 }
  73
  74 static void
  75 gfxhub_v3_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
  76                                              uint32_t status)
  77 {
  78         u32 cid = REG_GET_FIELD(status,
  79                                 GCVM_L2_PROTECTION_FAULT_STATUS, CID);
  80
  81         dev_err(adev->dev,
  82                 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
  83                 status);
  84         dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
  85                 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],
  86                 cid);
  87         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
  88                 REG_GET_FIELD(status,
  89                 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
  90         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
  91                 REG_GET_FIELD(status,
  92                 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
  93         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
  94                 REG_GET_FIELD(status,
  95                 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
  96         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
  97                 REG_GET_FIELD(status,
  98                 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
  99         dev_err(adev->dev, "\t RW: 0x%lx\n",
 100                 REG_GET_FIELD(status,
 101                 GCVM_L2_PROTECTION_FAULT_STATUS, RW));
 102 }
 103
 104 static u64 gfxhub_v3_0_get_fb_location(struct amdgpu_device *adev)
 105 {
 106         u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);
 107
 108         base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
 109         base <<= 24;
 110
 111         return base;
 112 }
 113
 114 static u64 gfxhub_v3_0_get_mc_fb_offset(struct amdgpu_device *adev)
 115 {
 116         return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24;
 117 }
 118
 119 static void gfxhub_v3_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
 120                                 uint64_t page_table_base)
 121 {
 122         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 123
 124         WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
 125                             hub->ctx_addr_distance * vmid,
 126                             lower_32_bits(page_table_base));
 127
 128         WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
 129                             hub->ctx_addr_distance * vmid,
 130                             upper_32_bits(page_table_base));
 131 }
 132
 133 static void gfxhub_v3_0_init_gart_aperture_regs(struct amdgpu_device *adev)
 134 {
 135         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
 136
 137         gfxhub_v3_0_setup_vm_pt_regs(adev, 0, pt_base);
 138
 139         WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
 140                      (u32)(adev->gmc.gart_start >> 12));
 141         WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
 142                      (u32)(adev->gmc.gart_start >> 44));
 143
 144         WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
 145                      (u32)(adev->gmc.gart_end >> 12));
 146         WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 147                      (u32)(adev->gmc.gart_end >> 44));
 148 }
 149
 150 static void gfxhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev)
 151 {
 152         uint64_t value;
 153
 154         /* Program the AGP BAR */
 155         WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0);
 156         WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
 157         WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 158
 159
 160         /* Program the system aperture low logical page number. */
 161         WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 162                      min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 163         WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 164                      max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 165
 166         /* Set default page address. */
 167         value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start
 168                 + adev->vm_manager.vram_base_offset;
 169         WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 170                      (u32)(value >> 12));
 171         WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 172                      (u32)(value >> 44));
 173
 174         /* Program "protection fault". */
 175         WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 176                      (u32)(adev->dummy_page_addr >> 12));
 177         WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 178                      (u32)((u64)adev->dummy_page_addr >> 44));
 179
 180         WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
 181                        ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 182 }
 183
 184
 185 static void gfxhub_v3_0_init_tlb_regs(struct amdgpu_device *adev)
 186 {
 187         uint32_t tmp;
 188
 189         /* Setup TLB control */
 190         tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
 191
 192         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 193         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 194         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 195                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 196         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 197                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 198         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 199         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 200                             MTYPE, MTYPE_UC); /* UC, uncached */
 201
 202         WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
 203 }
 204
 205 static void gfxhub_v3_0_init_cache_regs(struct amdgpu_device *adev)
 206 {
 207         uint32_t tmp;
 208
 209         /* These registers are not accessible to VF-SRIOV.
 210          * The PF will program them instead.
 211          */
 212         if (amdgpu_sriov_vf(adev))
 213                 return;
 214
 215         /* Setup L2 cache */
 216         tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);
 217         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
 218         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
 219         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
 220                             ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 221         /* XXX for emulation, Refer to closed source code.*/
 222         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
 223                             L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
 224         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 225         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 226         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 227         WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp);
 228
 229         tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);
 230         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 231         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 232         WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp);
 233
 234         tmp = regGCVM_L2_CNTL3_DEFAULT;
 235         if (adev->gmc.translate_further) {
 236                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
 237                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
 238                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 239         } else {
 240                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
 241                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
 242                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 243         }
 244         WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp);
 245
 246         tmp = regGCVM_L2_CNTL4_DEFAULT;
 247         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 248         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 249         WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp);
 250
 251         tmp = regGCVM_L2_CNTL5_DEFAULT;
 252         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
 253         WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp);
 254 }
 255
 256 static void gfxhub_v3_0_enable_system_domain(struct amdgpu_device *adev)
 257 {
 258         uint32_t tmp;
 259
 260         tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);
 261         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 262         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 263         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
 264                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 265         WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp);
 266 }
 267
 268 static void gfxhub_v3_0_disable_identity_aperture(struct amdgpu_device *adev)
 269 {
 270         /* These registers are not accessible to VF-SRIOV.
 271          * The PF will program them instead.
 272          */
 273         if (amdgpu_sriov_vf(adev))
 274                 return;
 275
 276         WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 277                      0xFFFFFFFF);
 278         WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 279                      0x0000000F);
 280
 281         WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
 282                      0);
 283         WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
 284                      0);
 285
 286         WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
 287         WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
 288
 289 }
 290
 291 static void gfxhub_v3_0_setup_vmid_config(struct amdgpu_device *adev)
 292 {
 293         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 294         int i;
 295         uint32_t tmp;
 296
 297         for (i = 0; i <= 14; i++) {
 298                 tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i);
 299                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 300                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 301                                     adev->vm_manager.num_level);
 302                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 303                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 304                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 305                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 306                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 307                                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 308                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 309                                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 310                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 311                                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 312                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 313                                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 314                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 315                                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 316                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 317                                 PAGE_TABLE_BLOCK_SIZE,
 318                                 adev->vm_manager.block_size - 9);
 319                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 320                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 321                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 322                                     !amdgpu_noretry);
 323                 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL,
 324                                     i * hub->ctx_distance, tmp);
 325                 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 326                                     i * hub->ctx_addr_distance, 0);
 327                 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 328                                     i * hub->ctx_addr_distance, 0);
 329                 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 330                                     i * hub->ctx_addr_distance,
 331                                     lower_32_bits(adev->vm_manager.max_pfn - 1));
 332                 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 333                                     i * hub->ctx_addr_distance,
 334                                     upper_32_bits(adev->vm_manager.max_pfn - 1));
 335         }
 336
 337         hub->vm_cntx_cntl = tmp;
 338 }
 339
 340 static void gfxhub_v3_0_program_invalidation(struct amdgpu_device *adev)
 341 {
 342         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 343         unsigned i;
 344
 345         for (i = 0 ; i < 18; ++i) {
 346                 WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 347                                     i * hub->eng_addr_distance, 0xffffffff);
 348                 WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 349                                     i * hub->eng_addr_distance, 0x1f);
 350         }
 351 }
 352
 353 static int gfxhub_v3_0_gart_enable(struct amdgpu_device *adev)
 354 {
 355         if (amdgpu_sriov_vf(adev)) {
 356                 /*
 357                  * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 358                  * VF copy registers so vbios post doesn't program them, for
 359                  * SRIOV driver need to program them
 360                  */
 361                 WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE,
 362                              adev->gmc.vram_start >> 24);
 363                 WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_TOP,
 364                              adev->gmc.vram_end >> 24);
 365         }
 366
 367         /* GART Enable. */
 368         gfxhub_v3_0_init_gart_aperture_regs(adev);
 369         gfxhub_v3_0_init_system_aperture_regs(adev);
 370         gfxhub_v3_0_init_tlb_regs(adev);
 371         gfxhub_v3_0_init_cache_regs(adev);
 372
 373         gfxhub_v3_0_enable_system_domain(adev);
 374         gfxhub_v3_0_disable_identity_aperture(adev);
 375         gfxhub_v3_0_setup_vmid_config(adev);
 376         gfxhub_v3_0_program_invalidation(adev);
 377
 378         return 0;
 379 }
 380
 381 static void gfxhub_v3_0_gart_disable(struct amdgpu_device *adev)
 382 {
 383         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 384         u32 tmp;
 385         u32 i;
 386
 387         /* Disable all tables */
 388         for (i = 0; i < 16; i++)
 389                 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL,
 390                                     i * hub->ctx_distance, 0);
 391
 392         /* Setup TLB control */
 393         tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
 394         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 395         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 396                             ENABLE_ADVANCED_DRIVER_MODEL, 0);
 397         WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
 398
 399         /* Setup L2 cache */
 400         WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
 401         WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0);
 402 }
 403
 404 /**
 405  * gfxhub_v3_0_set_fault_enable_default - update GART/VM fault handling
 406  *
 407  * @adev: amdgpu_device pointer
 408  * @value: true redirects VM faults to the default page
 409  */
 410 static void gfxhub_v3_0_set_fault_enable_default(struct amdgpu_device *adev,
 411                                           bool value)
 412 {
 413         u32 tmp;
 414
 415         /* NO halt CP when page fault */
 416         tmp = RREG32_SOC15(GC, 0, regCP_DEBUG);
 417         tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);
 418         WREG32_SOC15(GC, 0, regCP_DEBUG, tmp);
 419
 420         /**
 421          * Set GRBM_GFX_INDEX in broad cast mode
 422          * before programming GL1C_UTCL0_CNTL1 and SQG_CONFIG
 423          */
 424         WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, regGRBM_GFX_INDEX_DEFAULT);
 425
 426         /**
 427          * Retry respond mode: RETRY
 428          * Error (no retry) respond mode: SUCCESS
 429          */
 430         tmp = RREG32_SOC15(GC, 0, regGL1C_UTCL0_CNTL1);
 431         tmp = REG_SET_FIELD(tmp, GL1C_UTCL0_CNTL1, RESP_MODE, 0);
 432         tmp = REG_SET_FIELD(tmp, GL1C_UTCL0_CNTL1, RESP_FAULT_MODE, 0x2);
 433         WREG32_SOC15(GC, 0, regGL1C_UTCL0_CNTL1, tmp);
 434
 435         /* These registers are not accessible to VF-SRIOV.
 436          * The PF will program them instead.
 437          */
 438         if (amdgpu_sriov_vf(adev))
 439                 return;
 440
 441         /* Disable SQ XNACK interrupt for all VMIDs */
 442         tmp = RREG32_SOC15(GC, 0, regSQG_CONFIG);
 443         tmp = REG_SET_FIELD(tmp, SQG_CONFIG, XNACK_INTR_MASK,
 444                             SQG_CONFIG__XNACK_INTR_MASK_MASK >>
 445                             SQG_CONFIG__XNACK_INTR_MASK__SHIFT);
 446         WREG32_SOC15(GC, 0, regSQG_CONFIG, tmp);
 447
 448         tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
 449         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 450                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 451         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 452                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 453         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 454                             PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 455         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 456                             PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 457         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 458                             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 459                             value);
 460         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 461                             NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 462         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 463                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 464         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 465                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 466         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 467                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 468         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 469                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 470         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 471                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 472         if (!value) {
 473                 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 474                                 CRASH_ON_NO_RETRY_FAULT, 1);
 475                 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 476                                 CRASH_ON_RETRY_FAULT, 1);
 477         }
 478         WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
 479 }
 480
 481 static const struct amdgpu_vmhub_funcs gfxhub_v3_0_vmhub_funcs = {
 482         .print_l2_protection_fault_status = gfxhub_v3_0_print_l2_protection_fault_status,
 483         .get_invalidate_req = gfxhub_v3_0_get_invalidate_req,
 484 };
 485
 486 static void gfxhub_v3_0_init(struct amdgpu_device *adev)
 487 {
 488         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 489
 490         hub->ctx0_ptb_addr_lo32 =
 491                 SOC15_REG_OFFSET(GC, 0,
 492                                  regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 493         hub->ctx0_ptb_addr_hi32 =
 494                 SOC15_REG_OFFSET(GC, 0,
 495                                  regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 496         hub->vm_inv_eng0_sem =
 497                 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_SEM);
 498         hub->vm_inv_eng0_req =
 499                 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_REQ);
 500         hub->vm_inv_eng0_ack =
 501                 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ACK);
 502         hub->vm_context0_cntl =
 503                 SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL);
 504         hub->vm_l2_pro_fault_status =
 505                 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS);
 506         hub->vm_l2_pro_fault_cntl =
 507                 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
 508
 509         hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL;
 510         hub->ctx_addr_distance = regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 511                 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 512         hub->eng_distance = regGCVM_INVALIDATE_ENG1_REQ -
 513                 regGCVM_INVALIDATE_ENG0_REQ;
 514         hub->eng_addr_distance = regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 515                 regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 516
 517         hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 518                 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 519                 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 520                 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 521                 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 522                 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 523                 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 524
 525         hub->vmhub_funcs = &gfxhub_v3_0_vmhub_funcs;
 526 }
 527
 528 const struct amdgpu_gfxhub_funcs gfxhub_v3_0_funcs = {
 529         .get_fb_location = gfxhub_v3_0_get_fb_location,
 530         .get_mc_fb_offset = gfxhub_v3_0_get_mc_fb_offset,
 531         .setup_vm_pt_regs = gfxhub_v3_0_setup_vm_pt_regs,
 532         .gart_enable = gfxhub_v3_0_gart_enable,
 533         .gart_disable = gfxhub_v3_0_gart_disable,
 534         .set_fault_enable_default = gfxhub_v3_0_set_fault_enable_default,
 535         .init = gfxhub_v3_0_init,
 536 };