drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/delay.h>
  24 #include <linux/kernel.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_gfx.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_smu.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "imu_v11_0.h"
  34 #include "soc21.h"
  35 #include "nvd.h"
  36
  37 #include "gc/gc_11_0_0_offset.h"
  38 #include "gc/gc_11_0_0_sh_mask.h"
  39 #include "smuio/smuio_13_0_6_offset.h"
  40 #include "smuio/smuio_13_0_6_sh_mask.h"
  41 #include "navi10_enum.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "clearstate_gfx11.h"
  47 #include "v11_structs.h"
  48 #include "gfx_v11_0.h"
  49 #include "gfx_v11_0_3.h"
  50 #include "nbio_v4_3.h"
  51 #include "mes_v11_0.h"
  52
  53 #define GFX11_NUM_GFX_RINGS             1
  54 #define GFX11_MEC_HPD_SIZE      2048
  55
  56 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  57 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1        0x1388
  58
  59 #define regCGTT_WD_CLK_CTRL             0x5086
  60 #define regCGTT_WD_CLK_CTRL_BASE_IDX    1
  61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1   0x4e7e
  62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX  1
  63
  64 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin");
  65 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin");
  66 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin");
  67 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin");
  68 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin");
  69 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin");
  70 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin");
  71 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin");
  72 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin");
  73 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin");
  74 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin");
  75 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin");
  76 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin");
  77 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin");
  78 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin");
  79 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin");
  80 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin");
  81 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin");
  82 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin");
  83 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin");
  84 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin");
  85
  86 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =
  87 {
  88         SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
  89         SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010),
  90         SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
  91         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988),
  92         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007),
  93         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008),
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100),
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a)
  97 };
  98
  99 #define DEFAULT_SH_MEM_CONFIG \
 100         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
 101          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
 102          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
 103
 104 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev);
 105 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev);
 106 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev);
 107 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev);
 108 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev);
 109 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev);
 110 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev);
 111 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev,
 112                                  struct amdgpu_cu_info *cu_info);
 113 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 114 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 115                                    u32 sh_num, u32 instance);
 116 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
 117
 118 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
 119 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
 120 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
 121                                      uint32_t val);
 122 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
 123 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
 124                                            uint16_t pasid, uint32_t flush_type,
 125                                            bool all_hub, uint8_t dst_sel);
 126 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev);
 127 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev);
 128 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
 129                                       bool enable);
 130
 131 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
 132 {
 133         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
 134         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
 135                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
 136         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
 137         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
 138         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
 139         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
 140         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
 141         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
 142 }
 143
 144 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring,
 145                                  struct amdgpu_ring *ring)
 146 {
 147         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
 148         uint64_t wptr_addr = ring->wptr_gpu_addr;
 149         uint32_t me = 0, eng_sel = 0;
 150
 151         switch (ring->funcs->type) {
 152         case AMDGPU_RING_TYPE_COMPUTE:
 153                 me = 1;
 154                 eng_sel = 0;
 155                 break;
 156         case AMDGPU_RING_TYPE_GFX:
 157                 me = 0;
 158                 eng_sel = 4;
 159                 break;
 160         case AMDGPU_RING_TYPE_MES:
 161                 me = 2;
 162                 eng_sel = 5;
 163                 break;
 164         default:
 165                 WARN_ON(1);
 166         }
 167
 168         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
 169         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
 170         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 171                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
 172                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
 173                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
 174                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
 175                           PACKET3_MAP_QUEUES_ME((me)) |
 176                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
 177                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
 178                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
 179                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
 180         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
 181         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
 182         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
 183         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
 184         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
 185 }
 186
 187 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
 188                                    struct amdgpu_ring *ring,
 189                                    enum amdgpu_unmap_queues_action action,
 190                                    u64 gpu_addr, u64 seq)
 191 {
 192         struct amdgpu_device *adev = kiq_ring->adev;
 193         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 194
 195         if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) {
 196                 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
 197                 return;
 198         }
 199
 200         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
 201         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 202                           PACKET3_UNMAP_QUEUES_ACTION(action) |
 203                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
 204                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
 205                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
 206         amdgpu_ring_write(kiq_ring,
 207                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
 208
 209         if (action == PREEMPT_QUEUES_NO_UNMAP) {
 210                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
 211                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
 212                 amdgpu_ring_write(kiq_ring, seq);
 213         } else {
 214                 amdgpu_ring_write(kiq_ring, 0);
 215                 amdgpu_ring_write(kiq_ring, 0);
 216                 amdgpu_ring_write(kiq_ring, 0);
 217         }
 218 }
 219
 220 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring,
 221                                    struct amdgpu_ring *ring,
 222                                    u64 addr,
 223                                    u64 seq)
 224 {
 225         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 226
 227         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
 228         amdgpu_ring_write(kiq_ring,
 229                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
 230                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
 231                           PACKET3_QUERY_STATUS_COMMAND(2));
 232         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 233                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
 234                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
 235         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
 236         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
 237         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
 238         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
 239 }
 240
 241 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
 242                                 uint16_t pasid, uint32_t flush_type,
 243                                 bool all_hub)
 244 {
 245         gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
 246 }
 247
 248 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = {
 249         .kiq_set_resources = gfx11_kiq_set_resources,
 250         .kiq_map_queues = gfx11_kiq_map_queues,
 251         .kiq_unmap_queues = gfx11_kiq_unmap_queues,
 252         .kiq_query_status = gfx11_kiq_query_status,
 253         .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs,
 254         .set_resources_size = 8,
 255         .map_queues_size = 7,
 256         .unmap_queues_size = 6,
 257         .query_status_size = 7,
 258         .invalidate_tlbs_size = 2,
 259 };
 260
 261 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
 262 {
 263         adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs;
 264 }
 265
 266 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)
 267 {
 268         switch (adev->ip_versions[GC_HWIP][0]) {
 269         case IP_VERSION(11, 0, 1):
 270         case IP_VERSION(11, 0, 4):
 271                 soc15_program_register_sequence(adev,
 272                                                 golden_settings_gc_11_0_1,
 273                                                 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1));
 274                 break;
 275         default:
 276                 break;
 277         }
 278 }
 279
 280 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 281                                        bool wc, uint32_t reg, uint32_t val)
 282 {
 283         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 284         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 285                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
 286         amdgpu_ring_write(ring, reg);
 287         amdgpu_ring_write(ring, 0);
 288         amdgpu_ring_write(ring, val);
 289 }
 290
 291 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 292                                   int mem_space, int opt, uint32_t addr0,
 293                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 294                                   uint32_t inv)
 295 {
 296         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 297         amdgpu_ring_write(ring,
 298                           /* memory (1) or register (0) */
 299                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 300                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
 301                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 302                            WAIT_REG_MEM_ENGINE(eng_sel)));
 303
 304         if (mem_space)
 305                 BUG_ON(addr0 & 0x3); /* Dword align */
 306         amdgpu_ring_write(ring, addr0);
 307         amdgpu_ring_write(ring, addr1);
 308         amdgpu_ring_write(ring, ref);
 309         amdgpu_ring_write(ring, mask);
 310         amdgpu_ring_write(ring, inv); /* poll interval */
 311 }
 312
 313 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring)
 314 {
 315         struct amdgpu_device *adev = ring->adev;
 316         uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
 317         uint32_t tmp = 0;
 318         unsigned i;
 319         int r;
 320
 321         WREG32(scratch, 0xCAFEDEAD);
 322         r = amdgpu_ring_alloc(ring, 5);
 323         if (r) {
 324                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 325                           ring->idx, r);
 326                 return r;
 327         }
 328
 329         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) {
 330                 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);
 331         } else {
 332                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 333                 amdgpu_ring_write(ring, scratch -
 334                                   PACKET3_SET_UCONFIG_REG_START);
 335                 amdgpu_ring_write(ring, 0xDEADBEEF);
 336         }
 337         amdgpu_ring_commit(ring);
 338
 339         for (i = 0; i < adev->usec_timeout; i++) {
 340                 tmp = RREG32(scratch);
 341                 if (tmp == 0xDEADBEEF)
 342                         break;
 343                 if (amdgpu_emu_mode == 1)
 344                         msleep(1);
 345                 else
 346                         udelay(1);
 347         }
 348
 349         if (i >= adev->usec_timeout)
 350                 r = -ETIMEDOUT;
 351         return r;
 352 }
 353
 354 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 355 {
 356         struct amdgpu_device *adev = ring->adev;
 357         struct amdgpu_ib ib;
 358         struct dma_fence *f = NULL;
 359         unsigned index;
 360         uint64_t gpu_addr;
 361         volatile uint32_t *cpu_ptr;
 362         long r;
 363
 364         /* MES KIQ fw hasn't indirect buffer support for now */
 365         if (adev->enable_mes_kiq &&
 366             ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
 367                 return 0;
 368
 369         memset(&ib, 0, sizeof(ib));
 370
 371         if (ring->is_mes_queue) {
 372                 uint32_t padding, offset;
 373
 374                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
 375                 padding = amdgpu_mes_ctx_get_offs(ring,
 376                                                   AMDGPU_MES_CTX_PADDING_OFFS);
 377
 378                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 379                 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 380
 381                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
 382                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
 383                 *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
 384         } else {
 385                 r = amdgpu_device_wb_get(adev, &index);
 386                 if (r)
 387                         return r;
 388
 389                 gpu_addr = adev->wb.gpu_addr + (index * 4);
 390                 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 391                 cpu_ptr = &adev->wb.wb[index];
 392
 393                 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib);
 394                 if (r) {
 395                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 396                         goto err1;
 397                 }
 398         }
 399
 400         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 401         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 402         ib.ptr[2] = lower_32_bits(gpu_addr);
 403         ib.ptr[3] = upper_32_bits(gpu_addr);
 404         ib.ptr[4] = 0xDEADBEEF;
 405         ib.length_dw = 5;
 406
 407         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 408         if (r)
 409                 goto err2;
 410
 411         r = dma_fence_wait_timeout(f, false, timeout);
 412         if (r == 0) {
 413                 r = -ETIMEDOUT;
 414                 goto err2;
 415         } else if (r < 0) {
 416                 goto err2;
 417         }
 418
 419         if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
 420                 r = 0;
 421         else
 422                 r = -EINVAL;
 423 err2:
 424         if (!ring->is_mes_queue)
 425                 amdgpu_ib_free(adev, &ib, NULL);
 426         dma_fence_put(f);
 427 err1:
 428         if (!ring->is_mes_queue)
 429                 amdgpu_device_wb_free(adev, index);
 430         return r;
 431 }
 432
 433 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev)
 434 {
 435         amdgpu_ucode_release(&adev->gfx.pfp_fw);
 436         amdgpu_ucode_release(&adev->gfx.me_fw);
 437         amdgpu_ucode_release(&adev->gfx.rlc_fw);
 438         amdgpu_ucode_release(&adev->gfx.mec_fw);
 439
 440         kfree(adev->gfx.rlc.register_list_format);
 441 }
 442
 443 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix)
 444 {
 445         const struct psp_firmware_header_v1_0 *toc_hdr;
 446         int err = 0;
 447         char fw_name[40];
 448
 449         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix);
 450         err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name);
 451         if (err)
 452                 goto out;
 453
 454         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
 455         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
 456         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
 457         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
 458         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
 459                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
 460         return 0;
 461 out:
 462         amdgpu_ucode_release(&adev->psp.toc_fw);
 463         return err;
 464 }
 465
 466 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
 467 {
 468         char fw_name[40];
 469         char ucode_prefix[30];
 470         int err;
 471         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 472         uint16_t version_major;
 473         uint16_t version_minor;
 474
 475         DRM_DEBUG("\n");
 476
 477         amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
 478
 479         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix);
 480         err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
 481         if (err)
 482                 goto out;
 483         /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/
 484         adev->gfx.rs64_enable = amdgpu_ucode_hdr_version(
 485                                 (union amdgpu_firmware_header *)
 486                                 adev->gfx.pfp_fw->data, 2, 0);
 487         if (adev->gfx.rs64_enable) {
 488                 dev_info(adev->dev, "CP RS64 enable\n");
 489                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP);
 490                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK);
 491                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK);
 492         } else {
 493                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
 494         }
 495
 496         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix);
 497         err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
 498         if (err)
 499                 goto out;
 500         if (adev->gfx.rs64_enable) {
 501                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME);
 502                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK);
 503                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK);
 504         } else {
 505                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
 506         }
 507
 508         if (!amdgpu_sriov_vf(adev)) {
 509                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
 510                 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
 511                 if (err)
 512                         goto out;
 513                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 514                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 515                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 516                 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
 517                 if (err)
 518                         goto out;
 519         }
 520
 521         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix);
 522         err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
 523         if (err)
 524                 goto out;
 525         if (adev->gfx.rs64_enable) {
 526                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC);
 527                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK);
 528                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK);
 529                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK);
 530                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK);
 531         } else {
 532                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
 533                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
 534         }
 535
 536         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
 537                 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix);
 538
 539         /* only one MEC for gfx 11.0.0. */
 540         adev->gfx.mec2_fw = NULL;
 541
 542 out:
 543         if (err) {
 544                 amdgpu_ucode_release(&adev->gfx.pfp_fw);
 545                 amdgpu_ucode_release(&adev->gfx.me_fw);
 546                 amdgpu_ucode_release(&adev->gfx.rlc_fw);
 547                 amdgpu_ucode_release(&adev->gfx.mec_fw);
 548         }
 549
 550         return err;
 551 }
 552
 553 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev)
 554 {
 555         u32 count = 0;
 556         const struct cs_section_def *sect = NULL;
 557         const struct cs_extent_def *ext = NULL;
 558
 559         /* begin clear state */
 560         count += 2;
 561         /* context control state */
 562         count += 3;
 563
 564         for (sect = gfx11_cs_data; sect->section != NULL; ++sect) {
 565                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 566                         if (sect->id == SECT_CONTEXT)
 567                                 count += 2 + ext->reg_count;
 568                         else
 569                                 return 0;
 570                 }
 571         }
 572
 573         /* set PA_SC_TILE_STEERING_OVERRIDE */
 574         count += 3;
 575         /* end clear state */
 576         count += 2;
 577         /* clear state */
 578         count += 2;
 579
 580         return count;
 581 }
 582
 583 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev,
 584                                     volatile u32 *buffer)
 585 {
 586         u32 count = 0, i;
 587         const struct cs_section_def *sect = NULL;
 588         const struct cs_extent_def *ext = NULL;
 589         int ctx_reg_offset;
 590
 591         if (adev->gfx.rlc.cs_data == NULL)
 592                 return;
 593         if (buffer == NULL)
 594                 return;
 595
 596         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 597         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 598
 599         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 600         buffer[count++] = cpu_to_le32(0x80000000);
 601         buffer[count++] = cpu_to_le32(0x80000000);
 602
 603         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 604                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 605                         if (sect->id == SECT_CONTEXT) {
 606                                 buffer[count++] =
 607                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 608                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 609                                                 PACKET3_SET_CONTEXT_REG_START);
 610                                 for (i = 0; i < ext->reg_count; i++)
 611                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 612                         } else {
 613                                 return;
 614                         }
 615                 }
 616         }
 617
 618         ctx_reg_offset =
 619                 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
 620         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 621         buffer[count++] = cpu_to_le32(ctx_reg_offset);
 622         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
 623
 624         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 625         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 626
 627         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 628         buffer[count++] = cpu_to_le32(0);
 629 }
 630
 631 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev)
 632 {
 633         /* clear state block */
 634         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
 635                         &adev->gfx.rlc.clear_state_gpu_addr,
 636                         (void **)&adev->gfx.rlc.cs_ptr);
 637
 638         /* jump table block */
 639         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
 640                         &adev->gfx.rlc.cp_table_gpu_addr,
 641                         (void **)&adev->gfx.rlc.cp_table_ptr);
 642 }
 643
 644 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
 645 {
 646         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
 647
 648         reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
 649         reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
 650         reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1);
 651         reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2);
 652         reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3);
 653         reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL);
 654         reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);
 655         reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0);
 656         adev->gfx.rlc.rlcg_reg_access_supported = true;
 657 }
 658
 659 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev)
 660 {
 661         const struct cs_section_def *cs_data;
 662         int r;
 663
 664         adev->gfx.rlc.cs_data = gfx11_cs_data;
 665
 666         cs_data = adev->gfx.rlc.cs_data;
 667
 668         if (cs_data) {
 669                 /* init clear state block */
 670                 r = amdgpu_gfx_rlc_init_csb(adev);
 671                 if (r)
 672                         return r;
 673         }
 674
 675         /* init spm vmid with 0xf */
 676         if (adev->gfx.rlc.funcs->update_spm_vmid)
 677                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
 678
 679         return 0;
 680 }
 681
 682 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev)
 683 {
 684         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
 685         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
 686         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL);
 687 }
 688
 689 static void gfx_v11_0_me_init(struct amdgpu_device *adev)
 690 {
 691         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 692
 693         amdgpu_gfx_graphics_queue_acquire(adev);
 694 }
 695
 696 static int gfx_v11_0_mec_init(struct amdgpu_device *adev)
 697 {
 698         int r;
 699         u32 *hpd;
 700         size_t mec_hpd_size;
 701
 702         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 703
 704         /* take ownership of the relevant compute queues */
 705         amdgpu_gfx_compute_queue_acquire(adev);
 706         mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE;
 707
 708         if (mec_hpd_size) {
 709                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
 710                                               AMDGPU_GEM_DOMAIN_GTT,
 711                                               &adev->gfx.mec.hpd_eop_obj,
 712                                               &adev->gfx.mec.hpd_eop_gpu_addr,
 713                                               (void **)&hpd);
 714                 if (r) {
 715                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 716                         gfx_v11_0_mec_fini(adev);
 717                         return r;
 718                 }
 719
 720                 memset(hpd, 0, mec_hpd_size);
 721
 722                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 723                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 724         }
 725
 726         return 0;
 727 }
 728
 729 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
 730 {
 731         WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
 732                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 733                 (address << SQ_IND_INDEX__INDEX__SHIFT));
 734         return RREG32_SOC15(GC, 0, regSQ_IND_DATA);
 735 }
 736
 737 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
 738                            uint32_t thread, uint32_t regno,
 739                            uint32_t num, uint32_t *out)
 740 {
 741         WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
 742                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 743                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
 744                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
 745                 (SQ_IND_INDEX__AUTO_INCR_MASK));
 746         while (num--)
 747                 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);
 748 }
 749
 750 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
 751 {
 752         /* in gfx11 the SIMD_ID is specified as part of the INSTANCE
 753          * field when performing a select_se_sh so it should be
 754          * zero here */
 755         WARN_ON(simd != 0);
 756
 757         /* type 3 wave data */
 758         dst[(*no_fields)++] = 3;
 759         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
 760         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
 761         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
 762         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
 763         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
 764         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
 765         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
 766         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
 767         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
 768         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
 769         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
 770         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
 771         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
 772         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
 773         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
 774 }
 775
 776 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
 777                                      uint32_t wave, uint32_t start,
 778                                      uint32_t size, uint32_t *dst)
 779 {
 780         WARN_ON(simd != 0);
 781
 782         wave_read_regs(
 783                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
 784                 dst);
 785 }
 786
 787 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
 788                                       uint32_t wave, uint32_t thread,
 789                                       uint32_t start, uint32_t size,
 790                                       uint32_t *dst)
 791 {
 792         wave_read_regs(
 793                 adev, wave, thread,
 794                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
 795 }
 796
 797 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev,
 798                                                                           u32 me, u32 pipe, u32 q, u32 vm)
 799 {
 800         soc21_grbm_select(adev, me, pipe, q, vm);
 801 }
 802
 803 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = {
 804         .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter,
 805         .select_se_sh = &gfx_v11_0_select_se_sh,
 806         .read_wave_data = &gfx_v11_0_read_wave_data,
 807         .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs,
 808         .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs,
 809         .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q,
 810         .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk,
 811 };
 812
 813 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)
 814 {
 815
 816         switch (adev->ip_versions[GC_HWIP][0]) {
 817         case IP_VERSION(11, 0, 0):
 818         case IP_VERSION(11, 0, 2):
 819                 adev->gfx.config.max_hw_contexts = 8;
 820                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 821                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 822                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
 823                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
 824                 break;
 825         case IP_VERSION(11, 0, 3):
 826                 adev->gfx.ras = &gfx_v11_0_3_ras;
 827                 adev->gfx.config.max_hw_contexts = 8;
 828                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 829                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 830                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
 831                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
 832                 break;
 833         case IP_VERSION(11, 0, 1):
 834         case IP_VERSION(11, 0, 4):
 835                 adev->gfx.config.max_hw_contexts = 8;
 836                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 837                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 838                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;
 839                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300;
 840                 break;
 841         default:
 842                 BUG();
 843                 break;
 844         }
 845
 846         return 0;
 847 }
 848
 849 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
 850                                    int me, int pipe, int queue)
 851 {
 852         int r;
 853         struct amdgpu_ring *ring;
 854         unsigned int irq_type;
 855
 856         ring = &adev->gfx.gfx_ring[ring_id];
 857
 858         ring->me = me;
 859         ring->pipe = pipe;
 860         ring->queue = queue;
 861
 862         ring->ring_obj = NULL;
 863         ring->use_doorbell = true;
 864
 865         if (!ring_id)
 866                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
 867         else
 868                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
 869         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 870
 871         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
 872         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
 873                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 874         if (r)
 875                 return r;
 876         return 0;
 877 }
 878
 879 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
 880                                        int mec, int pipe, int queue)
 881 {
 882         int r;
 883         unsigned irq_type;
 884         struct amdgpu_ring *ring;
 885         unsigned int hw_prio;
 886
 887         ring = &adev->gfx.compute_ring[ring_id];
 888
 889         /* mec0 is me1 */
 890         ring->me = mec + 1;
 891         ring->pipe = pipe;
 892         ring->queue = queue;
 893
 894         ring->ring_obj = NULL;
 895         ring->use_doorbell = true;
 896         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
 897         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
 898                                 + (ring_id * GFX11_MEC_HPD_SIZE);
 899         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 900
 901         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
 902                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
 903                 + ring->pipe;
 904         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
 905                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
 906         /* type-2 packets are deprecated on MEC, use type-3 instead */
 907         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
 908                              hw_prio, NULL);
 909         if (r)
 910                 return r;
 911
 912         return 0;
 913 }
 914
 915 static struct {
 916         SOC21_FIRMWARE_ID       id;
 917         unsigned int            offset;
 918         unsigned int            size;
 919 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX];
 920
 921 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc)
 922 {
 923         RLC_TABLE_OF_CONTENT *ucode = rlc_toc;
 924
 925         while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) &&
 926                         (ucode->id < SOC21_FIRMWARE_ID_MAX)) {
 927                 rlc_autoload_info[ucode->id].id = ucode->id;
 928                 rlc_autoload_info[ucode->id].offset = ucode->offset * 4;
 929                 rlc_autoload_info[ucode->id].size = ucode->size * 4;
 930
 931                 ucode++;
 932         }
 933 }
 934
 935 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev)
 936 {
 937         uint32_t total_size = 0;
 938         SOC21_FIRMWARE_ID id;
 939
 940         gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr);
 941
 942         for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++)
 943                 total_size += rlc_autoload_info[id].size;
 944
 945         /* In case the offset in rlc toc ucode is aligned */
 946         if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset)
 947                 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset +
 948                         rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size;
 949
 950         return total_size;
 951 }
 952
 953 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev)
 954 {
 955         int r;
 956         uint32_t total_size;
 957
 958         total_size = gfx_v11_0_calc_toc_total_size(adev);
 959
 960         r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024,
 961                                       AMDGPU_GEM_DOMAIN_VRAM |
 962                                       AMDGPU_GEM_DOMAIN_GTT,
 963                                       &adev->gfx.rlc.rlc_autoload_bo,
 964                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
 965                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
 966
 967         if (r) {
 968                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
 969                 return r;
 970         }
 971
 972         return 0;
 973 }
 974
 975 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
 976                                               SOC21_FIRMWARE_ID id,
 977                                               const void *fw_data,
 978                                               uint32_t fw_size,
 979                                               uint32_t *fw_autoload_mask)
 980 {
 981         uint32_t toc_offset;
 982         uint32_t toc_fw_size;
 983         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
 984
 985         if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX)
 986                 return;
 987
 988         toc_offset = rlc_autoload_info[id].offset;
 989         toc_fw_size = rlc_autoload_info[id].size;
 990
 991         if (fw_size == 0)
 992                 fw_size = toc_fw_size;
 993
 994         if (fw_size > toc_fw_size)
 995                 fw_size = toc_fw_size;
 996
 997         memcpy(ptr + toc_offset, fw_data, fw_size);
 998
 999         if (fw_size < toc_fw_size)
1000                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
1001
1002         if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME))
1003                 *(uint64_t *)fw_autoload_mask |= 1ULL << id;
1004 }
1005
1006 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev,
1007                                                         uint32_t *fw_autoload_mask)
1008 {
1009         void *data;
1010         uint32_t size;
1011         uint64_t *toc_ptr;
1012
1013         *(uint64_t *)fw_autoload_mask |= 0x1;
1014
1015         DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask);
1016
1017         data = adev->psp.toc.start_addr;
1018         size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size;
1019
1020         toc_ptr = (uint64_t *)data + size / 8 - 1;
1021         *toc_ptr = *(uint64_t *)fw_autoload_mask;
1022
1023         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC,
1024                                         data, size, fw_autoload_mask);
1025 }
1026
1027 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev,
1028                                                         uint32_t *fw_autoload_mask)
1029 {
1030         const __le32 *fw_data;
1031         uint32_t fw_size;
1032         const struct gfx_firmware_header_v1_0 *cp_hdr;
1033         const struct gfx_firmware_header_v2_0 *cpv2_hdr;
1034         const struct rlc_firmware_header_v2_0 *rlc_hdr;
1035         const struct rlc_firmware_header_v2_2 *rlcv22_hdr;
1036         uint16_t version_major, version_minor;
1037
1038         if (adev->gfx.rs64_enable) {
1039                 /* pfp ucode */
1040                 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1041                         adev->gfx.pfp_fw->data;
1042                 /* instruction */
1043                 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1044                         le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1045                 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1046                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP,
1047                                                 fw_data, fw_size, fw_autoload_mask);
1048                 /* data */
1049                 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1050                         le32_to_cpu(cpv2_hdr->data_offset_bytes));
1051                 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1052                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK,
1053                                                 fw_data, fw_size, fw_autoload_mask);
1054                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK,
1055                                                 fw_data, fw_size, fw_autoload_mask);
1056                 /* me ucode */
1057                 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1058                         adev->gfx.me_fw->data;
1059                 /* instruction */
1060                 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1061                         le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1062                 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1063                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME,
1064                                                 fw_data, fw_size, fw_autoload_mask);
1065                 /* data */
1066                 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1067                         le32_to_cpu(cpv2_hdr->data_offset_bytes));
1068                 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1069                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK,
1070                                                 fw_data, fw_size, fw_autoload_mask);
1071                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK,
1072                                                 fw_data, fw_size, fw_autoload_mask);
1073                 /* mec ucode */
1074                 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1075                         adev->gfx.mec_fw->data;
1076                 /* instruction */
1077                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1078                         le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1079                 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1080                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC,
1081                                                 fw_data, fw_size, fw_autoload_mask);
1082                 /* data */
1083                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1084                         le32_to_cpu(cpv2_hdr->data_offset_bytes));
1085                 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1086                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK,
1087                                                 fw_data, fw_size, fw_autoload_mask);
1088                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK,
1089                                                 fw_data, fw_size, fw_autoload_mask);
1090                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK,
1091                                                 fw_data, fw_size, fw_autoload_mask);
1092                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK,
1093                                                 fw_data, fw_size, fw_autoload_mask);
1094         } else {
1095                 /* pfp ucode */
1096                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1097                         adev->gfx.pfp_fw->data;
1098                 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1099                                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1100                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1101                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP,
1102                                                 fw_data, fw_size, fw_autoload_mask);
1103
1104                 /* me ucode */
1105                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1106                         adev->gfx.me_fw->data;
1107                 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1108                                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1109                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1110                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME,
1111                                                 fw_data, fw_size, fw_autoload_mask);
1112
1113                 /* mec ucode */
1114                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1115                         adev->gfx.mec_fw->data;
1116                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1117                                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1118                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1119                         cp_hdr->jt_size * 4;
1120                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC,
1121                                                 fw_data, fw_size, fw_autoload_mask);
1122         }
1123
1124         /* rlc ucode */
1125         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
1126                 adev->gfx.rlc_fw->data;
1127         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1128                         le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
1129         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
1130         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE,
1131                                         fw_data, fw_size, fw_autoload_mask);
1132
1133         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
1134         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
1135         if (version_major == 2) {
1136                 if (version_minor >= 2) {
1137                         rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1138
1139                         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1140                                         le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes));
1141                         fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes);
1142                         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE,
1143                                         fw_data, fw_size, fw_autoload_mask);
1144
1145                         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1146                                         le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes));
1147                         fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes);
1148                         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT,
1149                                         fw_data, fw_size, fw_autoload_mask);
1150                 }
1151         }
1152 }
1153
1154 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev,
1155                                                         uint32_t *fw_autoload_mask)
1156 {
1157         const __le32 *fw_data;
1158         uint32_t fw_size;
1159         const struct sdma_firmware_header_v2_0 *sdma_hdr;
1160
1161         sdma_hdr = (const struct sdma_firmware_header_v2_0 *)
1162                 adev->sdma.instance[0].fw->data;
1163         fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1164                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
1165         fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes);
1166
1167         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1168                         SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask);
1169
1170         fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1171                         le32_to_cpu(sdma_hdr->ctl_ucode_offset));
1172         fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes);
1173
1174         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1175                         SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask);
1176 }
1177
1178 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev,
1179                                                         uint32_t *fw_autoload_mask)
1180 {
1181         const __le32 *fw_data;
1182         unsigned fw_size;
1183         const struct mes_firmware_header_v1_0 *mes_hdr;
1184         int pipe, ucode_id, data_id;
1185
1186         for (pipe = 0; pipe < 2; pipe++) {
1187                 if (pipe==0) {
1188                         ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0;
1189                         data_id  = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK;
1190                 } else {
1191                         ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1;
1192                         data_id  = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK;
1193                 }
1194
1195                 mes_hdr = (const struct mes_firmware_header_v1_0 *)
1196                         adev->mes.fw[pipe]->data;
1197
1198                 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1199                                 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
1200                 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
1201
1202                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1203                                 ucode_id, fw_data, fw_size, fw_autoload_mask);
1204
1205                 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1206                                 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
1207                 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
1208
1209                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1210                                 data_id, fw_data, fw_size, fw_autoload_mask);
1211         }
1212 }
1213
1214 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
1215 {
1216         uint32_t rlc_g_offset, rlc_g_size;
1217         uint64_t gpu_addr;
1218         uint32_t autoload_fw_id[2];
1219
1220         memset(autoload_fw_id, 0, sizeof(uint32_t) * 2);
1221
1222         /* RLC autoload sequence 2: copy ucode */
1223         gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id);
1224         gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id);
1225         gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id);
1226         gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id);
1227
1228         rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset;
1229         rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size;
1230         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
1231
1232         WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));
1233         WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
1234
1235         WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);
1236
1237         /* RLC autoload sequence 3: load IMU fw */
1238         if (adev->gfx.imu.funcs->load_microcode)
1239                 adev->gfx.imu.funcs->load_microcode(adev);
1240         /* RLC autoload sequence 4 init IMU fw */
1241         if (adev->gfx.imu.funcs->setup_imu)
1242                 adev->gfx.imu.funcs->setup_imu(adev);
1243         if (adev->gfx.imu.funcs->start_imu)
1244                 adev->gfx.imu.funcs->start_imu(adev);
1245
1246         /* RLC autoload sequence 5 disable gpa mode */
1247         gfx_v11_0_disable_gpa_mode(adev);
1248
1249         return 0;
1250 }
1251
1252 static int gfx_v11_0_sw_init(void *handle)
1253 {
1254         int i, j, k, r, ring_id = 0;
1255         struct amdgpu_kiq *kiq;
1256         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1257
1258         adev->gfxhub.funcs->init(adev);
1259
1260         switch (adev->ip_versions[GC_HWIP][0]) {
1261         case IP_VERSION(11, 0, 0):
1262         case IP_VERSION(11, 0, 2):
1263         case IP_VERSION(11, 0, 3):
1264                 adev->gfx.me.num_me = 1;
1265                 adev->gfx.me.num_pipe_per_me = 1;
1266                 adev->gfx.me.num_queue_per_pipe = 1;
1267                 adev->gfx.mec.num_mec = 2;
1268                 adev->gfx.mec.num_pipe_per_mec = 4;
1269                 adev->gfx.mec.num_queue_per_pipe = 4;
1270                 break;
1271         case IP_VERSION(11, 0, 1):
1272         case IP_VERSION(11, 0, 4):
1273                 adev->gfx.me.num_me = 1;
1274                 adev->gfx.me.num_pipe_per_me = 1;
1275                 adev->gfx.me.num_queue_per_pipe = 1;
1276                 adev->gfx.mec.num_mec = 1;
1277                 adev->gfx.mec.num_pipe_per_mec = 4;
1278                 adev->gfx.mec.num_queue_per_pipe = 4;
1279                 break;
1280         default:
1281                 adev->gfx.me.num_me = 1;
1282                 adev->gfx.me.num_pipe_per_me = 1;
1283                 adev->gfx.me.num_queue_per_pipe = 1;
1284                 adev->gfx.mec.num_mec = 1;
1285                 adev->gfx.mec.num_pipe_per_mec = 4;
1286                 adev->gfx.mec.num_queue_per_pipe = 8;
1287                 break;
1288         }
1289
1290         /* EOP Event */
1291         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1292                               GFX_11_0_0__SRCID__CP_EOP_INTERRUPT,
1293                               &adev->gfx.eop_irq);
1294         if (r)
1295                 return r;
1296
1297         /* Privileged reg */
1298         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1299                               GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT,
1300                               &adev->gfx.priv_reg_irq);
1301         if (r)
1302                 return r;
1303
1304         /* Privileged inst */
1305         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1306                               GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT,
1307                               &adev->gfx.priv_inst_irq);
1308         if (r)
1309                 return r;
1310
1311         /* ECC error */
1312         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1313                                   GFX_11_0_0__SRCID__CP_ECC_ERROR,
1314                                   &adev->gfx.cp_ecc_error_irq);
1315         if (r)
1316                 return r;
1317
1318         /* FED error */
1319         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1320                                   GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT,
1321                                   &adev->gfx.rlc_gc_fed_irq);
1322         if (r)
1323                 return r;
1324
1325         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1326
1327         if (adev->gfx.imu.funcs) {
1328                 if (adev->gfx.imu.funcs->init_microcode) {
1329                         r = adev->gfx.imu.funcs->init_microcode(adev);
1330                         if (r)
1331                                 DRM_ERROR("Failed to load imu firmware!\n");
1332                 }
1333         }
1334
1335         gfx_v11_0_me_init(adev);
1336
1337         r = gfx_v11_0_rlc_init(adev);
1338         if (r) {
1339                 DRM_ERROR("Failed to init rlc BOs!\n");
1340                 return r;
1341         }
1342
1343         r = gfx_v11_0_mec_init(adev);
1344         if (r) {
1345                 DRM_ERROR("Failed to init MEC BOs!\n");
1346                 return r;
1347         }
1348
1349         /* set up the gfx ring */
1350         for (i = 0; i < adev->gfx.me.num_me; i++) {
1351                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1352                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1353                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1354                                         continue;
1355
1356                                 r = gfx_v11_0_gfx_ring_init(adev, ring_id,
1357                                                             i, k, j);
1358                                 if (r)
1359                                         return r;
1360                                 ring_id++;
1361                         }
1362                 }
1363         }
1364
1365         ring_id = 0;
1366         /* set up the compute queues - allocate horizontally across pipes */
1367         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1368                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1369                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1370                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
1371                                                                      j))
1372                                         continue;
1373
1374                                 r = gfx_v11_0_compute_ring_init(adev, ring_id,
1375                                                                 i, k, j);
1376                                 if (r)
1377                                         return r;
1378
1379                                 ring_id++;
1380                         }
1381                 }
1382         }
1383
1384         if (!adev->enable_mes_kiq) {
1385                 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE);
1386                 if (r) {
1387                         DRM_ERROR("Failed to init KIQ BOs!\n");
1388                         return r;
1389                 }
1390
1391                 kiq = &adev->gfx.kiq;
1392                 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1393                 if (r)
1394                         return r;
1395         }
1396
1397         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd));
1398         if (r)
1399                 return r;
1400
1401         /* allocate visible FB for rlc auto-loading fw */
1402         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1403                 r = gfx_v11_0_rlc_autoload_buffer_init(adev);
1404                 if (r)
1405                         return r;
1406         }
1407
1408         r = gfx_v11_0_gpu_early_init(adev);
1409         if (r)
1410                 return r;
1411
1412         if (amdgpu_gfx_ras_sw_init(adev)) {
1413                 dev_err(adev->dev, "Failed to initialize gfx ras block!\n");
1414                 return -EINVAL;
1415         }
1416
1417         return 0;
1418 }
1419
1420 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev)
1421 {
1422         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1423                               &adev->gfx.pfp.pfp_fw_gpu_addr,
1424                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
1425
1426         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj,
1427                               &adev->gfx.pfp.pfp_fw_data_gpu_addr,
1428                               (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
1429 }
1430
1431 static void gfx_v11_0_me_fini(struct amdgpu_device *adev)
1432 {
1433         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1434                               &adev->gfx.me.me_fw_gpu_addr,
1435                               (void **)&adev->gfx.me.me_fw_ptr);
1436
1437         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj,
1438                                &adev->gfx.me.me_fw_data_gpu_addr,
1439                                (void **)&adev->gfx.me.me_fw_data_ptr);
1440 }
1441
1442 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev)
1443 {
1444         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
1445                         &adev->gfx.rlc.rlc_autoload_gpu_addr,
1446                         (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1447 }
1448
1449 static int gfx_v11_0_sw_fini(void *handle)
1450 {
1451         int i;
1452         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1453
1454         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1455                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1456         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1457                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1458
1459         amdgpu_gfx_mqd_sw_fini(adev);
1460
1461         if (!adev->enable_mes_kiq) {
1462                 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
1463                 amdgpu_gfx_kiq_fini(adev);
1464         }
1465
1466         gfx_v11_0_pfp_fini(adev);
1467         gfx_v11_0_me_fini(adev);
1468         gfx_v11_0_rlc_fini(adev);
1469         gfx_v11_0_mec_fini(adev);
1470
1471         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1472                 gfx_v11_0_rlc_autoload_buffer_fini(adev);
1473
1474         gfx_v11_0_free_microcode(adev);
1475
1476         return 0;
1477 }
1478
1479 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1480                                    u32 sh_num, u32 instance)
1481 {
1482         u32 data;
1483
1484         if (instance == 0xffffffff)
1485                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1486                                      INSTANCE_BROADCAST_WRITES, 1);
1487         else
1488                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1489                                      instance);
1490
1491         if (se_num == 0xffffffff)
1492                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1493                                      1);
1494         else
1495                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1496
1497         if (sh_num == 0xffffffff)
1498                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1499                                      1);
1500         else
1501                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1502
1503         WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);
1504 }
1505
1506 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1507 {
1508         u32 data, mask;
1509
1510         data = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);
1511         data |= RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);
1512
1513         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1514         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1515
1516         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1517                                          adev->gfx.config.max_sh_per_se);
1518
1519         return (~data) & mask;
1520 }
1521
1522 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev)
1523 {
1524         int i, j;
1525         u32 data;
1526         u32 active_rbs = 0;
1527         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1528                                         adev->gfx.config.max_sh_per_se;
1529
1530         mutex_lock(&adev->grbm_idx_mutex);
1531         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1532                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1533                         gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff);
1534                         data = gfx_v11_0_get_rb_active_bitmap(adev);
1535                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1536                                                rb_bitmap_width_per_sh);
1537                 }
1538         }
1539         gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1540         mutex_unlock(&adev->grbm_idx_mutex);
1541
1542         adev->gfx.config.backend_enable_mask = active_rbs;
1543         adev->gfx.config.num_rbs = hweight32(active_rbs);
1544 }
1545
1546 #define DEFAULT_SH_MEM_BASES    (0x6000)
1547 #define LDS_APP_BASE           0x1
1548 #define SCRATCH_APP_BASE       0x2
1549
1550 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev)
1551 {
1552         int i;
1553         uint32_t sh_mem_bases;
1554         uint32_t data;
1555
1556         /*
1557          * Configure apertures:
1558          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1559          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1560          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1561          */
1562         sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) |
1563                         SCRATCH_APP_BASE;
1564
1565         mutex_lock(&adev->srbm_mutex);
1566         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1567                 soc21_grbm_select(adev, 0, 0, 0, i);
1568                 /* CP and shaders */
1569                 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1570                 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases);
1571
1572                 /* Enable trap for each kfd vmid. */
1573                 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);
1574                 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
1575         }
1576         soc21_grbm_select(adev, 0, 0, 0, 0);
1577         mutex_unlock(&adev->srbm_mutex);
1578
1579         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
1580            acccess. These should be enabled by FW for target VMIDs. */
1581         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1582                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0);
1583                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0);
1584                 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0);
1585                 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0);
1586         }
1587 }
1588
1589 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev)
1590 {
1591         int vmid;
1592
1593         /*
1594          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1595          * access. Compute VMIDs should be enabled by FW for target VMIDs,
1596          * the driver can enable them for graphics. VMID0 should maintain
1597          * access so that HWS firmware can save/restore entries.
1598          */
1599         for (vmid = 1; vmid < 16; vmid++) {
1600                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0);
1601                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0);
1602                 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0);
1603                 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0);
1604         }
1605 }
1606
1607 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev)
1608 {
1609         /* TODO: harvest feature to be added later. */
1610 }
1611
1612 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev)
1613 {
1614         /* TCCs are global (not instanced). */
1615         uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) |
1616                                RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE);
1617
1618         adev->gfx.config.tcc_disabled_mask =
1619                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
1620                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
1621 }
1622
1623 static void gfx_v11_0_constants_init(struct amdgpu_device *adev)
1624 {
1625         u32 tmp;
1626         int i;
1627
1628         if (!amdgpu_sriov_vf(adev))
1629                 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1630
1631         gfx_v11_0_setup_rb(adev);
1632         gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info);
1633         gfx_v11_0_get_tcc_info(adev);
1634         adev->gfx.config.pa_sc_tile_steering_override = 0;
1635
1636         /* XXX SH_MEM regs */
1637         /* where to put LDS, scratch, GPUVM in FSA64 space */
1638         mutex_lock(&adev->srbm_mutex);
1639         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
1640                 soc21_grbm_select(adev, 0, 0, 0, i);
1641                 /* CP and shaders */
1642                 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1643                 if (i != 0) {
1644                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1645                                 (adev->gmc.private_aperture_start >> 48));
1646                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1647                                 (adev->gmc.shared_aperture_start >> 48));
1648                         WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp);
1649                 }
1650         }
1651         soc21_grbm_select(adev, 0, 0, 0, 0);
1652
1653         mutex_unlock(&adev->srbm_mutex);
1654
1655         gfx_v11_0_init_compute_vmid(adev);
1656         gfx_v11_0_init_gds_vmid(adev);
1657 }
1658
1659 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1660                                                bool enable)
1661 {
1662         u32 tmp;
1663
1664         if (amdgpu_sriov_vf(adev))
1665                 return;
1666
1667         tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0);
1668
1669         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1670                             enable ? 1 : 0);
1671         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1672                             enable ? 1 : 0);
1673         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1674                             enable ? 1 : 0);
1675         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1676                             enable ? 1 : 0);
1677
1678         WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp);
1679 }
1680
1681 static int gfx_v11_0_init_csb(struct amdgpu_device *adev)
1682 {
1683         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
1684
1685         WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI,
1686                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
1687         WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO,
1688                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1689         WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1690
1691         return 0;
1692 }
1693
1694 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev)
1695 {
1696         u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);
1697
1698         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1699         WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);
1700 }
1701
1702 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev)
1703 {
1704         WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1705         udelay(50);
1706         WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1707         udelay(50);
1708 }
1709
1710 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1711                                              bool enable)
1712 {
1713         uint32_t rlc_pg_cntl;
1714
1715         rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
1716
1717         if (!enable) {
1718                 /* RLC_PG_CNTL[23] = 0 (default)
1719                  * RLC will wait for handshake acks with SMU
1720                  * GFXOFF will be enabled
1721                  * RLC_PG_CNTL[23] = 1
1722                  * RLC will not issue any message to SMU
1723                  * hence no handshake between SMU & RLC
1724                  * GFXOFF will be disabled
1725                  */
1726                 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1727         } else
1728                 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1729         WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl);
1730 }
1731
1732 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev)
1733 {
1734         /* TODO: enable rlc & smu handshake until smu
1735          * and gfxoff feature works as expected */
1736         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1737                 gfx_v11_0_rlc_smu_handshake_cntl(adev, false);
1738
1739         WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1740         udelay(50);
1741 }
1742
1743 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev)
1744 {
1745         uint32_t tmp;
1746
1747         /* enable Save Restore Machine */
1748         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
1749         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1750         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1751         WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
1752 }
1753
1754 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev)
1755 {
1756         const struct rlc_firmware_header_v2_0 *hdr;
1757         const __le32 *fw_data;
1758         unsigned i, fw_size;
1759
1760         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1761         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1762                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1763         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1764
1765         WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR,
1766                      RLCG_UCODE_LOADING_START_ADDRESS);
1767
1768         for (i = 0; i < fw_size; i++)
1769                 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA,
1770                              le32_to_cpup(fw_data++));
1771
1772         WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1773 }
1774
1775 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev)
1776 {
1777         const struct rlc_firmware_header_v2_2 *hdr;
1778         const __le32 *fw_data;
1779         unsigned i, fw_size;
1780         u32 tmp;
1781
1782         hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1783
1784         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1785                         le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes));
1786         fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4;
1787
1788         WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0);
1789
1790         for (i = 0; i < fw_size; i++) {
1791                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1792                         msleep(1);
1793                 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA,
1794                                 le32_to_cpup(fw_data++));
1795         }
1796
1797         WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
1798
1799         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1800                         le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes));
1801         fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4;
1802
1803         WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0);
1804         for (i = 0; i < fw_size; i++) {
1805                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1806                         msleep(1);
1807                 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA,
1808                                 le32_to_cpup(fw_data++));
1809         }
1810
1811         WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
1812
1813         tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);
1814         tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);
1815         tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);
1816         WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp);
1817 }
1818
1819 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev)
1820 {
1821         const struct rlc_firmware_header_v2_3 *hdr;
1822         const __le32 *fw_data;
1823         unsigned i, fw_size;
1824         u32 tmp;
1825
1826         hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data;
1827
1828         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1829                         le32_to_cpu(hdr->rlcp_ucode_offset_bytes));
1830         fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4;
1831
1832         WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0);
1833
1834         for (i = 0; i < fw_size; i++) {
1835                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1836                         msleep(1);
1837                 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA,
1838                                 le32_to_cpup(fw_data++));
1839         }
1840
1841         WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version);
1842
1843         tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);
1844         tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);
1845         WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp);
1846
1847         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1848                         le32_to_cpu(hdr->rlcv_ucode_offset_bytes));
1849         fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4;
1850
1851         WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0);
1852
1853         for (i = 0; i < fw_size; i++) {
1854                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1855                         msleep(1);
1856                 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA,
1857                                 le32_to_cpup(fw_data++));
1858         }
1859
1860         WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version);
1861
1862         tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL);
1863         tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1);
1864         WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp);
1865 }
1866
1867 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev)
1868 {
1869         const struct rlc_firmware_header_v2_0 *hdr;
1870         uint16_t version_major;
1871         uint16_t version_minor;
1872
1873         if (!adev->gfx.rlc_fw)
1874                 return -EINVAL;
1875
1876         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1877         amdgpu_ucode_print_rlc_hdr(&hdr->header);
1878
1879         version_major = le16_to_cpu(hdr->header.header_version_major);
1880         version_minor = le16_to_cpu(hdr->header.header_version_minor);
1881
1882         if (version_major == 2) {
1883                 gfx_v11_0_load_rlcg_microcode(adev);
1884                 if (amdgpu_dpm == 1) {
1885                         if (version_minor >= 2)
1886                                 gfx_v11_0_load_rlc_iram_dram_microcode(adev);
1887                         if (version_minor == 3)
1888                                 gfx_v11_0_load_rlcp_rlcv_microcode(adev);
1889                 }
1890
1891                 return 0;
1892         }
1893
1894         return -EINVAL;
1895 }
1896
1897 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev)
1898 {
1899         int r;
1900
1901         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1902                 gfx_v11_0_init_csb(adev);
1903
1904                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
1905                         gfx_v11_0_rlc_enable_srm(adev);
1906         } else {
1907                 if (amdgpu_sriov_vf(adev)) {
1908                         gfx_v11_0_init_csb(adev);
1909                         return 0;
1910                 }
1911
1912                 adev->gfx.rlc.funcs->stop(adev);
1913
1914                 /* disable CG */
1915                 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0);
1916
1917                 /* disable PG */
1918                 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0);
1919
1920                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1921                         /* legacy rlc firmware loading */
1922                         r = gfx_v11_0_rlc_load_microcode(adev);
1923                         if (r)
1924                                 return r;
1925                 }
1926
1927                 gfx_v11_0_init_csb(adev);
1928
1929                 adev->gfx.rlc.funcs->start(adev);
1930         }
1931         return 0;
1932 }
1933
1934 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr)
1935 {
1936         uint32_t usec_timeout = 50000;  /* wait for 50ms */
1937         uint32_t tmp;
1938         int i;
1939
1940         /* Trigger an invalidation of the L1 instruction caches */
1941         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
1942         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
1943         WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
1944
1945         /* Wait for invalidation complete */
1946         for (i = 0; i < usec_timeout; i++) {
1947                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
1948                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
1949                                         INVALIDATE_CACHE_COMPLETE))
1950                         break;
1951                 udelay(1);
1952         }
1953
1954         if (i >= usec_timeout) {
1955                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
1956                 return -EINVAL;
1957         }
1958
1959         if (amdgpu_emu_mode == 1)
1960                 adev->hdp.funcs->flush_hdp(adev, NULL);
1961
1962         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
1963         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
1964         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
1965         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
1966         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
1967         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
1968
1969         /* Program me ucode address into intruction cache address register */
1970         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
1971                         lower_32_bits(addr) & 0xFFFFF000);
1972         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
1973                         upper_32_bits(addr));
1974
1975         return 0;
1976 }
1977
1978 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr)
1979 {
1980         uint32_t usec_timeout = 50000;  /* wait for 50ms */
1981         uint32_t tmp;
1982         int i;
1983
1984         /* Trigger an invalidation of the L1 instruction caches */
1985         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
1986         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
1987         WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
1988
1989         /* Wait for invalidation complete */
1990         for (i = 0; i < usec_timeout; i++) {
1991                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
1992                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
1993                                         INVALIDATE_CACHE_COMPLETE))
1994                         break;
1995                 udelay(1);
1996         }
1997
1998         if (i >= usec_timeout) {
1999                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2000                 return -EINVAL;
2001         }
2002
2003         if (amdgpu_emu_mode == 1)
2004                 adev->hdp.funcs->flush_hdp(adev, NULL);
2005
2006         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2007         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2008         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2009         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2010         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2011         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2012
2013         /* Program pfp ucode address into intruction cache address register */
2014         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2015                         lower_32_bits(addr) & 0xFFFFF000);
2016         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2017                         upper_32_bits(addr));
2018
2019         return 0;
2020 }
2021
2022 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr)
2023 {
2024         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2025         uint32_t tmp;
2026         int i;
2027
2028         /* Trigger an invalidation of the L1 instruction caches */
2029         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2030         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2031
2032         WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2033
2034         /* Wait for invalidation complete */
2035         for (i = 0; i < usec_timeout; i++) {
2036                 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2037                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2038                                         INVALIDATE_CACHE_COMPLETE))
2039                         break;
2040                 udelay(1);
2041         }
2042
2043         if (i >= usec_timeout) {
2044                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2045                 return -EINVAL;
2046         }
2047
2048         if (amdgpu_emu_mode == 1)
2049                 adev->hdp.funcs->flush_hdp(adev, NULL);
2050
2051         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2052         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2053         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2054         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2055         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2056
2057         /* Program mec1 ucode address into intruction cache address register */
2058         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO,
2059                         lower_32_bits(addr) & 0xFFFFF000);
2060         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2061                         upper_32_bits(addr));
2062
2063         return 0;
2064 }
2065
2066 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2067 {
2068         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2069         uint32_t tmp;
2070         unsigned i, pipe_id;
2071         const struct gfx_firmware_header_v2_0 *pfp_hdr;
2072
2073         pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2074                 adev->gfx.pfp_fw->data;
2075
2076         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2077                 lower_32_bits(addr));
2078         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2079                 upper_32_bits(addr));
2080
2081         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2082         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2083         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2084         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2085         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2086
2087         /*
2088          * Programming any of the CP_PFP_IC_BASE registers
2089          * forces invalidation of the ME L1 I$. Wait for the
2090          * invalidation complete
2091          */
2092         for (i = 0; i < usec_timeout; i++) {
2093                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2094                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2095                         INVALIDATE_CACHE_COMPLETE))
2096                         break;
2097                 udelay(1);
2098         }
2099
2100         if (i >= usec_timeout) {
2101                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2102                 return -EINVAL;
2103         }
2104
2105         /* Prime the L1 instruction caches */
2106         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2107         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
2108         WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2109         /* Waiting for cache primed*/
2110         for (i = 0; i < usec_timeout; i++) {
2111                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2112                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2113                         ICACHE_PRIMED))
2114                         break;
2115                 udelay(1);
2116         }
2117
2118         if (i >= usec_timeout) {
2119                 dev_err(adev->dev, "failed to prime instruction cache\n");
2120                 return -EINVAL;
2121         }
2122
2123         mutex_lock(&adev->srbm_mutex);
2124         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2125                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2126                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2127                         (pfp_hdr->ucode_start_addr_hi << 30) |
2128                         (pfp_hdr->ucode_start_addr_lo >> 2));
2129                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2130                         pfp_hdr->ucode_start_addr_hi >> 2);
2131
2132                 /*
2133                  * Program CP_ME_CNTL to reset given PIPE to take
2134                  * effect of CP_PFP_PRGRM_CNTR_START.
2135                  */
2136                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2137                 if (pipe_id == 0)
2138                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2139                                         PFP_PIPE0_RESET, 1);
2140                 else
2141                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2142                                         PFP_PIPE1_RESET, 1);
2143                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2144
2145                 /* Clear pfp pipe0 reset bit. */
2146                 if (pipe_id == 0)
2147                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2148                                         PFP_PIPE0_RESET, 0);
2149                 else
2150                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2151                                         PFP_PIPE1_RESET, 0);
2152                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2153
2154                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2155                         lower_32_bits(addr2));
2156                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2157                         upper_32_bits(addr2));
2158         }
2159         soc21_grbm_select(adev, 0, 0, 0, 0);
2160         mutex_unlock(&adev->srbm_mutex);
2161
2162         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2163         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2164         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2165         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2166
2167         /* Invalidate the data caches */
2168         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2169         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2170         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2171
2172         for (i = 0; i < usec_timeout; i++) {
2173                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2174                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2175                         INVALIDATE_DCACHE_COMPLETE))
2176                         break;
2177                 udelay(1);
2178         }
2179
2180         if (i >= usec_timeout) {
2181                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2182                 return -EINVAL;
2183         }
2184
2185         return 0;
2186 }
2187
2188 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2189 {
2190         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2191         uint32_t tmp;
2192         unsigned i, pipe_id;
2193         const struct gfx_firmware_header_v2_0 *me_hdr;
2194
2195         me_hdr = (const struct gfx_firmware_header_v2_0 *)
2196                 adev->gfx.me_fw->data;
2197
2198         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2199                 lower_32_bits(addr));
2200         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2201                 upper_32_bits(addr));
2202
2203         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2204         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2205         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2206         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2207         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2208
2209         /*
2210          * Programming any of the CP_ME_IC_BASE registers
2211          * forces invalidation of the ME L1 I$. Wait for the
2212          * invalidation complete
2213          */
2214         for (i = 0; i < usec_timeout; i++) {
2215                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2216                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2217                         INVALIDATE_CACHE_COMPLETE))
2218                         break;
2219                 udelay(1);
2220         }
2221
2222         if (i >= usec_timeout) {
2223                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2224                 return -EINVAL;
2225         }
2226
2227         /* Prime the instruction caches */
2228         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2229         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
2230         WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2231
2232         /* Waiting for instruction cache primed*/
2233         for (i = 0; i < usec_timeout; i++) {
2234                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2235                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2236                         ICACHE_PRIMED))
2237                         break;
2238                 udelay(1);
2239         }
2240
2241         if (i >= usec_timeout) {
2242                 dev_err(adev->dev, "failed to prime instruction cache\n");
2243                 return -EINVAL;
2244         }
2245
2246         mutex_lock(&adev->srbm_mutex);
2247         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2248                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2249                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2250                         (me_hdr->ucode_start_addr_hi << 30) |
2251                         (me_hdr->ucode_start_addr_lo >> 2) );
2252                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2253                         me_hdr->ucode_start_addr_hi>>2);
2254
2255                 /*
2256                  * Program CP_ME_CNTL to reset given PIPE to take
2257                  * effect of CP_PFP_PRGRM_CNTR_START.
2258                  */
2259                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2260                 if (pipe_id == 0)
2261                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2262                                         ME_PIPE0_RESET, 1);
2263                 else
2264                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2265                                         ME_PIPE1_RESET, 1);
2266                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2267
2268                 /* Clear pfp pipe0 reset bit. */
2269                 if (pipe_id == 0)
2270                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2271                                         ME_PIPE0_RESET, 0);
2272                 else
2273                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2274                                         ME_PIPE1_RESET, 0);
2275                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2276
2277                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
2278                         lower_32_bits(addr2));
2279                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
2280                         upper_32_bits(addr2));
2281         }
2282         soc21_grbm_select(adev, 0, 0, 0, 0);
2283         mutex_unlock(&adev->srbm_mutex);
2284
2285         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2286         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2287         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2288         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2289
2290         /* Invalidate the data caches */
2291         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2292         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2293         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2294
2295         for (i = 0; i < usec_timeout; i++) {
2296                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2297                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2298                         INVALIDATE_DCACHE_COMPLETE))
2299                         break;
2300                 udelay(1);
2301         }
2302
2303         if (i >= usec_timeout) {
2304                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2305                 return -EINVAL;
2306         }
2307
2308         return 0;
2309 }
2310
2311 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2312 {
2313         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2314         uint32_t tmp;
2315         unsigned i;
2316         const struct gfx_firmware_header_v2_0 *mec_hdr;
2317
2318         mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2319                 adev->gfx.mec_fw->data;
2320
2321         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2322         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2323         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2324         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2325         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2326
2327         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
2328         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
2329         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
2330         WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
2331
2332         mutex_lock(&adev->srbm_mutex);
2333         for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2334                 soc21_grbm_select(adev, 1, i, 0, 0);
2335
2336                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2);
2337                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
2338                      upper_32_bits(addr2));
2339
2340                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2341                                         mec_hdr->ucode_start_addr_lo >> 2 |
2342                                         mec_hdr->ucode_start_addr_hi << 30);
2343                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2344                                         mec_hdr->ucode_start_addr_hi >> 2);
2345
2346                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr);
2347                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2348                      upper_32_bits(addr));
2349         }
2350         mutex_unlock(&adev->srbm_mutex);
2351         soc21_grbm_select(adev, 0, 0, 0, 0);
2352
2353         /* Trigger an invalidation of the L1 instruction caches */
2354         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2355         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2356         WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
2357
2358         /* Wait for invalidation complete */
2359         for (i = 0; i < usec_timeout; i++) {
2360                 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2361                 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
2362                                        INVALIDATE_DCACHE_COMPLETE))
2363                         break;
2364                 udelay(1);
2365         }
2366
2367         if (i >= usec_timeout) {
2368                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2369                 return -EINVAL;
2370         }
2371
2372         /* Trigger an invalidation of the L1 instruction caches */
2373         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2374         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2375         WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2376
2377         /* Wait for invalidation complete */
2378         for (i = 0; i < usec_timeout; i++) {
2379                 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2380                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2381                                        INVALIDATE_CACHE_COMPLETE))
2382                         break;
2383                 udelay(1);
2384         }
2385
2386         if (i >= usec_timeout) {
2387                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2388                 return -EINVAL;
2389         }
2390
2391         return 0;
2392 }
2393
2394 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev)
2395 {
2396         const struct gfx_firmware_header_v2_0 *pfp_hdr;
2397         const struct gfx_firmware_header_v2_0 *me_hdr;
2398         const struct gfx_firmware_header_v2_0 *mec_hdr;
2399         uint32_t pipe_id, tmp;
2400
2401         mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2402                 adev->gfx.mec_fw->data;
2403         me_hdr = (const struct gfx_firmware_header_v2_0 *)
2404                 adev->gfx.me_fw->data;
2405         pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2406                 adev->gfx.pfp_fw->data;
2407
2408         /* config pfp program start addr */
2409         for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2410                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2411                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2412                         (pfp_hdr->ucode_start_addr_hi << 30) |
2413                         (pfp_hdr->ucode_start_addr_lo >> 2));
2414                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2415                         pfp_hdr->ucode_start_addr_hi >> 2);
2416         }
2417         soc21_grbm_select(adev, 0, 0, 0, 0);
2418
2419         /* reset pfp pipe */
2420         tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2421         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);
2422         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);
2423         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2424
2425         /* clear pfp pipe reset */
2426         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);
2427         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);
2428         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2429
2430         /* config me program start addr */
2431         for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2432                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2433                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2434                         (me_hdr->ucode_start_addr_hi << 30) |
2435                         (me_hdr->ucode_start_addr_lo >> 2) );
2436                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2437                         me_hdr->ucode_start_addr_hi>>2);
2438         }
2439         soc21_grbm_select(adev, 0, 0, 0, 0);
2440
2441         /* reset me pipe */
2442         tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2443         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);
2444         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);
2445         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2446
2447         /* clear me pipe reset */
2448         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);
2449         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);
2450         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2451
2452         /* config mec program start addr */
2453         for (pipe_id = 0; pipe_id < 4; pipe_id++) {
2454                 soc21_grbm_select(adev, 1, pipe_id, 0, 0);
2455                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2456                                         mec_hdr->ucode_start_addr_lo >> 2 |
2457                                         mec_hdr->ucode_start_addr_hi << 30);
2458                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2459                                         mec_hdr->ucode_start_addr_hi >> 2);
2460         }
2461         soc21_grbm_select(adev, 0, 0, 0, 0);
2462
2463         /* reset mec pipe */
2464         tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2465         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);
2466         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);
2467         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);
2468         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);
2469         WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2470
2471         /* clear mec pipe reset */
2472         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);
2473         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);
2474         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);
2475         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);
2476         WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2477 }
2478
2479 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2480 {
2481         uint32_t cp_status;
2482         uint32_t bootload_status;
2483         int i, r;
2484         uint64_t addr, addr2;
2485
2486         for (i = 0; i < adev->usec_timeout; i++) {
2487                 cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
2488
2489                 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1) ||
2490                                 adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 4))
2491                         bootload_status = RREG32_SOC15(GC, 0,
2492                                         regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);
2493                 else
2494                         bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);
2495
2496                 if ((cp_status == 0) &&
2497                     (REG_GET_FIELD(bootload_status,
2498                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2499                         break;
2500                 }
2501                 udelay(1);
2502         }
2503
2504         if (i >= adev->usec_timeout) {
2505                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2506                 return -ETIMEDOUT;
2507         }
2508
2509         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2510                 if (adev->gfx.rs64_enable) {
2511                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2512                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset;
2513                         addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2514                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset;
2515                         r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2);
2516                         if (r)
2517                                 return r;
2518                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2519                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset;
2520                         addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2521                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset;
2522                         r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2);
2523                         if (r)
2524                                 return r;
2525                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2526                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset;
2527                         addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2528                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset;
2529                         r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2);
2530                         if (r)
2531                                 return r;
2532                 } else {
2533                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2534                                 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset;
2535                         r = gfx_v11_0_config_me_cache(adev, addr);
2536                         if (r)
2537                                 return r;
2538                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2539                                 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset;
2540                         r = gfx_v11_0_config_pfp_cache(adev, addr);
2541                         if (r)
2542                                 return r;
2543                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2544                                 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset;
2545                         r = gfx_v11_0_config_mec_cache(adev, addr);
2546                         if (r)
2547                                 return r;
2548                 }
2549         }
2550
2551         return 0;
2552 }
2553
2554 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2555 {
2556         int i;
2557         u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2558
2559         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2560         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2561         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2562
2563         for (i = 0; i < adev->usec_timeout; i++) {
2564                 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)
2565                         break;
2566                 udelay(1);
2567         }
2568
2569         if (i >= adev->usec_timeout)
2570                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
2571
2572         return 0;
2573 }
2574
2575 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
2576 {
2577         int r;
2578         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2579         const __le32 *fw_data;
2580         unsigned i, fw_size;
2581
2582         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2583                 adev->gfx.pfp_fw->data;
2584
2585         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2586
2587         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2588                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2589         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
2590
2591         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
2592                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2593                                       &adev->gfx.pfp.pfp_fw_obj,
2594                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
2595                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
2596         if (r) {
2597                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
2598                 gfx_v11_0_pfp_fini(adev);
2599                 return r;
2600         }
2601
2602         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
2603
2604         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2605         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2606
2607         gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr);
2608
2609         WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0);
2610
2611         for (i = 0; i < pfp_hdr->jt_size; i++)
2612                 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA,
2613                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
2614
2615         WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2616
2617         return 0;
2618 }
2619
2620 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
2621 {
2622         int r;
2623         const struct gfx_firmware_header_v2_0 *pfp_hdr;
2624         const __le32 *fw_ucode, *fw_data;
2625         unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2626         uint32_t tmp;
2627         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2628
2629         pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2630                 adev->gfx.pfp_fw->data;
2631
2632         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2633
2634         /* instruction */
2635         fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data +
2636                 le32_to_cpu(pfp_hdr->ucode_offset_bytes));
2637         fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes);
2638         /* data */
2639         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2640                 le32_to_cpu(pfp_hdr->data_offset_bytes));
2641         fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes);
2642
2643         /* 64kb align */
2644         r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2645                                       64 * 1024,
2646                                       AMDGPU_GEM_DOMAIN_VRAM |
2647                                       AMDGPU_GEM_DOMAIN_GTT,
2648                                       &adev->gfx.pfp.pfp_fw_obj,
2649                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
2650                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
2651         if (r) {
2652                 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r);
2653                 gfx_v11_0_pfp_fini(adev);
2654                 return r;
2655         }
2656
2657         r = amdgpu_bo_create_reserved(adev, fw_data_size,
2658                                       64 * 1024,
2659                                       AMDGPU_GEM_DOMAIN_VRAM |
2660                                       AMDGPU_GEM_DOMAIN_GTT,
2661                                       &adev->gfx.pfp.pfp_fw_data_obj,
2662                                       &adev->gfx.pfp.pfp_fw_data_gpu_addr,
2663                                       (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
2664         if (r) {
2665                 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r);
2666                 gfx_v11_0_pfp_fini(adev);
2667                 return r;
2668         }
2669
2670         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size);
2671         memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size);
2672
2673         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2674         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj);
2675         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2676         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
2677
2678         if (amdgpu_emu_mode == 1)
2679                 adev->hdp.funcs->flush_hdp(adev, NULL);
2680
2681         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2682                 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2683         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2684                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2685
2686         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2687         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2688         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2689         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2690         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2691
2692         /*
2693          * Programming any of the CP_PFP_IC_BASE registers
2694          * forces invalidation of the ME L1 I$. Wait for the
2695          * invalidation complete
2696          */
2697         for (i = 0; i < usec_timeout; i++) {
2698                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2699                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2700                         INVALIDATE_CACHE_COMPLETE))
2701                         break;
2702                 udelay(1);
2703         }
2704
2705         if (i >= usec_timeout) {
2706                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2707                 return -EINVAL;
2708         }
2709
2710         /* Prime the L1 instruction caches */
2711         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2712         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
2713         WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2714         /* Waiting for cache primed*/
2715         for (i = 0; i < usec_timeout; i++) {
2716                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2717                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2718                         ICACHE_PRIMED))
2719                         break;
2720                 udelay(1);
2721         }
2722
2723         if (i >= usec_timeout) {
2724                 dev_err(adev->dev, "failed to prime instruction cache\n");
2725                 return -EINVAL;
2726         }
2727
2728         mutex_lock(&adev->srbm_mutex);
2729         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2730                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2731                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2732                         (pfp_hdr->ucode_start_addr_hi << 30) |
2733                         (pfp_hdr->ucode_start_addr_lo >> 2) );
2734                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2735                         pfp_hdr->ucode_start_addr_hi>>2);
2736
2737                 /*
2738                  * Program CP_ME_CNTL to reset given PIPE to take
2739                  * effect of CP_PFP_PRGRM_CNTR_START.
2740                  */
2741                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2742                 if (pipe_id == 0)
2743                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2744                                         PFP_PIPE0_RESET, 1);
2745                 else
2746                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2747                                         PFP_PIPE1_RESET, 1);
2748                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2749
2750                 /* Clear pfp pipe0 reset bit. */
2751                 if (pipe_id == 0)
2752                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2753                                         PFP_PIPE0_RESET, 0);
2754                 else
2755                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2756                                         PFP_PIPE1_RESET, 0);
2757                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2758
2759                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2760                         lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2761                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2762                         upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2763         }
2764         soc21_grbm_select(adev, 0, 0, 0, 0);
2765         mutex_unlock(&adev->srbm_mutex);
2766
2767         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2768         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2769         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2770         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2771
2772         /* Invalidate the data caches */
2773         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2774         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2775         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2776
2777         for (i = 0; i < usec_timeout; i++) {
2778                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2779                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2780                         INVALIDATE_DCACHE_COMPLETE))
2781                         break;
2782                 udelay(1);
2783         }
2784
2785         if (i >= usec_timeout) {
2786                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2787                 return -EINVAL;
2788         }
2789
2790         return 0;
2791 }
2792
2793 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
2794 {
2795         int r;
2796         const struct gfx_firmware_header_v1_0 *me_hdr;
2797         const __le32 *fw_data;
2798         unsigned i, fw_size;
2799
2800         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2801                 adev->gfx.me_fw->data;
2802
2803         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2804
2805         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2806                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2807         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
2808
2809         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
2810                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2811                                       &adev->gfx.me.me_fw_obj,
2812                                       &adev->gfx.me.me_fw_gpu_addr,
2813                                       (void **)&adev->gfx.me.me_fw_ptr);
2814         if (r) {
2815                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
2816                 gfx_v11_0_me_fini(adev);
2817                 return r;
2818         }
2819
2820         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
2821
2822         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2823         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2824
2825         gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr);
2826
2827         WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0);
2828
2829         for (i = 0; i < me_hdr->jt_size; i++)
2830                 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA,
2831                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
2832
2833         WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
2834
2835         return 0;
2836 }
2837
2838 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
2839 {
2840         int r;
2841         const struct gfx_firmware_header_v2_0 *me_hdr;
2842         const __le32 *fw_ucode, *fw_data;
2843         unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2844         uint32_t tmp;
2845         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2846
2847         me_hdr = (const struct gfx_firmware_header_v2_0 *)
2848                 adev->gfx.me_fw->data;
2849
2850         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2851
2852         /* instruction */
2853         fw_ucode = (const __le32 *)(adev->gfx.me_fw->data +
2854                 le32_to_cpu(me_hdr->ucode_offset_bytes));
2855         fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes);
2856         /* data */
2857         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2858                 le32_to_cpu(me_hdr->data_offset_bytes));
2859         fw_data_size = le32_to_cpu(me_hdr->data_size_bytes);
2860
2861         /* 64kb align*/
2862         r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2863                                       64 * 1024,
2864                                       AMDGPU_GEM_DOMAIN_VRAM |
2865                                       AMDGPU_GEM_DOMAIN_GTT,
2866                                       &adev->gfx.me.me_fw_obj,
2867                                       &adev->gfx.me.me_fw_gpu_addr,
2868                                       (void **)&adev->gfx.me.me_fw_ptr);
2869         if (r) {
2870                 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r);
2871                 gfx_v11_0_me_fini(adev);
2872                 return r;
2873         }
2874
2875         r = amdgpu_bo_create_reserved(adev, fw_data_size,
2876                                       64 * 1024,
2877                                       AMDGPU_GEM_DOMAIN_VRAM |
2878                                       AMDGPU_GEM_DOMAIN_GTT,
2879                                       &adev->gfx.me.me_fw_data_obj,
2880                                       &adev->gfx.me.me_fw_data_gpu_addr,
2881                                       (void **)&adev->gfx.me.me_fw_data_ptr);
2882         if (r) {
2883                 dev_err(adev->dev, "(%d) failed to create me data bo\n", r);
2884                 gfx_v11_0_pfp_fini(adev);
2885                 return r;
2886         }
2887
2888         memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size);
2889         memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size);
2890
2891         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2892         amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj);
2893         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2894         amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
2895
2896         if (amdgpu_emu_mode == 1)
2897                 adev->hdp.funcs->flush_hdp(adev, NULL);
2898
2899         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2900                 lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
2901         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2902                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
2903
2904         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2905         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2906         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2907         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2908         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2909
2910         /*
2911          * Programming any of the CP_ME_IC_BASE registers
2912          * forces invalidation of the ME L1 I$. Wait for the
2913          * invalidation complete
2914          */
2915         for (i = 0; i < usec_timeout; i++) {
2916                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2917                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2918                         INVALIDATE_CACHE_COMPLETE))
2919                         break;
2920                 udelay(1);
2921         }
2922
2923         if (i >= usec_timeout) {
2924                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2925                 return -EINVAL;
2926         }
2927
2928         /* Prime the instruction caches */
2929         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2930         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
2931         WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2932
2933         /* Waiting for instruction cache primed*/
2934         for (i = 0; i < usec_timeout; i++) {
2935                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2936                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2937                         ICACHE_PRIMED))
2938                         break;
2939                 udelay(1);
2940         }
2941
2942         if (i >= usec_timeout) {
2943                 dev_err(adev->dev, "failed to prime instruction cache\n");
2944                 return -EINVAL;
2945         }
2946
2947         mutex_lock(&adev->srbm_mutex);
2948         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2949                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2950                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2951                         (me_hdr->ucode_start_addr_hi << 30) |
2952                         (me_hdr->ucode_start_addr_lo >> 2) );
2953                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2954                         me_hdr->ucode_start_addr_hi>>2);
2955
2956                 /*
2957                  * Program CP_ME_CNTL to reset given PIPE to take
2958                  * effect of CP_PFP_PRGRM_CNTR_START.
2959                  */
2960                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2961                 if (pipe_id == 0)
2962                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2963                                         ME_PIPE0_RESET, 1);
2964                 else
2965                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2966                                         ME_PIPE1_RESET, 1);
2967                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2968
2969                 /* Clear pfp pipe0 reset bit. */
2970                 if (pipe_id == 0)
2971                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2972                                         ME_PIPE0_RESET, 0);
2973                 else
2974                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2975                                         ME_PIPE1_RESET, 0);
2976                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2977
2978                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
2979                         lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
2980                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
2981                         upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
2982         }
2983         soc21_grbm_select(adev, 0, 0, 0, 0);
2984         mutex_unlock(&adev->srbm_mutex);
2985
2986         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2987         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2988         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2989         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2990
2991         /* Invalidate the data caches */
2992         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2993         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2994         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2995
2996         for (i = 0; i < usec_timeout; i++) {
2997                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2998                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2999                         INVALIDATE_DCACHE_COMPLETE))
3000                         break;
3001                 udelay(1);
3002         }
3003
3004         if (i >= usec_timeout) {
3005                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
3006                 return -EINVAL;
3007         }
3008
3009         return 0;
3010 }
3011
3012 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
3013 {
3014         int r;
3015
3016         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw)
3017                 return -EINVAL;
3018
3019         gfx_v11_0_cp_gfx_enable(adev, false);
3020
3021         if (adev->gfx.rs64_enable)
3022                 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev);
3023         else
3024                 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev);
3025         if (r) {
3026                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
3027                 return r;
3028         }
3029
3030         if (adev->gfx.rs64_enable)
3031                 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev);
3032         else
3033                 r = gfx_v11_0_cp_gfx_load_me_microcode(adev);
3034         if (r) {
3035                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
3036                 return r;
3037         }
3038
3039         return 0;
3040 }
3041
3042 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev)
3043 {
3044         struct amdgpu_ring *ring;
3045         const struct cs_section_def *sect = NULL;
3046         const struct cs_extent_def *ext = NULL;
3047         int r, i;
3048         int ctx_reg_offset;
3049
3050         /* init the CP */
3051         WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT,
3052                      adev->gfx.config.max_hw_contexts - 1);
3053         WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1);
3054
3055         if (!amdgpu_async_gfx_ring)
3056                 gfx_v11_0_cp_gfx_enable(adev, true);
3057
3058         ring = &adev->gfx.gfx_ring[0];
3059         r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev));
3060         if (r) {
3061                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3062                 return r;
3063         }
3064
3065         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3066         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3067
3068         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3069         amdgpu_ring_write(ring, 0x80000000);
3070         amdgpu_ring_write(ring, 0x80000000);
3071
3072         for (sect = gfx11_cs_data; sect->section != NULL; ++sect) {
3073                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3074                         if (sect->id == SECT_CONTEXT) {
3075                                 amdgpu_ring_write(ring,
3076                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
3077                                                           ext->reg_count));
3078                                 amdgpu_ring_write(ring, ext->reg_index -
3079                                                   PACKET3_SET_CONTEXT_REG_START);
3080                                 for (i = 0; i < ext->reg_count; i++)
3081                                         amdgpu_ring_write(ring, ext->extent[i]);
3082                         }
3083                 }
3084         }
3085
3086         ctx_reg_offset =
3087                 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
3088         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
3089         amdgpu_ring_write(ring, ctx_reg_offset);
3090         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
3091
3092         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3093         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3094
3095         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3096         amdgpu_ring_write(ring, 0);
3097
3098         amdgpu_ring_commit(ring);
3099
3100         /* submit cs packet to copy state 0 to next available state */
3101         if (adev->gfx.num_gfx_rings > 1) {
3102                 /* maximum supported gfx ring is 2 */
3103                 ring = &adev->gfx.gfx_ring[1];
3104                 r = amdgpu_ring_alloc(ring, 2);
3105                 if (r) {
3106                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3107                         return r;
3108                 }
3109
3110                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3111                 amdgpu_ring_write(ring, 0);
3112
3113                 amdgpu_ring_commit(ring);
3114         }
3115         return 0;
3116 }
3117
3118 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
3119                                          CP_PIPE_ID pipe)
3120 {
3121         u32 tmp;
3122
3123         tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
3124         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
3125
3126         WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
3127 }
3128
3129 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
3130                                           struct amdgpu_ring *ring)
3131 {
3132         u32 tmp;
3133
3134         tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
3135         if (ring->use_doorbell) {
3136                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3137                                     DOORBELL_OFFSET, ring->doorbell_index);
3138                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3139                                     DOORBELL_EN, 1);
3140         } else {
3141                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3142                                     DOORBELL_EN, 0);
3143         }
3144         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp);
3145
3146         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
3147                             DOORBELL_RANGE_LOWER, ring->doorbell_index);
3148         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp);
3149
3150         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
3151                      CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
3152 }
3153
3154 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev)
3155 {
3156         struct amdgpu_ring *ring;
3157         u32 tmp;
3158         u32 rb_bufsz;
3159         u64 rb_addr, rptr_addr, wptr_gpu_addr;
3160         u32 i;
3161
3162         /* Set the write pointer delay */
3163         WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0);
3164
3165         /* set the RB to use vmid 0 */
3166         WREG32_SOC15(GC, 0, regCP_RB_VMID, 0);
3167
3168         /* Init gfx ring 0 for pipe 0 */
3169         mutex_lock(&adev->srbm_mutex);
3170         gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
3171
3172         /* Set ring buffer size */
3173         ring = &adev->gfx.gfx_ring[0];
3174         rb_bufsz = order_base_2(ring->ring_size / 8);
3175         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
3176         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
3177         WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
3178
3179         /* Initialize the ring buffer's write pointers */
3180         ring->wptr = 0;
3181         WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr));
3182         WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3183
3184         /* set the wb address wether it's enabled or not */
3185         rptr_addr = ring->rptr_gpu_addr;
3186         WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
3187         WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
3188                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
3189
3190         wptr_gpu_addr = ring->wptr_gpu_addr;
3191         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
3192                      lower_32_bits(wptr_gpu_addr));
3193         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
3194                      upper_32_bits(wptr_gpu_addr));
3195
3196         mdelay(1);
3197         WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
3198
3199         rb_addr = ring->gpu_addr >> 8;
3200         WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr);
3201         WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr));
3202
3203         WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1);
3204
3205         gfx_v11_0_cp_gfx_set_doorbell(adev, ring);
3206         mutex_unlock(&adev->srbm_mutex);
3207
3208         /* Init gfx ring 1 for pipe 1 */
3209         if (adev->gfx.num_gfx_rings > 1) {
3210                 mutex_lock(&adev->srbm_mutex);
3211                 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
3212                 /* maximum supported gfx ring is 2 */
3213                 ring = &adev->gfx.gfx_ring[1];
3214                 rb_bufsz = order_base_2(ring->ring_size / 8);
3215                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
3216                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
3217                 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);
3218                 /* Initialize the ring buffer's write pointers */
3219                 ring->wptr = 0;
3220                 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr));
3221                 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
3222                 /* Set the wb address wether it's enabled or not */
3223                 rptr_addr = ring->rptr_gpu_addr;
3224                 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
3225                 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
3226                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
3227                 wptr_gpu_addr = ring->wptr_gpu_addr;
3228                 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
3229                              lower_32_bits(wptr_gpu_addr));
3230                 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
3231                              upper_32_bits(wptr_gpu_addr));
3232
3233                 mdelay(1);
3234                 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);
3235
3236                 rb_addr = ring->gpu_addr >> 8;
3237                 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr);
3238                 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr));
3239                 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1);
3240
3241                 gfx_v11_0_cp_gfx_set_doorbell(adev, ring);
3242                 mutex_unlock(&adev->srbm_mutex);
3243         }
3244         /* Switch to pipe 0 */
3245         mutex_lock(&adev->srbm_mutex);
3246         gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
3247         mutex_unlock(&adev->srbm_mutex);
3248
3249         /* start the ring */
3250         gfx_v11_0_cp_gfx_start(adev);
3251
3252         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3253                 ring = &adev->gfx.gfx_ring[i];
3254                 ring->sched.ready = true;
3255         }
3256
3257         return 0;
3258 }
3259
3260 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
3261 {
3262         u32 data;
3263
3264         if (adev->gfx.rs64_enable) {
3265                 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
3266                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE,
3267                                                          enable ? 0 : 1);
3268                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET,
3269                                                          enable ? 0 : 1);
3270                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET,
3271                                                          enable ? 0 : 1);
3272                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET,
3273                                                          enable ? 0 : 1);
3274                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET,
3275                                                          enable ? 0 : 1);
3276                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE,
3277                                                          enable ? 1 : 0);
3278                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE,
3279                                                          enable ? 1 : 0);
3280                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE,
3281                                                          enable ? 1 : 0);
3282                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE,
3283                                                          enable ? 1 : 0);
3284                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT,
3285                                                          enable ? 0 : 1);
3286                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data);
3287         } else {
3288                 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL);
3289
3290                 if (enable) {
3291                         data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0);
3292                         if (!adev->enable_mes_kiq)
3293                                 data = REG_SET_FIELD(data, CP_MEC_CNTL,
3294                                                      MEC_ME2_HALT, 0);
3295                 } else {
3296                         data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1);
3297                         data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1);
3298                 }
3299                 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data);
3300         }
3301
3302         adev->gfx.kiq.ring.sched.ready = enable;
3303
3304         udelay(50);
3305 }
3306
3307 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3308 {
3309         const struct gfx_firmware_header_v1_0 *mec_hdr;
3310         const __le32 *fw_data;
3311         unsigned i, fw_size;
3312         u32 *fw = NULL;
3313         int r;
3314
3315         if (!adev->gfx.mec_fw)
3316                 return -EINVAL;
3317
3318         gfx_v11_0_cp_compute_enable(adev, false);
3319
3320         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3321         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3322
3323         fw_data = (const __le32 *)
3324                 (adev->gfx.mec_fw->data +
3325                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3326         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
3327
3328         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
3329                                           PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
3330                                           &adev->gfx.mec.mec_fw_obj,
3331                                           &adev->gfx.mec.mec_fw_gpu_addr,
3332                                           (void **)&fw);
3333         if (r) {
3334                 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
3335                 gfx_v11_0_mec_fini(adev);
3336                 return r;
3337         }
3338
3339         memcpy(fw, fw_data, fw_size);
3340
3341         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
3342         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
3343
3344         gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr);
3345
3346         /* MEC1 */
3347         WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0);
3348
3349         for (i = 0; i < mec_hdr->jt_size; i++)
3350                 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA,
3351                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
3352
3353         WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
3354
3355         return 0;
3356 }
3357
3358 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev)
3359 {
3360         const struct gfx_firmware_header_v2_0 *mec_hdr;
3361         const __le32 *fw_ucode, *fw_data;
3362         u32 tmp, fw_ucode_size, fw_data_size;
3363         u32 i, usec_timeout = 50000; /* Wait for 50 ms */
3364         u32 *fw_ucode_ptr, *fw_data_ptr;
3365         int r;
3366
3367         if (!adev->gfx.mec_fw)
3368                 return -EINVAL;
3369
3370         gfx_v11_0_cp_compute_enable(adev, false);
3371
3372         mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data;
3373         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3374
3375         fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data +
3376                                 le32_to_cpu(mec_hdr->ucode_offset_bytes));
3377         fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes);
3378
3379         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
3380                                 le32_to_cpu(mec_hdr->data_offset_bytes));
3381         fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes);
3382
3383         r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
3384                                       64 * 1024,
3385                                       AMDGPU_GEM_DOMAIN_VRAM |
3386                                       AMDGPU_GEM_DOMAIN_GTT,
3387                                       &adev->gfx.mec.mec_fw_obj,
3388                                       &adev->gfx.mec.mec_fw_gpu_addr,
3389                                       (void **)&fw_ucode_ptr);
3390         if (r) {
3391                 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
3392                 gfx_v11_0_mec_fini(adev);
3393                 return r;
3394         }
3395
3396         r = amdgpu_bo_create_reserved(adev, fw_data_size,
3397                                       64 * 1024,
3398                                       AMDGPU_GEM_DOMAIN_VRAM |
3399                                       AMDGPU_GEM_DOMAIN_GTT,
3400                                       &adev->gfx.mec.mec_fw_data_obj,
3401                                       &adev->gfx.mec.mec_fw_data_gpu_addr,
3402                                       (void **)&fw_data_ptr);
3403         if (r) {
3404                 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
3405                 gfx_v11_0_mec_fini(adev);
3406                 return r;
3407         }
3408
3409         memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size);
3410         memcpy(fw_data_ptr, fw_data, fw_data_size);
3411
3412         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
3413         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj);
3414         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
3415         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj);
3416
3417         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
3418         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
3419         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
3420         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
3421         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
3422
3423         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
3424         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
3425         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
3426         WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
3427
3428         mutex_lock(&adev->srbm_mutex);
3429         for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
3430                 soc21_grbm_select(adev, 1, i, 0, 0);
3431
3432                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr);
3433                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
3434                      upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr));
3435
3436                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
3437                                         mec_hdr->ucode_start_addr_lo >> 2 |
3438                                         mec_hdr->ucode_start_addr_hi << 30);
3439                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
3440                                         mec_hdr->ucode_start_addr_hi >> 2);
3441
3442                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr);
3443                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
3444                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
3445         }
3446         mutex_unlock(&adev->srbm_mutex);
3447         soc21_grbm_select(adev, 0, 0, 0, 0);
3448
3449         /* Trigger an invalidation of the L1 instruction caches */
3450         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
3451         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
3452         WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
3453
3454         /* Wait for invalidation complete */
3455         for (i = 0; i < usec_timeout; i++) {
3456                 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
3457                 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
3458                                        INVALIDATE_DCACHE_COMPLETE))
3459                         break;
3460                 udelay(1);
3461         }
3462
3463         if (i >= usec_timeout) {
3464                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
3465                 return -EINVAL;
3466         }
3467
3468         /* Trigger an invalidation of the L1 instruction caches */
3469         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
3470         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
3471         WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
3472
3473         /* Wait for invalidation complete */
3474         for (i = 0; i < usec_timeout; i++) {
3475                 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
3476                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
3477                                        INVALIDATE_CACHE_COMPLETE))
3478                         break;
3479                 udelay(1);
3480         }
3481
3482         if (i >= usec_timeout) {
3483                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
3484                 return -EINVAL;
3485         }
3486
3487         return 0;
3488 }
3489
3490 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring)
3491 {
3492         uint32_t tmp;
3493         struct amdgpu_device *adev = ring->adev;
3494
3495         /* tell RLC which is KIQ queue */
3496         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
3497         tmp &= 0xffffff00;
3498         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
3499         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
3500         tmp |= 0x80;
3501         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
3502 }
3503
3504 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev)
3505 {
3506         /* set graphics engine doorbell range */
3507         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER,
3508                      (adev->doorbell_index.gfx_ring0 * 2) << 2);
3509         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
3510                      (adev->doorbell_index.gfx_userqueue_end * 2) << 2);
3511
3512         /* set compute engine doorbell range */
3513         WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3514                      (adev->doorbell_index.kiq * 2) << 2);
3515         WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3516                      (adev->doorbell_index.userqueue_end * 2) << 2);
3517 }
3518
3519 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
3520                                   struct amdgpu_mqd_prop *prop)
3521 {
3522         struct v11_gfx_mqd *mqd = m;
3523         uint64_t hqd_gpu_addr, wb_gpu_addr;
3524         uint32_t tmp;
3525         uint32_t rb_bufsz;
3526
3527         /* set up gfx hqd wptr */
3528         mqd->cp_gfx_hqd_wptr = 0;
3529         mqd->cp_gfx_hqd_wptr_hi = 0;
3530
3531         /* set the pointer to the MQD */
3532         mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
3533         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
3534
3535         /* set up mqd control */
3536         tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL);
3537         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
3538         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
3539         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
3540         mqd->cp_gfx_mqd_control = tmp;
3541
3542         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
3543         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID);
3544         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
3545         mqd->cp_gfx_hqd_vmid = 0;
3546
3547         /* set up default queue priority level
3548          * 0x0 = low priority, 0x1 = high priority */
3549         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY);
3550         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
3551         mqd->cp_gfx_hqd_queue_priority = tmp;
3552
3553         /* set up time quantum */
3554         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM);
3555         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
3556         mqd->cp_gfx_hqd_quantum = tmp;
3557
3558         /* set up gfx hqd base. this is similar as CP_RB_BASE */
3559         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3560         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
3561         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
3562
3563         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
3564         wb_gpu_addr = prop->rptr_gpu_addr;
3565         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3566         mqd->cp_gfx_hqd_rptr_addr_hi =
3567                 upper_32_bits(wb_gpu_addr) & 0xffff;
3568
3569         /* set up rb_wptr_poll addr */
3570         wb_gpu_addr = prop->wptr_gpu_addr;
3571         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3572         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3573
3574         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
3575         rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
3576         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL);
3577         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
3578         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
3579 #ifdef __BIG_ENDIAN
3580         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
3581 #endif
3582         mqd->cp_gfx_hqd_cntl = tmp;
3583
3584         /* set up cp_doorbell_control */
3585         tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
3586         if (prop->use_doorbell) {
3587                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3588                                     DOORBELL_OFFSET, prop->doorbell_index);
3589                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3590                                     DOORBELL_EN, 1);
3591         } else
3592                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3593                                     DOORBELL_EN, 0);
3594         mqd->cp_rb_doorbell_control = tmp;
3595
3596         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3597         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR);
3598
3599         /* active the queue */
3600         mqd->cp_gfx_hqd_active = 1;
3601
3602         return 0;
3603 }
3604
3605 #ifdef BRING_UP_DEBUG
3606 static int gfx_v11_0_gfx_queue_init_register(struct amdgpu_ring *ring)
3607 {
3608         struct amdgpu_device *adev = ring->adev;
3609         struct v11_gfx_mqd *mqd = ring->mqd_ptr;
3610
3611         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
3612         WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
3613         WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
3614
3615         /* set GFX_MQD_BASE */
3616         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
3617         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3618
3619         /* set GFX_MQD_CONTROL */
3620         WREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
3621
3622         /* set GFX_HQD_VMID to 0 */
3623         WREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
3624
3625         WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY,
3626                         mqd->cp_gfx_hqd_queue_priority);
3627         WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
3628
3629         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
3630         WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
3631         WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
3632
3633         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
3634         WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
3635         WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
3636
3637         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
3638         WREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
3639
3640         /* set RB_WPTR_POLL_ADDR */
3641         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
3642         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
3643
3644         /* set RB_DOORBELL_CONTROL */
3645         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
3646
3647         /* active the queue */
3648         WREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
3649
3650         return 0;
3651 }
3652 #endif
3653
3654 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring)
3655 {
3656         struct amdgpu_device *adev = ring->adev;
3657         struct v11_gfx_mqd *mqd = ring->mqd_ptr;
3658         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
3659
3660         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
3661                 memset((void *)mqd, 0, sizeof(*mqd));
3662                 mutex_lock(&adev->srbm_mutex);
3663                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3664                 amdgpu_ring_init_mqd(ring);
3665 #ifdef BRING_UP_DEBUG
3666                 gfx_v11_0_gfx_queue_init_register(ring);
3667 #endif
3668                 soc21_grbm_select(adev, 0, 0, 0, 0);
3669                 mutex_unlock(&adev->srbm_mutex);
3670                 if (adev->gfx.me.mqd_backup[mqd_idx])
3671                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3672         } else if (amdgpu_in_reset(adev)) {
3673                 /* reset mqd with the backup copy */
3674                 if (adev->gfx.me.mqd_backup[mqd_idx])
3675                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
3676                 /* reset the ring */
3677                 ring->wptr = 0;
3678                 *ring->wptr_cpu_addr = 0;
3679                 amdgpu_ring_clear_ring(ring);
3680 #ifdef BRING_UP_DEBUG
3681                 mutex_lock(&adev->srbm_mutex);
3682                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3683                 gfx_v11_0_gfx_queue_init_register(ring);
3684                 soc21_grbm_select(adev, 0, 0, 0, 0);
3685                 mutex_unlock(&adev->srbm_mutex);
3686 #endif
3687         } else {
3688                 amdgpu_ring_clear_ring(ring);
3689         }
3690
3691         return 0;
3692 }
3693
3694 #ifndef BRING_UP_DEBUG
3695 static int gfx_v11_0_kiq_enable_kgq(struct amdgpu_device *adev)
3696 {
3697         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3698         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
3699         int r, i;
3700
3701         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
3702                 return -EINVAL;
3703
3704         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
3705                                         adev->gfx.num_gfx_rings);
3706         if (r) {
3707                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3708                 return r;
3709         }
3710
3711         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3712                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
3713
3714         return amdgpu_ring_test_helper(kiq_ring);
3715 }
3716 #endif
3717
3718 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3719 {
3720         int r, i;
3721         struct amdgpu_ring *ring;
3722
3723         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3724                 ring = &adev->gfx.gfx_ring[i];
3725
3726                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3727                 if (unlikely(r != 0))
3728                         goto done;
3729
3730                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3731                 if (!r) {
3732                         r = gfx_v11_0_gfx_init_queue(ring);
3733                         amdgpu_bo_kunmap(ring->mqd_obj);
3734                         ring->mqd_ptr = NULL;
3735                 }
3736                 amdgpu_bo_unreserve(ring->mqd_obj);
3737                 if (r)
3738                         goto done;
3739         }
3740 #ifndef BRING_UP_DEBUG
3741         r = gfx_v11_0_kiq_enable_kgq(adev);
3742         if (r)
3743                 goto done;
3744 #endif
3745         r = gfx_v11_0_cp_gfx_start(adev);
3746         if (r)
3747                 goto done;
3748
3749         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3750                 ring = &adev->gfx.gfx_ring[i];
3751                 ring->sched.ready = true;
3752         }
3753 done:
3754         return r;
3755 }
3756
3757 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
3758                                       struct amdgpu_mqd_prop *prop)
3759 {
3760         struct v11_compute_mqd *mqd = m;
3761         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3762         uint32_t tmp;
3763
3764         mqd->header = 0xC0310800;
3765         mqd->compute_pipelinestat_enable = 0x00000001;
3766         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3767         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3768         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3769         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3770         mqd->compute_misc_reserved = 0x00000007;
3771
3772         eop_base_addr = prop->eop_gpu_addr >> 8;
3773         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3774         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3775
3776         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3777         tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL);
3778         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3779                         (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1));
3780
3781         mqd->cp_hqd_eop_control = tmp;
3782
3783         /* enable doorbell? */
3784         tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
3785
3786         if (prop->use_doorbell) {
3787                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3788                                     DOORBELL_OFFSET, prop->doorbell_index);
3789                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3790                                     DOORBELL_EN, 1);
3791                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3792                                     DOORBELL_SOURCE, 0);
3793                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3794                                     DOORBELL_HIT, 0);
3795         } else {
3796                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3797                                     DOORBELL_EN, 0);
3798         }
3799
3800         mqd->cp_hqd_pq_doorbell_control = tmp;
3801
3802         /* disable the queue if it's active */
3803         mqd->cp_hqd_dequeue_request = 0;
3804         mqd->cp_hqd_pq_rptr = 0;
3805         mqd->cp_hqd_pq_wptr_lo = 0;
3806         mqd->cp_hqd_pq_wptr_hi = 0;
3807
3808         /* set the pointer to the MQD */
3809         mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
3810         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
3811
3812         /* set MQD vmid to 0 */
3813         tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
3814         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3815         mqd->cp_mqd_control = tmp;
3816
3817         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3818         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3819         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3820         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3821
3822         /* set up the HQD, this is similar to CP_RB0_CNTL */
3823         tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL);
3824         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3825                             (order_base_2(prop->queue_size / 4) - 1));
3826         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3827                             (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
3828         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3829         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3830         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3831         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3832         mqd->cp_hqd_pq_control = tmp;
3833
3834         /* set the wb address whether it's enabled or not */
3835         wb_gpu_addr = prop->rptr_gpu_addr;
3836         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3837         mqd->cp_hqd_pq_rptr_report_addr_hi =
3838                 upper_32_bits(wb_gpu_addr) & 0xffff;
3839
3840         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3841         wb_gpu_addr = prop->wptr_gpu_addr;
3842         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3843         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3844
3845         tmp = 0;
3846         /* enable the doorbell if requested */
3847         if (prop->use_doorbell) {
3848                 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
3849                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3850                                 DOORBELL_OFFSET, prop->doorbell_index);
3851
3852                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3853                                     DOORBELL_EN, 1);
3854                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3855                                     DOORBELL_SOURCE, 0);
3856                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3857                                     DOORBELL_HIT, 0);
3858         }
3859
3860         mqd->cp_hqd_pq_doorbell_control = tmp;
3861
3862         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3863         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR);
3864
3865         /* set the vmid for the queue */
3866         mqd->cp_hqd_vmid = 0;
3867
3868         tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE);
3869         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);
3870         mqd->cp_hqd_persistent_state = tmp;
3871
3872         /* set MIN_IB_AVAIL_SIZE */
3873         tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL);
3874         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3875         mqd->cp_hqd_ib_control = tmp;
3876
3877         /* set static priority for a compute queue/ring */
3878         mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
3879         mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
3880
3881         mqd->cp_hqd_active = prop->hqd_active;
3882
3883         return 0;
3884 }
3885
3886 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring)
3887 {
3888         struct amdgpu_device *adev = ring->adev;
3889         struct v11_compute_mqd *mqd = ring->mqd_ptr;
3890         int j;
3891
3892         /* inactivate the queue */
3893         if (amdgpu_sriov_vf(adev))
3894                 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);
3895
3896         /* disable wptr polling */
3897         WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3898
3899         /* write the EOP addr */
3900         WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR,
3901                mqd->cp_hqd_eop_base_addr_lo);
3902         WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI,
3903                mqd->cp_hqd_eop_base_addr_hi);
3904
3905         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3906         WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL,
3907                mqd->cp_hqd_eop_control);
3908
3909         /* enable doorbell? */
3910         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3911                mqd->cp_hqd_pq_doorbell_control);
3912
3913         /* disable the queue if it's active */
3914         if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
3915                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
3916                 for (j = 0; j < adev->usec_timeout; j++) {
3917                         if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
3918                                 break;
3919                         udelay(1);
3920                 }
3921                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST,
3922                        mqd->cp_hqd_dequeue_request);
3923                 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR,
3924                        mqd->cp_hqd_pq_rptr);
3925                 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3926                        mqd->cp_hqd_pq_wptr_lo);
3927                 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3928                        mqd->cp_hqd_pq_wptr_hi);
3929         }
3930
3931         /* set the pointer to the MQD */
3932         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR,
3933                mqd->cp_mqd_base_addr_lo);
3934         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI,
3935                mqd->cp_mqd_base_addr_hi);
3936
3937         /* set MQD vmid to 0 */
3938         WREG32_SOC15(GC, 0, regCP_MQD_CONTROL,
3939                mqd->cp_mqd_control);
3940
3941         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3942         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE,
3943                mqd->cp_hqd_pq_base_lo);
3944         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI,
3945                mqd->cp_hqd_pq_base_hi);
3946
3947         /* set up the HQD, this is similar to CP_RB0_CNTL */
3948         WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL,
3949                mqd->cp_hqd_pq_control);
3950
3951         /* set the wb address whether it's enabled or not */
3952         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
3953                 mqd->cp_hqd_pq_rptr_report_addr_lo);
3954         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3955                 mqd->cp_hqd_pq_rptr_report_addr_hi);
3956
3957         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3958         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
3959                mqd->cp_hqd_pq_wptr_poll_addr_lo);
3960         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3961                mqd->cp_hqd_pq_wptr_poll_addr_hi);
3962
3963         /* enable the doorbell if requested */
3964         if (ring->use_doorbell) {
3965                 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3966                         (adev->doorbell_index.kiq * 2) << 2);
3967                 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3968                         (adev->doorbell_index.userqueue_end * 2) << 2);
3969         }
3970
3971         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3972                mqd->cp_hqd_pq_doorbell_control);
3973
3974         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3975         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3976                mqd->cp_hqd_pq_wptr_lo);
3977         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3978                mqd->cp_hqd_pq_wptr_hi);
3979
3980         /* set the vmid for the queue */
3981         WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid);
3982
3983         WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE,
3984                mqd->cp_hqd_persistent_state);
3985
3986         /* activate the queue */
3987         WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE,
3988                mqd->cp_hqd_active);
3989
3990         if (ring->use_doorbell)
3991                 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3992
3993         return 0;
3994 }
3995
3996 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring)
3997 {
3998         struct amdgpu_device *adev = ring->adev;
3999         struct v11_compute_mqd *mqd = ring->mqd_ptr;
4000         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
4001
4002         gfx_v11_0_kiq_setting(ring);
4003
4004         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
4005                 /* reset MQD to a clean status */
4006                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4007                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
4008
4009                 /* reset ring buffer */
4010                 ring->wptr = 0;
4011                 amdgpu_ring_clear_ring(ring);
4012
4013                 mutex_lock(&adev->srbm_mutex);
4014                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4015                 gfx_v11_0_kiq_init_register(ring);
4016                 soc21_grbm_select(adev, 0, 0, 0, 0);
4017                 mutex_unlock(&adev->srbm_mutex);
4018         } else {
4019                 memset((void *)mqd, 0, sizeof(*mqd));
4020                 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
4021                         amdgpu_ring_clear_ring(ring);
4022                 mutex_lock(&adev->srbm_mutex);
4023                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4024                 amdgpu_ring_init_mqd(ring);
4025                 gfx_v11_0_kiq_init_register(ring);
4026                 soc21_grbm_select(adev, 0, 0, 0, 0);
4027                 mutex_unlock(&adev->srbm_mutex);
4028
4029                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4030                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
4031         }
4032
4033         return 0;
4034 }
4035
4036 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring)
4037 {
4038         struct amdgpu_device *adev = ring->adev;
4039         struct v11_compute_mqd *mqd = ring->mqd_ptr;
4040         int mqd_idx = ring - &adev->gfx.compute_ring[0];
4041
4042         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
4043                 memset((void *)mqd, 0, sizeof(*mqd));
4044                 mutex_lock(&adev->srbm_mutex);
4045                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4046                 amdgpu_ring_init_mqd(ring);
4047                 soc21_grbm_select(adev, 0, 0, 0, 0);
4048                 mutex_unlock(&adev->srbm_mutex);
4049
4050                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4051                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
4052         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
4053                 /* reset MQD to a clean status */
4054                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4055                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
4056
4057                 /* reset ring buffer */
4058                 ring->wptr = 0;
4059                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
4060                 amdgpu_ring_clear_ring(ring);
4061         } else {
4062                 amdgpu_ring_clear_ring(ring);
4063         }
4064
4065         return 0;
4066 }
4067
4068 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev)
4069 {
4070         struct amdgpu_ring *ring;
4071         int r;
4072
4073         ring = &adev->gfx.kiq.ring;
4074
4075         r = amdgpu_bo_reserve(ring->mqd_obj, false);
4076         if (unlikely(r != 0))
4077                 return r;
4078
4079         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
4080         if (unlikely(r != 0)) {
4081                 amdgpu_bo_unreserve(ring->mqd_obj);
4082                 return r;
4083         }
4084
4085         gfx_v11_0_kiq_init_queue(ring);
4086         amdgpu_bo_kunmap(ring->mqd_obj);
4087         ring->mqd_ptr = NULL;
4088         amdgpu_bo_unreserve(ring->mqd_obj);
4089         ring->sched.ready = true;
4090         return 0;
4091 }
4092
4093 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev)
4094 {
4095         struct amdgpu_ring *ring = NULL;
4096         int r = 0, i;
4097
4098         if (!amdgpu_async_gfx_ring)
4099                 gfx_v11_0_cp_compute_enable(adev, true);
4100
4101         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4102                 ring = &adev->gfx.compute_ring[i];
4103
4104                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4105                 if (unlikely(r != 0))
4106                         goto done;
4107                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
4108                 if (!r) {
4109                         r = gfx_v11_0_kcq_init_queue(ring);
4110                         amdgpu_bo_kunmap(ring->mqd_obj);
4111                         ring->mqd_ptr = NULL;
4112                 }
4113                 amdgpu_bo_unreserve(ring->mqd_obj);
4114                 if (r)
4115                         goto done;
4116         }
4117
4118         r = amdgpu_gfx_enable_kcq(adev);
4119 done:
4120         return r;
4121 }
4122
4123 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev)
4124 {
4125         int r, i;
4126         struct amdgpu_ring *ring;
4127
4128         if (!(adev->flags & AMD_IS_APU))
4129                 gfx_v11_0_enable_gui_idle_interrupt(adev, false);
4130
4131         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4132                 /* legacy firmware loading */
4133                 r = gfx_v11_0_cp_gfx_load_microcode(adev);
4134                 if (r)
4135                         return r;
4136
4137                 if (adev->gfx.rs64_enable)
4138                         r = gfx_v11_0_cp_compute_load_microcode_rs64(adev);
4139                 else
4140                         r = gfx_v11_0_cp_compute_load_microcode(adev);
4141                 if (r)
4142                         return r;
4143         }
4144
4145         gfx_v11_0_cp_set_doorbell_range(adev);
4146
4147         if (amdgpu_async_gfx_ring) {
4148                 gfx_v11_0_cp_compute_enable(adev, true);
4149                 gfx_v11_0_cp_gfx_enable(adev, true);
4150         }
4151
4152         if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
4153                 r = amdgpu_mes_kiq_hw_init(adev);
4154         else
4155                 r = gfx_v11_0_kiq_resume(adev);
4156         if (r)
4157                 return r;
4158
4159         r = gfx_v11_0_kcq_resume(adev);
4160         if (r)
4161                 return r;
4162
4163         if (!amdgpu_async_gfx_ring) {
4164                 r = gfx_v11_0_cp_gfx_resume(adev);
4165                 if (r)
4166                         return r;
4167         } else {
4168                 r = gfx_v11_0_cp_async_gfx_ring_resume(adev);
4169                 if (r)
4170                         return r;
4171         }
4172
4173         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4174                 ring = &adev->gfx.gfx_ring[i];
4175                 r = amdgpu_ring_test_helper(ring);
4176                 if (r)
4177                         return r;
4178         }
4179
4180         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4181                 ring = &adev->gfx.compute_ring[i];
4182                 r = amdgpu_ring_test_helper(ring);
4183                 if (r)
4184                         return r;
4185         }
4186
4187         return 0;
4188 }
4189
4190 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable)
4191 {
4192         gfx_v11_0_cp_gfx_enable(adev, enable);
4193         gfx_v11_0_cp_compute_enable(adev, enable);
4194 }
4195
4196 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev)
4197 {
4198         int r;
4199         bool value;
4200
4201         r = adev->gfxhub.funcs->gart_enable(adev);
4202         if (r)
4203                 return r;
4204
4205         adev->hdp.funcs->flush_hdp(adev, NULL);
4206
4207         value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
4208                 false : true;
4209
4210         adev->gfxhub.funcs->set_fault_enable_default(adev, value);
4211         amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
4212
4213         return 0;
4214 }
4215
4216 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev)
4217 {
4218         u32 tmp;
4219
4220         /* select RS64 */
4221         if (adev->gfx.rs64_enable) {
4222                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL);
4223                 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1);
4224                 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp);
4225
4226                 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL);
4227                 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1);
4228                 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp);
4229         }
4230
4231         if (amdgpu_emu_mode == 1)
4232                 msleep(100);
4233 }
4234
4235 static int get_gb_addr_config(struct amdgpu_device * adev)
4236 {
4237         u32 gb_addr_config;
4238
4239         gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);
4240         if (gb_addr_config == 0)
4241                 return -EINVAL;
4242
4243         adev->gfx.config.gb_addr_config_fields.num_pkrs =
4244                 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4245
4246         adev->gfx.config.gb_addr_config = gb_addr_config;
4247
4248         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4249                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4250                                       GB_ADDR_CONFIG, NUM_PIPES);
4251
4252         adev->gfx.config.max_tile_pipes =
4253                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4254
4255         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4256                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4257                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4258         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4259                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4260                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4261         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4262                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4263                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4264         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4265                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4266                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4267
4268         return 0;
4269 }
4270
4271 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev)
4272 {
4273         uint32_t data;
4274
4275         data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);
4276         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
4277         WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data);
4278
4279         data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);
4280         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
4281         WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);
4282 }
4283
4284 static int gfx_v11_0_hw_init(void *handle)
4285 {
4286         int r;
4287         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4288
4289         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4290                 if (adev->gfx.imu.funcs) {
4291                         /* RLC autoload sequence 1: Program rlc ram */
4292                         if (adev->gfx.imu.funcs->program_rlc_ram)
4293                                 adev->gfx.imu.funcs->program_rlc_ram(adev);
4294                 }
4295                 /* rlc autoload firmware */
4296                 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev);
4297                 if (r)
4298                         return r;
4299         } else {
4300                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4301                         if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
4302                                 if (adev->gfx.imu.funcs->load_microcode)
4303                                         adev->gfx.imu.funcs->load_microcode(adev);
4304                                 if (adev->gfx.imu.funcs->setup_imu)
4305                                         adev->gfx.imu.funcs->setup_imu(adev);
4306                                 if (adev->gfx.imu.funcs->start_imu)
4307                                         adev->gfx.imu.funcs->start_imu(adev);
4308                         }
4309
4310                         /* disable gpa mode in backdoor loading */
4311                         gfx_v11_0_disable_gpa_mode(adev);
4312                 }
4313         }
4314
4315         if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) ||
4316             (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
4317                 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev);
4318                 if (r) {
4319                         dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r);
4320                         return r;
4321                 }
4322         }
4323
4324         adev->gfx.is_poweron = true;
4325
4326         if(get_gb_addr_config(adev))
4327                 DRM_WARN("Invalid gb_addr_config !\n");
4328
4329         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
4330             adev->gfx.rs64_enable)
4331                 gfx_v11_0_config_gfx_rs64(adev);
4332
4333         r = gfx_v11_0_gfxhub_enable(adev);
4334         if (r)
4335                 return r;
4336
4337         if (!amdgpu_emu_mode)
4338                 gfx_v11_0_init_golden_registers(adev);
4339
4340         if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) ||
4341             (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) {
4342                 /**
4343                  * For gfx 11, rlc firmware loading relies on smu firmware is
4344                  * loaded firstly, so in direct type, it has to load smc ucode
4345                  * here before rlc.
4346                  */
4347                 if (!(adev->flags & AMD_IS_APU)) {
4348                         r = amdgpu_pm_load_smu_firmware(adev, NULL);
4349                         if (r)
4350                                 return r;
4351                 }
4352         }
4353
4354         gfx_v11_0_constants_init(adev);
4355
4356         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
4357                 gfx_v11_0_select_cp_fw_arch(adev);
4358
4359         if (adev->nbio.funcs->gc_doorbell_init)
4360                 adev->nbio.funcs->gc_doorbell_init(adev);
4361
4362         r = gfx_v11_0_rlc_resume(adev);
4363         if (r)
4364                 return r;
4365
4366         /*
4367          * init golden registers and rlc resume may override some registers,
4368          * reconfig them here
4369          */
4370         gfx_v11_0_tcp_harvest(adev);
4371
4372         r = gfx_v11_0_cp_resume(adev);
4373         if (r)
4374                 return r;
4375
4376         return r;
4377 }
4378
4379 #ifndef BRING_UP_DEBUG
4380 static int gfx_v11_0_kiq_disable_kgq(struct amdgpu_device *adev)
4381 {
4382         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
4383         struct amdgpu_ring *kiq_ring = &kiq->ring;
4384         int i, r = 0;
4385
4386         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
4387                 return -EINVAL;
4388
4389         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
4390                                         adev->gfx.num_gfx_rings))
4391                 return -ENOMEM;
4392
4393         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4394                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
4395                                            PREEMPT_QUEUES, 0, 0);
4396
4397         if (adev->gfx.kiq.ring.sched.ready)
4398                 r = amdgpu_ring_test_helper(kiq_ring);
4399
4400         return r;
4401 }
4402 #endif
4403
4404 static int gfx_v11_0_hw_fini(void *handle)
4405 {
4406         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4407         int r;
4408
4409         amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
4410         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4411         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4412
4413         if (!adev->no_hw_access) {
4414 #ifndef BRING_UP_DEBUG
4415                 if (amdgpu_async_gfx_ring) {
4416                         r = gfx_v11_0_kiq_disable_kgq(adev);
4417                         if (r)
4418                                 DRM_ERROR("KGQ disable failed\n");
4419                 }
4420 #endif
4421                 if (amdgpu_gfx_disable_kcq(adev))
4422                         DRM_ERROR("KCQ disable failed\n");
4423
4424                 amdgpu_mes_kiq_hw_fini(adev);
4425         }
4426
4427         if (amdgpu_sriov_vf(adev))
4428                 /* Remove the steps disabling CPG and clearing KIQ position,
4429                  * so that CP could perform IDLE-SAVE during switch. Those
4430                  * steps are necessary to avoid a DMAR error in gfx9 but it is
4431                  * not reproduced on gfx11.
4432                  */
4433                 return 0;
4434
4435         gfx_v11_0_cp_enable(adev, false);
4436         gfx_v11_0_enable_gui_idle_interrupt(adev, false);
4437
4438         adev->gfxhub.funcs->gart_disable(adev);
4439
4440         adev->gfx.is_poweron = false;
4441
4442         return 0;
4443 }
4444
4445 static int gfx_v11_0_suspend(void *handle)
4446 {
4447         return gfx_v11_0_hw_fini(handle);
4448 }
4449
4450 static int gfx_v11_0_resume(void *handle)
4451 {
4452         return gfx_v11_0_hw_init(handle);
4453 }
4454
4455 static bool gfx_v11_0_is_idle(void *handle)
4456 {
4457         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4458
4459         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
4460                                 GRBM_STATUS, GUI_ACTIVE))
4461                 return false;
4462         else
4463                 return true;
4464 }
4465
4466 static int gfx_v11_0_wait_for_idle(void *handle)
4467 {
4468         unsigned i;
4469         u32 tmp;
4470         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4471
4472         for (i = 0; i < adev->usec_timeout; i++) {
4473                 /* read MC_STATUS */
4474                 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &
4475                         GRBM_STATUS__GUI_ACTIVE_MASK;
4476
4477                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
4478                         return 0;
4479                 udelay(1);
4480         }
4481         return -ETIMEDOUT;
4482 }
4483
4484 static int gfx_v11_0_soft_reset(void *handle)
4485 {
4486         u32 grbm_soft_reset = 0;
4487         u32 tmp;
4488         int i, j, k;
4489         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4490
4491         tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4492         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0);
4493         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0);
4494         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0);
4495         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0);
4496         WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);
4497
4498         gfx_v11_0_set_safe_mode(adev);
4499
4500         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4501                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4502                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4503                                 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
4504                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i);
4505                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j);
4506                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k);
4507                                 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
4508
4509                                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);
4510                                 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);
4511                         }
4512                 }
4513         }
4514         for (i = 0; i < adev->gfx.me.num_me; ++i) {
4515                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4516                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4517                                 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
4518                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i);
4519                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j);
4520                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k);
4521                                 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
4522
4523                                 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1);
4524                         }
4525                 }
4526         }
4527
4528         WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe);
4529
4530         // Read CP_VMID_RESET register three times.
4531         // to get sufficient time for GFX_HQD_ACTIVE reach 0
4532         RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4533         RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4534         RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4535
4536         for (i = 0; i < adev->usec_timeout; i++) {
4537                 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &&
4538                     !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE))
4539                         break;
4540                 udelay(1);
4541         }
4542         if (i >= adev->usec_timeout) {
4543                 printk("Failed to wait all pipes clean\n");
4544                 return -EINVAL;
4545         }
4546
4547         /**********  trigger soft reset  ***********/
4548         grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
4549         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4550                                         SOFT_RESET_CP, 1);
4551         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4552                                         SOFT_RESET_GFX, 1);
4553         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4554                                         SOFT_RESET_CPF, 1);
4555         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4556                                         SOFT_RESET_CPC, 1);
4557         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4558                                         SOFT_RESET_CPG, 1);
4559         WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset);
4560         /**********  exit soft reset  ***********/
4561         grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
4562         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4563                                         SOFT_RESET_CP, 0);
4564         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4565                                         SOFT_RESET_GFX, 0);
4566         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4567                                         SOFT_RESET_CPF, 0);
4568         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4569                                         SOFT_RESET_CPC, 0);
4570         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4571                                         SOFT_RESET_CPG, 0);
4572         WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset);
4573
4574         tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL);
4575         tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1);
4576         WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp);
4577
4578         WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0);
4579         WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0);
4580
4581         for (i = 0; i < adev->usec_timeout; i++) {
4582                 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET))
4583                         break;
4584                 udelay(1);
4585         }
4586         if (i >= adev->usec_timeout) {
4587                 printk("Failed to wait CP_VMID_RESET to 0\n");
4588                 return -EINVAL;
4589         }
4590
4591         tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4592         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
4593         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
4594         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
4595         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
4596         WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);
4597
4598         gfx_v11_0_unset_safe_mode(adev);
4599
4600         return gfx_v11_0_cp_resume(adev);
4601 }
4602
4603 static bool gfx_v11_0_check_soft_reset(void *handle)
4604 {
4605         int i, r;
4606         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4607         struct amdgpu_ring *ring;
4608         long tmo = msecs_to_jiffies(1000);
4609
4610         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4611                 ring = &adev->gfx.gfx_ring[i];
4612                 r = amdgpu_ring_test_ib(ring, tmo);
4613                 if (r)
4614                         return true;
4615         }
4616
4617         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4618                 ring = &adev->gfx.compute_ring[i];
4619                 r = amdgpu_ring_test_ib(ring, tmo);
4620                 if (r)
4621                         return true;
4622         }
4623
4624         return false;
4625 }
4626
4627 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4628 {
4629         uint64_t clock;
4630
4631         amdgpu_gfx_off_ctrl(adev, false);
4632         mutex_lock(&adev->gfx.gpu_clock_mutex);
4633         clock = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER) |
4634                 ((uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER) << 32ULL);
4635         mutex_unlock(&adev->gfx.gpu_clock_mutex);
4636         amdgpu_gfx_off_ctrl(adev, true);
4637         return clock;
4638 }
4639
4640 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4641                                            uint32_t vmid,
4642                                            uint32_t gds_base, uint32_t gds_size,
4643                                            uint32_t gws_base, uint32_t gws_size,
4644                                            uint32_t oa_base, uint32_t oa_size)
4645 {
4646         struct amdgpu_device *adev = ring->adev;
4647
4648         /* GDS Base */
4649         gfx_v11_0_write_data_to_reg(ring, 0, false,
4650                                     SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid,
4651                                     gds_base);
4652
4653         /* GDS Size */
4654         gfx_v11_0_write_data_to_reg(ring, 0, false,
4655                                     SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid,
4656                                     gds_size);
4657
4658         /* GWS */
4659         gfx_v11_0_write_data_to_reg(ring, 0, false,
4660                                     SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid,
4661                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4662
4663         /* OA */
4664         gfx_v11_0_write_data_to_reg(ring, 0, false,
4665                                     SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid,
4666                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
4667 }
4668
4669 static int gfx_v11_0_early_init(void *handle)
4670 {
4671         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4672
4673         adev->gfx.funcs = &gfx_v11_0_gfx_funcs;
4674
4675         adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;
4676         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
4677                                           AMDGPU_MAX_COMPUTE_RINGS);
4678
4679         gfx_v11_0_set_kiq_pm4_funcs(adev);
4680         gfx_v11_0_set_ring_funcs(adev);
4681         gfx_v11_0_set_irq_funcs(adev);
4682         gfx_v11_0_set_gds_init(adev);
4683         gfx_v11_0_set_rlc_funcs(adev);
4684         gfx_v11_0_set_mqd_funcs(adev);
4685         gfx_v11_0_set_imu_funcs(adev);
4686
4687         gfx_v11_0_init_rlcg_reg_access_ctrl(adev);
4688
4689         return gfx_v11_0_init_microcode(adev);
4690 }
4691
4692 static int gfx_v11_0_ras_late_init(void *handle)
4693 {
4694         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4695         struct ras_common_if *gfx_common_if;
4696         int ret;
4697
4698         gfx_common_if = kzalloc(sizeof(struct ras_common_if), GFP_KERNEL);
4699         if (!gfx_common_if)
4700                 return -ENOMEM;
4701
4702         gfx_common_if->block = AMDGPU_RAS_BLOCK__GFX;
4703
4704         ret = amdgpu_ras_feature_enable(adev, gfx_common_if, true);
4705         if (ret)
4706                 dev_warn(adev->dev, "Failed to enable gfx11 ras feature\n");
4707
4708         kfree(gfx_common_if);
4709         return 0;
4710 }
4711
4712 static int gfx_v11_0_late_init(void *handle)
4713 {
4714         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4715         int r;
4716
4717         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4718         if (r)
4719                 return r;
4720
4721         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4722         if (r)
4723                 return r;
4724
4725         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3)) {
4726                 r = gfx_v11_0_ras_late_init(handle);
4727                 if (r)
4728                         return r;
4729         }
4730
4731         return 0;
4732 }
4733
4734 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev)
4735 {
4736         uint32_t rlc_cntl;
4737
4738         /* if RLC is not enabled, do nothing */
4739         rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);
4740         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
4741 }
4742
4743 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev)
4744 {
4745         uint32_t data;
4746         unsigned i;
4747
4748         data = RLC_SAFE_MODE__CMD_MASK;
4749         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
4750
4751         WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data);
4752
4753         /* wait for RLC_SAFE_MODE */
4754         for (i = 0; i < adev->usec_timeout; i++) {
4755                 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),
4756                                    RLC_SAFE_MODE, CMD))
4757                         break;
4758                 udelay(1);
4759         }
4760 }
4761
4762 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev)
4763 {
4764         WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);
4765 }
4766
4767 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
4768                                       bool enable)
4769 {
4770         uint32_t def, data;
4771
4772         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK))
4773                 return;
4774
4775         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4776
4777         if (enable)
4778                 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
4779         else
4780                 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
4781
4782         if (def != data)
4783                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4784 }
4785
4786 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev,
4787                                        bool enable)
4788 {
4789         uint32_t def, data;
4790
4791         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
4792                 return;
4793
4794         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4795
4796         if (enable)
4797                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4798         else
4799                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4800
4801         if (def != data)
4802                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4803 }
4804
4805 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev,
4806                                            bool enable)
4807 {
4808         uint32_t def, data;
4809
4810         if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
4811                 return;
4812
4813         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4814
4815         if (enable)
4816                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK;
4817         else
4818                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK;
4819
4820         if (def != data)
4821                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4822 }
4823
4824 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4825                                                        bool enable)
4826 {
4827         uint32_t data, def;
4828
4829         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
4830                 return;
4831
4832         /* It is disabled by HW by default */
4833         if (enable) {
4834                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4835                         /* 1 - RLC_CGTT_MGCG_OVERRIDE */
4836                         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4837
4838                         data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4839                                   RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4840                                   RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4841
4842                         if (def != data)
4843                                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4844                 }
4845         } else {
4846                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4847                         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4848
4849                         data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4850                                  RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4851                                  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4852
4853                         if (def != data)
4854                                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4855                 }
4856         }
4857 }
4858
4859 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4860                                                        bool enable)
4861 {
4862         uint32_t def, data;
4863
4864         if (!(adev->cg_flags &
4865               (AMD_CG_SUPPORT_GFX_CGCG |
4866               AMD_CG_SUPPORT_GFX_CGLS |
4867               AMD_CG_SUPPORT_GFX_3D_CGCG |
4868               AMD_CG_SUPPORT_GFX_3D_CGLS)))
4869                 return;
4870
4871         if (enable) {
4872                 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4873
4874                 /* unset CGCG override */
4875                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4876                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4877                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4878                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4879                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG ||
4880                     adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4881                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4882
4883                 /* update CGCG override bits */
4884                 if (def != data)
4885                         WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4886
4887                 /* enable cgcg FSM(0x0000363F) */
4888                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4889
4890                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
4891                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK;
4892                         data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4893                                  RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4894                 }
4895
4896                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
4897                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK;
4898                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4899                                  RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4900                 }
4901
4902                 if (def != data)
4903                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4904
4905                 /* Program RLC_CGCG_CGLS_CTRL_3D */
4906                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4907
4908                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
4909                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK;
4910                         data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4911                                  RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4912                 }
4913
4914                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
4915                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK;
4916                         data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4917                                  RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4918                 }
4919
4920                 if (def != data)
4921                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4922
4923                 /* set IDLE_POLL_COUNT(0x00900100) */
4924                 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);
4925
4926                 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK);
4927                 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4928                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4929
4930                 if (def != data)
4931                         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data);
4932
4933                 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4934                 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
4935                 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
4936                 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
4937                 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
4938                 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data);
4939
4940                 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
4941                 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4942                 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
4943
4944                 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
4945                 if (adev->sdma.num_instances > 1) {
4946                         data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
4947                         data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4948                         WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
4949                 }
4950         } else {
4951                 /* Program RLC_CGCG_CGLS_CTRL */
4952                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4953
4954                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4955                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4956
4957                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4958                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4959
4960                 if (def != data)
4961                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4962
4963                 /* Program RLC_CGCG_CGLS_CTRL_3D */
4964                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4965
4966                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
4967                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4968                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4969                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4970
4971                 if (def != data)
4972                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4973
4974                 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
4975                 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
4976                 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
4977
4978                 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
4979                 if (adev->sdma.num_instances > 1) {
4980                         data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
4981                         data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
4982                         WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
4983                 }
4984         }
4985 }
4986
4987 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4988                                             bool enable)
4989 {
4990         amdgpu_gfx_rlc_enter_safe_mode(adev);
4991
4992         gfx_v11_0_update_coarse_grain_clock_gating(adev, enable);
4993
4994         gfx_v11_0_update_medium_grain_clock_gating(adev, enable);
4995
4996         gfx_v11_0_update_repeater_fgcg(adev, enable);
4997
4998         gfx_v11_0_update_sram_fgcg(adev, enable);
4999
5000         gfx_v11_0_update_perf_clk(adev, enable);
5001
5002         if (adev->cg_flags &
5003             (AMD_CG_SUPPORT_GFX_MGCG |
5004              AMD_CG_SUPPORT_GFX_CGLS |
5005              AMD_CG_SUPPORT_GFX_CGCG |
5006              AMD_CG_SUPPORT_GFX_3D_CGCG |
5007              AMD_CG_SUPPORT_GFX_3D_CGLS))
5008                 gfx_v11_0_enable_gui_idle_interrupt(adev, enable);
5009
5010         amdgpu_gfx_rlc_exit_safe_mode(adev);
5011
5012         return 0;
5013 }
5014
5015 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
5016 {
5017         u32 reg, data;
5018
5019         amdgpu_gfx_off_ctrl(adev, false);
5020
5021         reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
5022         if (amdgpu_sriov_is_pp_one_vf(adev))
5023                 data = RREG32_NO_KIQ(reg);
5024         else
5025                 data = RREG32(reg);
5026
5027         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
5028         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
5029
5030         if (amdgpu_sriov_is_pp_one_vf(adev))
5031                 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
5032         else
5033                 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);
5034
5035         amdgpu_gfx_off_ctrl(adev, true);
5036 }
5037
5038 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = {
5039         .is_rlc_enabled = gfx_v11_0_is_rlc_enabled,
5040         .set_safe_mode = gfx_v11_0_set_safe_mode,
5041         .unset_safe_mode = gfx_v11_0_unset_safe_mode,
5042         .init = gfx_v11_0_rlc_init,
5043         .get_csb_size = gfx_v11_0_get_csb_size,
5044         .get_csb_buffer = gfx_v11_0_get_csb_buffer,
5045         .resume = gfx_v11_0_rlc_resume,
5046         .stop = gfx_v11_0_rlc_stop,
5047         .reset = gfx_v11_0_rlc_reset,
5048         .start = gfx_v11_0_rlc_start,
5049         .update_spm_vmid = gfx_v11_0_update_spm_vmid,
5050 };
5051
5052 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)
5053 {
5054         u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
5055
5056         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
5057                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
5058         else
5059                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
5060
5061         WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data);
5062
5063         // Program RLC_PG_DELAY3 for CGPG hysteresis
5064         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
5065                 switch (adev->ip_versions[GC_HWIP][0]) {
5066                 case IP_VERSION(11, 0, 1):
5067                 case IP_VERSION(11, 0, 4):
5068                         WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);
5069                         break;
5070                 default:
5071                         break;
5072                 }
5073         }
5074 }
5075
5076 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
5077 {
5078         amdgpu_gfx_rlc_enter_safe_mode(adev);
5079
5080         gfx_v11_cntl_power_gating(adev, enable);
5081
5082         amdgpu_gfx_rlc_exit_safe_mode(adev);
5083 }
5084
5085 static int gfx_v11_0_set_powergating_state(void *handle,
5086                                            enum amd_powergating_state state)
5087 {
5088         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5089         bool enable = (state == AMD_PG_STATE_GATE);
5090
5091         if (amdgpu_sriov_vf(adev))
5092                 return 0;
5093
5094         switch (adev->ip_versions[GC_HWIP][0]) {
5095         case IP_VERSION(11, 0, 0):
5096         case IP_VERSION(11, 0, 2):
5097         case IP_VERSION(11, 0, 3):
5098                 amdgpu_gfx_off_ctrl(adev, enable);
5099                 break;
5100         case IP_VERSION(11, 0, 1):
5101         case IP_VERSION(11, 0, 4):
5102                 gfx_v11_cntl_pg(adev, enable);
5103                 amdgpu_gfx_off_ctrl(adev, enable);
5104                 break;
5105         default:
5106                 break;
5107         }
5108
5109         return 0;
5110 }
5111
5112 static int gfx_v11_0_set_clockgating_state(void *handle,
5113                                           enum amd_clockgating_state state)
5114 {
5115         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5116
5117         if (amdgpu_sriov_vf(adev))
5118                 return 0;
5119
5120         switch (adev->ip_versions[GC_HWIP][0]) {
5121         case IP_VERSION(11, 0, 0):
5122         case IP_VERSION(11, 0, 1):
5123         case IP_VERSION(11, 0, 2):
5124         case IP_VERSION(11, 0, 3):
5125         case IP_VERSION(11, 0, 4):
5126                 gfx_v11_0_update_gfx_clock_gating(adev,
5127                                 state ==  AMD_CG_STATE_GATE);
5128                 break;
5129         default:
5130                 break;
5131         }
5132
5133         return 0;
5134 }
5135
5136 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags)
5137 {
5138         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5139         int data;
5140
5141         /* AMD_CG_SUPPORT_GFX_MGCG */
5142         data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
5143         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
5144                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
5145
5146         /* AMD_CG_SUPPORT_REPEATER_FGCG */
5147         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK))
5148                 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG;
5149
5150         /* AMD_CG_SUPPORT_GFX_FGCG */
5151         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
5152                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
5153
5154         /* AMD_CG_SUPPORT_GFX_PERF_CLK */
5155         if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK))
5156                 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK;
5157
5158         /* AMD_CG_SUPPORT_GFX_CGCG */
5159         data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
5160         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
5161                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
5162
5163         /* AMD_CG_SUPPORT_GFX_CGLS */
5164         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
5165                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
5166
5167         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5168         data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
5169         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
5170                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
5171
5172         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
5173         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
5174                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
5175 }
5176
5177 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
5178 {
5179         /* gfx11 is 32bit rptr*/
5180         return *(uint32_t *)ring->rptr_cpu_addr;
5181 }
5182
5183 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
5184 {
5185         struct amdgpu_device *adev = ring->adev;
5186         u64 wptr;
5187
5188         /* XXX check if swapping is necessary on BE */
5189         if (ring->use_doorbell) {
5190                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
5191         } else {
5192                 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);
5193                 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;
5194         }
5195
5196         return wptr;
5197 }
5198
5199 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
5200 {
5201         struct amdgpu_device *adev = ring->adev;
5202         uint32_t *wptr_saved;
5203         uint32_t *is_queue_unmap;
5204         uint64_t aggregated_db_index;
5205         uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size;
5206         uint64_t wptr_tmp;
5207
5208         if (ring->is_mes_queue) {
5209                 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
5210                 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
5211                                               sizeof(uint32_t));
5212                 aggregated_db_index =
5213                         amdgpu_mes_get_aggregated_doorbell_index(adev,
5214                                                                  ring->hw_prio);
5215
5216                 wptr_tmp = ring->wptr & ring->buf_mask;
5217                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
5218                 *wptr_saved = wptr_tmp;
5219                 /* assume doorbell always being used by mes mapped queue */
5220                 if (*is_queue_unmap) {
5221                         WDOORBELL64(aggregated_db_index, wptr_tmp);
5222                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
5223                 } else {
5224                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
5225
5226                         if (*is_queue_unmap)
5227                                 WDOORBELL64(aggregated_db_index, wptr_tmp);
5228                 }
5229         } else {
5230                 if (ring->use_doorbell) {
5231                         /* XXX check if swapping is necessary on BE */
5232                         atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
5233                                      ring->wptr);
5234                         WDOORBELL64(ring->doorbell_index, ring->wptr);
5235                 } else {
5236                         WREG32_SOC15(GC, 0, regCP_RB0_WPTR,
5237                                      lower_32_bits(ring->wptr));
5238                         WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI,
5239                                      upper_32_bits(ring->wptr));
5240                 }
5241         }
5242 }
5243
5244 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
5245 {
5246         /* gfx11 hardware is 32bit rptr */
5247         return *(uint32_t *)ring->rptr_cpu_addr;
5248 }
5249
5250 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
5251 {
5252         u64 wptr;
5253
5254         /* XXX check if swapping is necessary on BE */
5255         if (ring->use_doorbell)
5256                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
5257         else
5258                 BUG();
5259         return wptr;
5260 }
5261
5262 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
5263 {
5264         struct amdgpu_device *adev = ring->adev;
5265         uint32_t *wptr_saved;
5266         uint32_t *is_queue_unmap;
5267         uint64_t aggregated_db_index;
5268         uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size;
5269         uint64_t wptr_tmp;
5270
5271         if (ring->is_mes_queue) {
5272                 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
5273                 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
5274                                               sizeof(uint32_t));
5275                 aggregated_db_index =
5276                         amdgpu_mes_get_aggregated_doorbell_index(adev,
5277                                                                  ring->hw_prio);
5278
5279                 wptr_tmp = ring->wptr & ring->buf_mask;
5280                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
5281                 *wptr_saved = wptr_tmp;
5282                 /* assume doorbell always used by mes mapped queue */
5283                 if (*is_queue_unmap) {
5284                         WDOORBELL64(aggregated_db_index, wptr_tmp);
5285                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
5286                 } else {
5287                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
5288
5289                         if (*is_queue_unmap)
5290                                 WDOORBELL64(aggregated_db_index, wptr_tmp);
5291                 }
5292         } else {
5293                 /* XXX check if swapping is necessary on BE */
5294                 if (ring->use_doorbell) {
5295                         atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
5296                                      ring->wptr);
5297                         WDOORBELL64(ring->doorbell_index, ring->wptr);
5298                 } else {
5299                         BUG(); /* only DOORBELL method supported on gfx11 now */
5300                 }
5301         }
5302 }
5303
5304 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
5305 {
5306         struct amdgpu_device *adev = ring->adev;
5307         u32 ref_and_mask, reg_mem_engine;
5308         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
5309
5310         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
5311                 switch (ring->me) {
5312                 case 1:
5313                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
5314                         break;
5315                 case 2:
5316                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
5317                         break;
5318                 default:
5319                         return;
5320                 }
5321                 reg_mem_engine = 0;
5322         } else {
5323                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
5324                 reg_mem_engine = 1; /* pfp */
5325         }
5326
5327         gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
5328                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
5329                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
5330                                ref_and_mask, ref_and_mask, 0x20);
5331 }
5332
5333 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
5334                                        struct amdgpu_job *job,
5335                                        struct amdgpu_ib *ib,
5336                                        uint32_t flags)
5337 {
5338         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5339         u32 header, control = 0;
5340
5341         BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE);
5342
5343         header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
5344
5345         control |= ib->length_dw | (vmid << 24);
5346
5347         if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
5348                 control |= INDIRECT_BUFFER_PRE_ENB(1);
5349
5350                 if (flags & AMDGPU_IB_PREEMPTED)
5351                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
5352
5353                 if (vmid)
5354                         gfx_v11_0_ring_emit_de_meta(ring,
5355                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
5356         }
5357
5358         if (ring->is_mes_queue)
5359                 /* inherit vmid from mqd */
5360                 control |= 0x400000;
5361
5362         amdgpu_ring_write(ring, header);
5363         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
5364         amdgpu_ring_write(ring,
5365 #ifdef __BIG_ENDIAN
5366                 (2 << 0) |
5367 #endif
5368                 lower_32_bits(ib->gpu_addr));
5369         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5370         amdgpu_ring_write(ring, control);
5371 }
5372
5373 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
5374                                            struct amdgpu_job *job,
5375                                            struct amdgpu_ib *ib,
5376                                            uint32_t flags)
5377 {
5378         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5379         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
5380
5381         if (ring->is_mes_queue)
5382                 /* inherit vmid from mqd */
5383                 control |= 0x40000000;
5384
5385         /* Currently, there is a high possibility to get wave ID mismatch
5386          * between ME and GDS, leading to a hw deadlock, because ME generates
5387          * different wave IDs than the GDS expects. This situation happens
5388          * randomly when at least 5 compute pipes use GDS ordered append.
5389          * The wave IDs generated by ME are also wrong after suspend/resume.
5390          * Those are probably bugs somewhere else in the kernel driver.
5391          *
5392          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
5393          * GDS to 0 for this ring (me/pipe).
5394          */
5395         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
5396                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
5397                 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID);
5398                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
5399         }
5400
5401         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
5402         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
5403         amdgpu_ring_write(ring,
5404 #ifdef __BIG_ENDIAN
5405                                 (2 << 0) |
5406 #endif
5407                                 lower_32_bits(ib->gpu_addr));
5408         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5409         amdgpu_ring_write(ring, control);
5410 }
5411
5412 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
5413                                      u64 seq, unsigned flags)
5414 {
5415         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
5416         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
5417
5418         /* RELEASE_MEM - flush caches, send int */
5419         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
5420         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
5421                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
5422                                  PACKET3_RELEASE_MEM_GCR_GL2_INV |
5423                                  PACKET3_RELEASE_MEM_GCR_GL2_US |
5424                                  PACKET3_RELEASE_MEM_GCR_GL1_INV |
5425                                  PACKET3_RELEASE_MEM_GCR_GLV_INV |
5426                                  PACKET3_RELEASE_MEM_GCR_GLM_INV |
5427                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
5428                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
5429                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
5430                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
5431         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
5432                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
5433
5434         /*
5435          * the address should be Qword aligned if 64bit write, Dword
5436          * aligned if only send 32bit data low (discard data high)
5437          */
5438         if (write64bit)
5439                 BUG_ON(addr & 0x7);
5440         else
5441                 BUG_ON(addr & 0x3);
5442         amdgpu_ring_write(ring, lower_32_bits(addr));
5443         amdgpu_ring_write(ring, upper_32_bits(addr));
5444         amdgpu_ring_write(ring, lower_32_bits(seq));
5445         amdgpu_ring_write(ring, upper_32_bits(seq));
5446         amdgpu_ring_write(ring, ring->is_mes_queue ?
5447                          (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
5448 }
5449
5450 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
5451 {
5452         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5453         uint32_t seq = ring->fence_drv.sync_seq;
5454         uint64_t addr = ring->fence_drv.gpu_addr;
5455
5456         gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
5457                                upper_32_bits(addr), seq, 0xffffffff, 4);
5458 }
5459
5460 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
5461                                    uint16_t pasid, uint32_t flush_type,
5462                                    bool all_hub, uint8_t dst_sel)
5463 {
5464         amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
5465         amdgpu_ring_write(ring,
5466                           PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
5467                           PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
5468                           PACKET3_INVALIDATE_TLBS_PASID(pasid) |
5469                           PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
5470 }
5471
5472 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
5473                                          unsigned vmid, uint64_t pd_addr)
5474 {
5475         if (ring->is_mes_queue)
5476                 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
5477         else
5478                 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
5479
5480         /* compute doesn't have PFP */
5481         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
5482                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5483                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5484                 amdgpu_ring_write(ring, 0x0);
5485         }
5486 }
5487
5488 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
5489                                           u64 seq, unsigned int flags)
5490 {
5491         struct amdgpu_device *adev = ring->adev;
5492
5493         /* we only allocate 32bit for each seq wb address */
5494         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
5495
5496         /* write fence seq to the "addr" */
5497         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5498         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5499                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
5500         amdgpu_ring_write(ring, lower_32_bits(addr));
5501         amdgpu_ring_write(ring, upper_32_bits(addr));
5502         amdgpu_ring_write(ring, lower_32_bits(seq));
5503
5504         if (flags & AMDGPU_FENCE_FLAG_INT) {
5505                 /* set register to trigger INT */
5506                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5507                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5508                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
5509                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));
5510                 amdgpu_ring_write(ring, 0);
5511                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
5512         }
5513 }
5514
5515 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
5516                                          uint32_t flags)
5517 {
5518         uint32_t dw2 = 0;
5519
5520         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
5521         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
5522                 /* set load_global_config & load_global_uconfig */
5523                 dw2 |= 0x8001;
5524                 /* set load_cs_sh_regs */
5525                 dw2 |= 0x01000000;
5526                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
5527                 dw2 |= 0x10002;
5528         }
5529
5530         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5531         amdgpu_ring_write(ring, dw2);
5532         amdgpu_ring_write(ring, 0);
5533 }
5534
5535 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
5536 {
5537         unsigned ret;
5538
5539         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
5540         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
5541         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
5542         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
5543         ret = ring->wptr & ring->buf_mask;
5544         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
5545
5546         return ret;
5547 }
5548
5549 static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
5550 {
5551         unsigned cur;
5552         BUG_ON(offset > ring->buf_mask);
5553         BUG_ON(ring->ring[offset] != 0x55aa55aa);
5554
5555         cur = (ring->wptr - 1) & ring->buf_mask;
5556         if (likely(cur > offset))
5557                 ring->ring[offset] = cur - offset;
5558         else
5559                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
5560 }
5561
5562 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring)
5563 {
5564         int i, r = 0;
5565         struct amdgpu_device *adev = ring->adev;
5566         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
5567         struct amdgpu_ring *kiq_ring = &kiq->ring;
5568         unsigned long flags;
5569
5570         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
5571                 return -EINVAL;
5572
5573         spin_lock_irqsave(&kiq->ring_lock, flags);
5574
5575         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
5576                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
5577                 return -ENOMEM;
5578         }
5579
5580         /* assert preemption condition */
5581         amdgpu_ring_set_preempt_cond_exec(ring, false);
5582
5583         /* assert IB preemption, emit the trailing fence */
5584         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
5585                                    ring->trail_fence_gpu_addr,
5586                                    ++ring->trail_seq);
5587         amdgpu_ring_commit(kiq_ring);
5588
5589         spin_unlock_irqrestore(&kiq->ring_lock, flags);
5590
5591         /* poll the trailing fence */
5592         for (i = 0; i < adev->usec_timeout; i++) {
5593                 if (ring->trail_seq ==
5594                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
5595                         break;
5596                 udelay(1);
5597         }
5598
5599         if (i >= adev->usec_timeout) {
5600                 r = -EINVAL;
5601                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
5602         }
5603
5604         /* deassert preemption condition */
5605         amdgpu_ring_set_preempt_cond_exec(ring, true);
5606         return r;
5607 }
5608
5609 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
5610 {
5611         struct amdgpu_device *adev = ring->adev;
5612         struct v10_de_ib_state de_payload = {0};
5613         uint64_t offset, gds_addr, de_payload_gpu_addr;
5614         void *de_payload_cpu_addr;
5615         int cnt;
5616
5617         if (ring->is_mes_queue) {
5618                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5619                                   gfx[0].gfx_meta_data) +
5620                         offsetof(struct v10_gfx_meta_data, de_payload);
5621                 de_payload_gpu_addr =
5622                         amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
5623                 de_payload_cpu_addr =
5624                         amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
5625
5626                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5627                                   gfx[0].gds_backup) +
5628                         offsetof(struct v10_gfx_meta_data, de_payload);
5629                 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
5630         } else {
5631                 offset = offsetof(struct v10_gfx_meta_data, de_payload);
5632                 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
5633                 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
5634
5635                 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
5636                                  AMDGPU_CSA_SIZE - adev->gds.gds_size,
5637                                  PAGE_SIZE);
5638         }
5639
5640         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
5641         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
5642
5643         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
5644         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
5645         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5646                                  WRITE_DATA_DST_SEL(8) |
5647                                  WR_CONFIRM) |
5648                                  WRITE_DATA_CACHE_POLICY(0));
5649         amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
5650         amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
5651
5652         if (resume)
5653                 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
5654                                            sizeof(de_payload) >> 2);
5655         else
5656                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
5657                                            sizeof(de_payload) >> 2);
5658 }
5659
5660 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
5661                                     bool secure)
5662 {
5663         uint32_t v = secure ? FRAME_TMZ : 0;
5664
5665         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
5666         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
5667 }
5668
5669 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
5670                                      uint32_t reg_val_offs)
5671 {
5672         struct amdgpu_device *adev = ring->adev;
5673
5674         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
5675         amdgpu_ring_write(ring, 0 |     /* src: register*/
5676                                 (5 << 8) |      /* dst: memory */
5677                                 (1 << 20));     /* write confirm */
5678         amdgpu_ring_write(ring, reg);
5679         amdgpu_ring_write(ring, 0);
5680         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
5681                                 reg_val_offs * 4));
5682         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
5683                                 reg_val_offs * 4));
5684 }
5685
5686 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
5687                                    uint32_t val)
5688 {
5689         uint32_t cmd = 0;
5690
5691         switch (ring->funcs->type) {
5692         case AMDGPU_RING_TYPE_GFX:
5693                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
5694                 break;
5695         case AMDGPU_RING_TYPE_KIQ:
5696                 cmd = (1 << 16); /* no inc addr */
5697                 break;
5698         default:
5699                 cmd = WR_CONFIRM;
5700                 break;
5701         }
5702         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5703         amdgpu_ring_write(ring, cmd);
5704         amdgpu_ring_write(ring, reg);
5705         amdgpu_ring_write(ring, 0);
5706         amdgpu_ring_write(ring, val);
5707 }
5708
5709 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
5710                                         uint32_t val, uint32_t mask)
5711 {
5712         gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
5713 }
5714
5715 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
5716                                                    uint32_t reg0, uint32_t reg1,
5717                                                    uint32_t ref, uint32_t mask)
5718 {
5719         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5720
5721         gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
5722                                ref, mask, 0x20);
5723 }
5724
5725 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring,
5726                                          unsigned vmid)
5727 {
5728         struct amdgpu_device *adev = ring->adev;
5729         uint32_t value = 0;
5730
5731         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
5732         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
5733         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
5734         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
5735         WREG32_SOC15(GC, 0, regSQ_CMD, value);
5736 }
5737
5738 static void
5739 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
5740                                       uint32_t me, uint32_t pipe,
5741                                       enum amdgpu_interrupt_state state)
5742 {
5743         uint32_t cp_int_cntl, cp_int_cntl_reg;
5744
5745         if (!me) {
5746                 switch (pipe) {
5747                 case 0:
5748                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
5749                         break;
5750                 case 1:
5751                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1);
5752                         break;
5753                 default:
5754                         DRM_DEBUG("invalid pipe %d\n", pipe);
5755                         return;
5756                 }
5757         } else {
5758                 DRM_DEBUG("invalid me %d\n", me);
5759                 return;
5760         }
5761
5762         switch (state) {
5763         case AMDGPU_IRQ_STATE_DISABLE:
5764                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5765                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5766                                             TIME_STAMP_INT_ENABLE, 0);
5767                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5768                                             GENERIC0_INT_ENABLE, 0);
5769                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
5770                 break;
5771         case AMDGPU_IRQ_STATE_ENABLE:
5772                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5773                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5774                                             TIME_STAMP_INT_ENABLE, 1);
5775                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5776                                             GENERIC0_INT_ENABLE, 1);
5777                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
5778                 break;
5779         default:
5780                 break;
5781         }
5782 }
5783
5784 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
5785                                                      int me, int pipe,
5786                                                      enum amdgpu_interrupt_state state)
5787 {
5788         u32 mec_int_cntl, mec_int_cntl_reg;
5789
5790         /*
5791          * amdgpu controls only the first MEC. That's why this function only
5792          * handles the setting of interrupts for this specific MEC. All other
5793          * pipes' interrupts are set by amdkfd.
5794          */
5795
5796         if (me == 1) {
5797                 switch (pipe) {
5798                 case 0:
5799                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
5800                         break;
5801                 case 1:
5802                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
5803                         break;
5804                 case 2:
5805                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL);
5806                         break;
5807                 case 3:
5808                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL);
5809                         break;
5810                 default:
5811                         DRM_DEBUG("invalid pipe %d\n", pipe);
5812                         return;
5813                 }
5814         } else {
5815                 DRM_DEBUG("invalid me %d\n", me);
5816                 return;
5817         }
5818
5819         switch (state) {
5820         case AMDGPU_IRQ_STATE_DISABLE:
5821                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
5822                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5823                                              TIME_STAMP_INT_ENABLE, 0);
5824                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5825                                              GENERIC0_INT_ENABLE, 0);
5826                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
5827                 break;
5828         case AMDGPU_IRQ_STATE_ENABLE:
5829                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
5830                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5831                                              TIME_STAMP_INT_ENABLE, 1);
5832                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5833                                              GENERIC0_INT_ENABLE, 1);
5834                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
5835                 break;
5836         default:
5837                 break;
5838         }
5839 }
5840
5841 #define CP_ME1_PIPE_INST_ADDR_INTERVAL  0x1
5842 #define SET_ECC_ME_PIPE_STATE(reg_addr, state) \
5843         do { \
5844                 uint32_t tmp = RREG32_SOC15_IP(GC, reg_addr); \
5845                 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, state); \
5846                 WREG32_SOC15_IP(GC, reg_addr, tmp); \
5847         } while (0)
5848
5849 static int gfx_v11_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
5850                                                         struct amdgpu_irq_src *source,
5851                                                         unsigned type,
5852                                                         enum amdgpu_interrupt_state state)
5853 {
5854         uint32_t ecc_irq_state = 0;
5855         uint32_t pipe0_int_cntl_addr = 0;
5856         int i = 0;
5857
5858         ecc_irq_state = (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0;
5859
5860         pipe0_int_cntl_addr = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
5861
5862         WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, ecc_irq_state);
5863
5864         for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++)
5865                 SET_ECC_ME_PIPE_STATE(pipe0_int_cntl_addr + i * CP_ME1_PIPE_INST_ADDR_INTERVAL,
5866                                         ecc_irq_state);
5867
5868         return 0;
5869 }
5870
5871 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5872                                             struct amdgpu_irq_src *src,
5873                                             unsigned type,
5874                                             enum amdgpu_interrupt_state state)
5875 {
5876         switch (type) {
5877         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
5878                 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
5879                 break;
5880         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
5881                 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
5882                 break;
5883         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5884                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5885                 break;
5886         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5887                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5888                 break;
5889         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5890                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5891                 break;
5892         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5893                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5894                 break;
5895         default:
5896                 break;
5897         }
5898         return 0;
5899 }
5900
5901 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev,
5902                              struct amdgpu_irq_src *source,
5903                              struct amdgpu_iv_entry *entry)
5904 {
5905         int i;
5906         u8 me_id, pipe_id, queue_id;
5907         struct amdgpu_ring *ring;
5908         uint32_t mes_queue_id = entry->src_data[0];
5909
5910         DRM_DEBUG("IH: CP EOP\n");
5911
5912         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
5913                 struct amdgpu_mes_queue *queue;
5914
5915                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
5916
5917                 spin_lock(&adev->mes.queue_id_lock);
5918                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
5919                 if (queue) {
5920                         DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
5921                         amdgpu_fence_process(queue->ring);
5922                 }
5923                 spin_unlock(&adev->mes.queue_id_lock);
5924         } else {
5925                 me_id = (entry->ring_id & 0x0c) >> 2;
5926                 pipe_id = (entry->ring_id & 0x03) >> 0;
5927                 queue_id = (entry->ring_id & 0x70) >> 4;
5928
5929                 switch (me_id) {
5930                 case 0:
5931                         if (pipe_id == 0)
5932                                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5933                         else
5934                                 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
5935                         break;
5936                 case 1:
5937                 case 2:
5938                         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5939                                 ring = &adev->gfx.compute_ring[i];
5940                                 /* Per-queue interrupt is supported for MEC starting from VI.
5941                                  * The interrupt can only be enabled/disabled per pipe instead
5942                                  * of per queue.
5943                                  */
5944                                 if ((ring->me == me_id) &&
5945                                     (ring->pipe == pipe_id) &&
5946                                     (ring->queue == queue_id))
5947                                         amdgpu_fence_process(ring);
5948                         }
5949                         break;
5950                 }
5951         }
5952
5953         return 0;
5954 }
5955
5956 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
5957                                               struct amdgpu_irq_src *source,
5958                                               unsigned type,
5959                                               enum amdgpu_interrupt_state state)
5960 {
5961         switch (state) {
5962         case AMDGPU_IRQ_STATE_DISABLE:
5963         case AMDGPU_IRQ_STATE_ENABLE:
5964                 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
5965                                PRIV_REG_INT_ENABLE,
5966                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5967                 break;
5968         default:
5969                 break;
5970         }
5971
5972         return 0;
5973 }
5974
5975 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5976                                                struct amdgpu_irq_src *source,
5977                                                unsigned type,
5978                                                enum amdgpu_interrupt_state state)
5979 {
5980         switch (state) {
5981         case AMDGPU_IRQ_STATE_DISABLE:
5982         case AMDGPU_IRQ_STATE_ENABLE:
5983                 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
5984                                PRIV_INSTR_INT_ENABLE,
5985                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5986                 break;
5987         default:
5988                 break;
5989         }
5990
5991         return 0;
5992 }
5993
5994 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev,
5995                                         struct amdgpu_iv_entry *entry)
5996 {
5997         u8 me_id, pipe_id, queue_id;
5998         struct amdgpu_ring *ring;
5999         int i;
6000
6001         me_id = (entry->ring_id & 0x0c) >> 2;
6002         pipe_id = (entry->ring_id & 0x03) >> 0;
6003         queue_id = (entry->ring_id & 0x70) >> 4;
6004
6005         switch (me_id) {
6006         case 0:
6007                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6008                         ring = &adev->gfx.gfx_ring[i];
6009                         /* we only enabled 1 gfx queue per pipe for now */
6010                         if (ring->me == me_id && ring->pipe == pipe_id)
6011                                 drm_sched_fault(&ring->sched);
6012                 }
6013                 break;
6014         case 1:
6015         case 2:
6016                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6017                         ring = &adev->gfx.compute_ring[i];
6018                         if (ring->me == me_id && ring->pipe == pipe_id &&
6019                             ring->queue == queue_id)
6020                                 drm_sched_fault(&ring->sched);
6021                 }
6022                 break;
6023         default:
6024                 BUG();
6025                 break;
6026         }
6027 }
6028
6029 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev,
6030                                   struct amdgpu_irq_src *source,
6031                                   struct amdgpu_iv_entry *entry)
6032 {
6033         DRM_ERROR("Illegal register access in command stream\n");
6034         gfx_v11_0_handle_priv_fault(adev, entry);
6035         return 0;
6036 }
6037
6038 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev,
6039                                    struct amdgpu_irq_src *source,
6040                                    struct amdgpu_iv_entry *entry)
6041 {
6042         DRM_ERROR("Illegal instruction in command stream\n");
6043         gfx_v11_0_handle_priv_fault(adev, entry);
6044         return 0;
6045 }
6046
6047 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev,
6048                                   struct amdgpu_irq_src *source,
6049                                   struct amdgpu_iv_entry *entry)
6050 {
6051         if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq)
6052                 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry);
6053
6054         return 0;
6055 }
6056
6057 #if 0
6058 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
6059                                              struct amdgpu_irq_src *src,
6060                                              unsigned int type,
6061                                              enum amdgpu_interrupt_state state)
6062 {
6063         uint32_t tmp, target;
6064         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
6065
6066         target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
6067         target += ring->pipe;
6068
6069         switch (type) {
6070         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
6071                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
6072                         tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6073                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
6074                                             GENERIC2_INT_ENABLE, 0);
6075                         WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6076
6077                         tmp = RREG32_SOC15_IP(GC, target);
6078                         tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
6079                                             GENERIC2_INT_ENABLE, 0);
6080                         WREG32_SOC15_IP(GC, target, tmp);
6081                 } else {
6082                         tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6083                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
6084                                             GENERIC2_INT_ENABLE, 1);
6085                         WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6086
6087                         tmp = RREG32_SOC15_IP(GC, target);
6088                         tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
6089                                             GENERIC2_INT_ENABLE, 1);
6090                         WREG32_SOC15_IP(GC, target, tmp);
6091                 }
6092                 break;
6093         default:
6094                 BUG(); /* kiq only support GENERIC2_INT now */
6095                 break;
6096         }
6097         return 0;
6098 }
6099 #endif
6100
6101 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring)
6102 {
6103         const unsigned int gcr_cntl =
6104                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
6105                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
6106                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
6107                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
6108                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
6109                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
6110                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
6111                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
6112
6113         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
6114         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
6115         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
6116         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
6117         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
6118         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6119         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
6120         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
6121         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
6122 }
6123
6124 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = {
6125         .name = "gfx_v11_0",
6126         .early_init = gfx_v11_0_early_init,
6127         .late_init = gfx_v11_0_late_init,
6128         .sw_init = gfx_v11_0_sw_init,
6129         .sw_fini = gfx_v11_0_sw_fini,
6130         .hw_init = gfx_v11_0_hw_init,
6131         .hw_fini = gfx_v11_0_hw_fini,
6132         .suspend = gfx_v11_0_suspend,
6133         .resume = gfx_v11_0_resume,
6134         .is_idle = gfx_v11_0_is_idle,
6135         .wait_for_idle = gfx_v11_0_wait_for_idle,
6136         .soft_reset = gfx_v11_0_soft_reset,
6137         .check_soft_reset = gfx_v11_0_check_soft_reset,
6138         .set_clockgating_state = gfx_v11_0_set_clockgating_state,
6139         .set_powergating_state = gfx_v11_0_set_powergating_state,
6140         .get_clockgating_state = gfx_v11_0_get_clockgating_state,
6141 };
6142
6143 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
6144         .type = AMDGPU_RING_TYPE_GFX,
6145         .align_mask = 0xff,
6146         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6147         .support_64bit_ptrs = true,
6148         .secure_submission_supported = true,
6149         .vmhub = AMDGPU_GFXHUB_0,
6150         .get_rptr = gfx_v11_0_ring_get_rptr_gfx,
6151         .get_wptr = gfx_v11_0_ring_get_wptr_gfx,
6152         .set_wptr = gfx_v11_0_ring_set_wptr_gfx,
6153         .emit_frame_size = /* totally 242 maximum if 16 IBs */
6154                 5 + /* COND_EXEC */
6155                 7 + /* PIPELINE_SYNC */
6156                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6157                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6158                 2 + /* VM_FLUSH */
6159                 8 + /* FENCE for VM_FLUSH */
6160                 20 + /* GDS switch */
6161                 5 + /* COND_EXEC */
6162                 7 + /* HDP_flush */
6163                 4 + /* VGT_flush */
6164                 31 + /* DE_META */
6165                 3 + /* CNTX_CTRL */
6166                 5 + /* HDP_INVL */
6167                 8 + 8 + /* FENCE x2 */
6168                 8, /* gfx_v11_0_emit_mem_sync */
6169         .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */
6170         .emit_ib = gfx_v11_0_ring_emit_ib_gfx,
6171         .emit_fence = gfx_v11_0_ring_emit_fence,
6172         .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync,
6173         .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush,
6174         .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch,
6175         .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush,
6176         .test_ring = gfx_v11_0_ring_test_ring,
6177         .test_ib = gfx_v11_0_ring_test_ib,
6178         .insert_nop = amdgpu_ring_insert_nop,
6179         .pad_ib = amdgpu_ring_generic_pad_ib,
6180         .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl,
6181         .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec,
6182         .patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec,
6183         .preempt_ib = gfx_v11_0_ring_preempt_ib,
6184         .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl,
6185         .emit_wreg = gfx_v11_0_ring_emit_wreg,
6186         .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6187         .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6188         .soft_recovery = gfx_v11_0_ring_soft_recovery,
6189         .emit_mem_sync = gfx_v11_0_emit_mem_sync,
6190 };
6191
6192 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = {
6193         .type = AMDGPU_RING_TYPE_COMPUTE,
6194         .align_mask = 0xff,
6195         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6196         .support_64bit_ptrs = true,
6197         .vmhub = AMDGPU_GFXHUB_0,
6198         .get_rptr = gfx_v11_0_ring_get_rptr_compute,
6199         .get_wptr = gfx_v11_0_ring_get_wptr_compute,
6200         .set_wptr = gfx_v11_0_ring_set_wptr_compute,
6201         .emit_frame_size =
6202                 20 + /* gfx_v11_0_ring_emit_gds_switch */
6203                 7 + /* gfx_v11_0_ring_emit_hdp_flush */
6204                 5 + /* hdp invalidate */
6205                 7 + /* gfx_v11_0_ring_emit_pipeline_sync */
6206                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6207                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6208                 2 + /* gfx_v11_0_ring_emit_vm_flush */
6209                 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */
6210                 8, /* gfx_v11_0_emit_mem_sync */
6211         .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */
6212         .emit_ib = gfx_v11_0_ring_emit_ib_compute,
6213         .emit_fence = gfx_v11_0_ring_emit_fence,
6214         .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync,
6215         .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush,
6216         .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch,
6217         .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush,
6218         .test_ring = gfx_v11_0_ring_test_ring,
6219         .test_ib = gfx_v11_0_ring_test_ib,
6220         .insert_nop = amdgpu_ring_insert_nop,
6221         .pad_ib = amdgpu_ring_generic_pad_ib,
6222         .emit_wreg = gfx_v11_0_ring_emit_wreg,
6223         .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6224         .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6225         .emit_mem_sync = gfx_v11_0_emit_mem_sync,
6226 };
6227
6228 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = {
6229         .type = AMDGPU_RING_TYPE_KIQ,
6230         .align_mask = 0xff,
6231         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6232         .support_64bit_ptrs = true,
6233         .vmhub = AMDGPU_GFXHUB_0,
6234         .get_rptr = gfx_v11_0_ring_get_rptr_compute,
6235         .get_wptr = gfx_v11_0_ring_get_wptr_compute,
6236         .set_wptr = gfx_v11_0_ring_set_wptr_compute,
6237         .emit_frame_size =
6238                 20 + /* gfx_v11_0_ring_emit_gds_switch */
6239                 7 + /* gfx_v11_0_ring_emit_hdp_flush */
6240                 5 + /*hdp invalidate */
6241                 7 + /* gfx_v11_0_ring_emit_pipeline_sync */
6242                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6243                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6244                 2 + /* gfx_v11_0_ring_emit_vm_flush */
6245                 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */
6246         .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */
6247         .emit_ib = gfx_v11_0_ring_emit_ib_compute,
6248         .emit_fence = gfx_v11_0_ring_emit_fence_kiq,
6249         .test_ring = gfx_v11_0_ring_test_ring,
6250         .test_ib = gfx_v11_0_ring_test_ib,
6251         .insert_nop = amdgpu_ring_insert_nop,
6252         .pad_ib = amdgpu_ring_generic_pad_ib,
6253         .emit_rreg = gfx_v11_0_ring_emit_rreg,
6254         .emit_wreg = gfx_v11_0_ring_emit_wreg,
6255         .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6256         .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6257 };
6258
6259 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev)
6260 {
6261         int i;
6262
6263         adev->gfx.kiq.ring.funcs = &gfx_v11_0_ring_funcs_kiq;
6264
6265         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6266                 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx;
6267
6268         for (i = 0; i < adev->gfx.num_compute_rings; i++)
6269                 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute;
6270 }
6271
6272 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = {
6273         .set = gfx_v11_0_set_eop_interrupt_state,
6274         .process = gfx_v11_0_eop_irq,
6275 };
6276
6277 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = {
6278         .set = gfx_v11_0_set_priv_reg_fault_state,
6279         .process = gfx_v11_0_priv_reg_irq,
6280 };
6281
6282 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = {
6283         .set = gfx_v11_0_set_priv_inst_fault_state,
6284         .process = gfx_v11_0_priv_inst_irq,
6285 };
6286
6287 static const struct amdgpu_irq_src_funcs gfx_v11_0_cp_ecc_error_irq_funcs = {
6288         .set = gfx_v11_0_set_cp_ecc_error_state,
6289         .process = amdgpu_gfx_cp_ecc_error_irq,
6290 };
6291
6292 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = {
6293         .process = gfx_v11_0_rlc_gc_fed_irq,
6294 };
6295
6296 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev)
6297 {
6298         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
6299         adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs;
6300
6301         adev->gfx.priv_reg_irq.num_types = 1;
6302         adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs;
6303
6304         adev->gfx.priv_inst_irq.num_types = 1;
6305         adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs;
6306
6307         adev->gfx.cp_ecc_error_irq.num_types = 1; /* CP ECC error */
6308         adev->gfx.cp_ecc_error_irq.funcs = &gfx_v11_0_cp_ecc_error_irq_funcs;
6309
6310         adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */
6311         adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs;
6312
6313 }
6314
6315 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev)
6316 {
6317         if (adev->flags & AMD_IS_APU)
6318                 adev->gfx.imu.mode = MISSION_MODE;
6319         else
6320                 adev->gfx.imu.mode = DEBUG_MODE;
6321
6322         adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs;
6323 }
6324
6325 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev)
6326 {
6327         adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs;
6328 }
6329
6330 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev)
6331 {
6332         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
6333                             adev->gfx.config.max_sh_per_se *
6334                             adev->gfx.config.max_shader_engines;
6335
6336         adev->gds.gds_size = 0x1000;
6337         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
6338         adev->gds.gws_size = 64;
6339         adev->gds.oa_size = 16;
6340 }
6341
6342 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev)
6343 {
6344         /* set gfx eng mqd */
6345         adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
6346                 sizeof(struct v11_gfx_mqd);
6347         adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
6348                 gfx_v11_0_gfx_mqd_init;
6349         /* set compute eng mqd */
6350         adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
6351                 sizeof(struct v11_compute_mqd);
6352         adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
6353                 gfx_v11_0_compute_mqd_init;
6354 }
6355
6356 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
6357                                                           u32 bitmap)
6358 {
6359         u32 data;
6360
6361         if (!bitmap)
6362                 return;
6363
6364         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
6365         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
6366
6367         WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data);
6368 }
6369
6370 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
6371 {
6372         u32 data, wgp_bitmask;
6373         data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);
6374         data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);
6375
6376         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
6377         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
6378
6379         wgp_bitmask =
6380                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
6381
6382         return (~data) & wgp_bitmask;
6383 }
6384
6385 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
6386 {
6387         u32 wgp_idx, wgp_active_bitmap;
6388         u32 cu_bitmap_per_wgp, cu_active_bitmap;
6389
6390         wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev);
6391         cu_active_bitmap = 0;
6392
6393         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
6394                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
6395                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
6396                 if (wgp_active_bitmap & (1 << wgp_idx))
6397                         cu_active_bitmap |= cu_bitmap_per_wgp;
6398         }
6399
6400         return cu_active_bitmap;
6401 }
6402
6403 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev,
6404                                  struct amdgpu_cu_info *cu_info)
6405 {
6406         int i, j, k, counter, active_cu_number = 0;
6407         u32 mask, bitmap;
6408         unsigned disable_masks[8 * 2];
6409
6410         if (!adev || !cu_info)
6411                 return -EINVAL;
6412
6413         amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2);
6414
6415         mutex_lock(&adev->grbm_idx_mutex);
6416         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
6417                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
6418                         mask = 1;
6419                         counter = 0;
6420                         gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff);
6421                         if (i < 8 && j < 2)
6422                                 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(
6423                                         adev, disable_masks[i * 2 + j]);
6424                         bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev);
6425
6426                         /**
6427                          * GFX11 could support more than 4 SEs, while the bitmap
6428                          * in cu_info struct is 4x4 and ioctl interface struct
6429                          * drm_amdgpu_info_device should keep stable.
6430                          * So we use last two columns of bitmap to store cu mask for
6431                          * SEs 4 to 7, the layout of the bitmap is as below:
6432                          *    SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]}
6433                          *    SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]}
6434                          *    SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]}
6435                          *    SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]}
6436                          *    SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]}
6437                          *    SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]}
6438                          *    SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]}
6439                          *    SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]}
6440                          */
6441                         cu_info->bitmap[i % 4][j + (i / 4) * 2] = bitmap;
6442
6443                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
6444                                 if (bitmap & mask)
6445                                         counter++;
6446
6447                                 mask <<= 1;
6448                         }
6449                         active_cu_number += counter;
6450                 }
6451         }
6452         gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
6453         mutex_unlock(&adev->grbm_idx_mutex);
6454
6455         cu_info->number = active_cu_number;
6456         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
6457
6458         return 0;
6459 }
6460
6461 const struct amdgpu_ip_block_version gfx_v11_0_ip_block =
6462 {
6463         .type = AMD_IP_BLOCK_TYPE_GFX,
6464         .major = 11,
6465         .minor = 0,
6466         .rev = 0,
6467         .funcs = &gfx_v11_0_ip_funcs,
6468 };