drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <[email protected]>
  25  *    Keith Packard <[email protected]>
  26  *
  27  */
  28
  29 #include <linux/sched/mm.h>
  30 #include <linux/sort.h>
  31
  32 #include <drm/drm_debugfs.h>
  33
  34 #include "gem/i915_gem_context.h"
  35 #include "gt/intel_gt_buffer_pool.h"
  36 #include "gt/intel_gt_clock_utils.h"
  37 #include "gt/intel_gt.h"
  38 #include "gt/intel_gt_pm.h"
  39 #include "gt/intel_gt_requests.h"
  40 #include "gt/intel_reset.h"
  41 #include "gt/intel_rc6.h"
  42 #include "gt/intel_rps.h"
  43 #include "gt/intel_sseu_debugfs.h"
  44
  45 #include "i915_debugfs.h"
  46 #include "i915_debugfs_params.h"
  47 #include "i915_irq.h"
  48 #include "i915_scheduler.h"
  49 #include "i915_trace.h"
  50 #include "intel_pm.h"
  51 #include "intel_sideband.h"
  52
  53 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  54 {
  55         return to_i915(node->minor->dev);
  56 }
  57
  58 static int i915_capabilities(struct seq_file *m, void *data)
  59 {
  60         struct drm_i915_private *i915 = node_to_i915(m->private);
  61         struct drm_printer p = drm_seq_file_printer(m);
  62
  63         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
  64
  65         intel_device_info_print_static(INTEL_INFO(i915), &p);
  66         intel_device_info_print_runtime(RUNTIME_INFO(i915), &p);
  67         intel_gt_info_print(&i915->gt.info, &p);
  68         intel_driver_caps_print(&i915->caps, &p);
  69
  70         kernel_param_lock(THIS_MODULE);
  71         i915_params_dump(&i915->params, &p);
  72         kernel_param_unlock(THIS_MODULE);
  73
  74         return 0;
  75 }
  76
  77 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  78 {
  79         switch (i915_gem_object_get_tiling(obj)) {
  80         default:
  81         case I915_TILING_NONE: return ' ';
  82         case I915_TILING_X: return 'X';
  83         case I915_TILING_Y: return 'Y';
  84         }
  85 }
  86
  87 static char get_global_flag(struct drm_i915_gem_object *obj)
  88 {
  89         return READ_ONCE(obj->userfault_count) ? 'g' : ' ';
  90 }
  91
  92 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
  93 {
  94         return obj->mm.mapping ? 'M' : ' ';
  95 }
  96
  97 static const char *
  98 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
  99 {
 100         size_t x = 0;
 101
 102         switch (page_sizes) {
 103         case 0:
 104                 return "";
 105         case I915_GTT_PAGE_SIZE_4K:
 106                 return "4K";
 107         case I915_GTT_PAGE_SIZE_64K:
 108                 return "64K";
 109         case I915_GTT_PAGE_SIZE_2M:
 110                 return "2M";
 111         default:
 112                 if (!buf)
 113                         return "M";
 114
 115                 if (page_sizes & I915_GTT_PAGE_SIZE_2M)
 116                         x += snprintf(buf + x, len - x, "2M, ");
 117                 if (page_sizes & I915_GTT_PAGE_SIZE_64K)
 118                         x += snprintf(buf + x, len - x, "64K, ");
 119                 if (page_sizes & I915_GTT_PAGE_SIZE_4K)
 120                         x += snprintf(buf + x, len - x, "4K, ");
 121                 buf[x-2] = '\0';
 122
 123                 return buf;
 124         }
 125 }
 126
 127 void
 128 i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 129 {
 130         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 131         struct intel_engine_cs *engine;
 132         struct i915_vma *vma;
 133         int pin_count = 0;
 134
 135         seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s",
 136                    &obj->base,
 137                    get_tiling_flag(obj),
 138                    get_global_flag(obj),
 139                    get_pin_mapped_flag(obj),
 140                    obj->base.size / 1024,
 141                    obj->read_domains,
 142                    obj->write_domain,
 143                    i915_cache_level_str(dev_priv, obj->cache_level),
 144                    obj->mm.dirty ? " dirty" : "",
 145                    obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
 146         if (obj->base.name)
 147                 seq_printf(m, " (name: %d)", obj->base.name);
 148
 149         spin_lock(&obj->vma.lock);
 150         list_for_each_entry(vma, &obj->vma.list, obj_link) {
 151                 if (!drm_mm_node_allocated(&vma->node))
 152                         continue;
 153
 154                 spin_unlock(&obj->vma.lock);
 155
 156                 if (i915_vma_is_pinned(vma))
 157                         pin_count++;
 158
 159                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
 160                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 161                            vma->node.start, vma->node.size,
 162                            stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
 163                 if (i915_vma_is_ggtt(vma)) {
 164                         switch (vma->ggtt_view.type) {
 165                         case I915_GGTT_VIEW_NORMAL:
 166                                 seq_puts(m, ", normal");
 167                                 break;
 168
 169                         case I915_GGTT_VIEW_PARTIAL:
 170                                 seq_printf(m, ", partial [%08llx+%x]",
 171                                            vma->ggtt_view.partial.offset << PAGE_SHIFT,
 172                                            vma->ggtt_view.partial.size << PAGE_SHIFT);
 173                                 break;
 174
 175                         case I915_GGTT_VIEW_ROTATED:
 176                                 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
 177                                            vma->ggtt_view.rotated.plane[0].width,
 178                                            vma->ggtt_view.rotated.plane[0].height,
 179                                            vma->ggtt_view.rotated.plane[0].stride,
 180                                            vma->ggtt_view.rotated.plane[0].offset,
 181                                            vma->ggtt_view.rotated.plane[1].width,
 182                                            vma->ggtt_view.rotated.plane[1].height,
 183                                            vma->ggtt_view.rotated.plane[1].stride,
 184                                            vma->ggtt_view.rotated.plane[1].offset);
 185                                 break;
 186
 187                         case I915_GGTT_VIEW_REMAPPED:
 188                                 seq_printf(m, ", remapped [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
 189                                            vma->ggtt_view.remapped.plane[0].width,
 190                                            vma->ggtt_view.remapped.plane[0].height,
 191                                            vma->ggtt_view.remapped.plane[0].stride,
 192                                            vma->ggtt_view.remapped.plane[0].offset,
 193                                            vma->ggtt_view.remapped.plane[1].width,
 194                                            vma->ggtt_view.remapped.plane[1].height,
 195                                            vma->ggtt_view.remapped.plane[1].stride,
 196                                            vma->ggtt_view.remapped.plane[1].offset);
 197                                 break;
 198
 199                         default:
 200                                 MISSING_CASE(vma->ggtt_view.type);
 201                                 break;
 202                         }
 203                 }
 204                 if (vma->fence)
 205                         seq_printf(m, " , fence: %d", vma->fence->id);
 206                 seq_puts(m, ")");
 207
 208                 spin_lock(&obj->vma.lock);
 209         }
 210         spin_unlock(&obj->vma.lock);
 211
 212         seq_printf(m, " (pinned x %d)", pin_count);
 213         if (obj->stolen)
 214                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 215         if (i915_gem_object_is_framebuffer(obj))
 216                 seq_printf(m, " (fb)");
 217
 218         engine = i915_gem_object_last_write_engine(obj);
 219         if (engine)
 220                 seq_printf(m, " (%s)", engine->name);
 221 }
 222
 223 struct file_stats {
 224         struct i915_address_space *vm;
 225         unsigned long count;
 226         u64 total;
 227         u64 active, inactive;
 228         u64 closed;
 229 };
 230
 231 static int per_file_stats(int id, void *ptr, void *data)
 232 {
 233         struct drm_i915_gem_object *obj = ptr;
 234         struct file_stats *stats = data;
 235         struct i915_vma *vma;
 236
 237         if (IS_ERR_OR_NULL(obj) || !kref_get_unless_zero(&obj->base.refcount))
 238                 return 0;
 239
 240         stats->count++;
 241         stats->total += obj->base.size;
 242
 243         spin_lock(&obj->vma.lock);
 244         if (!stats->vm) {
 245                 for_each_ggtt_vma(vma, obj) {
 246                         if (!drm_mm_node_allocated(&vma->node))
 247                                 continue;
 248
 249                         if (i915_vma_is_active(vma))
 250                                 stats->active += vma->node.size;
 251                         else
 252                                 stats->inactive += vma->node.size;
 253
 254                         if (i915_vma_is_closed(vma))
 255                                 stats->closed += vma->node.size;
 256                 }
 257         } else {
 258                 struct rb_node *p = obj->vma.tree.rb_node;
 259
 260                 while (p) {
 261                         long cmp;
 262
 263                         vma = rb_entry(p, typeof(*vma), obj_node);
 264                         cmp = i915_vma_compare(vma, stats->vm, NULL);
 265                         if (cmp == 0) {
 266                                 if (drm_mm_node_allocated(&vma->node)) {
 267                                         if (i915_vma_is_active(vma))
 268                                                 stats->active += vma->node.size;
 269                                         else
 270                                                 stats->inactive += vma->node.size;
 271
 272                                         if (i915_vma_is_closed(vma))
 273                                                 stats->closed += vma->node.size;
 274                                 }
 275                                 break;
 276                         }
 277                         if (cmp < 0)
 278                                 p = p->rb_right;
 279                         else
 280                                 p = p->rb_left;
 281                 }
 282         }
 283         spin_unlock(&obj->vma.lock);
 284
 285         i915_gem_object_put(obj);
 286         return 0;
 287 }
 288
 289 #define print_file_stats(m, name, stats) do { \
 290         if (stats.count) \
 291                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu closed)\n", \
 292                            name, \
 293                            stats.count, \
 294                            stats.total, \
 295                            stats.active, \
 296                            stats.inactive, \
 297                            stats.closed); \
 298 } while (0)
 299
 300 static void print_context_stats(struct seq_file *m,
 301                                 struct drm_i915_private *i915)
 302 {
 303         struct file_stats kstats = {};
 304         struct i915_gem_context *ctx, *cn;
 305
 306         spin_lock(&i915->gem.contexts.lock);
 307         list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
 308                 struct i915_gem_engines_iter it;
 309                 struct intel_context *ce;
 310
 311                 if (!kref_get_unless_zero(&ctx->ref))
 312                         continue;
 313
 314                 spin_unlock(&i915->gem.contexts.lock);
 315
 316                 for_each_gem_engine(ce,
 317                                     i915_gem_context_lock_engines(ctx), it) {
 318                         if (intel_context_pin_if_active(ce)) {
 319                                 rcu_read_lock();
 320                                 if (ce->state)
 321                                         per_file_stats(0,
 322                                                        ce->state->obj, &kstats);
 323                                 per_file_stats(0, ce->ring->vma->obj, &kstats);
 324                                 rcu_read_unlock();
 325                                 intel_context_unpin(ce);
 326                         }
 327                 }
 328                 i915_gem_context_unlock_engines(ctx);
 329
 330                 mutex_lock(&ctx->mutex);
 331                 if (!IS_ERR_OR_NULL(ctx->file_priv)) {
 332                         struct file_stats stats = {
 333                                 .vm = rcu_access_pointer(ctx->vm),
 334                         };
 335                         struct drm_file *file = ctx->file_priv->file;
 336                         struct task_struct *task;
 337                         char name[80];
 338
 339                         rcu_read_lock();
 340                         idr_for_each(&file->object_idr, per_file_stats, &stats);
 341                         rcu_read_unlock();
 342
 343                         rcu_read_lock();
 344                         task = pid_task(ctx->pid ?: file->pid, PIDTYPE_PID);
 345                         snprintf(name, sizeof(name), "%s",
 346                                  task ? task->comm : "<unknown>");
 347                         rcu_read_unlock();
 348
 349                         print_file_stats(m, name, stats);
 350                 }
 351                 mutex_unlock(&ctx->mutex);
 352
 353                 spin_lock(&i915->gem.contexts.lock);
 354                 list_safe_reset_next(ctx, cn, link);
 355                 i915_gem_context_put(ctx);
 356         }
 357         spin_unlock(&i915->gem.contexts.lock);
 358
 359         print_file_stats(m, "[k]contexts", kstats);
 360 }
 361
 362 static int i915_gem_object_info(struct seq_file *m, void *data)
 363 {
 364         struct drm_i915_private *i915 = node_to_i915(m->private);
 365         struct intel_memory_region *mr;
 366         enum intel_region_id id;
 367
 368         seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n",
 369                    i915->mm.shrink_count,
 370                    atomic_read(&i915->mm.free_count),
 371                    i915->mm.shrink_memory);
 372         for_each_memory_region(mr, i915, id)
 373                 seq_printf(m, "%s: total:%pa, available:%pa bytes\n",
 374                            mr->name, &mr->total, &mr->avail);
 375         seq_putc(m, '\n');
 376
 377         print_context_stats(m, i915);
 378
 379         return 0;
 380 }
 381
 382 static void gen8_display_interrupt_info(struct seq_file *m)
 383 {
 384         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 385         enum pipe pipe;
 386
 387         for_each_pipe(dev_priv, pipe) {
 388                 enum intel_display_power_domain power_domain;
 389                 intel_wakeref_t wakeref;
 390
 391                 power_domain = POWER_DOMAIN_PIPE(pipe);
 392                 wakeref = intel_display_power_get_if_enabled(dev_priv,
 393                                                              power_domain);
 394                 if (!wakeref) {
 395                         seq_printf(m, "Pipe %c power disabled\n",
 396                                    pipe_name(pipe));
 397                         continue;
 398                 }
 399                 seq_printf(m, "Pipe %c IMR:\t%08x\n",
 400                            pipe_name(pipe),
 401                            I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 402                 seq_printf(m, "Pipe %c IIR:\t%08x\n",
 403                            pipe_name(pipe),
 404                            I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 405                 seq_printf(m, "Pipe %c IER:\t%08x\n",
 406                            pipe_name(pipe),
 407                            I915_READ(GEN8_DE_PIPE_IER(pipe)));
 408
 409                 intel_display_power_put(dev_priv, power_domain, wakeref);
 410         }
 411
 412         seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 413                    I915_READ(GEN8_DE_PORT_IMR));
 414         seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 415                    I915_READ(GEN8_DE_PORT_IIR));
 416         seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 417                    I915_READ(GEN8_DE_PORT_IER));
 418
 419         seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 420                    I915_READ(GEN8_DE_MISC_IMR));
 421         seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 422                    I915_READ(GEN8_DE_MISC_IIR));
 423         seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 424                    I915_READ(GEN8_DE_MISC_IER));
 425
 426         seq_printf(m, "PCU interrupt mask:\t%08x\n",
 427                    I915_READ(GEN8_PCU_IMR));
 428         seq_printf(m, "PCU interrupt identity:\t%08x\n",
 429                    I915_READ(GEN8_PCU_IIR));
 430         seq_printf(m, "PCU interrupt enable:\t%08x\n",
 431                    I915_READ(GEN8_PCU_IER));
 432 }
 433
 434 static int i915_interrupt_info(struct seq_file *m, void *data)
 435 {
 436         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 437         struct intel_engine_cs *engine;
 438         intel_wakeref_t wakeref;
 439         int i, pipe;
 440
 441         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 442
 443         if (IS_CHERRYVIEW(dev_priv)) {
 444                 intel_wakeref_t pref;
 445
 446                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 447                            I915_READ(GEN8_MASTER_IRQ));
 448
 449                 seq_printf(m, "Display IER:\t%08x\n",
 450                            I915_READ(VLV_IER));
 451                 seq_printf(m, "Display IIR:\t%08x\n",
 452                            I915_READ(VLV_IIR));
 453                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 454                            I915_READ(VLV_IIR_RW));
 455                 seq_printf(m, "Display IMR:\t%08x\n",
 456                            I915_READ(VLV_IMR));
 457                 for_each_pipe(dev_priv, pipe) {
 458                         enum intel_display_power_domain power_domain;
 459
 460                         power_domain = POWER_DOMAIN_PIPE(pipe);
 461                         pref = intel_display_power_get_if_enabled(dev_priv,
 462                                                                   power_domain);
 463                         if (!pref) {
 464                                 seq_printf(m, "Pipe %c power disabled\n",
 465                                            pipe_name(pipe));
 466                                 continue;
 467                         }
 468
 469                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 470                                    pipe_name(pipe),
 471                                    I915_READ(PIPESTAT(pipe)));
 472
 473                         intel_display_power_put(dev_priv, power_domain, pref);
 474                 }
 475
 476                 pref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 477                 seq_printf(m, "Port hotplug:\t%08x\n",
 478                            I915_READ(PORT_HOTPLUG_EN));
 479                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 480                            I915_READ(VLV_DPFLIPSTAT));
 481                 seq_printf(m, "DPINVGTT:\t%08x\n",
 482                            I915_READ(DPINVGTT));
 483                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, pref);
 484
 485                 for (i = 0; i < 4; i++) {
 486                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 487                                    i, I915_READ(GEN8_GT_IMR(i)));
 488                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 489                                    i, I915_READ(GEN8_GT_IIR(i)));
 490                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 491                                    i, I915_READ(GEN8_GT_IER(i)));
 492                 }
 493
 494                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 495                            I915_READ(GEN8_PCU_IMR));
 496                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 497                            I915_READ(GEN8_PCU_IIR));
 498                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 499                            I915_READ(GEN8_PCU_IER));
 500         } else if (INTEL_GEN(dev_priv) >= 11) {
 501                 if (HAS_MASTER_UNIT_IRQ(dev_priv))
 502                         seq_printf(m, "Master Unit Interrupt Control:  %08x\n",
 503                                    I915_READ(DG1_MSTR_UNIT_INTR));
 504
 505                 seq_printf(m, "Master Interrupt Control:  %08x\n",
 506                            I915_READ(GEN11_GFX_MSTR_IRQ));
 507
 508                 seq_printf(m, "Render/Copy Intr Enable:   %08x\n",
 509                            I915_READ(GEN11_RENDER_COPY_INTR_ENABLE));
 510                 seq_printf(m, "VCS/VECS Intr Enable:      %08x\n",
 511                            I915_READ(GEN11_VCS_VECS_INTR_ENABLE));
 512                 seq_printf(m, "GUC/SG Intr Enable:\t   %08x\n",
 513                            I915_READ(GEN11_GUC_SG_INTR_ENABLE));
 514                 seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
 515                            I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE));
 516                 seq_printf(m, "Crypto Intr Enable:\t   %08x\n",
 517                            I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE));
 518                 seq_printf(m, "GUnit/CSME Intr Enable:\t   %08x\n",
 519                            I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE));
 520
 521                 seq_printf(m, "Display Interrupt Control:\t%08x\n",
 522                            I915_READ(GEN11_DISPLAY_INT_CTL));
 523
 524                 gen8_display_interrupt_info(m);
 525         } else if (INTEL_GEN(dev_priv) >= 8) {
 526                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 527                            I915_READ(GEN8_MASTER_IRQ));
 528
 529                 for (i = 0; i < 4; i++) {
 530                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 531                                    i, I915_READ(GEN8_GT_IMR(i)));
 532                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 533                                    i, I915_READ(GEN8_GT_IIR(i)));
 534                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 535                                    i, I915_READ(GEN8_GT_IER(i)));
 536                 }
 537
 538                 gen8_display_interrupt_info(m);
 539         } else if (IS_VALLEYVIEW(dev_priv)) {
 540                 intel_wakeref_t pref;
 541
 542                 seq_printf(m, "Display IER:\t%08x\n",
 543                            I915_READ(VLV_IER));
 544                 seq_printf(m, "Display IIR:\t%08x\n",
 545                            I915_READ(VLV_IIR));
 546                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 547                            I915_READ(VLV_IIR_RW));
 548                 seq_printf(m, "Display IMR:\t%08x\n",
 549                            I915_READ(VLV_IMR));
 550                 for_each_pipe(dev_priv, pipe) {
 551                         enum intel_display_power_domain power_domain;
 552
 553                         power_domain = POWER_DOMAIN_PIPE(pipe);
 554                         pref = intel_display_power_get_if_enabled(dev_priv,
 555                                                                   power_domain);
 556                         if (!pref) {
 557                                 seq_printf(m, "Pipe %c power disabled\n",
 558                                            pipe_name(pipe));
 559                                 continue;
 560                         }
 561
 562                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 563                                    pipe_name(pipe),
 564                                    I915_READ(PIPESTAT(pipe)));
 565                         intel_display_power_put(dev_priv, power_domain, pref);
 566                 }
 567
 568                 seq_printf(m, "Master IER:\t%08x\n",
 569                            I915_READ(VLV_MASTER_IER));
 570
 571                 seq_printf(m, "Render IER:\t%08x\n",
 572                            I915_READ(GTIER));
 573                 seq_printf(m, "Render IIR:\t%08x\n",
 574                            I915_READ(GTIIR));
 575                 seq_printf(m, "Render IMR:\t%08x\n",
 576                            I915_READ(GTIMR));
 577
 578                 seq_printf(m, "PM IER:\t\t%08x\n",
 579                            I915_READ(GEN6_PMIER));
 580                 seq_printf(m, "PM IIR:\t\t%08x\n",
 581                            I915_READ(GEN6_PMIIR));
 582                 seq_printf(m, "PM IMR:\t\t%08x\n",
 583                            I915_READ(GEN6_PMIMR));
 584
 585                 pref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 586                 seq_printf(m, "Port hotplug:\t%08x\n",
 587                            I915_READ(PORT_HOTPLUG_EN));
 588                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 589                            I915_READ(VLV_DPFLIPSTAT));
 590                 seq_printf(m, "DPINVGTT:\t%08x\n",
 591                            I915_READ(DPINVGTT));
 592                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, pref);
 593
 594         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 595                 seq_printf(m, "Interrupt enable:    %08x\n",
 596                            I915_READ(GEN2_IER));
 597                 seq_printf(m, "Interrupt identity:  %08x\n",
 598                            I915_READ(GEN2_IIR));
 599                 seq_printf(m, "Interrupt mask:      %08x\n",
 600                            I915_READ(GEN2_IMR));
 601                 for_each_pipe(dev_priv, pipe)
 602                         seq_printf(m, "Pipe %c stat:         %08x\n",
 603                                    pipe_name(pipe),
 604                                    I915_READ(PIPESTAT(pipe)));
 605         } else {
 606                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 607                            I915_READ(DEIER));
 608                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 609                            I915_READ(DEIIR));
 610                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 611                            I915_READ(DEIMR));
 612                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 613                            I915_READ(SDEIER));
 614                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 615                            I915_READ(SDEIIR));
 616                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 617                            I915_READ(SDEIMR));
 618                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 619                            I915_READ(GTIER));
 620                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 621                            I915_READ(GTIIR));
 622                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 623                            I915_READ(GTIMR));
 624         }
 625
 626         if (INTEL_GEN(dev_priv) >= 11) {
 627                 seq_printf(m, "RCS Intr Mask:\t %08x\n",
 628                            I915_READ(GEN11_RCS0_RSVD_INTR_MASK));
 629                 seq_printf(m, "BCS Intr Mask:\t %08x\n",
 630                            I915_READ(GEN11_BCS_RSVD_INTR_MASK));
 631                 seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
 632                            I915_READ(GEN11_VCS0_VCS1_INTR_MASK));
 633                 seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
 634                            I915_READ(GEN11_VCS2_VCS3_INTR_MASK));
 635                 seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
 636                            I915_READ(GEN11_VECS0_VECS1_INTR_MASK));
 637                 seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
 638                            I915_READ(GEN11_GUC_SG_INTR_MASK));
 639                 seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
 640                            I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK));
 641                 seq_printf(m, "Crypto Intr Mask:\t %08x\n",
 642                            I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK));
 643                 seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
 644                            I915_READ(GEN11_GUNIT_CSME_INTR_MASK));
 645
 646         } else if (INTEL_GEN(dev_priv) >= 6) {
 647                 for_each_uabi_engine(engine, dev_priv) {
 648                         seq_printf(m,
 649                                    "Graphics Interrupt mask (%s):       %08x\n",
 650                                    engine->name, ENGINE_READ(engine, RING_IMR));
 651                 }
 652         }
 653
 654         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
 655
 656         return 0;
 657 }
 658
 659 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 660 {
 661         struct drm_i915_private *i915 = node_to_i915(m->private);
 662         unsigned int i;
 663
 664         seq_printf(m, "Total fences = %d\n", i915->ggtt.num_fences);
 665
 666         rcu_read_lock();
 667         for (i = 0; i < i915->ggtt.num_fences; i++) {
 668                 struct i915_fence_reg *reg = &i915->ggtt.fence_regs[i];
 669                 struct i915_vma *vma = reg->vma;
 670
 671                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 672                            i, atomic_read(&reg->pin_count));
 673                 if (!vma)
 674                         seq_puts(m, "unused");
 675                 else
 676                         i915_debugfs_describe_obj(m, vma->obj);
 677                 seq_putc(m, '\n');
 678         }
 679         rcu_read_unlock();
 680
 681         return 0;
 682 }
 683
 684 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 685 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
 686                               size_t count, loff_t *pos)
 687 {
 688         struct i915_gpu_coredump *error;
 689         ssize_t ret;
 690         void *buf;
 691
 692         error = file->private_data;
 693         if (!error)
 694                 return 0;
 695
 696         /* Bounce buffer required because of kernfs __user API convenience. */
 697         buf = kmalloc(count, GFP_KERNEL);
 698         if (!buf)
 699                 return -ENOMEM;
 700
 701         ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count);
 702         if (ret <= 0)
 703                 goto out;
 704
 705         if (!copy_to_user(ubuf, buf, ret))
 706                 *pos += ret;
 707         else
 708                 ret = -EFAULT;
 709
 710 out:
 711         kfree(buf);
 712         return ret;
 713 }
 714
 715 static int gpu_state_release(struct inode *inode, struct file *file)
 716 {
 717         i915_gpu_coredump_put(file->private_data);
 718         return 0;
 719 }
 720
 721 static int i915_gpu_info_open(struct inode *inode, struct file *file)
 722 {
 723         struct drm_i915_private *i915 = inode->i_private;
 724         struct i915_gpu_coredump *gpu;
 725         intel_wakeref_t wakeref;
 726
 727         gpu = NULL;
 728         with_intel_runtime_pm(&i915->runtime_pm, wakeref)
 729                 gpu = i915_gpu_coredump(&i915->gt, ALL_ENGINES);
 730         if (IS_ERR(gpu))
 731                 return PTR_ERR(gpu);
 732
 733         file->private_data = gpu;
 734         return 0;
 735 }
 736
 737 static const struct file_operations i915_gpu_info_fops = {
 738         .owner = THIS_MODULE,
 739         .open = i915_gpu_info_open,
 740         .read = gpu_state_read,
 741         .llseek = default_llseek,
 742         .release = gpu_state_release,
 743 };
 744
 745 static ssize_t
 746 i915_error_state_write(struct file *filp,
 747                        const char __user *ubuf,
 748                        size_t cnt,
 749                        loff_t *ppos)
 750 {
 751         struct i915_gpu_coredump *error = filp->private_data;
 752
 753         if (!error)
 754                 return 0;
 755
 756         drm_dbg(&error->i915->drm, "Resetting error state\n");
 757         i915_reset_error_state(error->i915);
 758
 759         return cnt;
 760 }
 761
 762 static int i915_error_state_open(struct inode *inode, struct file *file)
 763 {
 764         struct i915_gpu_coredump *error;
 765
 766         error = i915_first_error_state(inode->i_private);
 767         if (IS_ERR(error))
 768                 return PTR_ERR(error);
 769
 770         file->private_data  = error;
 771         return 0;
 772 }
 773
 774 static const struct file_operations i915_error_state_fops = {
 775         .owner = THIS_MODULE,
 776         .open = i915_error_state_open,
 777         .read = gpu_state_read,
 778         .write = i915_error_state_write,
 779         .llseek = default_llseek,
 780         .release = gpu_state_release,
 781 };
 782 #endif
 783
 784 static int i915_frequency_info(struct seq_file *m, void *unused)
 785 {
 786         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 787         struct intel_uncore *uncore = &dev_priv->uncore;
 788         struct intel_rps *rps = &dev_priv->gt.rps;
 789         intel_wakeref_t wakeref;
 790
 791         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 792
 793         if (IS_GEN(dev_priv, 5)) {
 794                 u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
 795                 u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
 796
 797                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
 798                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
 799                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
 800                            MEMSTAT_VID_SHIFT);
 801                 seq_printf(m, "Current P-state: %d\n",
 802                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
 803         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 804                 u32 rpmodectl, freq_sts;
 805
 806                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
 807                 seq_printf(m, "Video Turbo Mode: %s\n",
 808                            yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
 809                 seq_printf(m, "HW control enabled: %s\n",
 810                            yesno(rpmodectl & GEN6_RP_ENABLE));
 811                 seq_printf(m, "SW control enabled: %s\n",
 812                            yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
 813                                   GEN6_RP_MEDIA_SW_MODE));
 814
 815                 vlv_punit_get(dev_priv);
 816                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
 817                 vlv_punit_put(dev_priv);
 818
 819                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
 820                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
 821
 822                 seq_printf(m, "actual GPU freq: %d MHz\n",
 823                            intel_gpu_freq(rps, (freq_sts >> 8) & 0xff));
 824
 825                 seq_printf(m, "current GPU freq: %d MHz\n",
 826                            intel_gpu_freq(rps, rps->cur_freq));
 827
 828                 seq_printf(m, "max GPU freq: %d MHz\n",
 829                            intel_gpu_freq(rps, rps->max_freq));
 830
 831                 seq_printf(m, "min GPU freq: %d MHz\n",
 832                            intel_gpu_freq(rps, rps->min_freq));
 833
 834                 seq_printf(m, "idle GPU freq: %d MHz\n",
 835                            intel_gpu_freq(rps, rps->idle_freq));
 836
 837                 seq_printf(m,
 838                            "efficient (RPe) frequency: %d MHz\n",
 839                            intel_gpu_freq(rps, rps->efficient_freq));
 840         } else if (INTEL_GEN(dev_priv) >= 6) {
 841                 u32 rp_state_limits;
 842                 u32 gt_perf_status;
 843                 u32 rp_state_cap;
 844                 u32 rpmodectl, rpinclimit, rpdeclimit;
 845                 u32 rpstat, cagf, reqf;
 846                 u32 rpupei, rpcurup, rpprevup;
 847                 u32 rpdownei, rpcurdown, rpprevdown;
 848                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
 849                 int max_freq;
 850
 851                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
 852                 if (IS_GEN9_LP(dev_priv)) {
 853                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
 854                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
 855                 } else {
 856                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 857                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
 858                 }
 859
 860                 /* RPSTAT1 is in the GT power well */
 861                 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
 862
 863                 reqf = I915_READ(GEN6_RPNSWREQ);
 864                 if (INTEL_GEN(dev_priv) >= 9)
 865                         reqf >>= 23;
 866                 else {
 867                         reqf &= ~GEN6_TURBO_DISABLE;
 868                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 869                                 reqf >>= 24;
 870                         else
 871                                 reqf >>= 25;
 872                 }
 873                 reqf = intel_gpu_freq(rps, reqf);
 874
 875                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
 876                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
 877                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
 878
 879                 rpstat = I915_READ(GEN6_RPSTAT1);
 880                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
 881                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
 882                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
 883                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
 884                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
 885                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
 886                 cagf = intel_rps_read_actual_frequency(rps);
 887
 888                 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
 889
 890                 if (INTEL_GEN(dev_priv) >= 11) {
 891                         pm_ier = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
 892                         pm_imr = I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK);
 893                         /*
 894                          * The equivalent to the PM ISR & IIR cannot be read
 895                          * without affecting the current state of the system
 896                          */
 897                         pm_isr = 0;
 898                         pm_iir = 0;
 899                 } else if (INTEL_GEN(dev_priv) >= 8) {
 900                         pm_ier = I915_READ(GEN8_GT_IER(2));
 901                         pm_imr = I915_READ(GEN8_GT_IMR(2));
 902                         pm_isr = I915_READ(GEN8_GT_ISR(2));
 903                         pm_iir = I915_READ(GEN8_GT_IIR(2));
 904                 } else {
 905                         pm_ier = I915_READ(GEN6_PMIER);
 906                         pm_imr = I915_READ(GEN6_PMIMR);
 907                         pm_isr = I915_READ(GEN6_PMISR);
 908                         pm_iir = I915_READ(GEN6_PMIIR);
 909                 }
 910                 pm_mask = I915_READ(GEN6_PMINTRMSK);
 911
 912                 seq_printf(m, "Video Turbo Mode: %s\n",
 913                            yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
 914                 seq_printf(m, "HW control enabled: %s\n",
 915                            yesno(rpmodectl & GEN6_RP_ENABLE));
 916                 seq_printf(m, "SW control enabled: %s\n",
 917                            yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
 918                                   GEN6_RP_MEDIA_SW_MODE));
 919
 920                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
 921                            pm_ier, pm_imr, pm_mask);
 922                 if (INTEL_GEN(dev_priv) <= 10)
 923                         seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
 924                                    pm_isr, pm_iir);
 925                 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
 926                            rps->pm_intrmsk_mbz);
 927                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 928                 seq_printf(m, "Render p-state ratio: %d\n",
 929                            (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
 930                 seq_printf(m, "Render p-state VID: %d\n",
 931                            gt_perf_status & 0xff);
 932                 seq_printf(m, "Render p-state limit: %d\n",
 933                            rp_state_limits & 0xff);
 934                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
 935                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
 936                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
 937                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
 938                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
 939                 seq_printf(m, "CAGF: %dMHz\n", cagf);
 940                 seq_printf(m, "RP CUR UP EI: %d (%lldns)\n",
 941                            rpupei,
 942                            intel_gt_pm_interval_to_ns(&dev_priv->gt, rpupei));
 943                 seq_printf(m, "RP CUR UP: %d (%lldun)\n",
 944                            rpcurup,
 945                            intel_gt_pm_interval_to_ns(&dev_priv->gt, rpcurup));
 946                 seq_printf(m, "RP PREV UP: %d (%lldns)\n",
 947                            rpprevup,
 948                            intel_gt_pm_interval_to_ns(&dev_priv->gt, rpprevup));
 949                 seq_printf(m, "Up threshold: %d%%\n",
 950                            rps->power.up_threshold);
 951
 952                 seq_printf(m, "RP CUR DOWN EI: %d (%lldns)\n",
 953                            rpdownei,
 954                            intel_gt_pm_interval_to_ns(&dev_priv->gt,
 955                                                       rpdownei));
 956                 seq_printf(m, "RP CUR DOWN: %d (%lldns)\n",
 957                            rpcurdown,
 958                            intel_gt_pm_interval_to_ns(&dev_priv->gt,
 959                                                       rpcurdown));
 960                 seq_printf(m, "RP PREV DOWN: %d (%lldns)\n",
 961                            rpprevdown,
 962                            intel_gt_pm_interval_to_ns(&dev_priv->gt,
 963                                                       rpprevdown));
 964                 seq_printf(m, "Down threshold: %d%%\n",
 965                            rps->power.down_threshold);
 966
 967                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
 968                             rp_state_cap >> 16) & 0xff;
 969                 max_freq *= (IS_GEN9_BC(dev_priv) ||
 970                              INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
 971                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
 972                            intel_gpu_freq(rps, max_freq));
 973
 974                 max_freq = (rp_state_cap & 0xff00) >> 8;
 975                 max_freq *= (IS_GEN9_BC(dev_priv) ||
 976                              INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
 977                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
 978                            intel_gpu_freq(rps, max_freq));
 979
 980                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
 981                             rp_state_cap >> 0) & 0xff;
 982                 max_freq *= (IS_GEN9_BC(dev_priv) ||
 983                              INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
 984                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
 985                            intel_gpu_freq(rps, max_freq));
 986                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
 987                            intel_gpu_freq(rps, rps->max_freq));
 988
 989                 seq_printf(m, "Current freq: %d MHz\n",
 990                            intel_gpu_freq(rps, rps->cur_freq));
 991                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
 992                 seq_printf(m, "Idle freq: %d MHz\n",
 993                            intel_gpu_freq(rps, rps->idle_freq));
 994                 seq_printf(m, "Min freq: %d MHz\n",
 995                            intel_gpu_freq(rps, rps->min_freq));
 996                 seq_printf(m, "Boost freq: %d MHz\n",
 997                            intel_gpu_freq(rps, rps->boost_freq));
 998                 seq_printf(m, "Max freq: %d MHz\n",
 999                            intel_gpu_freq(rps, rps->max_freq));
1000                 seq_printf(m,
1001                            "efficient (RPe) frequency: %d MHz\n",
1002                            intel_gpu_freq(rps, rps->efficient_freq));
1003         } else {
1004                 seq_puts(m, "no P-state info available\n");
1005         }
1006
1007         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
1008         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1009         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1010
1011         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
1012         return 0;
1013 }
1014
1015 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1016 {
1017         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1018         struct intel_rps *rps = &dev_priv->gt.rps;
1019         unsigned int max_gpu_freq, min_gpu_freq;
1020         intel_wakeref_t wakeref;
1021         int gpu_freq, ia_freq;
1022
1023         if (!HAS_LLC(dev_priv))
1024                 return -ENODEV;
1025
1026         min_gpu_freq = rps->min_freq;
1027         max_gpu_freq = rps->max_freq;
1028         if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
1029                 /* Convert GT frequency to 50 HZ units */
1030                 min_gpu_freq /= GEN9_FREQ_SCALER;
1031                 max_gpu_freq /= GEN9_FREQ_SCALER;
1032         }
1033
1034         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1035
1036         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
1037         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1038                 ia_freq = gpu_freq;
1039                 sandybridge_pcode_read(dev_priv,
1040                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1041                                        &ia_freq, NULL);
1042                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1043                            intel_gpu_freq(rps,
1044                                           (gpu_freq *
1045                                            (IS_GEN9_BC(dev_priv) ||
1046                                             INTEL_GEN(dev_priv) >= 10 ?
1047                                             GEN9_FREQ_SCALER : 1))),
1048                            ((ia_freq >> 0) & 0xff) * 100,
1049                            ((ia_freq >> 8) & 0xff) * 100);
1050         }
1051         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
1052
1053         return 0;
1054 }
1055
1056 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1057 {
1058         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, emit: %u)",
1059                    ring->space, ring->head, ring->tail, ring->emit);
1060 }
1061
1062 static int i915_context_status(struct seq_file *m, void *unused)
1063 {
1064         struct drm_i915_private *i915 = node_to_i915(m->private);
1065         struct i915_gem_context *ctx, *cn;
1066
1067         spin_lock(&i915->gem.contexts.lock);
1068         list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
1069                 struct i915_gem_engines_iter it;
1070                 struct intel_context *ce;
1071
1072                 if (!kref_get_unless_zero(&ctx->ref))
1073                         continue;
1074
1075                 spin_unlock(&i915->gem.contexts.lock);
1076
1077                 seq_puts(m, "HW context ");
1078                 if (ctx->pid) {
1079                         struct task_struct *task;
1080
1081                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1082                         if (task) {
1083                                 seq_printf(m, "(%s [%d]) ",
1084                                            task->comm, task->pid);
1085                                 put_task_struct(task);
1086                         }
1087                 } else if (IS_ERR(ctx->file_priv)) {
1088                         seq_puts(m, "(deleted) ");
1089                 } else {
1090                         seq_puts(m, "(kernel) ");
1091                 }
1092
1093                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1094                 seq_putc(m, '\n');
1095
1096                 for_each_gem_engine(ce,
1097                                     i915_gem_context_lock_engines(ctx), it) {
1098                         if (intel_context_pin_if_active(ce)) {
1099                                 seq_printf(m, "%s: ", ce->engine->name);
1100                                 if (ce->state)
1101                                         i915_debugfs_describe_obj(m, ce->state->obj);
1102                                 describe_ctx_ring(m, ce->ring);
1103                                 seq_putc(m, '\n');
1104                                 intel_context_unpin(ce);
1105                         }
1106                 }
1107                 i915_gem_context_unlock_engines(ctx);
1108
1109                 seq_putc(m, '\n');
1110
1111                 spin_lock(&i915->gem.contexts.lock);
1112                 list_safe_reset_next(ctx, cn, link);
1113                 i915_gem_context_put(ctx);
1114         }
1115         spin_unlock(&i915->gem.contexts.lock);
1116
1117         return 0;
1118 }
1119
1120 static const char *swizzle_string(unsigned swizzle)
1121 {
1122         switch (swizzle) {
1123         case I915_BIT_6_SWIZZLE_NONE:
1124                 return "none";
1125         case I915_BIT_6_SWIZZLE_9:
1126                 return "bit9";
1127         case I915_BIT_6_SWIZZLE_9_10:
1128                 return "bit9/bit10";
1129         case I915_BIT_6_SWIZZLE_9_11:
1130                 return "bit9/bit11";
1131         case I915_BIT_6_SWIZZLE_9_10_11:
1132                 return "bit9/bit10/bit11";
1133         case I915_BIT_6_SWIZZLE_9_17:
1134                 return "bit9/bit17";
1135         case I915_BIT_6_SWIZZLE_9_10_17:
1136                 return "bit9/bit10/bit17";
1137         case I915_BIT_6_SWIZZLE_UNKNOWN:
1138                 return "unknown";
1139         }
1140
1141         return "bug";
1142 }
1143
1144 static int i915_swizzle_info(struct seq_file *m, void *data)
1145 {
1146         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1147         struct intel_uncore *uncore = &dev_priv->uncore;
1148         intel_wakeref_t wakeref;
1149
1150         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1151                    swizzle_string(dev_priv->ggtt.bit_6_swizzle_x));
1152         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1153                    swizzle_string(dev_priv->ggtt.bit_6_swizzle_y));
1154
1155         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
1156                 seq_puts(m, "L-shaped memory detected\n");
1157
1158         /* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */
1159         if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv))
1160                 return 0;
1161
1162         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
1163
1164         if (IS_GEN_RANGE(dev_priv, 3, 4)) {
1165                 seq_printf(m, "DDC = 0x%08x\n",
1166                            intel_uncore_read(uncore, DCC));
1167                 seq_printf(m, "DDC2 = 0x%08x\n",
1168                            intel_uncore_read(uncore, DCC2));
1169                 seq_printf(m, "C0DRB3 = 0x%04x\n",
1170                            intel_uncore_read16(uncore, C0DRB3));
1171                 seq_printf(m, "C1DRB3 = 0x%04x\n",
1172                            intel_uncore_read16(uncore, C1DRB3));
1173         } else if (INTEL_GEN(dev_priv) >= 6) {
1174                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1175                            intel_uncore_read(uncore, MAD_DIMM_C0));
1176                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1177                            intel_uncore_read(uncore, MAD_DIMM_C1));
1178                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1179                            intel_uncore_read(uncore, MAD_DIMM_C2));
1180                 seq_printf(m, "TILECTL = 0x%08x\n",
1181                            intel_uncore_read(uncore, TILECTL));
1182                 if (INTEL_GEN(dev_priv) >= 8)
1183                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1184                                    intel_uncore_read(uncore, GAMTARBMODE));
1185                 else
1186                         seq_printf(m, "ARB_MODE = 0x%08x\n",
1187                                    intel_uncore_read(uncore, ARB_MODE));
1188                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1189                            intel_uncore_read(uncore, DISP_ARB_CTL));
1190         }
1191
1192         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
1193
1194         return 0;
1195 }
1196
1197 static const char *rps_power_to_str(unsigned int power)
1198 {
1199         static const char * const strings[] = {
1200                 [LOW_POWER] = "low power",
1201                 [BETWEEN] = "mixed",
1202                 [HIGH_POWER] = "high power",
1203         };
1204
1205         if (power >= ARRAY_SIZE(strings) || !strings[power])
1206                 return "unknown";
1207
1208         return strings[power];
1209 }
1210
1211 static int i915_rps_boost_info(struct seq_file *m, void *data)
1212 {
1213         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1214         struct intel_rps *rps = &dev_priv->gt.rps;
1215
1216         seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps)));
1217         seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps)));
1218         seq_printf(m, "GPU busy? %s\n", yesno(dev_priv->gt.awake));
1219         seq_printf(m, "Boosts outstanding? %d\n",
1220                    atomic_read(&rps->num_waiters));
1221         seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
1222         seq_printf(m, "Frequency requested %d, actual %d\n",
1223                    intel_gpu_freq(rps, rps->cur_freq),
1224                    intel_rps_read_actual_frequency(rps));
1225         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
1226                    intel_gpu_freq(rps, rps->min_freq),
1227                    intel_gpu_freq(rps, rps->min_freq_softlimit),
1228                    intel_gpu_freq(rps, rps->max_freq_softlimit),
1229                    intel_gpu_freq(rps, rps->max_freq));
1230         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
1231                    intel_gpu_freq(rps, rps->idle_freq),
1232                    intel_gpu_freq(rps, rps->efficient_freq),
1233                    intel_gpu_freq(rps, rps->boost_freq));
1234
1235         seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
1236
1237         if (INTEL_GEN(dev_priv) >= 6 && intel_rps_is_active(rps)) {
1238                 u32 rpup, rpupei;
1239                 u32 rpdown, rpdownei;
1240
1241                 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
1242                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
1243                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
1244                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
1245                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
1246                 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
1247
1248                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
1249                            rps_power_to_str(rps->power.mode));
1250                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
1251                            rpup && rpupei ? 100 * rpup / rpupei : 0,
1252                            rps->power.up_threshold);
1253                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
1254                            rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
1255                            rps->power.down_threshold);
1256         } else {
1257                 seq_puts(m, "\nRPS Autotuning inactive\n");
1258         }
1259
1260         return 0;
1261 }
1262
1263 static int i915_llc(struct seq_file *m, void *data)
1264 {
1265         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1266         const bool edram = INTEL_GEN(dev_priv) > 8;
1267
1268         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
1269         seq_printf(m, "%s: %uMB\n", edram ? "eDRAM" : "eLLC",
1270                    dev_priv->edram_size_mb);
1271
1272         return 0;
1273 }
1274
1275 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
1276 {
1277         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1278         struct pci_dev *pdev = dev_priv->drm.pdev;
1279
1280         if (!HAS_RUNTIME_PM(dev_priv))
1281                 seq_puts(m, "Runtime power management not supported\n");
1282
1283         seq_printf(m, "Runtime power status: %s\n",
1284                    enableddisabled(!dev_priv->power_domains.wakeref));
1285
1286         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
1287         seq_printf(m, "IRQs disabled: %s\n",
1288                    yesno(!intel_irqs_enabled(dev_priv)));
1289 #ifdef CONFIG_PM
1290         seq_printf(m, "Usage count: %d\n",
1291                    atomic_read(&dev_priv->drm.dev->power.usage_count));
1292 #else
1293         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
1294 #endif
1295         seq_printf(m, "PCI device power state: %s [%d]\n",
1296                    pci_power_name(pdev->current_state),
1297                    pdev->current_state);
1298
1299         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) {
1300                 struct drm_printer p = drm_seq_file_printer(m);
1301
1302                 print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p);
1303         }
1304
1305         return 0;
1306 }
1307
1308 static int i915_engine_info(struct seq_file *m, void *unused)
1309 {
1310         struct drm_i915_private *i915 = node_to_i915(m->private);
1311         struct intel_engine_cs *engine;
1312         intel_wakeref_t wakeref;
1313         struct drm_printer p;
1314
1315         wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1316
1317         seq_printf(m, "GT awake? %s [%d], %llums\n",
1318                    yesno(i915->gt.awake),
1319                    atomic_read(&i915->gt.wakeref.count),
1320                    ktime_to_ms(intel_gt_get_awake_time(&i915->gt)));
1321         seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n",
1322                    i915->gt.clock_frequency,
1323                    i915->gt.clock_period_ns);
1324
1325         p = drm_seq_file_printer(m);
1326         for_each_uabi_engine(engine, i915)
1327                 intel_engine_dump(engine, &p, "%s\n", engine->name);
1328
1329         intel_gt_show_timelines(&i915->gt, &p, i915_request_show_with_schedule);
1330
1331         intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1332
1333         return 0;
1334 }
1335
1336 static int i915_shrinker_info(struct seq_file *m, void *unused)
1337 {
1338         struct drm_i915_private *i915 = node_to_i915(m->private);
1339
1340         seq_printf(m, "seeks = %d\n", i915->mm.shrinker.seeks);
1341         seq_printf(m, "batch = %lu\n", i915->mm.shrinker.batch);
1342
1343         return 0;
1344 }
1345
1346 static int i915_wa_registers(struct seq_file *m, void *unused)
1347 {
1348         struct drm_i915_private *i915 = node_to_i915(m->private);
1349         struct intel_engine_cs *engine;
1350
1351         for_each_uabi_engine(engine, i915) {
1352                 const struct i915_wa_list *wal = &engine->ctx_wa_list;
1353                 const struct i915_wa *wa;
1354                 unsigned int count;
1355
1356                 count = wal->count;
1357                 if (!count)
1358                         continue;
1359
1360                 seq_printf(m, "%s: Workarounds applied: %u\n",
1361                            engine->name, count);
1362
1363                 for (wa = wal->list; count--; wa++)
1364                         seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
1365                                    i915_mmio_reg_offset(wa->reg),
1366                                    wa->set, wa->clr);
1367
1368                 seq_printf(m, "\n");
1369         }
1370
1371         return 0;
1372 }
1373
1374 static int
1375 i915_wedged_get(void *data, u64 *val)
1376 {
1377         struct drm_i915_private *i915 = data;
1378         int ret = intel_gt_terminally_wedged(&i915->gt);
1379
1380         switch (ret) {
1381         case -EIO:
1382                 *val = 1;
1383                 return 0;
1384         case 0:
1385                 *val = 0;
1386                 return 0;
1387         default:
1388                 return ret;
1389         }
1390 }
1391
1392 static int
1393 i915_wedged_set(void *data, u64 val)
1394 {
1395         struct drm_i915_private *i915 = data;
1396
1397         /* Flush any previous reset before applying for a new one */
1398         wait_event(i915->gt.reset.queue,
1399                    !test_bit(I915_RESET_BACKOFF, &i915->gt.reset.flags));
1400
1401         intel_gt_handle_error(&i915->gt, val, I915_ERROR_CAPTURE,
1402                               "Manually set wedged engine mask = %llx", val);
1403         return 0;
1404 }
1405
1406 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
1407                         i915_wedged_get, i915_wedged_set,
1408                         "%llu\n");
1409
1410 static int
1411 i915_perf_noa_delay_set(void *data, u64 val)
1412 {
1413         struct drm_i915_private *i915 = data;
1414
1415         /*
1416          * This would lead to infinite waits as we're doing timestamp
1417          * difference on the CS with only 32bits.
1418          */
1419         if (intel_gt_ns_to_clock_interval(&i915->gt, val) > U32_MAX)
1420                 return -EINVAL;
1421
1422         atomic64_set(&i915->perf.noa_programming_delay, val);
1423         return 0;
1424 }
1425
1426 static int
1427 i915_perf_noa_delay_get(void *data, u64 *val)
1428 {
1429         struct drm_i915_private *i915 = data;
1430
1431         *val = atomic64_read(&i915->perf.noa_programming_delay);
1432         return 0;
1433 }
1434
1435 DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops,
1436                         i915_perf_noa_delay_get,
1437                         i915_perf_noa_delay_set,
1438                         "%llu\n");
1439
1440 #define DROP_UNBOUND    BIT(0)
1441 #define DROP_BOUND      BIT(1)
1442 #define DROP_RETIRE     BIT(2)
1443 #define DROP_ACTIVE     BIT(3)
1444 #define DROP_FREED      BIT(4)
1445 #define DROP_SHRINK_ALL BIT(5)
1446 #define DROP_IDLE       BIT(6)
1447 #define DROP_RESET_ACTIVE       BIT(7)
1448 #define DROP_RESET_SEQNO        BIT(8)
1449 #define DROP_RCU        BIT(9)
1450 #define DROP_ALL (DROP_UNBOUND  | \
1451                   DROP_BOUND    | \
1452                   DROP_RETIRE   | \
1453                   DROP_ACTIVE   | \
1454                   DROP_FREED    | \
1455                   DROP_SHRINK_ALL |\
1456                   DROP_IDLE     | \
1457                   DROP_RESET_ACTIVE | \
1458                   DROP_RESET_SEQNO | \
1459                   DROP_RCU)
1460 static int
1461 i915_drop_caches_get(void *data, u64 *val)
1462 {
1463         *val = DROP_ALL;
1464
1465         return 0;
1466 }
1467 static int
1468 gt_drop_caches(struct intel_gt *gt, u64 val)
1469 {
1470         int ret;
1471
1472         if (val & DROP_RESET_ACTIVE &&
1473             wait_for(intel_engines_are_idle(gt), I915_IDLE_ENGINES_TIMEOUT))
1474                 intel_gt_set_wedged(gt);
1475
1476         if (val & DROP_RETIRE)
1477                 intel_gt_retire_requests(gt);
1478
1479         if (val & (DROP_IDLE | DROP_ACTIVE)) {
1480                 ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
1481                 if (ret)
1482                         return ret;
1483         }
1484
1485         if (val & DROP_IDLE) {
1486                 ret = intel_gt_pm_wait_for_idle(gt);
1487                 if (ret)
1488                         return ret;
1489         }
1490
1491         if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt))
1492                 intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL);
1493
1494         if (val & DROP_FREED)
1495                 intel_gt_flush_buffer_pool(gt);
1496
1497         return 0;
1498 }
1499
1500 static int
1501 i915_drop_caches_set(void *data, u64 val)
1502 {
1503         struct drm_i915_private *i915 = data;
1504         int ret;
1505
1506         DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",
1507                   val, val & DROP_ALL);
1508
1509         ret = gt_drop_caches(&i915->gt, val);
1510         if (ret)
1511                 return ret;
1512
1513         fs_reclaim_acquire(GFP_KERNEL);
1514         if (val & DROP_BOUND)
1515                 i915_gem_shrink(i915, LONG_MAX, NULL, I915_SHRINK_BOUND);
1516
1517         if (val & DROP_UNBOUND)
1518                 i915_gem_shrink(i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
1519
1520         if (val & DROP_SHRINK_ALL)
1521                 i915_gem_shrink_all(i915);
1522         fs_reclaim_release(GFP_KERNEL);
1523
1524         if (val & DROP_RCU)
1525                 rcu_barrier();
1526
1527         if (val & DROP_FREED)
1528                 i915_gem_drain_freed_objects(i915);
1529
1530         return 0;
1531 }
1532
1533 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
1534                         i915_drop_caches_get, i915_drop_caches_set,
1535                         "0x%08llx\n");
1536
1537 static int
1538 i915_cache_sharing_get(void *data, u64 *val)
1539 {
1540         struct drm_i915_private *dev_priv = data;
1541         intel_wakeref_t wakeref;
1542         u32 snpcr = 0;
1543
1544         if (!(IS_GEN_RANGE(dev_priv, 6, 7)))
1545                 return -ENODEV;
1546
1547         with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
1548                 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1549
1550         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
1551
1552         return 0;
1553 }
1554
1555 static int
1556 i915_cache_sharing_set(void *data, u64 val)
1557 {
1558         struct drm_i915_private *dev_priv = data;
1559         intel_wakeref_t wakeref;
1560
1561         if (!(IS_GEN_RANGE(dev_priv, 6, 7)))
1562                 return -ENODEV;
1563
1564         if (val > 3)
1565                 return -EINVAL;
1566
1567         drm_dbg(&dev_priv->drm,
1568                 "Manually setting uncore sharing to %llu\n", val);
1569         with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
1570                 u32 snpcr;
1571
1572                 /* Update the cache sharing policy here as well */
1573                 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1574                 snpcr &= ~GEN6_MBC_SNPCR_MASK;
1575                 snpcr |= val << GEN6_MBC_SNPCR_SHIFT;
1576                 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
1577         }
1578
1579         return 0;
1580 }
1581
1582 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
1583                         i915_cache_sharing_get, i915_cache_sharing_set,
1584                         "%llu\n");
1585
1586 static int i915_sseu_status(struct seq_file *m, void *unused)
1587 {
1588         struct drm_i915_private *i915 = node_to_i915(m->private);
1589         struct intel_gt *gt = &i915->gt;
1590
1591         return intel_sseu_status(m, gt);
1592 }
1593
1594 static int i915_forcewake_open(struct inode *inode, struct file *file)
1595 {
1596         struct drm_i915_private *i915 = inode->i_private;
1597         struct intel_gt *gt = &i915->gt;
1598
1599         atomic_inc(&gt->user_wakeref);
1600         intel_gt_pm_get(gt);
1601         if (INTEL_GEN(i915) >= 6)
1602                 intel_uncore_forcewake_user_get(gt->uncore);
1603
1604         return 0;
1605 }
1606
1607 static int i915_forcewake_release(struct inode *inode, struct file *file)
1608 {
1609         struct drm_i915_private *i915 = inode->i_private;
1610         struct intel_gt *gt = &i915->gt;
1611
1612         if (INTEL_GEN(i915) >= 6)
1613                 intel_uncore_forcewake_user_put(&i915->uncore);
1614         intel_gt_pm_put(gt);
1615         atomic_dec(&gt->user_wakeref);
1616
1617         return 0;
1618 }
1619
1620 static const struct file_operations i915_forcewake_fops = {
1621         .owner = THIS_MODULE,
1622         .open = i915_forcewake_open,
1623         .release = i915_forcewake_release,
1624 };
1625
1626 static const struct drm_info_list i915_debugfs_list[] = {
1627         {"i915_capabilities", i915_capabilities, 0},
1628         {"i915_gem_objects", i915_gem_object_info, 0},
1629         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
1630         {"i915_gem_interrupt", i915_interrupt_info, 0},
1631         {"i915_frequency_info", i915_frequency_info, 0},
1632         {"i915_ring_freq_table", i915_ring_freq_table, 0},
1633         {"i915_context_status", i915_context_status, 0},
1634         {"i915_swizzle_info", i915_swizzle_info, 0},
1635         {"i915_llc", i915_llc, 0},
1636         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
1637         {"i915_engine_info", i915_engine_info, 0},
1638         {"i915_shrinker_info", i915_shrinker_info, 0},
1639         {"i915_wa_registers", i915_wa_registers, 0},
1640         {"i915_sseu_status", i915_sseu_status, 0},
1641         {"i915_rps_boost_info", i915_rps_boost_info, 0},
1642 };
1643 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
1644
1645 static const struct i915_debugfs_files {
1646         const char *name;
1647         const struct file_operations *fops;
1648 } i915_debugfs_files[] = {
1649         {"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
1650         {"i915_wedged", &i915_wedged_fops},
1651         {"i915_cache_sharing", &i915_cache_sharing_fops},
1652         {"i915_gem_drop_caches", &i915_drop_caches_fops},
1653 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1654         {"i915_error_state", &i915_error_state_fops},
1655         {"i915_gpu_info", &i915_gpu_info_fops},
1656 #endif
1657 };
1658
1659 void i915_debugfs_register(struct drm_i915_private *dev_priv)
1660 {
1661         struct drm_minor *minor = dev_priv->drm.primary;
1662         int i;
1663
1664         i915_debugfs_params(dev_priv);
1665
1666         debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root,
1667                             to_i915(minor->dev), &i915_forcewake_fops);
1668         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
1669                 debugfs_create_file(i915_debugfs_files[i].name,
1670                                     S_IRUGO | S_IWUSR,
1671                                     minor->debugfs_root,
1672                                     to_i915(minor->dev),
1673                                     i915_debugfs_files[i].fops);
1674         }
1675
1676         drm_debugfs_create_files(i915_debugfs_list,
1677                                  I915_DEBUGFS_ENTRIES,
1678                                  minor->debugfs_root, minor);
1679 }