drivers/gpu/drm/meson/meson_plane.c

   1 /*
   2  * Copyright (C) 2016 BayLibre, SAS
   3  * Author: Neil Armstrong <[email protected]>
   4  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
   5  * Copyright (C) 2014 Endless Mobile
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of the
  10  * License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  * Written by:
  21  *     Jasper St. Pierre <[email protected]>
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/mutex.h>
  27 #include <linux/bitfield.h>
  28 #include <linux/platform_device.h>
  29 #include <drm/drmP.h>
  30 #include <drm/drm_atomic.h>
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_plane_helper.h>
  33 #include <drm/drm_gem_cma_helper.h>
  34 #include <drm/drm_fb_cma_helper.h>
  35 #include <drm/drm_gem_framebuffer_helper.h>
  36 #include <drm/drm_rect.h>
  37
  38 #include "meson_plane.h"
  39 #include "meson_vpp.h"
  40 #include "meson_viu.h"
  41 #include "meson_canvas.h"
  42 #include "meson_registers.h"
  43
  44 /* OSD_SCI_WH_M1 */
  45 #define SCI_WH_M1_W(w)                  FIELD_PREP(GENMASK(28, 16), w)
  46 #define SCI_WH_M1_H(h)                  FIELD_PREP(GENMASK(12, 0), h)
  47
  48 /* OSD_SCO_H_START_END */
  49 /* OSD_SCO_V_START_END */
  50 #define SCO_HV_START(start)             FIELD_PREP(GENMASK(27, 16), start)
  51 #define SCO_HV_END(end)                 FIELD_PREP(GENMASK(11, 0), end)
  52
  53 /* OSD_SC_CTRL0 */
  54 #define SC_CTRL0_PATH_EN                BIT(3)
  55 #define SC_CTRL0_SEL_OSD1               BIT(2)
  56
  57 /* OSD_VSC_CTRL0 */
  58 #define VSC_BANK_LEN(value)             FIELD_PREP(GENMASK(2, 0), value)
  59 #define VSC_TOP_INI_RCV_NUM(value)      FIELD_PREP(GENMASK(6, 3), value)
  60 #define VSC_TOP_RPT_L0_NUM(value)       FIELD_PREP(GENMASK(9, 8), value)
  61 #define VSC_BOT_INI_RCV_NUM(value)      FIELD_PREP(GENMASK(14, 11), value)
  62 #define VSC_BOT_RPT_L0_NUM(value)       FIELD_PREP(GENMASK(17, 16), value)
  63 #define VSC_PROG_INTERLACE              BIT(23)
  64 #define VSC_VERTICAL_SCALER_EN          BIT(24)
  65
  66 /* OSD_VSC_INI_PHASE */
  67 #define VSC_INI_PHASE_BOT(bottom)       FIELD_PREP(GENMASK(31, 16), bottom)
  68 #define VSC_INI_PHASE_TOP(top)          FIELD_PREP(GENMASK(15, 0), top)
  69
  70 /* OSD_HSC_CTRL0 */
  71 #define HSC_BANK_LENGTH(value)          FIELD_PREP(GENMASK(2, 0), value)
  72 #define HSC_INI_RCV_NUM0(value)         FIELD_PREP(GENMASK(6, 3), value)
  73 #define HSC_RPT_P0_NUM0(value)          FIELD_PREP(GENMASK(9, 8), value)
  74 #define HSC_HORIZ_SCALER_EN             BIT(22)
  75
  76 /* VPP_OSD_VSC_PHASE_STEP */
  77 /* VPP_OSD_HSC_PHASE_STEP */
  78 #define SC_PHASE_STEP(value)            FIELD_PREP(GENMASK(27, 0), value)
  79
  80 struct meson_plane {
  81         struct drm_plane base;
  82         struct meson_drm *priv;
  83         bool enabled;
  84 };
  85 #define to_meson_plane(x) container_of(x, struct meson_plane, base)
  86
  87 #define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
  88
  89 static int meson_plane_atomic_check(struct drm_plane *plane,
  90                                     struct drm_plane_state *state)
  91 {
  92         struct drm_crtc_state *crtc_state;
  93
  94         if (!state->crtc)
  95                 return 0;
  96
  97         crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
  98         if (IS_ERR(crtc_state))
  99                 return PTR_ERR(crtc_state);
 100
 101         /*
 102          * Only allow :
 103          * - Upscaling up to 5x, vertical and horizontal
 104          * - Final coordinates must match crtc size
 105          */
 106         return drm_atomic_helper_check_plane_state(state, crtc_state,
 107                                                    FRAC_16_16(1, 5),
 108                                                    DRM_PLANE_HELPER_NO_SCALING,
 109                                                    false, true);
 110 }
 111
 112 /* Takes a fixed 16.16 number and converts it to integer. */
 113 static inline int64_t fixed16_to_int(int64_t value)
 114 {
 115         return value >> 16;
 116 }
 117
 118 static void meson_plane_atomic_update(struct drm_plane *plane,
 119                                       struct drm_plane_state *old_state)
 120 {
 121         struct meson_plane *meson_plane = to_meson_plane(plane);
 122         struct drm_plane_state *state = plane->state;
 123         struct drm_rect dest = drm_plane_state_dest(state);
 124         struct meson_drm *priv = meson_plane->priv;
 125         struct drm_framebuffer *fb = state->fb;
 126         struct drm_gem_cma_object *gem;
 127         unsigned long flags;
 128         int vsc_ini_rcv_num, vsc_ini_rpt_p0_num;
 129         int vsc_bot_rcv_num, vsc_bot_rpt_p0_num;
 130         int hsc_ini_rcv_num, hsc_ini_rpt_p0_num;
 131         int hf_phase_step, vf_phase_step;
 132         int src_w, src_h, dst_w, dst_h;
 133         int bot_ini_phase;
 134         int hf_bank_len;
 135         int vf_bank_len;
 136         u8 canvas_id_osd1;
 137
 138         /*
 139          * Update Coordinates
 140          * Update Formats
 141          * Update Buffer
 142          * Enable Plane
 143          */
 144         spin_lock_irqsave(&priv->drm->event_lock, flags);
 145
 146         /* Enable OSD and BLK0, set max global alpha */
 147         priv->viu.osd1_ctrl_stat = OSD_ENABLE |
 148                                    (0xFF << OSD_GLOBAL_ALPHA_SHIFT) |
 149                                    OSD_BLK0_ENABLE;
 150
 151         if (priv->canvas)
 152                 canvas_id_osd1 = priv->canvas_id_osd1;
 153         else
 154                 canvas_id_osd1 = MESON_CANVAS_ID_OSD1;
 155
 156         /* Set up BLK0 to point to the right canvas */
 157         priv->viu.osd1_blk0_cfg[0] = ((canvas_id_osd1 << OSD_CANVAS_SEL) |
 158                                       OSD_ENDIANNESS_LE);
 159
 160         /* On GXBB, Use the old non-HDR RGB2YUV converter */
 161         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
 162                 priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB;
 163
 164         switch (fb->format->format) {
 165         case DRM_FORMAT_XRGB8888:
 166                 /* For XRGB, replace the pixel's alpha by 0xFF */
 167                 writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN,
 168                                     priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
 169                 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
 170                                               OSD_COLOR_MATRIX_32_ARGB;
 171                 break;
 172         case DRM_FORMAT_ARGB8888:
 173                 /* For ARGB, use the pixel's alpha */
 174                 writel_bits_relaxed(OSD_REPLACE_EN, 0,
 175                                     priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
 176                 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
 177                                               OSD_COLOR_MATRIX_32_ARGB;
 178                 break;
 179         case DRM_FORMAT_RGB888:
 180                 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_24 |
 181                                               OSD_COLOR_MATRIX_24_RGB;
 182                 break;
 183         case DRM_FORMAT_RGB565:
 184                 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_16 |
 185                                               OSD_COLOR_MATRIX_16_RGB565;
 186                 break;
 187         };
 188
 189         /* Default scaler parameters */
 190         vsc_bot_rcv_num = 0;
 191         vsc_bot_rpt_p0_num = 0;
 192         hf_bank_len = 4;
 193         vf_bank_len = 4;
 194
 195         if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
 196                 vsc_bot_rcv_num = 6;
 197                 vsc_bot_rpt_p0_num = 2;
 198         }
 199
 200         hsc_ini_rcv_num = hf_bank_len;
 201         vsc_ini_rcv_num = vf_bank_len;
 202         hsc_ini_rpt_p0_num = (hf_bank_len / 2) - 1;
 203         vsc_ini_rpt_p0_num = (vf_bank_len / 2) - 1;
 204
 205         src_w = fixed16_to_int(state->src_w);
 206         src_h = fixed16_to_int(state->src_h);
 207         dst_w = state->crtc_w;
 208         dst_h = state->crtc_h;
 209
 210         /*
 211          * When the output is interlaced, the OSD must switch between
 212          * each field using the INTERLACE_SEL_ODD (0) of VIU_OSD1_BLK0_CFG_W0
 213          * at each vsync.
 214          * But the vertical scaler can provide such funtionnality if
 215          * is configured for 2:1 scaling with interlace options enabled.
 216          */
 217         if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
 218                 dest.y1 /= 2;
 219                 dest.y2 /= 2;
 220                 dst_h /= 2;
 221         }
 222
 223         hf_phase_step = ((src_w << 18) / dst_w) << 6;
 224         vf_phase_step = (src_h << 20) / dst_h;
 225
 226         if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
 227                 bot_ini_phase = ((vf_phase_step / 2) >> 4);
 228         else
 229                 bot_ini_phase = 0;
 230
 231         vf_phase_step = (vf_phase_step << 4);
 232
 233         /* In interlaced mode, scaler is always active */
 234         if (src_h != dst_h || src_w != dst_w) {
 235                 priv->viu.osd_sc_i_wh_m1 = SCI_WH_M1_W(src_w - 1) |
 236                                            SCI_WH_M1_H(src_h - 1);
 237                 priv->viu.osd_sc_o_h_start_end = SCO_HV_START(dest.x1) |
 238                                                  SCO_HV_END(dest.x2 - 1);
 239                 priv->viu.osd_sc_o_v_start_end = SCO_HV_START(dest.y1) |
 240                                                  SCO_HV_END(dest.y2 - 1);
 241                 /* Enable OSD Scaler */
 242                 priv->viu.osd_sc_ctrl0 = SC_CTRL0_PATH_EN | SC_CTRL0_SEL_OSD1;
 243         } else {
 244                 priv->viu.osd_sc_i_wh_m1 = 0;
 245                 priv->viu.osd_sc_o_h_start_end = 0;
 246                 priv->viu.osd_sc_o_v_start_end = 0;
 247                 priv->viu.osd_sc_ctrl0 = 0;
 248         }
 249
 250         /* In interlaced mode, vertical scaler is always active */
 251         if (src_h != dst_h) {
 252                 priv->viu.osd_sc_v_ctrl0 =
 253                                         VSC_BANK_LEN(vf_bank_len) |
 254                                         VSC_TOP_INI_RCV_NUM(vsc_ini_rcv_num) |
 255                                         VSC_TOP_RPT_L0_NUM(vsc_ini_rpt_p0_num) |
 256                                         VSC_VERTICAL_SCALER_EN;
 257
 258                 if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
 259                         priv->viu.osd_sc_v_ctrl0 |=
 260                                         VSC_BOT_INI_RCV_NUM(vsc_bot_rcv_num) |
 261                                         VSC_BOT_RPT_L0_NUM(vsc_bot_rpt_p0_num) |
 262                                         VSC_PROG_INTERLACE;
 263
 264                 priv->viu.osd_sc_v_phase_step = SC_PHASE_STEP(vf_phase_step);
 265                 priv->viu.osd_sc_v_ini_phase = VSC_INI_PHASE_BOT(bot_ini_phase);
 266         } else {
 267                 priv->viu.osd_sc_v_ctrl0 = 0;
 268                 priv->viu.osd_sc_v_phase_step = 0;
 269                 priv->viu.osd_sc_v_ini_phase = 0;
 270         }
 271
 272         /* Horizontal scaler is only used if width does not match */
 273         if (src_w != dst_w) {
 274                 priv->viu.osd_sc_h_ctrl0 =
 275                                         HSC_BANK_LENGTH(hf_bank_len) |
 276                                         HSC_INI_RCV_NUM0(hsc_ini_rcv_num) |
 277                                         HSC_RPT_P0_NUM0(hsc_ini_rpt_p0_num) |
 278                                         HSC_HORIZ_SCALER_EN;
 279                 priv->viu.osd_sc_h_phase_step = SC_PHASE_STEP(hf_phase_step);
 280                 priv->viu.osd_sc_h_ini_phase = 0;
 281         } else {
 282                 priv->viu.osd_sc_h_ctrl0 = 0;
 283                 priv->viu.osd_sc_h_phase_step = 0;
 284                 priv->viu.osd_sc_h_ini_phase = 0;
 285         }
 286
 287         /*
 288          * The format of these registers is (x2 << 16 | x1),
 289          * where x2 is exclusive.
 290          * e.g. +30x1920 would be (1919 << 16) | 30
 291          */
 292         priv->viu.osd1_blk0_cfg[1] =
 293                                 ((fixed16_to_int(state->src.x2) - 1) << 16) |
 294                                 fixed16_to_int(state->src.x1);
 295         priv->viu.osd1_blk0_cfg[2] =
 296                                 ((fixed16_to_int(state->src.y2) - 1) << 16) |
 297                                 fixed16_to_int(state->src.y1);
 298         priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1;
 299         priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1;
 300
 301         /* Update Canvas with buffer address */
 302         gem = drm_fb_cma_get_gem_obj(fb, 0);
 303
 304         priv->viu.osd1_addr = gem->paddr;
 305         priv->viu.osd1_stride = fb->pitches[0];
 306         priv->viu.osd1_height = fb->height;
 307
 308         if (!meson_plane->enabled) {
 309                 /* Reset OSD1 before enabling it on GXL+ SoCs */
 310                 if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
 311                     meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
 312                         meson_viu_osd1_reset(priv);
 313
 314                 meson_plane->enabled = true;
 315         }
 316
 317         spin_unlock_irqrestore(&priv->drm->event_lock, flags);
 318 }
 319
 320 static void meson_plane_atomic_disable(struct drm_plane *plane,
 321                                        struct drm_plane_state *old_state)
 322 {
 323         struct meson_plane *meson_plane = to_meson_plane(plane);
 324         struct meson_drm *priv = meson_plane->priv;
 325
 326         /* Disable OSD1 */
 327         writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,
 328                             priv->io_base + _REG(VPP_MISC));
 329
 330         meson_plane->enabled = false;
 331
 332 }
 333
 334 static const struct drm_plane_helper_funcs meson_plane_helper_funcs = {
 335         .atomic_check   = meson_plane_atomic_check,
 336         .atomic_disable = meson_plane_atomic_disable,
 337         .atomic_update  = meson_plane_atomic_update,
 338         .prepare_fb     = drm_gem_fb_prepare_fb,
 339 };
 340
 341 static const struct drm_plane_funcs meson_plane_funcs = {
 342         .update_plane           = drm_atomic_helper_update_plane,
 343         .disable_plane          = drm_atomic_helper_disable_plane,
 344         .destroy                = drm_plane_cleanup,
 345         .reset                  = drm_atomic_helper_plane_reset,
 346         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 347         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 348 };
 349
 350 static const uint32_t supported_drm_formats[] = {
 351         DRM_FORMAT_ARGB8888,
 352         DRM_FORMAT_XRGB8888,
 353         DRM_FORMAT_RGB888,
 354         DRM_FORMAT_RGB565,
 355 };
 356
 357 int meson_plane_create(struct meson_drm *priv)
 358 {
 359         struct meson_plane *meson_plane;
 360         struct drm_plane *plane;
 361
 362         meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane),
 363                                    GFP_KERNEL);
 364         if (!meson_plane)
 365                 return -ENOMEM;
 366
 367         meson_plane->priv = priv;
 368         plane = &meson_plane->base;
 369
 370         drm_universal_plane_init(priv->drm, plane, 0xFF,
 371                                  &meson_plane_funcs,
 372                                  supported_drm_formats,
 373                                  ARRAY_SIZE(supported_drm_formats),
 374                                  NULL,
 375                                  DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane");
 376
 377         drm_plane_helper_add(plane, &meson_plane_helper_funcs);
 378
 379         priv->primary_plane = plane;
 380
 381         return 0;
 382 }