drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_ras.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_xgmi.h"
  35 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  36
  37 static const char *RAS_FS_NAME = "ras";
  38
  39 const char *ras_error_string[] = {
  40         "none",
  41         "parity",
  42         "single_correctable",
  43         "multi_uncorrectable",
  44         "poison",
  45 };
  46
  47 const char *ras_block_string[] = {
  48         "umc",
  49         "sdma",
  50         "gfx",
  51         "mmhub",
  52         "athub",
  53         "pcie_bif",
  54         "hdp",
  55         "xgmi_wafl",
  56         "df",
  57         "smn",
  58         "sem",
  59         "mp0",
  60         "mp1",
  61         "fuse",
  62 };
  63
  64 #define ras_err_str(i) (ras_error_string[ffs(i)])
  65 #define ras_block_str(i) (ras_block_string[i])
  66
  67 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
  68
  69 /* inject address is 52 bits */
  70 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
  71
  72 /* typical ECC bad page rate(1 bad page per 100MB VRAM) */
  73 #define RAS_BAD_PAGE_RATE               (100 * 1024 * 1024ULL)
  74
  75 enum amdgpu_ras_retire_page_reservation {
  76         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
  77         AMDGPU_RAS_RETIRE_PAGE_PENDING,
  78         AMDGPU_RAS_RETIRE_PAGE_FAULT,
  79 };
  80
  81 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
  82
  83 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
  84                                 uint64_t addr);
  85 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
  86                                 uint64_t addr);
  87
  88 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
  89 {
  90         if (adev && amdgpu_ras_get_context(adev))
  91                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
  92 }
  93
  94 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
  95 {
  96         if (adev && amdgpu_ras_get_context(adev))
  97                 return amdgpu_ras_get_context(adev)->error_query_ready;
  98
  99         return false;
 100 }
 101
 102 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 103                                         size_t size, loff_t *pos)
 104 {
 105         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 106         struct ras_query_if info = {
 107                 .head = obj->head,
 108         };
 109         ssize_t s;
 110         char val[128];
 111
 112         if (amdgpu_ras_query_error_status(obj->adev, &info))
 113                 return -EINVAL;
 114
 115         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 116                         "ue", info.ue_count,
 117                         "ce", info.ce_count);
 118         if (*pos >= s)
 119                 return 0;
 120
 121         s -= *pos;
 122         s = min_t(u64, s, size);
 123
 124
 125         if (copy_to_user(buf, &val[*pos], s))
 126                 return -EINVAL;
 127
 128         *pos += s;
 129
 130         return s;
 131 }
 132
 133 static const struct file_operations amdgpu_ras_debugfs_ops = {
 134         .owner = THIS_MODULE,
 135         .read = amdgpu_ras_debugfs_read,
 136         .write = NULL,
 137         .llseek = default_llseek
 138 };
 139
 140 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 141 {
 142         int i;
 143
 144         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 145                 *block_id = i;
 146                 if (strcmp(name, ras_block_str(i)) == 0)
 147                         return 0;
 148         }
 149         return -EINVAL;
 150 }
 151
 152 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 153                 const char __user *buf, size_t size,
 154                 loff_t *pos, struct ras_debug_if *data)
 155 {
 156         ssize_t s = min_t(u64, 64, size);
 157         char str[65];
 158         char block_name[33];
 159         char err[9] = "ue";
 160         int op = -1;
 161         int block_id;
 162         uint32_t sub_block;
 163         u64 address, value;
 164
 165         if (*pos)
 166                 return -EINVAL;
 167         *pos = size;
 168
 169         memset(str, 0, sizeof(str));
 170         memset(data, 0, sizeof(*data));
 171
 172         if (copy_from_user(str, buf, s))
 173                 return -EINVAL;
 174
 175         if (sscanf(str, "disable %32s", block_name) == 1)
 176                 op = 0;
 177         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 178                 op = 1;
 179         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 180                 op = 2;
 181         else if (str[0] && str[1] && str[2] && str[3])
 182                 /* ascii string, but commands are not matched. */
 183                 return -EINVAL;
 184
 185         if (op != -1) {
 186                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 187                         return -EINVAL;
 188
 189                 data->head.block = block_id;
 190                 /* only ue and ce errors are supported */
 191                 if (!memcmp("ue", err, 2))
 192                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 193                 else if (!memcmp("ce", err, 2))
 194                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 195                 else
 196                         return -EINVAL;
 197
 198                 data->op = op;
 199
 200                 if (op == 2) {
 201                         if (sscanf(str, "%*s %*s %*s %u %llu %llu",
 202                                                 &sub_block, &address, &value) != 3)
 203                                 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 204                                                         &sub_block, &address, &value) != 3)
 205                                         return -EINVAL;
 206                         data->head.sub_block_index = sub_block;
 207                         data->inject.address = address;
 208                         data->inject.value = value;
 209                 }
 210         } else {
 211                 if (size < sizeof(*data))
 212                         return -EINVAL;
 213
 214                 if (copy_from_user(data, buf, sizeof(*data)))
 215                         return -EINVAL;
 216         }
 217
 218         return 0;
 219 }
 220
 221 /**
 222  * DOC: AMDGPU RAS debugfs control interface
 223  *
 224  * It accepts struct ras_debug_if who has two members.
 225  *
 226  * First member: ras_debug_if::head or ras_debug_if::inject.
 227  *
 228  * head is used to indicate which IP block will be under control.
 229  *
 230  * head has four members, they are block, type, sub_block_index, name.
 231  * block: which IP will be under control.
 232  * type: what kind of error will be enabled/disabled/injected.
 233  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 234  * name: the name of IP.
 235  *
 236  * inject has two more members than head, they are address, value.
 237  * As their names indicate, inject operation will write the
 238  * value to the address.
 239  *
 240  * The second member: struct ras_debug_if::op.
 241  * It has three kinds of operations.
 242  *
 243  * - 0: disable RAS on the block. Take ::head as its data.
 244  * - 1: enable RAS on the block. Take ::head as its data.
 245  * - 2: inject errors on the block. Take ::inject as its data.
 246  *
 247  * How to use the interface?
 248  *
 249  * Programs
 250  *
 251  * Copy the struct ras_debug_if in your codes and initialize it.
 252  * Write the struct to the control node.
 253  *
 254  * Shells
 255  *
 256  * .. code-block:: bash
 257  *
 258  *      echo op block [error [sub_block address value]] > .../ras/ras_ctrl
 259  *
 260  * Parameters:
 261  *
 262  * op: disable, enable, inject
 263  *      disable: only block is needed
 264  *      enable: block and error are needed
 265  *      inject: error, address, value are needed
 266  * block: umc, sdma, gfx, .........
 267  *      see ras_block_string[] for details
 268  * error: ue, ce
 269  *      ue: multi_uncorrectable
 270  *      ce: single_correctable
 271  * sub_block:
 272  *      sub block index, pass 0 if there is no sub block
 273  *
 274  * here are some examples for bash commands:
 275  *
 276  * .. code-block:: bash
 277  *
 278  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 279  *      echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 280  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 281  *
 282  * How to check the result?
 283  *
 284  * For disable/enable, please check ras features at
 285  * /sys/class/drm/card[0/1/2...]/device/ras/features
 286  *
 287  * For inject, please check corresponding err count at
 288  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 289  *
 290  * .. note::
 291  *      Operations are only allowed on blocks which are supported.
 292  *      Please check ras mask at /sys/module/amdgpu/parameters/ras_mask
 293  *      to see which blocks support RAS on a particular asic.
 294  *
 295  */
 296 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
 297                 size_t size, loff_t *pos)
 298 {
 299         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 300         struct ras_debug_if data;
 301         int ret = 0;
 302
 303         if (!amdgpu_ras_get_error_query_ready(adev)) {
 304                 dev_warn(adev->dev, "RAS WARN: error injection "
 305                                 "currently inaccessible\n");
 306                 return size;
 307         }
 308
 309         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 310         if (ret)
 311                 return -EINVAL;
 312
 313         if (!amdgpu_ras_is_supported(adev, data.head.block))
 314                 return -EINVAL;
 315
 316         switch (data.op) {
 317         case 0:
 318                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 319                 break;
 320         case 1:
 321                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 322                 break;
 323         case 2:
 324                 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
 325                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 326                         dev_warn(adev->dev, "RAS WARN: input address "
 327                                         "0x%llx is invalid.",
 328                                         data.inject.address);
 329                         ret = -EINVAL;
 330                         break;
 331                 }
 332
 333                 /* umc ce/ue error injection for a bad page is not allowed */
 334                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 335                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 336                         dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked "
 337                                         "as bad before error injection!\n",
 338                                         data.inject.address);
 339                         break;
 340                 }
 341
 342                 /* data.inject.address is offset instead of absolute gpu address */
 343                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 344                 break;
 345         default:
 346                 ret = -EINVAL;
 347                 break;
 348         }
 349
 350         if (ret)
 351                 return -EINVAL;
 352
 353         return size;
 354 }
 355
 356 /**
 357  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 358  *
 359  * Some boards contain an EEPROM which is used to persistently store a list of
 360  * bad pages which experiences ECC errors in vram.  This interface provides
 361  * a way to reset the EEPROM, e.g., after testing error injection.
 362  *
 363  * Usage:
 364  *
 365  * .. code-block:: bash
 366  *
 367  *      echo 1 > ../ras/ras_eeprom_reset
 368  *
 369  * will reset EEPROM table to 0 entries.
 370  *
 371  */
 372 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf,
 373                 size_t size, loff_t *pos)
 374 {
 375         struct amdgpu_device *adev =
 376                 (struct amdgpu_device *)file_inode(f)->i_private;
 377         int ret;
 378
 379         ret = amdgpu_ras_eeprom_reset_table(
 380                         &(amdgpu_ras_get_context(adev)->eeprom_control));
 381
 382         if (ret == 1) {
 383                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 384                 return size;
 385         } else {
 386                 return -EIO;
 387         }
 388 }
 389
 390 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 391         .owner = THIS_MODULE,
 392         .read = NULL,
 393         .write = amdgpu_ras_debugfs_ctrl_write,
 394         .llseek = default_llseek
 395 };
 396
 397 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 398         .owner = THIS_MODULE,
 399         .read = NULL,
 400         .write = amdgpu_ras_debugfs_eeprom_write,
 401         .llseek = default_llseek
 402 };
 403
 404 /**
 405  * DOC: AMDGPU RAS sysfs Error Count Interface
 406  *
 407  * It allows the user to read the error count for each IP block on the gpu through
 408  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 409  *
 410  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 411  * (ce) error counts.
 412  *
 413  * The format of one line is below,
 414  *
 415  * [ce|ue]: count
 416  *
 417  * Example:
 418  *
 419  * .. code-block:: bash
 420  *
 421  *      ue: 0
 422  *      ce: 1
 423  *
 424  */
 425 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 426                 struct device_attribute *attr, char *buf)
 427 {
 428         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 429         struct ras_query_if info = {
 430                 .head = obj->head,
 431         };
 432
 433         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 434                 return sysfs_emit(buf, "Query currently inaccessible\n");
 435
 436         if (amdgpu_ras_query_error_status(obj->adev, &info))
 437                 return -EINVAL;
 438
 439         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 440                           "ce", info.ce_count);
 441 }
 442
 443 /* obj begin */
 444
 445 #define get_obj(obj) do { (obj)->use++; } while (0)
 446 #define alive_obj(obj) ((obj)->use)
 447
 448 static inline void put_obj(struct ras_manager *obj)
 449 {
 450         if (obj && --obj->use == 0)
 451                 list_del(&obj->node);
 452         if (obj && obj->use < 0) {
 453                  DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
 454         }
 455 }
 456
 457 /* make one obj and return it. */
 458 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 459                 struct ras_common_if *head)
 460 {
 461         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 462         struct ras_manager *obj;
 463
 464         if (!adev->ras_features || !con)
 465                 return NULL;
 466
 467         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 468                 return NULL;
 469
 470         obj = &con->objs[head->block];
 471         /* already exist. return obj? */
 472         if (alive_obj(obj))
 473                 return NULL;
 474
 475         obj->head = *head;
 476         obj->adev = adev;
 477         list_add(&obj->node, &con->head);
 478         get_obj(obj);
 479
 480         return obj;
 481 }
 482
 483 /* return an obj equal to head, or the first when head is NULL */
 484 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 485                 struct ras_common_if *head)
 486 {
 487         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 488         struct ras_manager *obj;
 489         int i;
 490
 491         if (!adev->ras_features || !con)
 492                 return NULL;
 493
 494         if (head) {
 495                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 496                         return NULL;
 497
 498                 obj = &con->objs[head->block];
 499
 500                 if (alive_obj(obj)) {
 501                         WARN_ON(head->block != obj->head.block);
 502                         return obj;
 503                 }
 504         } else {
 505                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 506                         obj = &con->objs[i];
 507                         if (alive_obj(obj)) {
 508                                 WARN_ON(i != obj->head.block);
 509                                 return obj;
 510                         }
 511                 }
 512         }
 513
 514         return NULL;
 515 }
 516 /* obj end */
 517
 518 static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,
 519                                          const char* invoke_type,
 520                                          const char* block_name,
 521                                          enum ta_ras_status ret)
 522 {
 523         switch (ret) {
 524         case TA_RAS_STATUS__SUCCESS:
 525                 return;
 526         case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
 527                 dev_warn(adev->dev,
 528                         "RAS WARN: %s %s currently unavailable\n",
 529                         invoke_type,
 530                         block_name);
 531                 break;
 532         default:
 533                 dev_err(adev->dev,
 534                         "RAS ERROR: %s %s error failed ret 0x%X\n",
 535                         invoke_type,
 536                         block_name,
 537                         ret);
 538         }
 539 }
 540
 541 /* feature ctl begin */
 542 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 543                 struct ras_common_if *head)
 544 {
 545         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 546
 547         return con->hw_supported & BIT(head->block);
 548 }
 549
 550 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 551                 struct ras_common_if *head)
 552 {
 553         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 554
 555         return con->features & BIT(head->block);
 556 }
 557
 558 /*
 559  * if obj is not created, then create one.
 560  * set feature enable flag.
 561  */
 562 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 563                 struct ras_common_if *head, int enable)
 564 {
 565         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 566         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 567
 568         /* If hardware does not support ras, then do not create obj.
 569          * But if hardware support ras, we can create the obj.
 570          * Ras framework checks con->hw_supported to see if it need do
 571          * corresponding initialization.
 572          * IP checks con->support to see if it need disable ras.
 573          */
 574         if (!amdgpu_ras_is_feature_allowed(adev, head))
 575                 return 0;
 576         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
 577                 return 0;
 578
 579         if (enable) {
 580                 if (!obj) {
 581                         obj = amdgpu_ras_create_obj(adev, head);
 582                         if (!obj)
 583                                 return -EINVAL;
 584                 } else {
 585                         /* In case we create obj somewhere else */
 586                         get_obj(obj);
 587                 }
 588                 con->features |= BIT(head->block);
 589         } else {
 590                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 591                         /* skip clean gfx ras context feature for VEGA20 Gaming.
 592                          * will clean later
 593                          */
 594                         if (!(!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)))
 595                                 con->features &= ~BIT(head->block);
 596                         put_obj(obj);
 597                 }
 598         }
 599
 600         return 0;
 601 }
 602
 603 /* wrapper of psp_ras_enable_features */
 604 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 605                 struct ras_common_if *head, bool enable)
 606 {
 607         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 608         union ta_ras_cmd_input *info;
 609         int ret;
 610
 611         if (!con)
 612                 return -EINVAL;
 613
 614         info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 615         if (!info)
 616                 return -ENOMEM;
 617
 618         if (!enable) {
 619                 info->disable_features = (struct ta_ras_disable_features_input) {
 620                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 621                         .error_type = amdgpu_ras_error_to_ta(head->type),
 622                 };
 623         } else {
 624                 info->enable_features = (struct ta_ras_enable_features_input) {
 625                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 626                         .error_type = amdgpu_ras_error_to_ta(head->type),
 627                 };
 628         }
 629
 630         /* Do not enable if it is not allowed. */
 631         WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
 632         /* Are we alerady in that state we are going to set? */
 633         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) {
 634                 ret = 0;
 635                 goto out;
 636         }
 637
 638         if (!amdgpu_ras_intr_triggered()) {
 639                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 640                 if (ret) {
 641                         amdgpu_ras_parse_status_code(adev,
 642                                                      enable ? "enable":"disable",
 643                                                      ras_block_str(head->block),
 644                                                     (enum ta_ras_status)ret);
 645                         if (ret == TA_RAS_STATUS__RESET_NEEDED)
 646                                 ret = -EAGAIN;
 647                         else
 648                                 ret = -EINVAL;
 649
 650                         goto out;
 651                 }
 652         }
 653
 654         /* setup the obj */
 655         __amdgpu_ras_feature_enable(adev, head, enable);
 656         ret = 0;
 657 out:
 658         kfree(info);
 659         return ret;
 660 }
 661
 662 /* Only used in device probe stage and called only once. */
 663 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 664                 struct ras_common_if *head, bool enable)
 665 {
 666         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 667         int ret;
 668
 669         if (!con)
 670                 return -EINVAL;
 671
 672         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 673                 if (enable) {
 674                         /* There is no harm to issue a ras TA cmd regardless of
 675                          * the currecnt ras state.
 676                          * If current state == target state, it will do nothing
 677                          * But sometimes it requests driver to reset and repost
 678                          * with error code -EAGAIN.
 679                          */
 680                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 681                         /* With old ras TA, we might fail to enable ras.
 682                          * Log it and just setup the object.
 683                          * TODO need remove this WA in the future.
 684                          */
 685                         if (ret == -EINVAL) {
 686                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 687                                 if (!ret)
 688                                         dev_info(adev->dev,
 689                                                 "RAS INFO: %s setup object\n",
 690                                                 ras_block_str(head->block));
 691                         }
 692                 } else {
 693                         /* setup the object then issue a ras TA disable cmd.*/
 694                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 695                         if (ret)
 696                                 return ret;
 697
 698                         /* gfx block ras dsiable cmd must send to ras-ta */
 699                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 700                                 con->features |= BIT(head->block);
 701
 702                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 703                 }
 704         } else
 705                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 706
 707         return ret;
 708 }
 709
 710 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 711                 bool bypass)
 712 {
 713         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 714         struct ras_manager *obj, *tmp;
 715
 716         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 717                 /* bypass psp.
 718                  * aka just release the obj and corresponding flags
 719                  */
 720                 if (bypass) {
 721                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 722                                 break;
 723                 } else {
 724                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 725                                 break;
 726                 }
 727         }
 728
 729         return con->features;
 730 }
 731
 732 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 733                 bool bypass)
 734 {
 735         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 736         int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
 737         int i;
 738         const enum amdgpu_ras_error_type default_ras_type =
 739                 AMDGPU_RAS_ERROR__NONE;
 740
 741         for (i = 0; i < ras_block_count; i++) {
 742                 struct ras_common_if head = {
 743                         .block = i,
 744                         .type = default_ras_type,
 745                         .sub_block_index = 0,
 746                 };
 747                 strcpy(head.name, ras_block_str(i));
 748                 if (bypass) {
 749                         /*
 750                          * bypass psp. vbios enable ras for us.
 751                          * so just create the obj
 752                          */
 753                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 754                                 break;
 755                 } else {
 756                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 757                                 break;
 758                 }
 759         }
 760
 761         return con->features;
 762 }
 763 /* feature ctl end */
 764
 765 /* query/inject/cure begin */
 766 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 767         struct ras_query_if *info)
 768 {
 769         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 770         struct ras_err_data err_data = {0, 0, 0, NULL};
 771         int i;
 772
 773         if (!obj)
 774                 return -EINVAL;
 775
 776         switch (info->head.block) {
 777         case AMDGPU_RAS_BLOCK__UMC:
 778                 if (adev->umc.funcs->query_ras_error_count)
 779                         adev->umc.funcs->query_ras_error_count(adev, &err_data);
 780                 /* umc query_ras_error_address is also responsible for clearing
 781                  * error status
 782                  */
 783                 if (adev->umc.funcs->query_ras_error_address)
 784                         adev->umc.funcs->query_ras_error_address(adev, &err_data);
 785                 break;
 786         case AMDGPU_RAS_BLOCK__SDMA:
 787                 if (adev->sdma.funcs->query_ras_error_count) {
 788                         for (i = 0; i < adev->sdma.num_instances; i++)
 789                                 adev->sdma.funcs->query_ras_error_count(adev, i,
 790                                                                         &err_data);
 791                 }
 792                 break;
 793         case AMDGPU_RAS_BLOCK__GFX:
 794                 if (adev->gfx.funcs->query_ras_error_count)
 795                         adev->gfx.funcs->query_ras_error_count(adev, &err_data);
 796
 797                 if (adev->gfx.funcs->query_ras_error_status)
 798                         adev->gfx.funcs->query_ras_error_status(adev);
 799                 break;
 800         case AMDGPU_RAS_BLOCK__MMHUB:
 801                 if (adev->mmhub.funcs->query_ras_error_count)
 802                         adev->mmhub.funcs->query_ras_error_count(adev, &err_data);
 803
 804                 if (adev->mmhub.funcs->query_ras_error_status)
 805                         adev->mmhub.funcs->query_ras_error_status(adev);
 806                 break;
 807         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 808                 if (adev->nbio.funcs->query_ras_error_count)
 809                         adev->nbio.funcs->query_ras_error_count(adev, &err_data);
 810                 break;
 811         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 812                 amdgpu_xgmi_query_ras_error_count(adev, &err_data);
 813                 break;
 814         default:
 815                 break;
 816         }
 817
 818         obj->err_data.ue_count += err_data.ue_count;
 819         obj->err_data.ce_count += err_data.ce_count;
 820
 821         info->ue_count = obj->err_data.ue_count;
 822         info->ce_count = obj->err_data.ce_count;
 823
 824         if (err_data.ce_count) {
 825                 dev_info(adev->dev, "%ld correctable hardware errors "
 826                                         "detected in %s block, no user "
 827                                         "action is needed.\n",
 828                                         obj->err_data.ce_count,
 829                                         ras_block_str(info->head.block));
 830         }
 831         if (err_data.ue_count) {
 832                 dev_info(adev->dev, "%ld uncorrectable hardware errors "
 833                                         "detected in %s block\n",
 834                                         obj->err_data.ue_count,
 835                                         ras_block_str(info->head.block));
 836         }
 837
 838         return 0;
 839 }
 840
 841 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
 842                 enum amdgpu_ras_block block)
 843 {
 844         if (!amdgpu_ras_is_supported(adev, block))
 845                 return -EINVAL;
 846
 847         switch (block) {
 848         case AMDGPU_RAS_BLOCK__GFX:
 849                 if (adev->gfx.funcs->reset_ras_error_count)
 850                         adev->gfx.funcs->reset_ras_error_count(adev);
 851
 852                 if (adev->gfx.funcs->reset_ras_error_status)
 853                         adev->gfx.funcs->reset_ras_error_status(adev);
 854                 break;
 855         case AMDGPU_RAS_BLOCK__MMHUB:
 856                 if (adev->mmhub.funcs->reset_ras_error_count)
 857                         adev->mmhub.funcs->reset_ras_error_count(adev);
 858                 break;
 859         case AMDGPU_RAS_BLOCK__SDMA:
 860                 if (adev->sdma.funcs->reset_ras_error_count)
 861                         adev->sdma.funcs->reset_ras_error_count(adev);
 862                 break;
 863         default:
 864                 break;
 865         }
 866
 867         return 0;
 868 }
 869
 870 /* Trigger XGMI/WAFL error */
 871 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
 872                                  struct ta_ras_trigger_error_input *block_info)
 873 {
 874         int ret;
 875
 876         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
 877                 dev_warn(adev->dev, "Failed to disallow df cstate");
 878
 879         if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
 880                 dev_warn(adev->dev, "Failed to disallow XGMI power down");
 881
 882         ret = psp_ras_trigger_error(&adev->psp, block_info);
 883
 884         if (amdgpu_ras_intr_triggered())
 885                 return ret;
 886
 887         if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
 888                 dev_warn(adev->dev, "Failed to allow XGMI power down");
 889
 890         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
 891                 dev_warn(adev->dev, "Failed to allow df cstate");
 892
 893         return ret;
 894 }
 895
 896 /* wrapper of psp_ras_trigger_error */
 897 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 898                 struct ras_inject_if *info)
 899 {
 900         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 901         struct ta_ras_trigger_error_input block_info = {
 902                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
 903                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
 904                 .sub_block_index = info->head.sub_block_index,
 905                 .address = info->address,
 906                 .value = info->value,
 907         };
 908         int ret = 0;
 909
 910         if (!obj)
 911                 return -EINVAL;
 912
 913         /* Calculate XGMI relative offset */
 914         if (adev->gmc.xgmi.num_physical_nodes > 1) {
 915                 block_info.address =
 916                         amdgpu_xgmi_get_relative_phy_addr(adev,
 917                                                           block_info.address);
 918         }
 919
 920         switch (info->head.block) {
 921         case AMDGPU_RAS_BLOCK__GFX:
 922                 if (adev->gfx.funcs->ras_error_inject)
 923                         ret = adev->gfx.funcs->ras_error_inject(adev, info);
 924                 else
 925                         ret = -EINVAL;
 926                 break;
 927         case AMDGPU_RAS_BLOCK__UMC:
 928         case AMDGPU_RAS_BLOCK__MMHUB:
 929         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 930                 ret = psp_ras_trigger_error(&adev->psp, &block_info);
 931                 break;
 932         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 933                 ret = amdgpu_ras_error_inject_xgmi(adev, &block_info);
 934                 break;
 935         default:
 936                 dev_info(adev->dev, "%s error injection is not supported yet\n",
 937                          ras_block_str(info->head.block));
 938                 ret = -EINVAL;
 939         }
 940
 941         amdgpu_ras_parse_status_code(adev,
 942                                      "inject",
 943                                      ras_block_str(info->head.block),
 944                                      (enum ta_ras_status)ret);
 945
 946         return ret;
 947 }
 948
 949 /* get the total error counts on all IPs */
 950 unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
 951                 bool is_ce)
 952 {
 953         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 954         struct ras_manager *obj;
 955         struct ras_err_data data = {0, 0};
 956
 957         if (!adev->ras_features || !con)
 958                 return 0;
 959
 960         list_for_each_entry(obj, &con->head, node) {
 961                 struct ras_query_if info = {
 962                         .head = obj->head,
 963                 };
 964
 965                 if (amdgpu_ras_query_error_status(adev, &info))
 966                         return 0;
 967
 968                 data.ce_count += info.ce_count;
 969                 data.ue_count += info.ue_count;
 970         }
 971
 972         return is_ce ? data.ce_count : data.ue_count;
 973 }
 974 /* query/inject/cure end */
 975
 976
 977 /* sysfs begin */
 978
 979 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
 980                 struct ras_badpage **bps, unsigned int *count);
 981
 982 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
 983 {
 984         switch (flags) {
 985         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
 986                 return "R";
 987         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
 988                 return "P";
 989         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
 990         default:
 991                 return "F";
 992         }
 993 }
 994
 995 /**
 996  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
 997  *
 998  * It allows user to read the bad pages of vram on the gpu through
 999  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1000  *
1001  * It outputs multiple lines, and each line stands for one gpu page.
1002  *
1003  * The format of one line is below,
1004  * gpu pfn : gpu page size : flags
1005  *
1006  * gpu pfn and gpu page size are printed in hex format.
1007  * flags can be one of below character,
1008  *
1009  * R: reserved, this gpu page is reserved and not able to use.
1010  *
1011  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1012  * in next window of page_reserve.
1013  *
1014  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1015  *
1016  * Examples:
1017  *
1018  * .. code-block:: bash
1019  *
1020  *      0x00000001 : 0x00001000 : R
1021  *      0x00000002 : 0x00001000 : P
1022  *
1023  */
1024
1025 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1026                 struct kobject *kobj, struct bin_attribute *attr,
1027                 char *buf, loff_t ppos, size_t count)
1028 {
1029         struct amdgpu_ras *con =
1030                 container_of(attr, struct amdgpu_ras, badpages_attr);
1031         struct amdgpu_device *adev = con->adev;
1032         const unsigned int element_size =
1033                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1034         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1035         unsigned int end = div64_ul(ppos + count - 1, element_size);
1036         ssize_t s = 0;
1037         struct ras_badpage *bps = NULL;
1038         unsigned int bps_count = 0;
1039
1040         memset(buf, 0, count);
1041
1042         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1043                 return 0;
1044
1045         for (; start < end && start < bps_count; start++)
1046                 s += scnprintf(&buf[s], element_size + 1,
1047                                 "0x%08x : 0x%08x : %1s\n",
1048                                 bps[start].bp,
1049                                 bps[start].size,
1050                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1051
1052         kfree(bps);
1053
1054         return s;
1055 }
1056
1057 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1058                 struct device_attribute *attr, char *buf)
1059 {
1060         struct amdgpu_ras *con =
1061                 container_of(attr, struct amdgpu_ras, features_attr);
1062
1063         return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1064 }
1065
1066 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1067 {
1068         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1069
1070         sysfs_remove_file_from_group(&adev->dev->kobj,
1071                                 &con->badpages_attr.attr,
1072                                 RAS_FS_NAME);
1073 }
1074
1075 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1076 {
1077         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1078         struct attribute *attrs[] = {
1079                 &con->features_attr.attr,
1080                 NULL
1081         };
1082         struct attribute_group group = {
1083                 .name = RAS_FS_NAME,
1084                 .attrs = attrs,
1085         };
1086
1087         sysfs_remove_group(&adev->dev->kobj, &group);
1088
1089         return 0;
1090 }
1091
1092 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1093                 struct ras_fs_if *head)
1094 {
1095         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1096
1097         if (!obj || obj->attr_inuse)
1098                 return -EINVAL;
1099
1100         get_obj(obj);
1101
1102         memcpy(obj->fs_data.sysfs_name,
1103                         head->sysfs_name,
1104                         sizeof(obj->fs_data.sysfs_name));
1105
1106         obj->sysfs_attr = (struct device_attribute){
1107                 .attr = {
1108                         .name = obj->fs_data.sysfs_name,
1109                         .mode = S_IRUGO,
1110                 },
1111                         .show = amdgpu_ras_sysfs_read,
1112         };
1113         sysfs_attr_init(&obj->sysfs_attr.attr);
1114
1115         if (sysfs_add_file_to_group(&adev->dev->kobj,
1116                                 &obj->sysfs_attr.attr,
1117                                 RAS_FS_NAME)) {
1118                 put_obj(obj);
1119                 return -EINVAL;
1120         }
1121
1122         obj->attr_inuse = 1;
1123
1124         return 0;
1125 }
1126
1127 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1128                 struct ras_common_if *head)
1129 {
1130         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1131
1132         if (!obj || !obj->attr_inuse)
1133                 return -EINVAL;
1134
1135         sysfs_remove_file_from_group(&adev->dev->kobj,
1136                                 &obj->sysfs_attr.attr,
1137                                 RAS_FS_NAME);
1138         obj->attr_inuse = 0;
1139         put_obj(obj);
1140
1141         return 0;
1142 }
1143
1144 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1145 {
1146         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1147         struct ras_manager *obj, *tmp;
1148
1149         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1150                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1151         }
1152
1153         if (amdgpu_bad_page_threshold != 0)
1154                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1155
1156         amdgpu_ras_sysfs_remove_feature_node(adev);
1157
1158         return 0;
1159 }
1160 /* sysfs end */
1161
1162 /**
1163  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1164  *
1165  * Normally when there is an uncorrectable error, the driver will reset
1166  * the GPU to recover.  However, in the event of an unrecoverable error,
1167  * the driver provides an interface to reboot the system automatically
1168  * in that event.
1169  *
1170  * The following file in debugfs provides that interface:
1171  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1172  *
1173  * Usage:
1174  *
1175  * .. code-block:: bash
1176  *
1177  *      echo true > .../ras/auto_reboot
1178  *
1179  */
1180 /* debugfs begin */
1181 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1182 {
1183         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1184         struct dentry *dir;
1185         struct drm_minor *minor = adev_to_drm(adev)->primary;
1186
1187         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1188         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1189                             &amdgpu_ras_debugfs_ctrl_ops);
1190         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1191                             &amdgpu_ras_debugfs_eeprom_ops);
1192
1193         /*
1194          * After one uncorrectable error happens, usually GPU recovery will
1195          * be scheduled. But due to the known problem in GPU recovery failing
1196          * to bring GPU back, below interface provides one direct way to
1197          * user to reboot system automatically in such case within
1198          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1199          * will never be called.
1200          */
1201         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1202
1203         /*
1204          * User could set this not to clean up hardware's error count register
1205          * of RAS IPs during ras recovery.
1206          */
1207         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1208                             &con->disable_ras_err_cnt_harvest);
1209         return dir;
1210 }
1211
1212 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1213                                       struct ras_fs_if *head,
1214                                       struct dentry *dir)
1215 {
1216         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1217
1218         if (!obj || !dir)
1219                 return;
1220
1221         get_obj(obj);
1222
1223         memcpy(obj->fs_data.debugfs_name,
1224                         head->debugfs_name,
1225                         sizeof(obj->fs_data.debugfs_name));
1226
1227         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1228                             obj, &amdgpu_ras_debugfs_ops);
1229 }
1230
1231 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1232 {
1233         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1234         struct dentry *dir;
1235         struct ras_manager *obj;
1236         struct ras_fs_if fs_info;
1237
1238         /*
1239          * it won't be called in resume path, no need to check
1240          * suspend and gpu reset status
1241          */
1242         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1243                 return;
1244
1245         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1246
1247         list_for_each_entry(obj, &con->head, node) {
1248                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1249                         (obj->attr_inuse == 1)) {
1250                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1251                                         ras_block_str(obj->head.block));
1252                         fs_info.head = obj->head;
1253                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1254                 }
1255         }
1256 }
1257
1258 /* debugfs end */
1259
1260 /* ras fs */
1261 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1262                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1263 static DEVICE_ATTR(features, S_IRUGO,
1264                 amdgpu_ras_sysfs_features_read, NULL);
1265 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1266 {
1267         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1268         struct attribute_group group = {
1269                 .name = RAS_FS_NAME,
1270         };
1271         struct attribute *attrs[] = {
1272                 &con->features_attr.attr,
1273                 NULL
1274         };
1275         struct bin_attribute *bin_attrs[] = {
1276                 NULL,
1277                 NULL,
1278         };
1279         int r;
1280
1281         /* add features entry */
1282         con->features_attr = dev_attr_features;
1283         group.attrs = attrs;
1284         sysfs_attr_init(attrs[0]);
1285
1286         if (amdgpu_bad_page_threshold != 0) {
1287                 /* add bad_page_features entry */
1288                 bin_attr_gpu_vram_bad_pages.private = NULL;
1289                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1290                 bin_attrs[0] = &con->badpages_attr;
1291                 group.bin_attrs = bin_attrs;
1292                 sysfs_bin_attr_init(bin_attrs[0]);
1293         }
1294
1295         r = sysfs_create_group(&adev->dev->kobj, &group);
1296         if (r)
1297                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1298
1299         return 0;
1300 }
1301
1302 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1303 {
1304         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1305         struct ras_manager *con_obj, *ip_obj, *tmp;
1306
1307         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1308                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1309                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1310                         if (ip_obj)
1311                                 put_obj(ip_obj);
1312                 }
1313         }
1314
1315         amdgpu_ras_sysfs_remove_all(adev);
1316         return 0;
1317 }
1318 /* ras fs end */
1319
1320 /* ih begin */
1321 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1322 {
1323         struct ras_ih_data *data = &obj->ih_data;
1324         struct amdgpu_iv_entry entry;
1325         int ret;
1326         struct ras_err_data err_data = {0, 0, 0, NULL};
1327
1328         while (data->rptr != data->wptr) {
1329                 rmb();
1330                 memcpy(&entry, &data->ring[data->rptr],
1331                                 data->element_size);
1332
1333                 wmb();
1334                 data->rptr = (data->aligned_element_size +
1335                                 data->rptr) % data->ring_size;
1336
1337                 /* Let IP handle its data, maybe we need get the output
1338                  * from the callback to udpate the error type/count, etc
1339                  */
1340                 if (data->cb) {
1341                         ret = data->cb(obj->adev, &err_data, &entry);
1342                         /* ue will trigger an interrupt, and in that case
1343                          * we need do a reset to recovery the whole system.
1344                          * But leave IP do that recovery, here we just dispatch
1345                          * the error.
1346                          */
1347                         if (ret == AMDGPU_RAS_SUCCESS) {
1348                                 /* these counts could be left as 0 if
1349                                  * some blocks do not count error number
1350                                  */
1351                                 obj->err_data.ue_count += err_data.ue_count;
1352                                 obj->err_data.ce_count += err_data.ce_count;
1353                         }
1354                 }
1355         }
1356 }
1357
1358 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1359 {
1360         struct ras_ih_data *data =
1361                 container_of(work, struct ras_ih_data, ih_work);
1362         struct ras_manager *obj =
1363                 container_of(data, struct ras_manager, ih_data);
1364
1365         amdgpu_ras_interrupt_handler(obj);
1366 }
1367
1368 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1369                 struct ras_dispatch_if *info)
1370 {
1371         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1372         struct ras_ih_data *data = &obj->ih_data;
1373
1374         if (!obj)
1375                 return -EINVAL;
1376
1377         if (data->inuse == 0)
1378                 return 0;
1379
1380         /* Might be overflow... */
1381         memcpy(&data->ring[data->wptr], info->entry,
1382                         data->element_size);
1383
1384         wmb();
1385         data->wptr = (data->aligned_element_size +
1386                         data->wptr) % data->ring_size;
1387
1388         schedule_work(&data->ih_work);
1389
1390         return 0;
1391 }
1392
1393 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1394                 struct ras_ih_if *info)
1395 {
1396         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1397         struct ras_ih_data *data;
1398
1399         if (!obj)
1400                 return -EINVAL;
1401
1402         data = &obj->ih_data;
1403         if (data->inuse == 0)
1404                 return 0;
1405
1406         cancel_work_sync(&data->ih_work);
1407
1408         kfree(data->ring);
1409         memset(data, 0, sizeof(*data));
1410         put_obj(obj);
1411
1412         return 0;
1413 }
1414
1415 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1416                 struct ras_ih_if *info)
1417 {
1418         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1419         struct ras_ih_data *data;
1420
1421         if (!obj) {
1422                 /* in case we registe the IH before enable ras feature */
1423                 obj = amdgpu_ras_create_obj(adev, &info->head);
1424                 if (!obj)
1425                         return -EINVAL;
1426         } else
1427                 get_obj(obj);
1428
1429         data = &obj->ih_data;
1430         /* add the callback.etc */
1431         *data = (struct ras_ih_data) {
1432                 .inuse = 0,
1433                 .cb = info->cb,
1434                 .element_size = sizeof(struct amdgpu_iv_entry),
1435                 .rptr = 0,
1436                 .wptr = 0,
1437         };
1438
1439         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1440
1441         data->aligned_element_size = ALIGN(data->element_size, 8);
1442         /* the ring can store 64 iv entries. */
1443         data->ring_size = 64 * data->aligned_element_size;
1444         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1445         if (!data->ring) {
1446                 put_obj(obj);
1447                 return -ENOMEM;
1448         }
1449
1450         /* IH is ready */
1451         data->inuse = 1;
1452
1453         return 0;
1454 }
1455
1456 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1457 {
1458         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1459         struct ras_manager *obj, *tmp;
1460
1461         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1462                 struct ras_ih_if info = {
1463                         .head = obj->head,
1464                 };
1465                 amdgpu_ras_interrupt_remove_handler(adev, &info);
1466         }
1467
1468         return 0;
1469 }
1470 /* ih end */
1471
1472 /* traversal all IPs except NBIO to query error counter */
1473 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1474 {
1475         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1476         struct ras_manager *obj;
1477
1478         if (!adev->ras_features || !con)
1479                 return;
1480
1481         list_for_each_entry(obj, &con->head, node) {
1482                 struct ras_query_if info = {
1483                         .head = obj->head,
1484                 };
1485
1486                 /*
1487                  * PCIE_BIF IP has one different isr by ras controller
1488                  * interrupt, the specific ras counter query will be
1489                  * done in that isr. So skip such block from common
1490                  * sync flood interrupt isr calling.
1491                  */
1492                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1493                         continue;
1494
1495                 amdgpu_ras_query_error_status(adev, &info);
1496         }
1497 }
1498
1499 /* Parse RdRspStatus and WrRspStatus */
1500 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1501                                           struct ras_query_if *info)
1502 {
1503         /*
1504          * Only two block need to query read/write
1505          * RspStatus at current state
1506          */
1507         switch (info->head.block) {
1508         case AMDGPU_RAS_BLOCK__GFX:
1509                 if (adev->gfx.funcs->query_ras_error_status)
1510                         adev->gfx.funcs->query_ras_error_status(adev);
1511                 break;
1512         case AMDGPU_RAS_BLOCK__MMHUB:
1513                 if (adev->mmhub.funcs->query_ras_error_status)
1514                         adev->mmhub.funcs->query_ras_error_status(adev);
1515                 break;
1516         default:
1517                 break;
1518         }
1519 }
1520
1521 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1522 {
1523         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1524         struct ras_manager *obj;
1525
1526         if (!adev->ras_features || !con)
1527                 return;
1528
1529         list_for_each_entry(obj, &con->head, node) {
1530                 struct ras_query_if info = {
1531                         .head = obj->head,
1532                 };
1533
1534                 amdgpu_ras_error_status_query(adev, &info);
1535         }
1536 }
1537
1538 /* recovery begin */
1539
1540 /* return 0 on success.
1541  * caller need free bps.
1542  */
1543 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1544                 struct ras_badpage **bps, unsigned int *count)
1545 {
1546         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1547         struct ras_err_handler_data *data;
1548         int i = 0;
1549         int ret = 0, status;
1550
1551         if (!con || !con->eh_data || !bps || !count)
1552                 return -EINVAL;
1553
1554         mutex_lock(&con->recovery_lock);
1555         data = con->eh_data;
1556         if (!data || data->count == 0) {
1557                 *bps = NULL;
1558                 ret = -EINVAL;
1559                 goto out;
1560         }
1561
1562         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1563         if (!*bps) {
1564                 ret = -ENOMEM;
1565                 goto out;
1566         }
1567
1568         for (; i < data->count; i++) {
1569                 (*bps)[i] = (struct ras_badpage){
1570                         .bp = data->bps[i].retired_page,
1571                         .size = AMDGPU_GPU_PAGE_SIZE,
1572                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1573                 };
1574                 status = amdgpu_vram_mgr_query_page_status(
1575                                 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1576                                 data->bps[i].retired_page);
1577                 if (status == -EBUSY)
1578                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1579                 else if (status == -ENOENT)
1580                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1581         }
1582
1583         *count = data->count;
1584 out:
1585         mutex_unlock(&con->recovery_lock);
1586         return ret;
1587 }
1588
1589 static void amdgpu_ras_do_recovery(struct work_struct *work)
1590 {
1591         struct amdgpu_ras *ras =
1592                 container_of(work, struct amdgpu_ras, recovery_work);
1593         struct amdgpu_device *remote_adev = NULL;
1594         struct amdgpu_device *adev = ras->adev;
1595         struct list_head device_list, *device_list_handle =  NULL;
1596
1597         if (!ras->disable_ras_err_cnt_harvest) {
1598                 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1599
1600                 /* Build list of devices to query RAS related errors */
1601                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1602                         device_list_handle = &hive->device_list;
1603                 } else {
1604                         INIT_LIST_HEAD(&device_list);
1605                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
1606                         device_list_handle = &device_list;
1607                 }
1608
1609                 list_for_each_entry(remote_adev,
1610                                 device_list_handle, gmc.xgmi.head) {
1611                         amdgpu_ras_query_err_status(remote_adev);
1612                         amdgpu_ras_log_on_err_counter(remote_adev);
1613                 }
1614
1615                 amdgpu_put_xgmi_hive(hive);
1616         }
1617
1618         if (amdgpu_device_should_recover_gpu(ras->adev))
1619                 amdgpu_device_gpu_recover(ras->adev, NULL);
1620         atomic_set(&ras->in_recovery, 0);
1621 }
1622
1623 /* alloc/realloc bps array */
1624 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1625                 struct ras_err_handler_data *data, int pages)
1626 {
1627         unsigned int old_space = data->count + data->space_left;
1628         unsigned int new_space = old_space + pages;
1629         unsigned int align_space = ALIGN(new_space, 512);
1630         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1631
1632         if (!bps) {
1633                 kfree(bps);
1634                 return -ENOMEM;
1635         }
1636
1637         if (data->bps) {
1638                 memcpy(bps, data->bps,
1639                                 data->count * sizeof(*data->bps));
1640                 kfree(data->bps);
1641         }
1642
1643         data->bps = bps;
1644         data->space_left += align_space - old_space;
1645         return 0;
1646 }
1647
1648 /* it deal with vram only. */
1649 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1650                 struct eeprom_table_record *bps, int pages)
1651 {
1652         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1653         struct ras_err_handler_data *data;
1654         int ret = 0;
1655         uint32_t i;
1656
1657         if (!con || !con->eh_data || !bps || pages <= 0)
1658                 return 0;
1659
1660         mutex_lock(&con->recovery_lock);
1661         data = con->eh_data;
1662         if (!data)
1663                 goto out;
1664
1665         for (i = 0; i < pages; i++) {
1666                 if (amdgpu_ras_check_bad_page_unlock(con,
1667                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1668                         continue;
1669
1670                 if (!data->space_left &&
1671                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1672                         ret = -ENOMEM;
1673                         goto out;
1674                 }
1675
1676                 amdgpu_vram_mgr_reserve_range(
1677                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1678                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1679                         AMDGPU_GPU_PAGE_SIZE);
1680
1681                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1682                 data->count++;
1683                 data->space_left--;
1684         }
1685 out:
1686         mutex_unlock(&con->recovery_lock);
1687
1688         return ret;
1689 }
1690
1691 /*
1692  * write error record array to eeprom, the function should be
1693  * protected by recovery_lock
1694  */
1695 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1696 {
1697         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1698         struct ras_err_handler_data *data;
1699         struct amdgpu_ras_eeprom_control *control;
1700         int save_count;
1701
1702         if (!con || !con->eh_data)
1703                 return 0;
1704
1705         control = &con->eeprom_control;
1706         data = con->eh_data;
1707         save_count = data->count - control->num_recs;
1708         /* only new entries are saved */
1709         if (save_count > 0) {
1710                 if (amdgpu_ras_eeprom_process_recods(control,
1711                                                         &data->bps[control->num_recs],
1712                                                         true,
1713                                                         save_count)) {
1714                         dev_err(adev->dev, "Failed to save EEPROM table data!");
1715                         return -EIO;
1716                 }
1717
1718                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
1719         }
1720
1721         return 0;
1722 }
1723
1724 /*
1725  * read error record array in eeprom and reserve enough space for
1726  * storing new bad pages
1727  */
1728 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1729 {
1730         struct amdgpu_ras_eeprom_control *control =
1731                                         &adev->psp.ras.ras->eeprom_control;
1732         struct eeprom_table_record *bps = NULL;
1733         int ret = 0;
1734
1735         /* no bad page record, skip eeprom access */
1736         if (!control->num_recs || (amdgpu_bad_page_threshold == 0))
1737                 return ret;
1738
1739         bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL);
1740         if (!bps)
1741                 return -ENOMEM;
1742
1743         if (amdgpu_ras_eeprom_process_recods(control, bps, false,
1744                 control->num_recs)) {
1745                 dev_err(adev->dev, "Failed to load EEPROM table records!");
1746                 ret = -EIO;
1747                 goto out;
1748         }
1749
1750         ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
1751
1752 out:
1753         kfree(bps);
1754         return ret;
1755 }
1756
1757 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
1758                                 uint64_t addr)
1759 {
1760         struct ras_err_handler_data *data = con->eh_data;
1761         int i;
1762
1763         addr >>= AMDGPU_GPU_PAGE_SHIFT;
1764         for (i = 0; i < data->count; i++)
1765                 if (addr == data->bps[i].retired_page)
1766                         return true;
1767
1768         return false;
1769 }
1770
1771 /*
1772  * check if an address belongs to bad page
1773  *
1774  * Note: this check is only for umc block
1775  */
1776 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
1777                                 uint64_t addr)
1778 {
1779         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1780         bool ret = false;
1781
1782         if (!con || !con->eh_data)
1783                 return ret;
1784
1785         mutex_lock(&con->recovery_lock);
1786         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
1787         mutex_unlock(&con->recovery_lock);
1788         return ret;
1789 }
1790
1791 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
1792                                         uint32_t max_length)
1793 {
1794         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1795         int tmp_threshold = amdgpu_bad_page_threshold;
1796         u64 val;
1797
1798         /*
1799          * Justification of value bad_page_cnt_threshold in ras structure
1800          *
1801          * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
1802          * in eeprom, and introduce two scenarios accordingly.
1803          *
1804          * Bad page retirement enablement:
1805          *    - If amdgpu_bad_page_threshold = -1,
1806          *      bad_page_cnt_threshold = typical value by formula.
1807          *
1808          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
1809          *      max record length in eeprom, use it directly.
1810          *
1811          * Bad page retirement disablement:
1812          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
1813          *      functionality is disabled, and bad_page_cnt_threshold will
1814          *      take no effect.
1815          */
1816
1817         if (tmp_threshold < -1)
1818                 tmp_threshold = -1;
1819         else if (tmp_threshold > max_length)
1820                 tmp_threshold = max_length;
1821
1822         if (tmp_threshold == -1) {
1823                 val = adev->gmc.mc_vram_size;
1824                 do_div(val, RAS_BAD_PAGE_RATE);
1825                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
1826                                                 max_length);
1827         } else {
1828                 con->bad_page_cnt_threshold = tmp_threshold;
1829         }
1830 }
1831
1832 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1833 {
1834         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1835         struct ras_err_handler_data **data;
1836         uint32_t max_eeprom_records_len = 0;
1837         bool exc_err_limit = false;
1838         int ret;
1839
1840         if (adev->ras_features && con)
1841                 data = &con->eh_data;
1842         else
1843                 return 0;
1844
1845         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
1846         if (!*data) {
1847                 ret = -ENOMEM;
1848                 goto out;
1849         }
1850
1851         mutex_init(&con->recovery_lock);
1852         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1853         atomic_set(&con->in_recovery, 0);
1854         con->adev = adev;
1855
1856         max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length();
1857         amdgpu_ras_validate_threshold(adev, max_eeprom_records_len);
1858
1859         /* Todo: During test the SMU might fail to read the eeprom through I2C
1860          * when the GPU is pending on XGMI reset during probe time
1861          * (Mostly after second bus reset), skip it now
1862          */
1863         if (adev->gmc.xgmi.pending_reset)
1864                 return 0;
1865         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
1866         /*
1867          * This calling fails when exc_err_limit is true or
1868          * ret != 0.
1869          */
1870         if (exc_err_limit || ret)
1871                 goto free;
1872
1873         if (con->eeprom_control.num_recs) {
1874                 ret = amdgpu_ras_load_bad_pages(adev);
1875                 if (ret)
1876                         goto free;
1877         }
1878
1879         return 0;
1880
1881 free:
1882         kfree((*data)->bps);
1883         kfree(*data);
1884         con->eh_data = NULL;
1885 out:
1886         dev_warn(adev->dev, "Failed to initialize ras recovery!\n");
1887
1888         /*
1889          * Except error threshold exceeding case, other failure cases in this
1890          * function would not fail amdgpu driver init.
1891          */
1892         if (!exc_err_limit)
1893                 ret = 0;
1894         else
1895                 ret = -EINVAL;
1896
1897         return ret;
1898 }
1899
1900 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
1901 {
1902         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1903         struct ras_err_handler_data *data = con->eh_data;
1904
1905         /* recovery_init failed to init it, fini is useless */
1906         if (!data)
1907                 return 0;
1908
1909         cancel_work_sync(&con->recovery_work);
1910
1911         mutex_lock(&con->recovery_lock);
1912         con->eh_data = NULL;
1913         kfree(data->bps);
1914         kfree(data);
1915         mutex_unlock(&con->recovery_lock);
1916
1917         return 0;
1918 }
1919 /* recovery end */
1920
1921 /* return 0 if ras will reset gpu and repost.*/
1922 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
1923                 unsigned int block)
1924 {
1925         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1926
1927         if (!ras)
1928                 return -EINVAL;
1929
1930         ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET;
1931         return 0;
1932 }
1933
1934 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
1935 {
1936         return adev->asic_type == CHIP_VEGA10 ||
1937                 adev->asic_type == CHIP_VEGA20 ||
1938                 adev->asic_type == CHIP_ARCTURUS ||
1939                 adev->asic_type == CHIP_SIENNA_CICHLID;
1940 }
1941
1942 /*
1943  * check hardware's ras ability which will be saved in hw_supported.
1944  * if hardware does not support ras, we can skip some ras initializtion and
1945  * forbid some ras operations from IP.
1946  * if software itself, say boot parameter, limit the ras ability. We still
1947  * need allow IP do some limited operations, like disable. In such case,
1948  * we have to initialize ras as normal. but need check if operation is
1949  * allowed or not in each function.
1950  */
1951 static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
1952                 uint32_t *hw_supported, uint32_t *supported)
1953 {
1954         *hw_supported = 0;
1955         *supported = 0;
1956
1957         if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
1958             !amdgpu_ras_asic_supported(adev))
1959                 return;
1960
1961         if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
1962                 dev_info(adev->dev, "MEM ECC is active.\n");
1963                 *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC |
1964                                 1 << AMDGPU_RAS_BLOCK__DF);
1965         } else
1966                 dev_info(adev->dev, "MEM ECC is not presented.\n");
1967
1968         if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
1969                 dev_info(adev->dev, "SRAM ECC is active.\n");
1970                 *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
1971                                 1 << AMDGPU_RAS_BLOCK__DF);
1972         } else
1973                 dev_info(adev->dev, "SRAM ECC is not presented.\n");
1974
1975         /* hw_supported needs to be aligned with RAS block mask. */
1976         *hw_supported &= AMDGPU_RAS_BLOCK_MASK;
1977
1978         *supported = amdgpu_ras_enable == 0 ?
1979                         0 : *hw_supported & amdgpu_ras_mask;
1980         adev->ras_features = *supported;
1981 }
1982
1983 int amdgpu_ras_init(struct amdgpu_device *adev)
1984 {
1985         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1986         int r;
1987
1988         if (con)
1989                 return 0;
1990
1991         con = kmalloc(sizeof(struct amdgpu_ras) +
1992                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
1993                         GFP_KERNEL|__GFP_ZERO);
1994         if (!con)
1995                 return -ENOMEM;
1996
1997         con->objs = (struct ras_manager *)(con + 1);
1998
1999         amdgpu_ras_set_context(adev, con);
2000
2001         amdgpu_ras_check_supported(adev, &con->hw_supported,
2002                         &con->supported);
2003         if (!con->hw_supported || (adev->asic_type == CHIP_VEGA10)) {
2004                 /* set gfx block ras context feature for VEGA20 Gaming
2005                  * send ras disable cmd to ras ta during ras late init.
2006                  */
2007                 if (!adev->ras_features && adev->asic_type == CHIP_VEGA20) {
2008                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2009
2010                         return 0;
2011                 }
2012
2013                 r = 0;
2014                 goto release_con;
2015         }
2016
2017         con->features = 0;
2018         INIT_LIST_HEAD(&con->head);
2019         /* Might need get this flag from vbios. */
2020         con->flags = RAS_DEFAULT_FLAGS;
2021
2022         if (adev->nbio.funcs->init_ras_controller_interrupt) {
2023                 r = adev->nbio.funcs->init_ras_controller_interrupt(adev);
2024                 if (r)
2025                         goto release_con;
2026         }
2027
2028         if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) {
2029                 r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev);
2030                 if (r)
2031                         goto release_con;
2032         }
2033
2034         if (amdgpu_ras_fs_init(adev)) {
2035                 r = -EINVAL;
2036                 goto release_con;
2037         }
2038
2039         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2040                         "hardware ability[%x] ras_mask[%x]\n",
2041                         con->hw_supported, con->supported);
2042         return 0;
2043 release_con:
2044         amdgpu_ras_set_context(adev, NULL);
2045         kfree(con);
2046
2047         return r;
2048 }
2049
2050 /* helper function to handle common stuff in ip late init phase */
2051 int amdgpu_ras_late_init(struct amdgpu_device *adev,
2052                          struct ras_common_if *ras_block,
2053                          struct ras_fs_if *fs_info,
2054                          struct ras_ih_if *ih_info)
2055 {
2056         int r;
2057
2058         /* disable RAS feature per IP block if it is not supported */
2059         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2060                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2061                 return 0;
2062         }
2063
2064         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2065         if (r) {
2066                 if (r == -EAGAIN) {
2067                         /* request gpu reset. will run again */
2068                         amdgpu_ras_request_reset_on_boot(adev,
2069                                         ras_block->block);
2070                         return 0;
2071                 } else if (adev->in_suspend || amdgpu_in_reset(adev)) {
2072                         /* in resume phase, if fail to enable ras,
2073                          * clean up all ras fs nodes, and disable ras */
2074                         goto cleanup;
2075                 } else
2076                         return r;
2077         }
2078
2079         /* in resume phase, no need to create ras fs node */
2080         if (adev->in_suspend || amdgpu_in_reset(adev))
2081                 return 0;
2082
2083         if (ih_info->cb) {
2084                 r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
2085                 if (r)
2086                         goto interrupt;
2087         }
2088
2089         r = amdgpu_ras_sysfs_create(adev, fs_info);
2090         if (r)
2091                 goto sysfs;
2092
2093         return 0;
2094 cleanup:
2095         amdgpu_ras_sysfs_remove(adev, ras_block);
2096 sysfs:
2097         if (ih_info->cb)
2098                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2099 interrupt:
2100         amdgpu_ras_feature_enable(adev, ras_block, 0);
2101         return r;
2102 }
2103
2104 /* helper function to remove ras fs node and interrupt handler */
2105 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
2106                           struct ras_common_if *ras_block,
2107                           struct ras_ih_if *ih_info)
2108 {
2109         if (!ras_block || !ih_info)
2110                 return;
2111
2112         amdgpu_ras_sysfs_remove(adev, ras_block);
2113         if (ih_info->cb)
2114                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2115         amdgpu_ras_feature_enable(adev, ras_block, 0);
2116 }
2117
2118 /* do some init work after IP late init as dependence.
2119  * and it runs in resume/gpu reset/booting up cases.
2120  */
2121 void amdgpu_ras_resume(struct amdgpu_device *adev)
2122 {
2123         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2124         struct ras_manager *obj, *tmp;
2125
2126         if (!adev->ras_features || !con) {
2127                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2128                 amdgpu_release_ras_context(adev);
2129
2130                 return;
2131         }
2132
2133         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2134                 /* Set up all other IPs which are not implemented. There is a
2135                  * tricky thing that IP's actual ras error type should be
2136                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2137                  * ERROR_NONE make sense anyway.
2138                  */
2139                 amdgpu_ras_enable_all_features(adev, 1);
2140
2141                 /* We enable ras on all hw_supported block, but as boot
2142                  * parameter might disable some of them and one or more IP has
2143                  * not implemented yet. So we disable them on behalf.
2144                  */
2145                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2146                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2147                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2148                                 /* there should be no any reference. */
2149                                 WARN_ON(alive_obj(obj));
2150                         }
2151                 }
2152         }
2153
2154         if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) {
2155                 con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2156                 /* setup ras obj state as disabled.
2157                  * for init_by_vbios case.
2158                  * if we want to enable ras, just enable it in a normal way.
2159                  * If we want do disable it, need setup ras obj as enabled,
2160                  * then issue another TA disable cmd.
2161                  * See feature_enable_on_boot
2162                  */
2163                 amdgpu_ras_disable_all_features(adev, 1);
2164                 amdgpu_ras_reset_gpu(adev);
2165         }
2166 }
2167
2168 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2169 {
2170         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2171
2172         if (!adev->ras_features || !con)
2173                 return;
2174
2175         amdgpu_ras_disable_all_features(adev, 0);
2176         /* Make sure all ras objects are disabled. */
2177         if (con->features)
2178                 amdgpu_ras_disable_all_features(adev, 1);
2179 }
2180
2181 /* do some fini work before IP fini as dependence */
2182 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2183 {
2184         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2185
2186         if (!adev->ras_features || !con)
2187                 return 0;
2188
2189         /* Need disable ras on all IPs here before ip [hw/sw]fini */
2190         amdgpu_ras_disable_all_features(adev, 0);
2191         amdgpu_ras_recovery_fini(adev);
2192         return 0;
2193 }
2194
2195 int amdgpu_ras_fini(struct amdgpu_device *adev)
2196 {
2197         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2198
2199         if (!adev->ras_features || !con)
2200                 return 0;
2201
2202         amdgpu_ras_fs_fini(adev);
2203         amdgpu_ras_interrupt_remove_all(adev);
2204
2205         WARN(con->features, "Feature mask is not cleared");
2206
2207         if (con->features)
2208                 amdgpu_ras_disable_all_features(adev, 1);
2209
2210         amdgpu_ras_set_context(adev, NULL);
2211         kfree(con);
2212
2213         return 0;
2214 }
2215
2216 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2217 {
2218         uint32_t hw_supported, supported;
2219
2220         amdgpu_ras_check_supported(adev, &hw_supported, &supported);
2221         if (!hw_supported)
2222                 return;
2223
2224         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2225                 dev_info(adev->dev, "uncorrectable hardware error"
2226                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2227
2228                 amdgpu_ras_reset_gpu(adev);
2229         }
2230 }
2231
2232 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2233 {
2234         if (adev->asic_type == CHIP_VEGA20 &&
2235             adev->pm.fw_version <= 0x283400) {
2236                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2237                                 amdgpu_ras_intr_triggered();
2238         }
2239
2240         return false;
2241 }
2242
2243 void amdgpu_release_ras_context(struct amdgpu_device *adev)
2244 {
2245         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2246
2247         if (!con)
2248                 return;
2249
2250         if (!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
2251                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2252                 amdgpu_ras_set_context(adev, NULL);
2253                 kfree(con);
2254         }
2255 }