drivers/spi/spi-fsl-lpspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Freescale i.MX7ULP LPSPI driver
   4 //
   5 // Copyright 2016 Freescale Semiconductor, Inc.
   6 // Copyright 2018 NXP Semiconductors
   7
   8 #include <linux/clk.h>
   9 #include <linux/completion.h>
  10 #include <linux/delay.h>
  11 #include <linux/dmaengine.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/err.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/irq.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/pinctrl/consumer.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma/imx-dma.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/slab.h>
  26 #include <linux/spi/spi.h>
  27 #include <linux/spi/spi_bitbang.h>
  28 #include <linux/types.h>
  29
  30 #define DRIVER_NAME "fsl_lpspi"
  31
  32 #define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */
  33
  34 /* The maximum bytes that edma can transfer once.*/
  35 #define FSL_LPSPI_MAX_EDMA_BYTES  ((1 << 15) - 1)
  36
  37 /* i.MX7ULP LPSPI registers */
  38 #define IMX7ULP_VERID   0x0
  39 #define IMX7ULP_PARAM   0x4
  40 #define IMX7ULP_CR      0x10
  41 #define IMX7ULP_SR      0x14
  42 #define IMX7ULP_IER     0x18
  43 #define IMX7ULP_DER     0x1c
  44 #define IMX7ULP_CFGR0   0x20
  45 #define IMX7ULP_CFGR1   0x24
  46 #define IMX7ULP_DMR0    0x30
  47 #define IMX7ULP_DMR1    0x34
  48 #define IMX7ULP_CCR     0x40
  49 #define IMX7ULP_FCR     0x58
  50 #define IMX7ULP_FSR     0x5c
  51 #define IMX7ULP_TCR     0x60
  52 #define IMX7ULP_TDR     0x64
  53 #define IMX7ULP_RSR     0x70
  54 #define IMX7ULP_RDR     0x74
  55
  56 /* General control register field define */
  57 #define CR_RRF          BIT(9)
  58 #define CR_RTF          BIT(8)
  59 #define CR_RST          BIT(1)
  60 #define CR_MEN          BIT(0)
  61 #define SR_MBF          BIT(24)
  62 #define SR_TCF          BIT(10)
  63 #define SR_FCF          BIT(9)
  64 #define SR_RDF          BIT(1)
  65 #define SR_TDF          BIT(0)
  66 #define IER_TCIE        BIT(10)
  67 #define IER_FCIE        BIT(9)
  68 #define IER_RDIE        BIT(1)
  69 #define IER_TDIE        BIT(0)
  70 #define DER_RDDE        BIT(1)
  71 #define DER_TDDE        BIT(0)
  72 #define CFGR1_PCSCFG    BIT(27)
  73 #define CFGR1_PINCFG    (BIT(24)|BIT(25))
  74 #define CFGR1_PCSPOL    BIT(8)
  75 #define CFGR1_NOSTALL   BIT(3)
  76 #define CFGR1_MASTER    BIT(0)
  77 #define FSR_TXCOUNT     (0xFF)
  78 #define RSR_RXEMPTY     BIT(1)
  79 #define TCR_CPOL        BIT(31)
  80 #define TCR_CPHA        BIT(30)
  81 #define TCR_CONT        BIT(21)
  82 #define TCR_CONTC       BIT(20)
  83 #define TCR_RXMSK       BIT(19)
  84 #define TCR_TXMSK       BIT(18)
  85
  86 struct lpspi_config {
  87         u8 bpw;
  88         u8 chip_select;
  89         u8 prescale;
  90         u16 mode;
  91         u32 speed_hz;
  92 };
  93
  94 struct fsl_lpspi_data {
  95         struct device *dev;
  96         void __iomem *base;
  97         unsigned long base_phys;
  98         struct clk *clk_ipg;
  99         struct clk *clk_per;
 100         bool is_slave;
 101         u32 num_cs;
 102         bool is_only_cs1;
 103         bool is_first_byte;
 104
 105         void *rx_buf;
 106         const void *tx_buf;
 107         void (*tx)(struct fsl_lpspi_data *);
 108         void (*rx)(struct fsl_lpspi_data *);
 109
 110         u32 remain;
 111         u8 watermark;
 112         u8 txfifosize;
 113         u8 rxfifosize;
 114
 115         struct lpspi_config config;
 116         struct completion xfer_done;
 117
 118         bool slave_aborted;
 119
 120         /* DMA */
 121         bool usedma;
 122         struct completion dma_rx_completion;
 123         struct completion dma_tx_completion;
 124 };
 125
 126 static const struct of_device_id fsl_lpspi_dt_ids[] = {
 127         { .compatible = "fsl,imx7ulp-spi", },
 128         { /* sentinel */ }
 129 };
 130 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
 131
 132 #define LPSPI_BUF_RX(type)                                              \
 133 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi)   \
 134 {                                                                       \
 135         unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR);        \
 136                                                                         \
 137         if (fsl_lpspi->rx_buf) {                                        \
 138                 *(type *)fsl_lpspi->rx_buf = val;                       \
 139                 fsl_lpspi->rx_buf += sizeof(type);                      \
 140         }                                                               \
 141 }
 142
 143 #define LPSPI_BUF_TX(type)                                              \
 144 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi)   \
 145 {                                                                       \
 146         type val = 0;                                                   \
 147                                                                         \
 148         if (fsl_lpspi->tx_buf) {                                        \
 149                 val = *(type *)fsl_lpspi->tx_buf;                       \
 150                 fsl_lpspi->tx_buf += sizeof(type);                      \
 151         }                                                               \
 152                                                                         \
 153         fsl_lpspi->remain -= sizeof(type);                              \
 154         writel(val, fsl_lpspi->base + IMX7ULP_TDR);                     \
 155 }
 156
 157 LPSPI_BUF_RX(u8)
 158 LPSPI_BUF_TX(u8)
 159 LPSPI_BUF_RX(u16)
 160 LPSPI_BUF_TX(u16)
 161 LPSPI_BUF_RX(u32)
 162 LPSPI_BUF_TX(u32)
 163
 164 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
 165                               unsigned int enable)
 166 {
 167         writel(enable, fsl_lpspi->base + IMX7ULP_IER);
 168 }
 169
 170 static int fsl_lpspi_bytes_per_word(const int bpw)
 171 {
 172         return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
 173 }
 174
 175 static bool fsl_lpspi_can_dma(struct spi_controller *controller,
 176                               struct spi_device *spi,
 177                               struct spi_transfer *transfer)
 178 {
 179         unsigned int bytes_per_word;
 180
 181         if (!controller->dma_rx)
 182                 return false;
 183
 184         bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
 185
 186         switch (bytes_per_word) {
 187         case 1:
 188         case 2:
 189         case 4:
 190                 break;
 191         default:
 192                 return false;
 193         }
 194
 195         return true;
 196 }
 197
 198 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
 199 {
 200         struct fsl_lpspi_data *fsl_lpspi =
 201                                 spi_controller_get_devdata(controller);
 202         int ret;
 203
 204         ret = pm_runtime_resume_and_get(fsl_lpspi->dev);
 205         if (ret < 0) {
 206                 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
 207                 return ret;
 208         }
 209
 210         return 0;
 211 }
 212
 213 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
 214 {
 215         struct fsl_lpspi_data *fsl_lpspi =
 216                                 spi_controller_get_devdata(controller);
 217
 218         pm_runtime_mark_last_busy(fsl_lpspi->dev);
 219         pm_runtime_put_autosuspend(fsl_lpspi->dev);
 220
 221         return 0;
 222 }
 223
 224 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
 225 {
 226         u8 txfifo_cnt;
 227         u32 temp;
 228
 229         txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
 230
 231         while (txfifo_cnt < fsl_lpspi->txfifosize) {
 232                 if (!fsl_lpspi->remain)
 233                         break;
 234                 fsl_lpspi->tx(fsl_lpspi);
 235                 txfifo_cnt++;
 236         }
 237
 238         if (txfifo_cnt < fsl_lpspi->txfifosize) {
 239                 if (!fsl_lpspi->is_slave) {
 240                         temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
 241                         temp &= ~TCR_CONTC;
 242                         writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
 243                 }
 244
 245                 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
 246         } else
 247                 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
 248 }
 249
 250 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
 251 {
 252         while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
 253                 fsl_lpspi->rx(fsl_lpspi);
 254 }
 255
 256 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
 257 {
 258         u32 temp = 0;
 259
 260         temp |= fsl_lpspi->config.bpw - 1;
 261         temp |= (fsl_lpspi->config.mode & 0x3) << 30;
 262         temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
 263         if (!fsl_lpspi->is_slave) {
 264                 temp |= fsl_lpspi->config.prescale << 27;
 265                 /*
 266                  * Set TCR_CONT will keep SS asserted after current transfer.
 267                  * For the first transfer, clear TCR_CONTC to assert SS.
 268                  * For subsequent transfer, set TCR_CONTC to keep SS asserted.
 269                  */
 270                 if (!fsl_lpspi->usedma) {
 271                         temp |= TCR_CONT;
 272                         if (fsl_lpspi->is_first_byte)
 273                                 temp &= ~TCR_CONTC;
 274                         else
 275                                 temp |= TCR_CONTC;
 276                 }
 277         }
 278         writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
 279
 280         dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
 281 }
 282
 283 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
 284 {
 285         u32 temp;
 286
 287         if (!fsl_lpspi->usedma)
 288                 temp = fsl_lpspi->watermark >> 1 |
 289                        (fsl_lpspi->watermark >> 1) << 16;
 290         else
 291                 temp = fsl_lpspi->watermark >> 1;
 292
 293         writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
 294
 295         dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
 296 }
 297
 298 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
 299 {
 300         struct lpspi_config config = fsl_lpspi->config;
 301         unsigned int perclk_rate, scldiv;
 302         u8 prescale;
 303
 304         perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
 305
 306         if (config.speed_hz > perclk_rate / 2) {
 307                 dev_err(fsl_lpspi->dev,
 308                       "per-clk should be at least two times of transfer speed");
 309                 return -EINVAL;
 310         }
 311
 312         for (prescale = 0; prescale < 8; prescale++) {
 313                 scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2;
 314                 if (scldiv < 256) {
 315                         fsl_lpspi->config.prescale = prescale;
 316                         break;
 317                 }
 318         }
 319
 320         if (scldiv >= 256)
 321                 return -EINVAL;
 322
 323         writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
 324                                         fsl_lpspi->base + IMX7ULP_CCR);
 325
 326         dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n",
 327                 perclk_rate, config.speed_hz, prescale, scldiv);
 328
 329         return 0;
 330 }
 331
 332 static int fsl_lpspi_dma_configure(struct spi_controller *controller)
 333 {
 334         int ret;
 335         enum dma_slave_buswidth buswidth;
 336         struct dma_slave_config rx = {}, tx = {};
 337         struct fsl_lpspi_data *fsl_lpspi =
 338                                 spi_controller_get_devdata(controller);
 339
 340         switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
 341         case 4:
 342                 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
 343                 break;
 344         case 2:
 345                 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
 346                 break;
 347         case 1:
 348                 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
 349                 break;
 350         default:
 351                 return -EINVAL;
 352         }
 353
 354         tx.direction = DMA_MEM_TO_DEV;
 355         tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
 356         tx.dst_addr_width = buswidth;
 357         tx.dst_maxburst = 1;
 358         ret = dmaengine_slave_config(controller->dma_tx, &tx);
 359         if (ret) {
 360                 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
 361                         ret);
 362                 return ret;
 363         }
 364
 365         rx.direction = DMA_DEV_TO_MEM;
 366         rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
 367         rx.src_addr_width = buswidth;
 368         rx.src_maxburst = 1;
 369         ret = dmaengine_slave_config(controller->dma_rx, &rx);
 370         if (ret) {
 371                 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
 372                         ret);
 373                 return ret;
 374         }
 375
 376         return 0;
 377 }
 378
 379 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
 380 {
 381         u32 temp;
 382         int ret;
 383
 384         if (!fsl_lpspi->is_slave) {
 385                 ret = fsl_lpspi_set_bitrate(fsl_lpspi);
 386                 if (ret)
 387                         return ret;
 388         }
 389
 390         fsl_lpspi_set_watermark(fsl_lpspi);
 391
 392         if (!fsl_lpspi->is_slave)
 393                 temp = CFGR1_MASTER;
 394         else
 395                 temp = CFGR1_PINCFG;
 396         if (fsl_lpspi->config.mode & SPI_CS_HIGH)
 397                 temp |= CFGR1_PCSPOL;
 398         writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
 399
 400         temp = readl(fsl_lpspi->base + IMX7ULP_CR);
 401         temp |= CR_RRF | CR_RTF | CR_MEN;
 402         writel(temp, fsl_lpspi->base + IMX7ULP_CR);
 403
 404         temp = 0;
 405         if (fsl_lpspi->usedma)
 406                 temp = DER_TDDE | DER_RDDE;
 407         writel(temp, fsl_lpspi->base + IMX7ULP_DER);
 408
 409         return 0;
 410 }
 411
 412 static int fsl_lpspi_setup_transfer(struct spi_controller *controller,
 413                                      struct spi_device *spi,
 414                                      struct spi_transfer *t)
 415 {
 416         struct fsl_lpspi_data *fsl_lpspi =
 417                                 spi_controller_get_devdata(spi->controller);
 418
 419         if (t == NULL)
 420                 return -EINVAL;
 421
 422         fsl_lpspi->config.mode = spi->mode;
 423         fsl_lpspi->config.bpw = t->bits_per_word;
 424         fsl_lpspi->config.speed_hz = t->speed_hz;
 425         if (fsl_lpspi->is_only_cs1)
 426                 fsl_lpspi->config.chip_select = 1;
 427         else
 428                 fsl_lpspi->config.chip_select = spi->chip_select;
 429
 430         if (!fsl_lpspi->config.speed_hz)
 431                 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
 432         if (!fsl_lpspi->config.bpw)
 433                 fsl_lpspi->config.bpw = spi->bits_per_word;
 434
 435         /* Initialize the functions for transfer */
 436         if (fsl_lpspi->config.bpw <= 8) {
 437                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
 438                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
 439         } else if (fsl_lpspi->config.bpw <= 16) {
 440                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
 441                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
 442         } else {
 443                 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
 444                 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
 445         }
 446
 447         if (t->len <= fsl_lpspi->txfifosize)
 448                 fsl_lpspi->watermark = t->len;
 449         else
 450                 fsl_lpspi->watermark = fsl_lpspi->txfifosize;
 451
 452         if (fsl_lpspi_can_dma(controller, spi, t))
 453                 fsl_lpspi->usedma = true;
 454         else
 455                 fsl_lpspi->usedma = false;
 456
 457         return fsl_lpspi_config(fsl_lpspi);
 458 }
 459
 460 static int fsl_lpspi_slave_abort(struct spi_controller *controller)
 461 {
 462         struct fsl_lpspi_data *fsl_lpspi =
 463                                 spi_controller_get_devdata(controller);
 464
 465         fsl_lpspi->slave_aborted = true;
 466         if (!fsl_lpspi->usedma)
 467                 complete(&fsl_lpspi->xfer_done);
 468         else {
 469                 complete(&fsl_lpspi->dma_tx_completion);
 470                 complete(&fsl_lpspi->dma_rx_completion);
 471         }
 472
 473         return 0;
 474 }
 475
 476 static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
 477 {
 478         struct fsl_lpspi_data *fsl_lpspi =
 479                                 spi_controller_get_devdata(controller);
 480
 481         if (fsl_lpspi->is_slave) {
 482                 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
 483                         fsl_lpspi->slave_aborted) {
 484                         dev_dbg(fsl_lpspi->dev, "interrupted\n");
 485                         return -EINTR;
 486                 }
 487         } else {
 488                 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
 489                         dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
 490                         return -ETIMEDOUT;
 491                 }
 492         }
 493
 494         return 0;
 495 }
 496
 497 static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
 498 {
 499         u32 temp;
 500
 501         if (!fsl_lpspi->usedma) {
 502                 /* Disable all interrupt */
 503                 fsl_lpspi_intctrl(fsl_lpspi, 0);
 504         }
 505
 506         /* W1C for all flags in SR */
 507         temp = 0x3F << 8;
 508         writel(temp, fsl_lpspi->base + IMX7ULP_SR);
 509
 510         /* Clear FIFO and disable module */
 511         temp = CR_RRF | CR_RTF;
 512         writel(temp, fsl_lpspi->base + IMX7ULP_CR);
 513
 514         return 0;
 515 }
 516
 517 static void fsl_lpspi_dma_rx_callback(void *cookie)
 518 {
 519         struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
 520
 521         complete(&fsl_lpspi->dma_rx_completion);
 522 }
 523
 524 static void fsl_lpspi_dma_tx_callback(void *cookie)
 525 {
 526         struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
 527
 528         complete(&fsl_lpspi->dma_tx_completion);
 529 }
 530
 531 static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
 532                                        int size)
 533 {
 534         unsigned long timeout = 0;
 535
 536         /* Time with actual data transfer and CS change delay related to HW */
 537         timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
 538
 539         /* Add extra second for scheduler related activities */
 540         timeout += 1;
 541
 542         /* Double calculated timeout */
 543         return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
 544 }
 545
 546 static int fsl_lpspi_dma_transfer(struct spi_controller *controller,
 547                                 struct fsl_lpspi_data *fsl_lpspi,
 548                                 struct spi_transfer *transfer)
 549 {
 550         struct dma_async_tx_descriptor *desc_tx, *desc_rx;
 551         unsigned long transfer_timeout;
 552         unsigned long timeout;
 553         struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
 554         int ret;
 555
 556         ret = fsl_lpspi_dma_configure(controller);
 557         if (ret)
 558                 return ret;
 559
 560         desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
 561                                 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
 562                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 563         if (!desc_rx)
 564                 return -EINVAL;
 565
 566         desc_rx->callback = fsl_lpspi_dma_rx_callback;
 567         desc_rx->callback_param = (void *)fsl_lpspi;
 568         dmaengine_submit(desc_rx);
 569         reinit_completion(&fsl_lpspi->dma_rx_completion);
 570         dma_async_issue_pending(controller->dma_rx);
 571
 572         desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
 573                                 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
 574                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 575         if (!desc_tx) {
 576                 dmaengine_terminate_all(controller->dma_tx);
 577                 return -EINVAL;
 578         }
 579
 580         desc_tx->callback = fsl_lpspi_dma_tx_callback;
 581         desc_tx->callback_param = (void *)fsl_lpspi;
 582         dmaengine_submit(desc_tx);
 583         reinit_completion(&fsl_lpspi->dma_tx_completion);
 584         dma_async_issue_pending(controller->dma_tx);
 585
 586         fsl_lpspi->slave_aborted = false;
 587
 588         if (!fsl_lpspi->is_slave) {
 589                 transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
 590                                                                transfer->len);
 591
 592                 /* Wait eDMA to finish the data transfer.*/
 593                 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
 594                                                       transfer_timeout);
 595                 if (!timeout) {
 596                         dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
 597                         dmaengine_terminate_all(controller->dma_tx);
 598                         dmaengine_terminate_all(controller->dma_rx);
 599                         fsl_lpspi_reset(fsl_lpspi);
 600                         return -ETIMEDOUT;
 601                 }
 602
 603                 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
 604                                                       transfer_timeout);
 605                 if (!timeout) {
 606                         dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
 607                         dmaengine_terminate_all(controller->dma_tx);
 608                         dmaengine_terminate_all(controller->dma_rx);
 609                         fsl_lpspi_reset(fsl_lpspi);
 610                         return -ETIMEDOUT;
 611                 }
 612         } else {
 613                 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
 614                         fsl_lpspi->slave_aborted) {
 615                         dev_dbg(fsl_lpspi->dev,
 616                                 "I/O Error in DMA TX interrupted\n");
 617                         dmaengine_terminate_all(controller->dma_tx);
 618                         dmaengine_terminate_all(controller->dma_rx);
 619                         fsl_lpspi_reset(fsl_lpspi);
 620                         return -EINTR;
 621                 }
 622
 623                 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
 624                         fsl_lpspi->slave_aborted) {
 625                         dev_dbg(fsl_lpspi->dev,
 626                                 "I/O Error in DMA RX interrupted\n");
 627                         dmaengine_terminate_all(controller->dma_tx);
 628                         dmaengine_terminate_all(controller->dma_rx);
 629                         fsl_lpspi_reset(fsl_lpspi);
 630                         return -EINTR;
 631                 }
 632         }
 633
 634         fsl_lpspi_reset(fsl_lpspi);
 635
 636         return 0;
 637 }
 638
 639 static void fsl_lpspi_dma_exit(struct spi_controller *controller)
 640 {
 641         if (controller->dma_rx) {
 642                 dma_release_channel(controller->dma_rx);
 643                 controller->dma_rx = NULL;
 644         }
 645
 646         if (controller->dma_tx) {
 647                 dma_release_channel(controller->dma_tx);
 648                 controller->dma_tx = NULL;
 649         }
 650 }
 651
 652 static int fsl_lpspi_dma_init(struct device *dev,
 653                               struct fsl_lpspi_data *fsl_lpspi,
 654                               struct spi_controller *controller)
 655 {
 656         int ret;
 657
 658         /* Prepare for TX DMA: */
 659         controller->dma_tx = dma_request_chan(dev, "tx");
 660         if (IS_ERR(controller->dma_tx)) {
 661                 ret = PTR_ERR(controller->dma_tx);
 662                 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
 663                 controller->dma_tx = NULL;
 664                 goto err;
 665         }
 666
 667         /* Prepare for RX DMA: */
 668         controller->dma_rx = dma_request_chan(dev, "rx");
 669         if (IS_ERR(controller->dma_rx)) {
 670                 ret = PTR_ERR(controller->dma_rx);
 671                 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
 672                 controller->dma_rx = NULL;
 673                 goto err;
 674         }
 675
 676         init_completion(&fsl_lpspi->dma_rx_completion);
 677         init_completion(&fsl_lpspi->dma_tx_completion);
 678         controller->can_dma = fsl_lpspi_can_dma;
 679         controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
 680
 681         return 0;
 682 err:
 683         fsl_lpspi_dma_exit(controller);
 684         return ret;
 685 }
 686
 687 static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
 688                                   struct spi_transfer *t)
 689 {
 690         struct fsl_lpspi_data *fsl_lpspi =
 691                                 spi_controller_get_devdata(controller);
 692         int ret;
 693
 694         fsl_lpspi->tx_buf = t->tx_buf;
 695         fsl_lpspi->rx_buf = t->rx_buf;
 696         fsl_lpspi->remain = t->len;
 697
 698         reinit_completion(&fsl_lpspi->xfer_done);
 699         fsl_lpspi->slave_aborted = false;
 700
 701         fsl_lpspi_write_tx_fifo(fsl_lpspi);
 702
 703         ret = fsl_lpspi_wait_for_completion(controller);
 704         if (ret)
 705                 return ret;
 706
 707         fsl_lpspi_reset(fsl_lpspi);
 708
 709         return 0;
 710 }
 711
 712 static int fsl_lpspi_transfer_one(struct spi_controller *controller,
 713                                   struct spi_device *spi,
 714                                   struct spi_transfer *t)
 715 {
 716         struct fsl_lpspi_data *fsl_lpspi =
 717                                         spi_controller_get_devdata(controller);
 718         int ret;
 719
 720         fsl_lpspi->is_first_byte = true;
 721         ret = fsl_lpspi_setup_transfer(controller, spi, t);
 722         if (ret < 0)
 723                 return ret;
 724
 725         fsl_lpspi_set_cmd(fsl_lpspi);
 726         fsl_lpspi->is_first_byte = false;
 727
 728         if (fsl_lpspi->usedma)
 729                 ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
 730         else
 731                 ret = fsl_lpspi_pio_transfer(controller, t);
 732         if (ret < 0)
 733                 return ret;
 734
 735         return 0;
 736 }
 737
 738 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
 739 {
 740         u32 temp_SR, temp_IER;
 741         struct fsl_lpspi_data *fsl_lpspi = dev_id;
 742
 743         temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
 744         fsl_lpspi_intctrl(fsl_lpspi, 0);
 745         temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
 746
 747         fsl_lpspi_read_rx_fifo(fsl_lpspi);
 748
 749         if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
 750                 fsl_lpspi_write_tx_fifo(fsl_lpspi);
 751                 return IRQ_HANDLED;
 752         }
 753
 754         if (temp_SR & SR_MBF ||
 755             readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
 756                 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
 757                 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
 758                 return IRQ_HANDLED;
 759         }
 760
 761         if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
 762                 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
 763                 complete(&fsl_lpspi->xfer_done);
 764                 return IRQ_HANDLED;
 765         }
 766
 767         return IRQ_NONE;
 768 }
 769
 770 #ifdef CONFIG_PM
 771 static int fsl_lpspi_runtime_resume(struct device *dev)
 772 {
 773         struct spi_controller *controller = dev_get_drvdata(dev);
 774         struct fsl_lpspi_data *fsl_lpspi;
 775         int ret;
 776
 777         fsl_lpspi = spi_controller_get_devdata(controller);
 778
 779         ret = clk_prepare_enable(fsl_lpspi->clk_per);
 780         if (ret)
 781                 return ret;
 782
 783         ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
 784         if (ret) {
 785                 clk_disable_unprepare(fsl_lpspi->clk_per);
 786                 return ret;
 787         }
 788
 789         return 0;
 790 }
 791
 792 static int fsl_lpspi_runtime_suspend(struct device *dev)
 793 {
 794         struct spi_controller *controller = dev_get_drvdata(dev);
 795         struct fsl_lpspi_data *fsl_lpspi;
 796
 797         fsl_lpspi = spi_controller_get_devdata(controller);
 798
 799         clk_disable_unprepare(fsl_lpspi->clk_per);
 800         clk_disable_unprepare(fsl_lpspi->clk_ipg);
 801
 802         return 0;
 803 }
 804 #endif
 805
 806 static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
 807 {
 808         struct device *dev = fsl_lpspi->dev;
 809
 810         pm_runtime_enable(dev);
 811         pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT);
 812         pm_runtime_use_autosuspend(dev);
 813
 814         return 0;
 815 }
 816
 817 static int fsl_lpspi_probe(struct platform_device *pdev)
 818 {
 819         struct fsl_lpspi_data *fsl_lpspi;
 820         struct spi_controller *controller;
 821         struct resource *res;
 822         int ret, irq;
 823         u32 temp;
 824         bool is_slave;
 825
 826         is_slave = of_property_read_bool((&pdev->dev)->of_node, "spi-slave");
 827         if (is_slave)
 828                 controller = spi_alloc_slave(&pdev->dev,
 829                                         sizeof(struct fsl_lpspi_data));
 830         else
 831                 controller = spi_alloc_master(&pdev->dev,
 832                                         sizeof(struct fsl_lpspi_data));
 833
 834         if (!controller)
 835                 return -ENOMEM;
 836
 837         platform_set_drvdata(pdev, controller);
 838
 839         fsl_lpspi = spi_controller_get_devdata(controller);
 840         fsl_lpspi->dev = &pdev->dev;
 841         fsl_lpspi->is_slave = is_slave;
 842         fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node,
 843                                                 "fsl,spi-only-use-cs1-sel");
 844         if (of_property_read_u32((&pdev->dev)->of_node, "num-cs",
 845                                  &fsl_lpspi->num_cs))
 846                 fsl_lpspi->num_cs = 1;
 847
 848         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
 849         controller->transfer_one = fsl_lpspi_transfer_one;
 850         controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
 851         controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
 852         controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 853         controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
 854         controller->dev.of_node = pdev->dev.of_node;
 855         controller->bus_num = pdev->id;
 856         controller->num_chipselect = fsl_lpspi->num_cs;
 857         controller->slave_abort = fsl_lpspi_slave_abort;
 858         if (!fsl_lpspi->is_slave)
 859                 controller->use_gpio_descriptors = true;
 860
 861         init_completion(&fsl_lpspi->xfer_done);
 862
 863         fsl_lpspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 864         if (IS_ERR(fsl_lpspi->base)) {
 865                 ret = PTR_ERR(fsl_lpspi->base);
 866                 goto out_controller_put;
 867         }
 868         fsl_lpspi->base_phys = res->start;
 869
 870         irq = platform_get_irq(pdev, 0);
 871         if (irq < 0) {
 872                 ret = irq;
 873                 goto out_controller_put;
 874         }
 875
 876         ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
 877                                dev_name(&pdev->dev), fsl_lpspi);
 878         if (ret) {
 879                 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
 880                 goto out_controller_put;
 881         }
 882
 883         fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
 884         if (IS_ERR(fsl_lpspi->clk_per)) {
 885                 ret = PTR_ERR(fsl_lpspi->clk_per);
 886                 goto out_controller_put;
 887         }
 888
 889         fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
 890         if (IS_ERR(fsl_lpspi->clk_ipg)) {
 891                 ret = PTR_ERR(fsl_lpspi->clk_ipg);
 892                 goto out_controller_put;
 893         }
 894
 895         /* enable the clock */
 896         ret = fsl_lpspi_init_rpm(fsl_lpspi);
 897         if (ret)
 898                 goto out_controller_put;
 899
 900         ret = pm_runtime_get_sync(fsl_lpspi->dev);
 901         if (ret < 0) {
 902                 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
 903                 goto out_pm_get;
 904         }
 905
 906         temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
 907         fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
 908         fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
 909
 910         ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
 911         if (ret == -EPROBE_DEFER)
 912                 goto out_pm_get;
 913
 914         if (ret < 0)
 915                 dev_err(&pdev->dev, "dma setup error %d, use pio\n", ret);
 916
 917         ret = devm_spi_register_controller(&pdev->dev, controller);
 918         if (ret < 0) {
 919                 dev_err_probe(&pdev->dev, ret, "spi_register_controller error\n");
 920                 goto free_dma;
 921         }
 922
 923         pm_runtime_mark_last_busy(fsl_lpspi->dev);
 924         pm_runtime_put_autosuspend(fsl_lpspi->dev);
 925
 926         return 0;
 927
 928 free_dma:
 929         fsl_lpspi_dma_exit(controller);
 930 out_pm_get:
 931         pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
 932         pm_runtime_put_sync(fsl_lpspi->dev);
 933         pm_runtime_disable(fsl_lpspi->dev);
 934 out_controller_put:
 935         spi_controller_put(controller);
 936
 937         return ret;
 938 }
 939
 940 static int fsl_lpspi_remove(struct platform_device *pdev)
 941 {
 942         struct spi_controller *controller = platform_get_drvdata(pdev);
 943         struct fsl_lpspi_data *fsl_lpspi =
 944                                 spi_controller_get_devdata(controller);
 945
 946         fsl_lpspi_dma_exit(controller);
 947
 948         pm_runtime_disable(fsl_lpspi->dev);
 949         return 0;
 950 }
 951
 952 static int __maybe_unused fsl_lpspi_suspend(struct device *dev)
 953 {
 954         pinctrl_pm_select_sleep_state(dev);
 955         return pm_runtime_force_suspend(dev);
 956 }
 957
 958 static int __maybe_unused fsl_lpspi_resume(struct device *dev)
 959 {
 960         int ret;
 961
 962         ret = pm_runtime_force_resume(dev);
 963         if (ret) {
 964                 dev_err(dev, "Error in resume: %d\n", ret);
 965                 return ret;
 966         }
 967
 968         pinctrl_pm_select_default_state(dev);
 969
 970         return 0;
 971 }
 972
 973 static const struct dev_pm_ops fsl_lpspi_pm_ops = {
 974         SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend,
 975                                 fsl_lpspi_runtime_resume, NULL)
 976         SET_SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume)
 977 };
 978
 979 static struct platform_driver fsl_lpspi_driver = {
 980         .driver = {
 981                 .name = DRIVER_NAME,
 982                 .of_match_table = fsl_lpspi_dt_ids,
 983                 .pm = &fsl_lpspi_pm_ops,
 984         },
 985         .probe = fsl_lpspi_probe,
 986         .remove = fsl_lpspi_remove,
 987 };
 988 module_platform_driver(fsl_lpspi_driver);
 989
 990 MODULE_DESCRIPTION("LPSPI Controller driver");
 991 MODULE_AUTHOR("Gao Pan <[email protected]>");
 992 MODULE_LICENSE("GPL");