drivers/staging/rts5208/sd.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for Realtek PCI-Express card reader
   4  *
   5  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   6  *
   7  * Author:
   8  *   Wei WANG ([email protected])
   9  *   Micky Ching ([email protected])
  10  */
  11
  12 #include <linux/blkdev.h>
  13 #include <linux/kthread.h>
  14 #include <linux/sched.h>
  15
  16 #include "rtsx.h"
  17 #include "sd.h"
  18
  19 #define SD_MAX_RETRY_COUNT      3
  20
  21 static u16 REG_SD_CFG1;
  22 static u16 REG_SD_CFG2;
  23 static u16 REG_SD_CFG3;
  24 static u16 REG_SD_STAT1;
  25 static u16 REG_SD_STAT2;
  26 static u16 REG_SD_BUS_STAT;
  27 static u16 REG_SD_PAD_CTL;
  28 static u16 REG_SD_SAMPLE_POINT_CTL;
  29 static u16 REG_SD_PUSH_POINT_CTL;
  30 static u16 REG_SD_CMD0;
  31 static u16 REG_SD_CMD1;
  32 static u16 REG_SD_CMD2;
  33 static u16 REG_SD_CMD3;
  34 static u16 REG_SD_CMD4;
  35 static u16 REG_SD_CMD5;
  36 static u16 REG_SD_BYTE_CNT_L;
  37 static u16 REG_SD_BYTE_CNT_H;
  38 static u16 REG_SD_BLOCK_CNT_L;
  39 static u16 REG_SD_BLOCK_CNT_H;
  40 static u16 REG_SD_TRANSFER;
  41 static u16 REG_SD_VPCLK0_CTL;
  42 static u16 REG_SD_VPCLK1_CTL;
  43 static u16 REG_SD_DCMPS0_CTL;
  44 static u16 REG_SD_DCMPS1_CTL;
  45
  46 static inline void sd_set_err_code(struct rtsx_chip *chip, u8 err_code)
  47 {
  48         struct sd_info *sd_card = &chip->sd_card;
  49
  50         sd_card->err_code |= err_code;
  51 }
  52
  53 static inline void sd_clr_err_code(struct rtsx_chip *chip)
  54 {
  55         struct sd_info *sd_card = &chip->sd_card;
  56
  57         sd_card->err_code = 0;
  58 }
  59
  60 static inline int sd_check_err_code(struct rtsx_chip *chip, u8 err_code)
  61 {
  62         struct sd_info *sd_card = &chip->sd_card;
  63
  64         return sd_card->err_code & err_code;
  65 }
  66
  67 static void sd_init_reg_addr(struct rtsx_chip *chip)
  68 {
  69         REG_SD_CFG1 = 0xFD31;
  70         REG_SD_CFG2 = 0xFD33;
  71         REG_SD_CFG3 = 0xFD3E;
  72         REG_SD_STAT1 = 0xFD30;
  73         REG_SD_STAT2 = 0;
  74         REG_SD_BUS_STAT = 0;
  75         REG_SD_PAD_CTL = 0;
  76         REG_SD_SAMPLE_POINT_CTL = 0;
  77         REG_SD_PUSH_POINT_CTL = 0;
  78         REG_SD_CMD0 = 0xFD34;
  79         REG_SD_CMD1 = 0xFD35;
  80         REG_SD_CMD2 = 0xFD36;
  81         REG_SD_CMD3 = 0xFD37;
  82         REG_SD_CMD4 = 0xFD38;
  83         REG_SD_CMD5 = 0xFD5A;
  84         REG_SD_BYTE_CNT_L = 0xFD39;
  85         REG_SD_BYTE_CNT_H = 0xFD3A;
  86         REG_SD_BLOCK_CNT_L = 0xFD3B;
  87         REG_SD_BLOCK_CNT_H = 0xFD3C;
  88         REG_SD_TRANSFER = 0xFD32;
  89         REG_SD_VPCLK0_CTL = 0;
  90         REG_SD_VPCLK1_CTL = 0;
  91         REG_SD_DCMPS0_CTL = 0;
  92         REG_SD_DCMPS1_CTL = 0;
  93 }
  94
  95 static int sd_check_data0_status(struct rtsx_chip *chip)
  96 {
  97         int retval;
  98         u8 stat;
  99
 100         retval = rtsx_read_register(chip, REG_SD_STAT1, &stat);
 101         if (retval)
 102                 return retval;
 103
 104         if (!(stat & SD_DAT0_STATUS)) {
 105                 sd_set_err_code(chip, SD_BUSY);
 106                 return STATUS_FAIL;
 107         }
 108
 109         return STATUS_SUCCESS;
 110 }
 111
 112 static int sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
 113                                u32 arg, u8 rsp_type, u8 *rsp, int rsp_len)
 114 {
 115         struct sd_info *sd_card = &chip->sd_card;
 116         int retval;
 117         int timeout = 100;
 118         u16 reg_addr;
 119         u8 *ptr;
 120         int stat_idx = 0;
 121         int rty_cnt = 0;
 122
 123         sd_clr_err_code(chip);
 124
 125         dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg);
 126
 127         if (rsp_type == SD_RSP_TYPE_R1b)
 128                 timeout = 3000;
 129
 130 RTY_SEND_CMD:
 131
 132         rtsx_init_cmd(chip);
 133
 134         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
 135         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
 136         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
 137         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
 138         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
 139
 140         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
 141         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
 142                      0x01, PINGPONG_BUFFER);
 143         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
 144                      0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
 145         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
 146                      SD_TRANSFER_END | SD_STAT_IDLE, SD_TRANSFER_END |
 147                      SD_STAT_IDLE);
 148
 149         if (rsp_type == SD_RSP_TYPE_R2) {
 150                 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
 151                      reg_addr++)
 152                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
 153
 154                 stat_idx = 16;
 155         } else if (rsp_type != SD_RSP_TYPE_R0) {
 156                 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
 157                      reg_addr++)
 158                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
 159
 160                 stat_idx = 5;
 161         }
 162
 163         rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
 164
 165         retval = rtsx_send_cmd(chip, SD_CARD, timeout);
 166         if (retval < 0) {
 167                 u8 val;
 168
 169                 rtsx_read_register(chip, REG_SD_STAT1, &val);
 170                 dev_dbg(rtsx_dev(chip), "SD_STAT1: 0x%x\n", val);
 171
 172                 rtsx_read_register(chip, REG_SD_CFG3, &val);
 173                 dev_dbg(rtsx_dev(chip), "SD_CFG3: 0x%x\n", val);
 174
 175                 if (retval == -ETIMEDOUT) {
 176                         if (rsp_type & SD_WAIT_BUSY_END) {
 177                                 retval = sd_check_data0_status(chip);
 178                                 if (retval != STATUS_SUCCESS) {
 179                                         rtsx_clear_sd_error(chip);
 180                                         return retval;
 181                                 }
 182                         } else {
 183                                 sd_set_err_code(chip, SD_TO_ERR);
 184                         }
 185                         retval = STATUS_TIMEDOUT;
 186                 } else {
 187                         retval = STATUS_FAIL;
 188                 }
 189                 rtsx_clear_sd_error(chip);
 190
 191                 return retval;
 192         }
 193
 194         if (rsp_type == SD_RSP_TYPE_R0)
 195                 return STATUS_SUCCESS;
 196
 197         ptr = rtsx_get_cmd_data(chip) + 1;
 198
 199         if ((ptr[0] & 0xC0) != 0) {
 200                 sd_set_err_code(chip, SD_STS_ERR);
 201                 return STATUS_FAIL;
 202         }
 203
 204         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
 205                 if (ptr[stat_idx] & SD_CRC7_ERR) {
 206                         if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
 207                                 sd_set_err_code(chip, SD_CRC_ERR);
 208                                 return STATUS_FAIL;
 209                         }
 210                         if (rty_cnt < SD_MAX_RETRY_COUNT) {
 211                                 wait_timeout(20);
 212                                 rty_cnt++;
 213                                 goto RTY_SEND_CMD;
 214                         } else {
 215                                 sd_set_err_code(chip, SD_CRC_ERR);
 216                                 return STATUS_FAIL;
 217                         }
 218                 }
 219         }
 220
 221         if ((rsp_type == SD_RSP_TYPE_R1) || (rsp_type == SD_RSP_TYPE_R1b)) {
 222                 if ((cmd_idx != SEND_RELATIVE_ADDR) &&
 223                     (cmd_idx != SEND_IF_COND)) {
 224                         if (cmd_idx != STOP_TRANSMISSION) {
 225                                 if (ptr[1] & 0x80)
 226                                         return STATUS_FAIL;
 227                         }
 228 #ifdef SUPPORT_SD_LOCK
 229                         if (ptr[1] & 0x7D) {
 230 #else
 231                         if (ptr[1] & 0x7F) {
 232 #endif
 233                                 dev_dbg(rtsx_dev(chip), "ptr[1]: 0x%02x\n",
 234                                         ptr[1]);
 235                                 return STATUS_FAIL;
 236                         }
 237                         if (ptr[2] & 0xFF) {
 238                                 dev_dbg(rtsx_dev(chip), "ptr[2]: 0x%02x\n",
 239                                         ptr[2]);
 240                                 return STATUS_FAIL;
 241                         }
 242                         if (ptr[3] & 0x80) {
 243                                 dev_dbg(rtsx_dev(chip), "ptr[3]: 0x%02x\n",
 244                                         ptr[3]);
 245                                 return STATUS_FAIL;
 246                         }
 247                         if (ptr[3] & 0x01)
 248                                 sd_card->sd_data_buf_ready = 1;
 249                         else
 250                                 sd_card->sd_data_buf_ready = 0;
 251                 }
 252         }
 253
 254         if (rsp && rsp_len)
 255                 memcpy(rsp, ptr, rsp_len);
 256
 257         return STATUS_SUCCESS;
 258 }
 259
 260 static int sd_read_data(struct rtsx_chip *chip,
 261                         u8 trans_mode, u8 *cmd, int cmd_len, u16 byte_cnt,
 262                         u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len,
 263                         int timeout)
 264 {
 265         struct sd_info *sd_card = &chip->sd_card;
 266         int retval;
 267         int i;
 268
 269         sd_clr_err_code(chip);
 270
 271         if (!buf)
 272                 buf_len = 0;
 273
 274         if (buf_len > 512)
 275                 return STATUS_FAIL;
 276
 277         rtsx_init_cmd(chip);
 278
 279         if (cmd_len) {
 280                 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", cmd[0] - 0x40);
 281                 for (i = 0; i < (min(cmd_len, 6)); i++)
 282                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0 + i,
 283                                      0xFF, cmd[i]);
 284         }
 285         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
 286                      (u8)byte_cnt);
 287         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
 288                      (u8)(byte_cnt >> 8));
 289         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
 290                      (u8)blk_cnt);
 291         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
 292                      (u8)(blk_cnt >> 8));
 293
 294         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
 295
 296         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
 297                      SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
 298                      SD_CHECK_CRC7 | SD_RSP_LEN_6);
 299         if (trans_mode != SD_TM_AUTO_TUNING)
 300                 rtsx_add_cmd(chip, WRITE_REG_CMD,
 301                              CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
 302
 303         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
 304                      trans_mode | SD_TRANSFER_START);
 305         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
 306                      SD_TRANSFER_END);
 307
 308         retval = rtsx_send_cmd(chip, SD_CARD, timeout);
 309         if (retval < 0) {
 310                 if (retval == -ETIMEDOUT) {
 311                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
 312                                             SD_RSP_TYPE_R1, NULL, 0);
 313                 }
 314
 315                 return STATUS_FAIL;
 316         }
 317
 318         if (buf && buf_len) {
 319                 retval = rtsx_read_ppbuf(chip, buf, buf_len);
 320                 if (retval != STATUS_SUCCESS)
 321                         return STATUS_FAIL;
 322         }
 323
 324         return STATUS_SUCCESS;
 325 }
 326
 327 static int sd_write_data(struct rtsx_chip *chip, u8 trans_mode,
 328                          u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt,
 329                          u8 bus_width, u8 *buf, int buf_len, int timeout)
 330 {
 331         struct sd_info *sd_card = &chip->sd_card;
 332         int retval;
 333         int i;
 334
 335         sd_clr_err_code(chip);
 336
 337         if (!buf)
 338                 buf_len = 0;
 339
 340         if (buf_len > 512) {
 341                 /* This function can't write data more than one page */
 342                 return STATUS_FAIL;
 343         }
 344
 345         if (buf && buf_len) {
 346                 retval = rtsx_write_ppbuf(chip, buf, buf_len);
 347                 if (retval != STATUS_SUCCESS)
 348                         return STATUS_FAIL;
 349         }
 350
 351         rtsx_init_cmd(chip);
 352
 353         if (cmd_len) {
 354                 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", cmd[0] - 0x40);
 355                 for (i = 0; i < (min(cmd_len, 6)); i++) {
 356                         rtsx_add_cmd(chip, WRITE_REG_CMD,
 357                                      REG_SD_CMD0 + i, 0xFF, cmd[i]);
 358                 }
 359         }
 360         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
 361                      (u8)byte_cnt);
 362         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
 363                      (u8)(byte_cnt >> 8));
 364         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
 365                      (u8)blk_cnt);
 366         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
 367                      (u8)(blk_cnt >> 8));
 368
 369         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
 370
 371         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
 372                      SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
 373                      SD_CHECK_CRC7 | SD_RSP_LEN_6);
 374
 375         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
 376                      trans_mode | SD_TRANSFER_START);
 377         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
 378                      SD_TRANSFER_END);
 379
 380         retval = rtsx_send_cmd(chip, SD_CARD, timeout);
 381         if (retval < 0) {
 382                 if (retval == -ETIMEDOUT) {
 383                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
 384                                             SD_RSP_TYPE_R1, NULL, 0);
 385                 }
 386
 387                 return STATUS_FAIL;
 388         }
 389
 390         return STATUS_SUCCESS;
 391 }
 392
 393 static int sd_check_csd(struct rtsx_chip *chip, char check_wp)
 394 {
 395         struct sd_info *sd_card = &chip->sd_card;
 396         int retval;
 397         int i;
 398         u8 csd_ver, trans_speed;
 399         u8 rsp[16];
 400
 401         for (i = 0; i < 6; i++) {
 402                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
 403                         sd_set_err_code(chip, SD_NO_CARD);
 404                         return STATUS_FAIL;
 405                 }
 406
 407                 retval = sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr,
 408                                              SD_RSP_TYPE_R2, rsp, 16);
 409                 if (retval == STATUS_SUCCESS)
 410                         break;
 411         }
 412
 413         if (i == 6)
 414                 return STATUS_FAIL;
 415
 416         memcpy(sd_card->raw_csd, rsp + 1, 15);
 417
 418         dev_dbg(rtsx_dev(chip), "CSD Response:\n");
 419         dev_dbg(rtsx_dev(chip), "%*ph\n", 16, sd_card->raw_csd);
 420
 421         csd_ver = (rsp[1] & 0xc0) >> 6;
 422         dev_dbg(rtsx_dev(chip), "csd_ver = %d\n", csd_ver);
 423
 424         trans_speed = rsp[4];
 425         if ((trans_speed & 0x07) == 0x02) {
 426                 if ((trans_speed & 0xf8) >= 0x30) {
 427                         if (chip->asic_code)
 428                                 sd_card->sd_clock = 47;
 429                         else
 430                                 sd_card->sd_clock = CLK_50;
 431
 432                 } else if ((trans_speed & 0xf8) == 0x28) {
 433                         if (chip->asic_code)
 434                                 sd_card->sd_clock = 39;
 435                         else
 436                                 sd_card->sd_clock = CLK_40;
 437
 438                 } else if ((trans_speed & 0xf8) == 0x20) {
 439                         if (chip->asic_code)
 440                                 sd_card->sd_clock = 29;
 441                         else
 442                                 sd_card->sd_clock = CLK_30;
 443
 444                 } else if ((trans_speed & 0xf8) >= 0x10) {
 445                         if (chip->asic_code)
 446                                 sd_card->sd_clock = 23;
 447                         else
 448                                 sd_card->sd_clock = CLK_20;
 449
 450                 } else if ((trans_speed & 0x08) >= 0x08) {
 451                         if (chip->asic_code)
 452                                 sd_card->sd_clock = 19;
 453                         else
 454                                 sd_card->sd_clock = CLK_20;
 455                 } else {
 456                         return STATUS_FAIL;
 457                 }
 458         } else {
 459                 return STATUS_FAIL;
 460         }
 461
 462         if (CHK_MMC_SECTOR_MODE(sd_card)) {
 463                 sd_card->capacity = 0;
 464         } else {
 465                 if ((!CHK_SD_HCXC(sd_card)) || (csd_ver == 0)) {
 466                         u8 blk_size, c_size_mult;
 467                         u16 c_size;
 468
 469                         blk_size = rsp[6] & 0x0F;
 470                         c_size =  ((u16)(rsp[7] & 0x03) << 10)
 471                                         + ((u16)rsp[8] << 2)
 472                                         + ((u16)(rsp[9] & 0xC0) >> 6);
 473                         c_size_mult = (u8)((rsp[10] & 0x03) << 1);
 474                         c_size_mult += (rsp[11] & 0x80) >> 7;
 475                         sd_card->capacity = (((u32)(c_size + 1)) *
 476                                         (1 << (c_size_mult + 2)))
 477                                 << (blk_size - 9);
 478                 } else {
 479                         u32 total_sector = 0;
 480
 481                         total_sector = (((u32)rsp[8] & 0x3f) << 16) |
 482                                 ((u32)rsp[9] << 8) | (u32)rsp[10];
 483                         sd_card->capacity = (total_sector + 1) << 10;
 484                 }
 485         }
 486
 487         if (check_wp) {
 488                 if (rsp[15] & 0x30)
 489                         chip->card_wp |= SD_CARD;
 490
 491                 dev_dbg(rtsx_dev(chip), "CSD WP Status: 0x%x\n", rsp[15]);
 492         }
 493
 494         return STATUS_SUCCESS;
 495 }
 496
 497 static int sd_set_sample_push_timing(struct rtsx_chip *chip)
 498 {
 499         int retval;
 500         struct sd_info *sd_card = &chip->sd_card;
 501         u8 val = 0;
 502
 503         if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY)
 504                 val |= 0x10;
 505
 506         if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) {
 507                 if (chip->asic_code) {
 508                         if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) {
 509                                 if (val & 0x10)
 510                                         val |= 0x04;
 511                                 else
 512                                         val |= 0x08;
 513                         }
 514                 } else {
 515                         if (val & 0x10)
 516                                 val |= 0x04;
 517                         else
 518                                 val |= 0x08;
 519                 }
 520         } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) ==
 521                 SD_SAMPLE_POINT_DELAY) {
 522                 if (val & 0x10)
 523                         val |= 0x04;
 524                 else
 525                         val |= 0x08;
 526         }
 527
 528         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x1C, val);
 529         if (retval)
 530                 return retval;
 531
 532         return STATUS_SUCCESS;
 533 }
 534
 535 static void sd_choose_proper_clock(struct rtsx_chip *chip)
 536 {
 537         struct sd_info *sd_card = &chip->sd_card;
 538
 539         if (CHK_SD_SDR104(sd_card)) {
 540                 if (chip->asic_code)
 541                         sd_card->sd_clock = chip->asic_sd_sdr104_clk;
 542                 else
 543                         sd_card->sd_clock = chip->fpga_sd_sdr104_clk;
 544
 545         } else if (CHK_SD_DDR50(sd_card)) {
 546                 if (chip->asic_code)
 547                         sd_card->sd_clock = chip->asic_sd_ddr50_clk;
 548                 else
 549                         sd_card->sd_clock = chip->fpga_sd_ddr50_clk;
 550
 551         } else if (CHK_SD_SDR50(sd_card)) {
 552                 if (chip->asic_code)
 553                         sd_card->sd_clock = chip->asic_sd_sdr50_clk;
 554                 else
 555                         sd_card->sd_clock = chip->fpga_sd_sdr50_clk;
 556
 557         } else if (CHK_SD_HS(sd_card)) {
 558                 if (chip->asic_code)
 559                         sd_card->sd_clock = chip->asic_sd_hs_clk;
 560                 else
 561                         sd_card->sd_clock = chip->fpga_sd_hs_clk;
 562
 563         } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) {
 564                 if (chip->asic_code)
 565                         sd_card->sd_clock = chip->asic_mmc_52m_clk;
 566                 else
 567                         sd_card->sd_clock = chip->fpga_mmc_52m_clk;
 568
 569         } else if (CHK_MMC_26M(sd_card)) {
 570                 if (chip->asic_code)
 571                         sd_card->sd_clock = 48;
 572                 else
 573                         sd_card->sd_clock = CLK_50;
 574         }
 575 }
 576
 577 static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div)
 578 {
 579         int retval;
 580         u8 mask = 0, val = 0;
 581
 582         mask = 0x60;
 583         if (clk_div == SD_CLK_DIVIDE_0)
 584                 val = 0x00;
 585         else if (clk_div == SD_CLK_DIVIDE_128)
 586                 val = 0x40;
 587         else if (clk_div == SD_CLK_DIVIDE_256)
 588                 val = 0x20;
 589
 590         retval = rtsx_write_register(chip, REG_SD_CFG1, mask, val);
 591         if (retval)
 592                 return retval;
 593
 594         return STATUS_SUCCESS;
 595 }
 596
 597 static int sd_set_init_para(struct rtsx_chip *chip)
 598 {
 599         struct sd_info *sd_card = &chip->sd_card;
 600         int retval;
 601
 602         retval = sd_set_sample_push_timing(chip);
 603         if (retval != STATUS_SUCCESS)
 604                 return STATUS_FAIL;
 605
 606         sd_choose_proper_clock(chip);
 607
 608         retval = switch_clock(chip, sd_card->sd_clock);
 609         if (retval != STATUS_SUCCESS)
 610                 return STATUS_FAIL;
 611
 612         return STATUS_SUCCESS;
 613 }
 614
 615 int sd_select_card(struct rtsx_chip *chip, int select)
 616 {
 617         struct sd_info *sd_card = &chip->sd_card;
 618         int retval;
 619         u8 cmd_idx, cmd_type;
 620         u32 addr;
 621
 622         if (select) {
 623                 cmd_idx = SELECT_CARD;
 624                 cmd_type = SD_RSP_TYPE_R1;
 625                 addr = sd_card->sd_addr;
 626         } else {
 627                 cmd_idx = DESELECT_CARD;
 628                 cmd_type = SD_RSP_TYPE_R0;
 629                 addr = 0;
 630         }
 631
 632         retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0);
 633         if (retval != STATUS_SUCCESS)
 634                 return STATUS_FAIL;
 635
 636         return STATUS_SUCCESS;
 637 }
 638
 639 #ifdef SUPPORT_SD_LOCK
 640 static int sd_update_lock_status(struct rtsx_chip *chip)
 641 {
 642         struct sd_info *sd_card = &chip->sd_card;
 643         int retval;
 644         u8 rsp[5];
 645
 646         retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
 647                                      SD_RSP_TYPE_R1, rsp, 5);
 648         if (retval != STATUS_SUCCESS)
 649                 return STATUS_FAIL;
 650
 651         if (rsp[1] & 0x02)
 652                 sd_card->sd_lock_status |= SD_LOCKED;
 653         else
 654                 sd_card->sd_lock_status &= ~SD_LOCKED;
 655
 656         dev_dbg(rtsx_dev(chip), "sd_card->sd_lock_status = 0x%x\n",
 657                 sd_card->sd_lock_status);
 658
 659         if (rsp[1] & 0x01)
 660                 return STATUS_FAIL;
 661
 662         return STATUS_SUCCESS;
 663 }
 664 #endif
 665
 666 static int sd_wait_state_data_ready(struct rtsx_chip *chip, u8 state,
 667                                     u8 data_ready, int polling_cnt)
 668 {
 669         struct sd_info *sd_card = &chip->sd_card;
 670         int retval, i;
 671         u8 rsp[5];
 672
 673         for (i = 0; i < polling_cnt; i++) {
 674                 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
 675                                              sd_card->sd_addr, SD_RSP_TYPE_R1,
 676                                              rsp, 5);
 677                 if (retval != STATUS_SUCCESS)
 678                         return STATUS_FAIL;
 679
 680                 if (((rsp[3] & 0x1E) == state) &&
 681                     ((rsp[3] & 0x01) == data_ready))
 682                         return STATUS_SUCCESS;
 683         }
 684
 685         return STATUS_FAIL;
 686 }
 687
 688 static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage)
 689 {
 690         int retval;
 691
 692         if (voltage == SD_IO_3V3) {
 693                 if (chip->asic_code) {
 694                         retval = rtsx_write_phy_register(chip, 0x08,
 695                                                          0x4FC0 |
 696                                                          chip->phy_voltage);
 697                         if (retval != STATUS_SUCCESS)
 698                                 return STATUS_FAIL;
 699                 } else {
 700                         retval = rtsx_write_register(chip, SD_PAD_CTL,
 701                                                      SD_IO_USING_1V8, 0);
 702                         if (retval)
 703                                 return retval;
 704                 }
 705         } else if (voltage == SD_IO_1V8) {
 706                 if (chip->asic_code) {
 707                         retval = rtsx_write_phy_register(chip, 0x08,
 708                                                          0x4C40 |
 709                                                          chip->phy_voltage);
 710                         if (retval != STATUS_SUCCESS)
 711                                 return STATUS_FAIL;
 712                 } else {
 713                         retval = rtsx_write_register(chip, SD_PAD_CTL,
 714                                                      SD_IO_USING_1V8,
 715                                                      SD_IO_USING_1V8);
 716                         if (retval)
 717                                 return retval;
 718                 }
 719         } else {
 720                 return STATUS_FAIL;
 721         }
 722
 723         return STATUS_SUCCESS;
 724 }
 725
 726 static int sd_voltage_switch(struct rtsx_chip *chip)
 727 {
 728         int retval;
 729         u8 stat;
 730
 731         retval = rtsx_write_register(chip, SD_BUS_STAT,
 732                                      SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP,
 733                                      SD_CLK_TOGGLE_EN);
 734         if (retval)
 735                 return retval;
 736
 737         retval = sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1,
 738                                      NULL, 0);
 739         if (retval != STATUS_SUCCESS)
 740                 return STATUS_FAIL;
 741
 742         udelay(chip->sd_voltage_switch_delay);
 743
 744         retval = rtsx_read_register(chip, SD_BUS_STAT, &stat);
 745         if (retval)
 746                 return retval;
 747         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
 748                                 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
 749                 return STATUS_FAIL;
 750         }
 751
 752         retval = rtsx_write_register(chip, SD_BUS_STAT, 0xFF,
 753                                      SD_CLK_FORCE_STOP);
 754         if (retval)
 755                 return retval;
 756         retval = sd_change_bank_voltage(chip, SD_IO_1V8);
 757         if (retval != STATUS_SUCCESS)
 758                 return STATUS_FAIL;
 759
 760         wait_timeout(50);
 761
 762         retval = rtsx_write_register(chip, SD_BUS_STAT, 0xFF,
 763                                      SD_CLK_TOGGLE_EN);
 764         if (retval)
 765                 return retval;
 766         wait_timeout(10);
 767
 768         retval = rtsx_read_register(chip, SD_BUS_STAT, &stat);
 769         if (retval)
 770                 return retval;
 771         if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
 772                                 SD_DAT1_STATUS | SD_DAT0_STATUS)) !=
 773                         (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
 774                                 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
 775                 dev_dbg(rtsx_dev(chip), "SD_BUS_STAT: 0x%x\n", stat);
 776                 rtsx_write_register(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN |
 777                                     SD_CLK_FORCE_STOP, 0);
 778                 rtsx_write_register(chip, CARD_CLK_EN, 0xFF, 0);
 779                 return STATUS_FAIL;
 780         }
 781
 782         retval = rtsx_write_register(chip, SD_BUS_STAT,
 783                                      SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
 784         if (retval)
 785                 return retval;
 786
 787         return STATUS_SUCCESS;
 788 }
 789
 790 static int sd_reset_dcm(struct rtsx_chip *chip, u8 tune_dir)
 791 {
 792         int retval;
 793
 794         if (tune_dir == TUNE_RX) {
 795                 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF,
 796                                              DCM_RESET | DCM_RX);
 797                 if (retval)
 798                         return retval;
 799                 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, DCM_RX);
 800                 if (retval)
 801                         return retval;
 802         } else {
 803                 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF,
 804                                              DCM_RESET | DCM_TX);
 805                 if (retval)
 806                         return retval;
 807                 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, DCM_TX);
 808                 if (retval)
 809                         return retval;
 810         }
 811
 812         return STATUS_SUCCESS;
 813 }
 814
 815 static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
 816 {
 817         struct sd_info *sd_card = &chip->sd_card;
 818         u16 SD_VP_CTL, SD_DCMPS_CTL;
 819         u8 val;
 820         int retval;
 821         bool ddr_rx = false;
 822
 823         dev_dbg(rtsx_dev(chip), "%s (sample_point = %d, tune_dir = %d)\n",
 824                 __func__, sample_point, tune_dir);
 825
 826         if (tune_dir == TUNE_RX) {
 827                 SD_VP_CTL = SD_VPRX_CTL;
 828                 SD_DCMPS_CTL = SD_DCMPS_RX_CTL;
 829                 if (CHK_SD_DDR50(sd_card))
 830                         ddr_rx = true;
 831         } else {
 832                 SD_VP_CTL = SD_VPTX_CTL;
 833                 SD_DCMPS_CTL = SD_DCMPS_TX_CTL;
 834         }
 835
 836         if (chip->asic_code) {
 837                 retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK,
 838                                              CHANGE_CLK);
 839                 if (retval)
 840                         return retval;
 841                 retval = rtsx_write_register(chip, SD_VP_CTL, 0x1F,
 842                                              sample_point);
 843                 if (retval)
 844                         return retval;
 845                 retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
 846                                              PHASE_NOT_RESET, 0);
 847                 if (retval)
 848                         return retval;
 849                 retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
 850                                              PHASE_NOT_RESET, PHASE_NOT_RESET);
 851                 if (retval)
 852                         return retval;
 853                 retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK, 0);
 854                 if (retval)
 855                         return retval;
 856         } else {
 857                 rtsx_read_register(chip, SD_VP_CTL, &val);
 858                 dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val);
 859                 rtsx_read_register(chip, SD_DCMPS_CTL, &val);
 860                 dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val);
 861
 862                 if (ddr_rx) {
 863                         retval = rtsx_write_register(chip, SD_VP_CTL,
 864                                                      PHASE_CHANGE,
 865                                                      PHASE_CHANGE);
 866                         if (retval)
 867                                 return retval;
 868                         udelay(50);
 869                         retval = rtsx_write_register(chip, SD_VP_CTL, 0xFF,
 870                                                      PHASE_CHANGE |
 871                                                      PHASE_NOT_RESET |
 872                                                      sample_point);
 873                         if (retval)
 874                                 return retval;
 875                 } else {
 876                         retval = rtsx_write_register(chip, CLK_CTL,
 877                                                      CHANGE_CLK, CHANGE_CLK);
 878                         if (retval)
 879                                 return retval;
 880                         udelay(50);
 881                         retval = rtsx_write_register(chip, SD_VP_CTL, 0xFF,
 882                                                      PHASE_NOT_RESET |
 883                                                      sample_point);
 884                         if (retval)
 885                                 return retval;
 886                 }
 887                 udelay(100);
 888
 889                 rtsx_init_cmd(chip);
 890                 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE,
 891                              DCMPS_CHANGE);
 892                 rtsx_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL,
 893                              DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE);
 894                 retval = rtsx_send_cmd(chip, SD_CARD, 100);
 895                 if (retval != STATUS_SUCCESS)
 896                         goto fail;
 897
 898                 val = *rtsx_get_cmd_data(chip);
 899                 if (val & DCMPS_ERROR)
 900                         goto fail;
 901
 902                 if ((val & DCMPS_CURRENT_PHASE) != sample_point)
 903                         goto fail;
 904
 905                 retval = rtsx_write_register(chip, SD_DCMPS_CTL,
 906                                              DCMPS_CHANGE, 0);
 907                 if (retval)
 908                         return retval;
 909                 if (ddr_rx) {
 910                         retval = rtsx_write_register(chip, SD_VP_CTL,
 911                                                      PHASE_CHANGE, 0);
 912                         if (retval)
 913                                 return retval;
 914                 } else {
 915                         retval = rtsx_write_register(chip, CLK_CTL,
 916                                                      CHANGE_CLK, 0);
 917                         if (retval)
 918                                 return retval;
 919                 }
 920
 921                 udelay(50);
 922         }
 923
 924         retval = rtsx_write_register(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
 925         if (retval)
 926                 return retval;
 927
 928         return STATUS_SUCCESS;
 929
 930 fail:
 931         rtsx_read_register(chip, SD_VP_CTL, &val);
 932         dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val);
 933         rtsx_read_register(chip, SD_DCMPS_CTL, &val);
 934         dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val);
 935
 936         rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
 937         rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0);
 938         mdelay(10);
 939         sd_reset_dcm(chip, tune_dir);
 940         return STATUS_FAIL;
 941 }
 942
 943 static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width)
 944 {
 945         struct sd_info *sd_card = &chip->sd_card;
 946         int retval;
 947         u8 cmd[5], buf[8];
 948
 949         retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
 950                                      SD_RSP_TYPE_R1, NULL, 0);
 951         if (retval != STATUS_SUCCESS)
 952                 return STATUS_FAIL;
 953
 954         cmd[0] = 0x40 | SEND_SCR;
 955         cmd[1] = 0;
 956         cmd[2] = 0;
 957         cmd[3] = 0;
 958         cmd[4] = 0;
 959
 960         retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width,
 961                               buf, 8, 250);
 962         if (retval != STATUS_SUCCESS) {
 963                 rtsx_clear_sd_error(chip);
 964                 return STATUS_FAIL;
 965         }
 966
 967         memcpy(sd_card->raw_scr, buf, 8);
 968
 969         if ((buf[0] & 0x0F) == 0)
 970                 return STATUS_FAIL;
 971
 972         return STATUS_SUCCESS;
 973 }
 974
 975 static int sd_query_switch_result(struct rtsx_chip *chip, u8 func_group,
 976                                   u8 func_to_switch, u8 *buf, int buf_len)
 977 {
 978         u8 support_mask = 0, query_switch = 0, switch_busy = 0;
 979         int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0;
 980
 981         if (func_group == SD_FUNC_GROUP_1) {
 982                 support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET;
 983                 query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET;
 984                 check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET;
 985
 986                 switch (func_to_switch) {
 987                 case HS_SUPPORT:
 988                         support_mask = HS_SUPPORT_MASK;
 989                         query_switch = HS_QUERY_SWITCH_OK;
 990                         switch_busy = HS_SWITCH_BUSY;
 991                         break;
 992
 993                 case SDR50_SUPPORT:
 994                         support_mask = SDR50_SUPPORT_MASK;
 995                         query_switch = SDR50_QUERY_SWITCH_OK;
 996                         switch_busy = SDR50_SWITCH_BUSY;
 997                         break;
 998
 999                 case SDR104_SUPPORT:
1000                         support_mask = SDR104_SUPPORT_MASK;
1001                         query_switch = SDR104_QUERY_SWITCH_OK;
1002                         switch_busy = SDR104_SWITCH_BUSY;
1003                         break;
1004
1005                 case DDR50_SUPPORT:
1006                         support_mask = DDR50_SUPPORT_MASK;
1007                         query_switch = DDR50_QUERY_SWITCH_OK;
1008                         switch_busy = DDR50_SWITCH_BUSY;
1009                         break;
1010
1011                 default:
1012                         return STATUS_FAIL;
1013                 }
1014         } else if (func_group == SD_FUNC_GROUP_3) {
1015                 support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET;
1016                 query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET;
1017                 check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET;
1018
1019                 switch (func_to_switch) {
1020                 case DRIVING_TYPE_A:
1021                         support_mask = DRIVING_TYPE_A_MASK;
1022                         query_switch = TYPE_A_QUERY_SWITCH_OK;
1023                         switch_busy = TYPE_A_SWITCH_BUSY;
1024                         break;
1025
1026                 case DRIVING_TYPE_C:
1027                         support_mask = DRIVING_TYPE_C_MASK;
1028                         query_switch = TYPE_C_QUERY_SWITCH_OK;
1029                         switch_busy = TYPE_C_SWITCH_BUSY;
1030                         break;
1031
1032                 case DRIVING_TYPE_D:
1033                         support_mask = DRIVING_TYPE_D_MASK;
1034                         query_switch = TYPE_D_QUERY_SWITCH_OK;
1035                         switch_busy = TYPE_D_SWITCH_BUSY;
1036                         break;
1037
1038                 default:
1039                         return STATUS_FAIL;
1040                 }
1041         } else if (func_group == SD_FUNC_GROUP_4) {
1042                 support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET;
1043                 query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET;
1044                 check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET;
1045
1046                 switch (func_to_switch) {
1047                 case CURRENT_LIMIT_400:
1048                         support_mask = CURRENT_LIMIT_400_MASK;
1049                         query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK;
1050                         switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY;
1051                         break;
1052
1053                 case CURRENT_LIMIT_600:
1054                         support_mask = CURRENT_LIMIT_600_MASK;
1055                         query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK;
1056                         switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY;
1057                         break;
1058
1059                 case CURRENT_LIMIT_800:
1060                         support_mask = CURRENT_LIMIT_800_MASK;
1061                         query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK;
1062                         switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY;
1063                         break;
1064
1065                 default:
1066                         return STATUS_FAIL;
1067                 }
1068         } else {
1069                 return STATUS_FAIL;
1070         }
1071
1072         if (func_group == SD_FUNC_GROUP_1) {
1073                 if (!(buf[support_offset] & support_mask) ||
1074                     ((buf[query_switch_offset] & 0x0F) != query_switch)) {
1075                         return STATUS_FAIL;
1076                 }
1077         }
1078
1079         /* Check 'Busy Status' */
1080         if ((buf[DATA_STRUCTURE_VER_OFFSET] == 0x01) &&
1081             ((buf[check_busy_offset] & switch_busy) == switch_busy)) {
1082                 return STATUS_FAIL;
1083         }
1084
1085         return STATUS_SUCCESS;
1086 }
1087
1088 static int sd_check_switch_mode(struct rtsx_chip *chip, u8 mode, u8 func_group,
1089                                 u8 func_to_switch, u8 bus_width)
1090 {
1091         struct sd_info *sd_card = &chip->sd_card;
1092         int retval;
1093         u8 cmd[5], buf[64];
1094
1095         dev_dbg(rtsx_dev(chip), "%s (mode = %d, func_group = %d, func_to_switch = %d)\n",
1096                 __func__, mode, func_group, func_to_switch);
1097
1098         cmd[0] = 0x40 | SWITCH;
1099         cmd[1] = mode;
1100
1101         if (func_group == SD_FUNC_GROUP_1) {
1102                 cmd[2] = 0xFF;
1103                 cmd[3] = 0xFF;
1104                 cmd[4] = 0xF0 + func_to_switch;
1105         } else if (func_group == SD_FUNC_GROUP_3) {
1106                 cmd[2] = 0xFF;
1107                 cmd[3] = 0xF0 + func_to_switch;
1108                 cmd[4] = 0xFF;
1109         } else if (func_group == SD_FUNC_GROUP_4) {
1110                 cmd[2] = 0xFF;
1111                 cmd[3] = 0x0F + (func_to_switch << 4);
1112                 cmd[4] = 0xFF;
1113         } else {
1114                 cmd[1] = SD_CHECK_MODE;
1115                 cmd[2] = 0xFF;
1116                 cmd[3] = 0xFF;
1117                 cmd[4] = 0xFF;
1118         }
1119
1120         retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width,
1121                               buf, 64, 250);
1122         if (retval != STATUS_SUCCESS) {
1123                 rtsx_clear_sd_error(chip);
1124                 return STATUS_FAIL;
1125         }
1126
1127         dev_dbg(rtsx_dev(chip), "%*ph\n", 64, buf);
1128
1129         if (func_group == NO_ARGUMENT) {
1130                 sd_card->func_group1_mask = buf[0x0D];
1131                 sd_card->func_group2_mask = buf[0x0B];
1132                 sd_card->func_group3_mask = buf[0x09];
1133                 sd_card->func_group4_mask = buf[0x07];
1134
1135                 dev_dbg(rtsx_dev(chip), "func_group1_mask = 0x%02x\n",
1136                         buf[0x0D]);
1137                 dev_dbg(rtsx_dev(chip), "func_group2_mask = 0x%02x\n",
1138                         buf[0x0B]);
1139                 dev_dbg(rtsx_dev(chip), "func_group3_mask = 0x%02x\n",
1140                         buf[0x09]);
1141                 dev_dbg(rtsx_dev(chip), "func_group4_mask = 0x%02x\n",
1142                         buf[0x07]);
1143         } else {
1144                 /* Maximum current consumption, check whether current is
1145                  * acceptable; bit[511:496] = 0x0000 means some error happened.
1146                  */
1147                 u16 cc = ((u16)buf[0] << 8) | buf[1];
1148
1149                 dev_dbg(rtsx_dev(chip), "Maximum current consumption: %dmA\n",
1150                         cc);
1151                 if ((cc == 0) || (cc > 800))
1152                         return STATUS_FAIL;
1153
1154                 retval = sd_query_switch_result(chip, func_group,
1155                                                 func_to_switch, buf, 64);
1156                 if (retval != STATUS_SUCCESS)
1157                         return STATUS_FAIL;
1158
1159                 if ((cc > 400) || (func_to_switch > CURRENT_LIMIT_400)) {
1160                         retval = rtsx_write_register(chip, OCPPARA2,
1161                                                      SD_OCP_THD_MASK,
1162                                                      chip->sd_800mA_ocp_thd);
1163                         if (retval)
1164                                 return retval;
1165                         retval = rtsx_write_register(chip, CARD_PWR_CTL,
1166                                                      PMOS_STRG_MASK,
1167                                                      PMOS_STRG_800mA);
1168                         if (retval)
1169                                 return retval;
1170                 }
1171         }
1172
1173         return STATUS_SUCCESS;
1174 }
1175
1176 static u8 downgrade_switch_mode(u8 func_group, u8 func_to_switch)
1177 {
1178         if (func_group == SD_FUNC_GROUP_1) {
1179                 if (func_to_switch > HS_SUPPORT)
1180                         func_to_switch--;
1181
1182         } else if (func_group == SD_FUNC_GROUP_4) {
1183                 if (func_to_switch > CURRENT_LIMIT_200)
1184                         func_to_switch--;
1185         }
1186
1187         return func_to_switch;
1188 }
1189
1190 static int sd_check_switch(struct rtsx_chip *chip,
1191                            u8 func_group, u8 func_to_switch, u8 bus_width)
1192 {
1193         int retval;
1194         int i;
1195         bool switch_good = false;
1196
1197         for (i = 0; i < 3; i++) {
1198                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1199                         sd_set_err_code(chip, SD_NO_CARD);
1200                         return STATUS_FAIL;
1201                 }
1202
1203                 retval = sd_check_switch_mode(chip, SD_CHECK_MODE, func_group,
1204                                               func_to_switch, bus_width);
1205                 if (retval == STATUS_SUCCESS) {
1206                         u8 stat;
1207
1208                         retval = sd_check_switch_mode(chip, SD_SWITCH_MODE,
1209                                                       func_group,
1210                                                       func_to_switch,
1211                                                       bus_width);
1212                         if (retval == STATUS_SUCCESS) {
1213                                 switch_good = true;
1214                                 break;
1215                         }
1216
1217                         retval = rtsx_read_register(chip, SD_STAT1, &stat);
1218                         if (retval)
1219                                 return retval;
1220                         if (stat & SD_CRC16_ERR) {
1221                                 dev_dbg(rtsx_dev(chip), "SD CRC16 error when switching mode\n");
1222                                 return STATUS_FAIL;
1223                         }
1224                 }
1225
1226                 func_to_switch = downgrade_switch_mode(func_group,
1227                                                        func_to_switch);
1228
1229                 wait_timeout(20);
1230         }
1231
1232         if (!switch_good)
1233                 return STATUS_FAIL;
1234
1235         return STATUS_SUCCESS;
1236 }
1237
1238 static int sd_switch_function(struct rtsx_chip *chip, u8 bus_width)
1239 {
1240         struct sd_info *sd_card = &chip->sd_card;
1241         int retval;
1242         int i;
1243         u8 func_to_switch = 0;
1244
1245         /* Get supported functions */
1246         retval = sd_check_switch_mode(chip, SD_CHECK_MODE, NO_ARGUMENT,
1247                                       NO_ARGUMENT, bus_width);
1248         if (retval != STATUS_SUCCESS)
1249                 return STATUS_FAIL;
1250
1251         sd_card->func_group1_mask &= ~(sd_card->sd_switch_fail);
1252
1253         /* Function Group 1: Access Mode */
1254         for (i = 0; i < 4; i++) {
1255                 switch ((u8)(chip->sd_speed_prior >> (i * 8))) {
1256                 case SDR104_SUPPORT:
1257                         if ((sd_card->func_group1_mask & SDR104_SUPPORT_MASK) &&
1258                             chip->sdr104_en) {
1259                                 func_to_switch = SDR104_SUPPORT;
1260                         }
1261                         break;
1262
1263                 case DDR50_SUPPORT:
1264                         if ((sd_card->func_group1_mask & DDR50_SUPPORT_MASK) &&
1265                             chip->ddr50_en) {
1266                                 func_to_switch = DDR50_SUPPORT;
1267                         }
1268                         break;
1269
1270                 case SDR50_SUPPORT:
1271                         if ((sd_card->func_group1_mask & SDR50_SUPPORT_MASK) &&
1272                             chip->sdr50_en) {
1273                                 func_to_switch = SDR50_SUPPORT;
1274                         }
1275                         break;
1276
1277                 case HS_SUPPORT:
1278                         if (sd_card->func_group1_mask & HS_SUPPORT_MASK)
1279                                 func_to_switch = HS_SUPPORT;
1280
1281                         break;
1282
1283                 default:
1284                         continue;
1285                 }
1286
1287                 if (func_to_switch)
1288                         break;
1289         }
1290         dev_dbg(rtsx_dev(chip), "SD_FUNC_GROUP_1: func_to_switch = 0x%02x",
1291                 func_to_switch);
1292
1293 #ifdef SUPPORT_SD_LOCK
1294         if ((sd_card->sd_lock_status & SD_SDR_RST) &&
1295             (func_to_switch == DDR50_SUPPORT) &&
1296             (sd_card->func_group1_mask & SDR50_SUPPORT_MASK)) {
1297                 func_to_switch = SDR50_SUPPORT;
1298                 dev_dbg(rtsx_dev(chip), "Using SDR50 instead of DDR50 for SD Lock\n");
1299         }
1300 #endif
1301
1302         if (func_to_switch) {
1303                 retval = sd_check_switch(chip, SD_FUNC_GROUP_1, func_to_switch,
1304                                          bus_width);
1305                 if (retval != STATUS_SUCCESS) {
1306                         if (func_to_switch == SDR104_SUPPORT) {
1307                                 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK;
1308                         } else if (func_to_switch == DDR50_SUPPORT) {
1309                                 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
1310                                         DDR50_SUPPORT_MASK;
1311                         } else if (func_to_switch == SDR50_SUPPORT) {
1312                                 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
1313                                         DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;
1314                         }
1315                         return STATUS_FAIL;
1316                 }
1317
1318                 if (func_to_switch == SDR104_SUPPORT)
1319                         SET_SD_SDR104(sd_card);
1320                 else if (func_to_switch == DDR50_SUPPORT)
1321                         SET_SD_DDR50(sd_card);
1322                 else if (func_to_switch == SDR50_SUPPORT)
1323                         SET_SD_SDR50(sd_card);
1324                 else
1325                         SET_SD_HS(sd_card);
1326         }
1327
1328         if (CHK_SD_DDR50(sd_card)) {
1329                 retval = rtsx_write_register(chip, SD_PUSH_POINT_CTL, 0x06,
1330                                              0x04);
1331                 if (retval)
1332                         return retval;
1333                 retval = sd_set_sample_push_timing(chip);
1334                 if (retval != STATUS_SUCCESS)
1335                         return STATUS_FAIL;
1336         }
1337
1338         if (!func_to_switch || (func_to_switch == HS_SUPPORT)) {
1339                 /* Do not try to switch current limit if the card doesn't
1340                  * support UHS mode or we don't want it to support UHS mode
1341                  */
1342                 return STATUS_SUCCESS;
1343         }
1344
1345         /* Function Group 4: Current Limit */
1346         func_to_switch = 0xFF;
1347
1348         for (i = 0; i < 4; i++) {
1349                 switch ((u8)(chip->sd_current_prior >> (i * 8))) {
1350                 case CURRENT_LIMIT_800:
1351                         if (sd_card->func_group4_mask & CURRENT_LIMIT_800_MASK)
1352                                 func_to_switch = CURRENT_LIMIT_800;
1353
1354                         break;
1355
1356                 case CURRENT_LIMIT_600:
1357                         if (sd_card->func_group4_mask & CURRENT_LIMIT_600_MASK)
1358                                 func_to_switch = CURRENT_LIMIT_600;
1359
1360                         break;
1361
1362                 case CURRENT_LIMIT_400:
1363                         if (sd_card->func_group4_mask & CURRENT_LIMIT_400_MASK)
1364                                 func_to_switch = CURRENT_LIMIT_400;
1365
1366                         break;
1367
1368                 case CURRENT_LIMIT_200:
1369                         if (sd_card->func_group4_mask & CURRENT_LIMIT_200_MASK)
1370                                 func_to_switch = CURRENT_LIMIT_200;
1371
1372                         break;
1373
1374                 default:
1375                         continue;
1376                 }
1377
1378                 if (func_to_switch != 0xFF)
1379                         break;
1380         }
1381
1382         dev_dbg(rtsx_dev(chip), "SD_FUNC_GROUP_4: func_to_switch = 0x%02x",
1383                 func_to_switch);
1384
1385         if (func_to_switch <= CURRENT_LIMIT_800) {
1386                 retval = sd_check_switch(chip, SD_FUNC_GROUP_4, func_to_switch,
1387                                          bus_width);
1388                 if (retval != STATUS_SUCCESS) {
1389                         if (sd_check_err_code(chip, SD_NO_CARD))
1390                                 return STATUS_FAIL;
1391                 }
1392                 dev_dbg(rtsx_dev(chip), "Switch current limit finished! (%d)\n",
1393                         retval);
1394         }
1395
1396         if (CHK_SD_DDR50(sd_card)) {
1397                 retval = rtsx_write_register(chip, SD_PUSH_POINT_CTL, 0x06, 0);
1398                 if (retval)
1399                         return retval;
1400         }
1401
1402         return STATUS_SUCCESS;
1403 }
1404
1405 static int sd_wait_data_idle(struct rtsx_chip *chip)
1406 {
1407         int retval = STATUS_TIMEDOUT;
1408         int i;
1409         u8 val = 0;
1410
1411         for (i = 0; i < 100; i++) {
1412                 retval = rtsx_read_register(chip, SD_DATA_STATE, &val);
1413                 if (retval)
1414                         return retval;
1415                 if (val & SD_DATA_IDLE) {
1416                         retval = STATUS_SUCCESS;
1417                         break;
1418                 }
1419                 udelay(100);
1420         }
1421         dev_dbg(rtsx_dev(chip), "SD_DATA_STATE: 0x%02x\n", val);
1422
1423         return retval;
1424 }
1425
1426 static int sd_sdr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1427 {
1428         int retval;
1429         u8 cmd[5];
1430
1431         retval = sd_change_phase(chip, sample_point, TUNE_RX);
1432         if (retval != STATUS_SUCCESS)
1433                 return STATUS_FAIL;
1434
1435         cmd[0] = 0x40 | SEND_TUNING_PATTERN;
1436         cmd[1] = 0;
1437         cmd[2] = 0;
1438         cmd[3] = 0;
1439         cmd[4] = 0;
1440
1441         retval = sd_read_data(chip, SD_TM_AUTO_TUNING, cmd, 5, 0x40, 1,
1442                               SD_BUS_WIDTH_4, NULL, 0, 100);
1443         if (retval != STATUS_SUCCESS) {
1444                 (void)sd_wait_data_idle(chip);
1445
1446                 rtsx_clear_sd_error(chip);
1447                 return STATUS_FAIL;
1448         }
1449
1450         return STATUS_SUCCESS;
1451 }
1452
1453 static int sd_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1454 {
1455         struct sd_info *sd_card = &chip->sd_card;
1456         int retval;
1457         u8 cmd[5];
1458
1459         retval = sd_change_phase(chip, sample_point, TUNE_RX);
1460         if (retval != STATUS_SUCCESS)
1461                 return STATUS_FAIL;
1462
1463         dev_dbg(rtsx_dev(chip), "sd ddr tuning rx\n");
1464
1465         retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
1466                                      SD_RSP_TYPE_R1, NULL, 0);
1467         if (retval != STATUS_SUCCESS)
1468                 return STATUS_FAIL;
1469
1470         cmd[0] = 0x40 | SD_STATUS;
1471         cmd[1] = 0;
1472         cmd[2] = 0;
1473         cmd[3] = 0;
1474         cmd[4] = 0;
1475
1476         retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1,
1477                               SD_BUS_WIDTH_4, NULL, 0, 100);
1478         if (retval != STATUS_SUCCESS) {
1479                 (void)sd_wait_data_idle(chip);
1480
1481                 rtsx_clear_sd_error(chip);
1482                 return STATUS_FAIL;
1483         }
1484
1485         return STATUS_SUCCESS;
1486 }
1487
1488 static int mmc_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1489 {
1490         struct sd_info *sd_card = &chip->sd_card;
1491         int retval;
1492         u8 cmd[5], bus_width;
1493
1494         if (CHK_MMC_8BIT(sd_card))
1495                 bus_width = SD_BUS_WIDTH_8;
1496         else if (CHK_MMC_4BIT(sd_card))
1497                 bus_width = SD_BUS_WIDTH_4;
1498         else
1499                 bus_width = SD_BUS_WIDTH_1;
1500
1501         retval = sd_change_phase(chip, sample_point, TUNE_RX);
1502         if (retval != STATUS_SUCCESS)
1503                 return STATUS_FAIL;
1504
1505         dev_dbg(rtsx_dev(chip), "mmc ddr tuning rx\n");
1506
1507         cmd[0] = 0x40 | SEND_EXT_CSD;
1508         cmd[1] = 0;
1509         cmd[2] = 0;
1510         cmd[3] = 0;
1511         cmd[4] = 0;
1512
1513         retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 0x200, 1,
1514                               bus_width, NULL, 0, 100);
1515         if (retval != STATUS_SUCCESS) {
1516                 (void)sd_wait_data_idle(chip);
1517
1518                 rtsx_clear_sd_error(chip);
1519                 return STATUS_FAIL;
1520         }
1521
1522         return STATUS_SUCCESS;
1523 }
1524
1525 static int sd_sdr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1526 {
1527         struct sd_info *sd_card = &chip->sd_card;
1528         int retval;
1529
1530         retval = sd_change_phase(chip, sample_point, TUNE_TX);
1531         if (retval != STATUS_SUCCESS)
1532                 return STATUS_FAIL;
1533
1534         retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1535                                      SD_RSP_80CLK_TIMEOUT_EN);
1536         if (retval)
1537                 return retval;
1538
1539         retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1540                                      SD_RSP_TYPE_R1, NULL, 0);
1541         if (retval != STATUS_SUCCESS) {
1542                 if (sd_check_err_code(chip, SD_RSP_TIMEOUT)) {
1543                         rtsx_write_register(chip, SD_CFG3,
1544                                             SD_RSP_80CLK_TIMEOUT_EN, 0);
1545                         return STATUS_FAIL;
1546                 }
1547         }
1548
1549         retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1550                                      0);
1551         if (retval)
1552                 return retval;
1553
1554         return STATUS_SUCCESS;
1555 }
1556
1557 static int sd_ddr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1558 {
1559         struct sd_info *sd_card = &chip->sd_card;
1560         int retval;
1561         u8 cmd[5], bus_width;
1562
1563         retval = sd_change_phase(chip, sample_point, TUNE_TX);
1564         if (retval != STATUS_SUCCESS)
1565                 return STATUS_FAIL;
1566
1567         if (CHK_SD(sd_card)) {
1568                 bus_width = SD_BUS_WIDTH_4;
1569         } else {
1570                 if (CHK_MMC_8BIT(sd_card))
1571                         bus_width = SD_BUS_WIDTH_8;
1572                 else if (CHK_MMC_4BIT(sd_card))
1573                         bus_width = SD_BUS_WIDTH_4;
1574                 else
1575                         bus_width = SD_BUS_WIDTH_1;
1576         }
1577
1578         retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
1579         if (retval != STATUS_SUCCESS)
1580                 return STATUS_FAIL;
1581
1582         retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1583                                      SD_RSP_80CLK_TIMEOUT_EN);
1584         if (retval)
1585                 return retval;
1586
1587         cmd[0] = 0x40 | PROGRAM_CSD;
1588         cmd[1] = 0;
1589         cmd[2] = 0;
1590         cmd[3] = 0;
1591         cmd[4] = 0;
1592
1593         retval = sd_write_data(chip, SD_TM_AUTO_WRITE_2, cmd, 5, 16, 1,
1594                                bus_width, sd_card->raw_csd, 16, 100);
1595         if (retval != STATUS_SUCCESS) {
1596                 rtsx_clear_sd_error(chip);
1597                 rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1598                 return STATUS_FAIL;
1599         }
1600
1601         retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1602                                      0);
1603         if (retval)
1604                 return retval;
1605
1606         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1,
1607                             NULL, 0);
1608
1609         return STATUS_SUCCESS;
1610 }
1611
1612 static u8 sd_search_final_phase(struct rtsx_chip *chip, u32 phase_map,
1613                                 u8 tune_dir)
1614 {
1615         struct sd_info *sd_card = &chip->sd_card;
1616         struct timing_phase_path path[MAX_PHASE + 1];
1617         int i, j, cont_path_cnt;
1618         bool new_block;
1619         int max_len, final_path_idx;
1620         u8 final_phase = 0xFF;
1621
1622         if (phase_map == 0xFFFFFFFF) {
1623                 if (tune_dir == TUNE_RX)
1624                         final_phase = (u8)chip->sd_default_rx_phase;
1625                 else
1626                         final_phase = (u8)chip->sd_default_tx_phase;
1627
1628                 goto search_finish;
1629         }
1630
1631         cont_path_cnt = 0;
1632         new_block = true;
1633         j = 0;
1634         for (i = 0; i < MAX_PHASE + 1; i++) {
1635                 if (phase_map & (1 << i)) {
1636                         if (new_block) {
1637                                 new_block = false;
1638                                 j = cont_path_cnt++;
1639                                 path[j].start = i;
1640                                 path[j].end = i;
1641                         } else {
1642                                 path[j].end = i;
1643                         }
1644                 } else {
1645                         new_block = true;
1646                         if (cont_path_cnt) {
1647                                 int idx = cont_path_cnt - 1;
1648
1649                                 path[idx].len = path[idx].end -
1650                                         path[idx].start + 1;
1651                                 path[idx].mid = path[idx].start +
1652                                         path[idx].len / 2;
1653                         }
1654                 }
1655         }
1656
1657         if (cont_path_cnt == 0) {
1658                 dev_dbg(rtsx_dev(chip), "No continuous phase path\n");
1659                 goto search_finish;
1660         } else {
1661                 int idx = cont_path_cnt - 1;
1662
1663                 path[idx].len = path[idx].end - path[idx].start + 1;
1664                 path[idx].mid = path[idx].start + path[idx].len / 2;
1665         }
1666
1667         if ((path[0].start == 0) &&
1668             (path[cont_path_cnt - 1].end == MAX_PHASE)) {
1669                 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
1670                 path[0].len += path[cont_path_cnt - 1].len;
1671                 path[0].mid = path[0].start + path[0].len / 2;
1672                 if (path[0].mid < 0)
1673                         path[0].mid += MAX_PHASE + 1;
1674
1675                 cont_path_cnt--;
1676         }
1677
1678         max_len = 0;
1679         final_phase = 0;
1680         final_path_idx = 0;
1681         for (i = 0; i < cont_path_cnt; i++) {
1682                 if (path[i].len > max_len) {
1683                         max_len = path[i].len;
1684                         final_phase = (u8)path[i].mid;
1685                         final_path_idx = i;
1686                 }
1687
1688                 dev_dbg(rtsx_dev(chip), "path[%d].start = %d\n",
1689                         i, path[i].start);
1690                 dev_dbg(rtsx_dev(chip), "path[%d].end = %d\n", i, path[i].end);
1691                 dev_dbg(rtsx_dev(chip), "path[%d].len = %d\n", i, path[i].len);
1692                 dev_dbg(rtsx_dev(chip), "path[%d].mid = %d\n", i, path[i].mid);
1693                 dev_dbg(rtsx_dev(chip), "\n");
1694         }
1695
1696         if (tune_dir == TUNE_TX) {
1697                 if (CHK_SD_SDR104(sd_card)) {
1698                         if (max_len > 15) {
1699                                 int temp_mid = (max_len - 16) / 2;
1700                                 int temp_final_phase =
1701                                         path[final_path_idx].end -
1702                                         (max_len - (6 + temp_mid));
1703
1704                                 if (temp_final_phase < 0)
1705                                         final_phase = (u8)(temp_final_phase +
1706                                                         MAX_PHASE + 1);
1707                                 else
1708                                         final_phase = (u8)temp_final_phase;
1709                         }
1710                 } else if (CHK_SD_SDR50(sd_card)) {
1711                         if (max_len > 12) {
1712                                 int temp_mid = (max_len - 13) / 2;
1713                                 int temp_final_phase =
1714                                         path[final_path_idx].end -
1715                                         (max_len - (3 + temp_mid));
1716
1717                                 if (temp_final_phase < 0)
1718                                         final_phase = (u8)(temp_final_phase +
1719                                                         MAX_PHASE + 1);
1720                                 else
1721                                         final_phase = (u8)temp_final_phase;
1722                         }
1723                 }
1724         }
1725
1726 search_finish:
1727         dev_dbg(rtsx_dev(chip), "Final chosen phase: %d\n", final_phase);
1728         return final_phase;
1729 }
1730
1731 static int sd_tuning_rx(struct rtsx_chip *chip)
1732 {
1733         struct sd_info *sd_card = &chip->sd_card;
1734         int retval;
1735         int i, j;
1736         u32 raw_phase_map[3], phase_map;
1737         u8 final_phase;
1738         int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1739
1740         if (CHK_SD(sd_card)) {
1741                 if (CHK_SD_DDR50(sd_card))
1742                         tuning_cmd = sd_ddr_tuning_rx_cmd;
1743                 else
1744                         tuning_cmd = sd_sdr_tuning_rx_cmd;
1745
1746         } else {
1747                 if (CHK_MMC_DDR52(sd_card))
1748                         tuning_cmd = mmc_ddr_tuning_rx_cmd;
1749                 else
1750                         return STATUS_FAIL;
1751         }
1752
1753         for (i = 0; i < 3; i++) {
1754                 raw_phase_map[i] = 0;
1755                 for (j = MAX_PHASE; j >= 0; j--) {
1756                         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1757                                 sd_set_err_code(chip, SD_NO_CARD);
1758                                 return STATUS_FAIL;
1759                         }
1760
1761                         retval = tuning_cmd(chip, (u8)j);
1762                         if (retval == STATUS_SUCCESS)
1763                                 raw_phase_map[i] |= 1 << j;
1764                 }
1765         }
1766
1767         phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1768         for (i = 0; i < 3; i++)
1769                 dev_dbg(rtsx_dev(chip), "RX raw_phase_map[%d] = 0x%08x\n",
1770                         i, raw_phase_map[i]);
1771
1772         dev_dbg(rtsx_dev(chip), "RX phase_map = 0x%08x\n", phase_map);
1773
1774         final_phase = sd_search_final_phase(chip, phase_map, TUNE_RX);
1775         if (final_phase == 0xFF)
1776                 return STATUS_FAIL;
1777
1778         retval = sd_change_phase(chip, final_phase, TUNE_RX);
1779         if (retval != STATUS_SUCCESS)
1780                 return STATUS_FAIL;
1781
1782         return STATUS_SUCCESS;
1783 }
1784
1785 static int sd_ddr_pre_tuning_tx(struct rtsx_chip *chip)
1786 {
1787         struct sd_info *sd_card = &chip->sd_card;
1788         int retval;
1789         int i;
1790         u32 phase_map;
1791         u8 final_phase;
1792
1793         retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1794                                      SD_RSP_80CLK_TIMEOUT_EN);
1795         if (retval)
1796                 return retval;
1797
1798         phase_map = 0;
1799         for (i = MAX_PHASE; i >= 0; i--) {
1800                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1801                         sd_set_err_code(chip, SD_NO_CARD);
1802                         rtsx_write_register(chip, SD_CFG3,
1803                                             SD_RSP_80CLK_TIMEOUT_EN, 0);
1804                         return STATUS_FAIL;
1805                 }
1806
1807                 retval = sd_change_phase(chip, (u8)i, TUNE_TX);
1808                 if (retval != STATUS_SUCCESS)
1809                         continue;
1810
1811                 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
1812                                              sd_card->sd_addr, SD_RSP_TYPE_R1,
1813                                              NULL, 0);
1814                 if ((retval == STATUS_SUCCESS) ||
1815                     !sd_check_err_code(chip, SD_RSP_TIMEOUT))
1816                         phase_map |= 1 << i;
1817         }
1818
1819         retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1820                                      0);
1821         if (retval)
1822                 return retval;
1823
1824         dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase_map = 0x%08x\n",
1825                 phase_map);
1826
1827         final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1828         if (final_phase == 0xFF)
1829                 return STATUS_FAIL;
1830
1831         retval = sd_change_phase(chip, final_phase, TUNE_TX);
1832         if (retval != STATUS_SUCCESS)
1833                 return STATUS_FAIL;
1834
1835         dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase: %d\n",
1836                 (int)final_phase);
1837
1838         return STATUS_SUCCESS;
1839 }
1840
1841 static int sd_tuning_tx(struct rtsx_chip *chip)
1842 {
1843         struct sd_info *sd_card = &chip->sd_card;
1844         int retval;
1845         int i, j;
1846         u32 raw_phase_map[3], phase_map;
1847         u8 final_phase;
1848         int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1849
1850         if (CHK_SD(sd_card)) {
1851                 if (CHK_SD_DDR50(sd_card))
1852                         tuning_cmd = sd_ddr_tuning_tx_cmd;
1853                 else
1854                         tuning_cmd = sd_sdr_tuning_tx_cmd;
1855
1856         } else {
1857                 if (CHK_MMC_DDR52(sd_card))
1858                         tuning_cmd = sd_ddr_tuning_tx_cmd;
1859                 else
1860                         return STATUS_FAIL;
1861         }
1862
1863         for (i = 0; i < 3; i++) {
1864                 raw_phase_map[i] = 0;
1865                 for (j = MAX_PHASE; j >= 0; j--) {
1866                         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1867                                 sd_set_err_code(chip, SD_NO_CARD);
1868                                 rtsx_write_register(chip, SD_CFG3,
1869                                                     SD_RSP_80CLK_TIMEOUT_EN, 0);
1870                                 return STATUS_FAIL;
1871                         }
1872
1873                         retval = tuning_cmd(chip, (u8)j);
1874                         if (retval == STATUS_SUCCESS)
1875                                 raw_phase_map[i] |= 1 << j;
1876                 }
1877         }
1878
1879         phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1880         for (i = 0; i < 3; i++)
1881                 dev_dbg(rtsx_dev(chip), "TX raw_phase_map[%d] = 0x%08x\n",
1882                         i, raw_phase_map[i]);
1883
1884         dev_dbg(rtsx_dev(chip), "TX phase_map = 0x%08x\n", phase_map);
1885
1886         final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1887         if (final_phase == 0xFF)
1888                 return STATUS_FAIL;
1889
1890         retval = sd_change_phase(chip, final_phase, TUNE_TX);
1891         if (retval != STATUS_SUCCESS)
1892                 return STATUS_FAIL;
1893
1894         return STATUS_SUCCESS;
1895 }
1896
1897 static int sd_sdr_tuning(struct rtsx_chip *chip)
1898 {
1899         int retval;
1900
1901         retval = sd_tuning_tx(chip);
1902         if (retval != STATUS_SUCCESS)
1903                 return STATUS_FAIL;
1904
1905         retval = sd_tuning_rx(chip);
1906         if (retval != STATUS_SUCCESS)
1907                 return STATUS_FAIL;
1908
1909         return STATUS_SUCCESS;
1910 }
1911
1912 static int sd_ddr_tuning(struct rtsx_chip *chip)
1913 {
1914         int retval;
1915
1916         if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1917                 retval = sd_ddr_pre_tuning_tx(chip);
1918                 if (retval != STATUS_SUCCESS)
1919                         return STATUS_FAIL;
1920         } else {
1921                 retval = sd_change_phase(chip, (u8)chip->sd_ddr_tx_phase,
1922                                          TUNE_TX);
1923                 if (retval != STATUS_SUCCESS)
1924                         return STATUS_FAIL;
1925         }
1926
1927         retval = sd_tuning_rx(chip);
1928         if (retval != STATUS_SUCCESS)
1929                 return STATUS_FAIL;
1930
1931         if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1932                 retval = sd_tuning_tx(chip);
1933                 if (retval != STATUS_SUCCESS)
1934                         return STATUS_FAIL;
1935         }
1936
1937         return STATUS_SUCCESS;
1938 }
1939
1940 static int mmc_ddr_tuning(struct rtsx_chip *chip)
1941 {
1942         int retval;
1943
1944         if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1945                 retval = sd_ddr_pre_tuning_tx(chip);
1946                 if (retval != STATUS_SUCCESS)
1947                         return STATUS_FAIL;
1948         } else {
1949                 retval = sd_change_phase(chip, (u8)chip->mmc_ddr_tx_phase,
1950                                          TUNE_TX);
1951                 if (retval != STATUS_SUCCESS)
1952                         return STATUS_FAIL;
1953         }
1954
1955         retval = sd_tuning_rx(chip);
1956         if (retval != STATUS_SUCCESS)
1957                 return STATUS_FAIL;
1958
1959         if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1960                 retval = sd_tuning_tx(chip);
1961                 if (retval != STATUS_SUCCESS)
1962                         return STATUS_FAIL;
1963         }
1964
1965         return STATUS_SUCCESS;
1966 }
1967
1968 int sd_switch_clock(struct rtsx_chip *chip)
1969 {
1970         struct sd_info *sd_card = &chip->sd_card;
1971         int retval;
1972         int re_tuning = 0;
1973
1974         retval = select_card(chip, SD_CARD);
1975         if (retval != STATUS_SUCCESS)
1976                 return STATUS_FAIL;
1977
1978         retval = switch_clock(chip, sd_card->sd_clock);
1979         if (retval != STATUS_SUCCESS)
1980                 return STATUS_FAIL;
1981
1982         if (re_tuning) {
1983                 if (CHK_SD(sd_card)) {
1984                         if (CHK_SD_DDR50(sd_card))
1985                                 retval = sd_ddr_tuning(chip);
1986                         else
1987                                 retval = sd_sdr_tuning(chip);
1988                 } else {
1989                         if (CHK_MMC_DDR52(sd_card))
1990                                 retval = mmc_ddr_tuning(chip);
1991                 }
1992
1993                 if (retval != STATUS_SUCCESS)
1994                         return STATUS_FAIL;
1995         }
1996
1997         return STATUS_SUCCESS;
1998 }
1999
2000 static int sd_prepare_reset(struct rtsx_chip *chip)
2001 {
2002         struct sd_info *sd_card = &chip->sd_card;
2003         int retval;
2004
2005         if (chip->asic_code)
2006                 sd_card->sd_clock = 29;
2007         else
2008                 sd_card->sd_clock = CLK_30;
2009
2010         sd_card->sd_type = 0;
2011         sd_card->seq_mode = 0;
2012         sd_card->sd_data_buf_ready = 0;
2013         sd_card->capacity = 0;
2014
2015 #ifdef SUPPORT_SD_LOCK
2016         sd_card->sd_lock_status = 0;
2017         sd_card->sd_erase_status = 0;
2018 #endif
2019
2020         chip->capacity[chip->card2lun[SD_CARD]] = 0;
2021         chip->sd_io = 0;
2022
2023         retval = sd_set_init_para(chip);
2024         if (retval != STATUS_SUCCESS)
2025                 return retval;
2026
2027         retval = rtsx_write_register(chip, REG_SD_CFG1, 0xFF, 0x40);
2028         if (retval)
2029                 return retval;
2030
2031         retval = rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR,
2032                                      SD_STOP | SD_CLR_ERR);
2033         if (retval)
2034                 return retval;
2035
2036         retval = select_card(chip, SD_CARD);
2037         if (retval != STATUS_SUCCESS)
2038                 return STATUS_FAIL;
2039
2040         return STATUS_SUCCESS;
2041 }
2042
2043 static int sd_pull_ctl_disable(struct rtsx_chip *chip)
2044 {
2045         int retval;
2046
2047         if (CHECK_PID(chip, 0x5208)) {
2048                 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF,
2049                                              XD_D3_PD | SD_D7_PD | SD_CLK_PD |
2050                                              SD_D5_PD);
2051                 if (retval)
2052                         return retval;
2053                 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF,
2054                                              SD_D6_PD | SD_D0_PD | SD_D1_PD |
2055                                              XD_D5_PD);
2056                 if (retval)
2057                         return retval;
2058                 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF,
2059                                              SD_D4_PD | XD_CE_PD | XD_CLE_PD |
2060                                              XD_CD_PU);
2061                 if (retval)
2062                         return retval;
2063                 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF,
2064                                              XD_RDY_PD | SD_D3_PD | SD_D2_PD |
2065                                              XD_ALE_PD);
2066                 if (retval)
2067                         return retval;
2068                 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF,
2069                                              MS_INS_PU | SD_WP_PD | SD_CD_PU |
2070                                              SD_CMD_PD);
2071                 if (retval)
2072                         return retval;
2073                 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF,
2074                                              MS_D5_PD | MS_D4_PD);
2075                 if (retval)
2076                         return retval;
2077         } else if (CHECK_PID(chip, 0x5288)) {
2078                 if (CHECK_BARO_PKG(chip, QFN)) {
2079                         retval = rtsx_write_register(chip, CARD_PULL_CTL1,
2080                                                      0xFF, 0x55);
2081                         if (retval)
2082                                 return retval;
2083                         retval = rtsx_write_register(chip, CARD_PULL_CTL2,
2084                                                      0xFF, 0x55);
2085                         if (retval)
2086                                 return retval;
2087                         retval = rtsx_write_register(chip, CARD_PULL_CTL3,
2088                                                      0xFF, 0x4B);
2089                         if (retval)
2090                                 return retval;
2091                         retval = rtsx_write_register(chip, CARD_PULL_CTL4,
2092                                                      0xFF, 0x69);
2093                         if (retval)
2094                                 return retval;
2095                 }
2096         }
2097
2098         return STATUS_SUCCESS;
2099 }
2100
2101 int sd_pull_ctl_enable(struct rtsx_chip *chip)
2102 {
2103         int retval;
2104
2105         rtsx_init_cmd(chip);
2106
2107         if (CHECK_PID(chip, 0x5208)) {
2108                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
2109                              XD_D3_PD | SD_DAT7_PU | SD_CLK_NP | SD_D5_PU);
2110                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
2111                              SD_D6_PU | SD_D0_PU | SD_D1_PU | XD_D5_PD);
2112                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
2113                              SD_D4_PU | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
2114                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
2115                              XD_RDY_PD | SD_D3_PU | SD_D2_PU | XD_ALE_PD);
2116                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
2117                              MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
2118                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
2119                              MS_D5_PD | MS_D4_PD);
2120         } else if (CHECK_PID(chip, 0x5288)) {
2121                 if (CHECK_BARO_PKG(chip, QFN)) {
2122                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
2123                                      0xA8);
2124                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
2125                                      0x5A);
2126                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
2127                                      0x95);
2128                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
2129                                      0xAA);
2130                 }
2131         }
2132
2133         retval = rtsx_send_cmd(chip, SD_CARD, 100);
2134         if (retval < 0)
2135                 return STATUS_FAIL;
2136
2137         return STATUS_SUCCESS;
2138 }
2139
2140 static int sd_init_power(struct rtsx_chip *chip)
2141 {
2142         int retval;
2143
2144         retval = sd_power_off_card3v3(chip);
2145         if (retval != STATUS_SUCCESS)
2146                 return STATUS_FAIL;
2147
2148         if (!chip->ft2_fast_mode)
2149                 wait_timeout(250);
2150
2151         retval = enable_card_clock(chip, SD_CARD);
2152         if (retval != STATUS_SUCCESS)
2153                 return STATUS_FAIL;
2154
2155         if (chip->asic_code) {
2156                 retval = sd_pull_ctl_enable(chip);
2157                 if (retval != STATUS_SUCCESS)
2158                         return STATUS_FAIL;
2159         } else {
2160                 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
2161                                              FPGA_SD_PULL_CTL_BIT | 0x20, 0);
2162                 if (retval)
2163                         return retval;
2164         }
2165
2166         if (!chip->ft2_fast_mode) {
2167                 retval = card_power_on(chip, SD_CARD);
2168                 if (retval != STATUS_SUCCESS)
2169                         return STATUS_FAIL;
2170
2171                 wait_timeout(260);
2172
2173 #ifdef SUPPORT_OCP
2174                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
2175                         dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
2176                                 chip->ocp_stat);
2177                         return STATUS_FAIL;
2178                 }
2179 #endif
2180         }
2181
2182         retval = rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN,
2183                                      SD_OUTPUT_EN);
2184         if (retval)
2185                 return retval;
2186
2187         return STATUS_SUCCESS;
2188 }
2189
2190 static int sd_dummy_clock(struct rtsx_chip *chip)
2191 {
2192         int retval;
2193
2194         retval = rtsx_write_register(chip, REG_SD_CFG3, 0x01, 0x01);
2195         if (retval)
2196                 return retval;
2197         wait_timeout(5);
2198         retval = rtsx_write_register(chip, REG_SD_CFG3, 0x01, 0);
2199         if (retval)
2200                 return retval;
2201
2202         return STATUS_SUCCESS;
2203 }
2204
2205 static int sd_read_lba0(struct rtsx_chip *chip)
2206 {
2207         struct sd_info *sd_card = &chip->sd_card;
2208         int retval;
2209         u8 cmd[5], bus_width;
2210
2211         cmd[0] = 0x40 | READ_SINGLE_BLOCK;
2212         cmd[1] = 0;
2213         cmd[2] = 0;
2214         cmd[3] = 0;
2215         cmd[4] = 0;
2216
2217         if (CHK_SD(sd_card)) {
2218                 bus_width = SD_BUS_WIDTH_4;
2219         } else {
2220                 if (CHK_MMC_8BIT(sd_card))
2221                         bus_width = SD_BUS_WIDTH_8;
2222                 else if (CHK_MMC_4BIT(sd_card))
2223                         bus_width = SD_BUS_WIDTH_4;
2224                 else
2225                         bus_width = SD_BUS_WIDTH_1;
2226         }
2227
2228         retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 512, 1,
2229                               bus_width, NULL, 0, 100);
2230         if (retval != STATUS_SUCCESS) {
2231                 rtsx_clear_sd_error(chip);
2232                 return STATUS_FAIL;
2233         }
2234
2235         return STATUS_SUCCESS;
2236 }
2237
2238 static int sd_check_wp_state(struct rtsx_chip *chip)
2239 {
2240         struct sd_info *sd_card = &chip->sd_card;
2241         int retval;
2242         u32 val;
2243         u16 sd_card_type;
2244         u8 cmd[5], buf[64];
2245
2246         retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2247                                      SD_RSP_TYPE_R1, NULL, 0);
2248         if (retval != STATUS_SUCCESS)
2249                 return STATUS_FAIL;
2250
2251         cmd[0] = 0x40 | SD_STATUS;
2252         cmd[1] = 0;
2253         cmd[2] = 0;
2254         cmd[3] = 0;
2255         cmd[4] = 0;
2256
2257         retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1,
2258                               SD_BUS_WIDTH_4, buf, 64, 250);
2259         if (retval != STATUS_SUCCESS) {
2260                 rtsx_clear_sd_error(chip);
2261
2262                 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2263                                     SD_RSP_TYPE_R1, NULL, 0);
2264                 return STATUS_FAIL;
2265         }
2266
2267         dev_dbg(rtsx_dev(chip), "ACMD13:\n");
2268         dev_dbg(rtsx_dev(chip), "%*ph\n", 64, buf);
2269
2270         sd_card_type = ((u16)buf[2] << 8) | buf[3];
2271         dev_dbg(rtsx_dev(chip), "sd_card_type = 0x%04x\n", sd_card_type);
2272         if ((sd_card_type == 0x0001) || (sd_card_type == 0x0002)) {
2273                 /* ROM card or OTP */
2274                 chip->card_wp |= SD_CARD;
2275         }
2276
2277         /* Check SD Machanical Write-Protect Switch */
2278         val = rtsx_readl(chip, RTSX_BIPR);
2279         if (val & SD_WRITE_PROTECT)
2280                 chip->card_wp |= SD_CARD;
2281
2282         return STATUS_SUCCESS;
2283 }
2284
2285 static int reset_sd(struct rtsx_chip *chip)
2286 {
2287         struct sd_info *sd_card = &chip->sd_card;
2288         bool hi_cap_flow = false;
2289         int retval, i = 0, j = 0, k = 0;
2290         bool sd_dont_switch = false;
2291         bool support_1v8 = false;
2292         bool try_sdio = true;
2293         u8 rsp[16];
2294         u8 switch_bus_width;
2295         u32 voltage = 0;
2296         bool sd20_mode = false;
2297
2298         SET_SD(sd_card);
2299
2300 switch_fail:
2301
2302         i = 0;
2303         j = 0;
2304         k = 0;
2305         hi_cap_flow = false;
2306
2307 #ifdef SUPPORT_SD_LOCK
2308         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2309                 goto SD_UNLOCK_ENTRY;
2310 #endif
2311
2312         retval = sd_prepare_reset(chip);
2313         if (retval != STATUS_SUCCESS)
2314                 goto status_fail;
2315
2316         retval = sd_dummy_clock(chip);
2317         if (retval != STATUS_SUCCESS)
2318                 goto status_fail;
2319
2320         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && try_sdio) {
2321                 int rty_cnt = 0;
2322
2323                 for (; rty_cnt < chip->sdio_retry_cnt; rty_cnt++) {
2324                         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2325                                 sd_set_err_code(chip, SD_NO_CARD);
2326                                 goto status_fail;
2327                         }
2328
2329                         retval = sd_send_cmd_get_rsp(chip, IO_SEND_OP_COND, 0,
2330                                                      SD_RSP_TYPE_R4, rsp, 5);
2331                         if (retval == STATUS_SUCCESS) {
2332                                 int func_num = (rsp[1] >> 4) & 0x07;
2333
2334                                 if (func_num) {
2335                                         dev_dbg(rtsx_dev(chip), "SD_IO card (Function number: %d)!\n",
2336                                                 func_num);
2337                                         chip->sd_io = 1;
2338                                         goto status_fail;
2339                                 }
2340
2341                                 break;
2342                         }
2343
2344                         sd_init_power(chip);
2345
2346                         sd_dummy_clock(chip);
2347                 }
2348
2349                 dev_dbg(rtsx_dev(chip), "Normal card!\n");
2350         }
2351
2352         /* Start Initialization Process of SD Card */
2353 RTY_SD_RST:
2354         retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0,
2355                                      NULL, 0);
2356         if (retval != STATUS_SUCCESS)
2357                 goto status_fail;
2358
2359         wait_timeout(20);
2360
2361         retval = sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA,
2362                                      SD_RSP_TYPE_R7, rsp, 5);
2363         if (retval == STATUS_SUCCESS) {
2364                 if ((rsp[4] == 0xAA) && ((rsp[3] & 0x0f) == 0x01)) {
2365                         hi_cap_flow = true;
2366                         voltage = SUPPORT_VOLTAGE | 0x40000000;
2367                 }
2368         }
2369
2370         if (!hi_cap_flow) {
2371                 voltage = SUPPORT_VOLTAGE;
2372
2373                 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0,
2374                                              SD_RSP_TYPE_R0, NULL, 0);
2375                 if (retval != STATUS_SUCCESS)
2376                         goto status_fail;
2377
2378                 wait_timeout(20);
2379         }
2380
2381         do {
2382                 retval = sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1,
2383                                              NULL, 0);
2384                 if (retval != STATUS_SUCCESS) {
2385                         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2386                                 sd_set_err_code(chip, SD_NO_CARD);
2387                                 goto status_fail;
2388                         }
2389
2390                         j++;
2391                         if (j < 3)
2392                                 goto RTY_SD_RST;
2393                         else
2394                                 goto status_fail;
2395                 }
2396
2397                 retval = sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage,
2398                                              SD_RSP_TYPE_R3, rsp, 5);
2399                 if (retval != STATUS_SUCCESS) {
2400                         k++;
2401                         if (k < 3)
2402                                 goto RTY_SD_RST;
2403                         else
2404                                 goto status_fail;
2405                 }
2406
2407                 i++;
2408                 wait_timeout(20);
2409         } while (!(rsp[1] & 0x80) && (i < 255));
2410
2411         if (i == 255)
2412                 goto status_fail;
2413
2414         if (hi_cap_flow) {
2415                 if (rsp[1] & 0x40)
2416                         SET_SD_HCXC(sd_card);
2417                 else
2418                         CLR_SD_HCXC(sd_card);
2419
2420                 support_1v8 = false;
2421         } else {
2422                 CLR_SD_HCXC(sd_card);
2423                 support_1v8 = false;
2424         }
2425         dev_dbg(rtsx_dev(chip), "support_1v8 = %d\n", support_1v8);
2426
2427         if (support_1v8) {
2428                 retval = sd_voltage_switch(chip);
2429                 if (retval != STATUS_SUCCESS)
2430                         goto status_fail;
2431         }
2432
2433         retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2,
2434                                      NULL, 0);
2435         if (retval != STATUS_SUCCESS)
2436                 goto status_fail;
2437
2438         for (i = 0; i < 3; i++) {
2439                 retval = sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0,
2440                                              SD_RSP_TYPE_R6, rsp, 5);
2441                 if (retval != STATUS_SUCCESS)
2442                         goto status_fail;
2443
2444                 sd_card->sd_addr = (u32)rsp[1] << 24;
2445                 sd_card->sd_addr += (u32)rsp[2] << 16;
2446
2447                 if (sd_card->sd_addr)
2448                         break;
2449         }
2450
2451         retval = sd_check_csd(chip, 1);
2452         if (retval != STATUS_SUCCESS)
2453                 goto status_fail;
2454
2455         retval = sd_select_card(chip, 1);
2456         if (retval != STATUS_SUCCESS)
2457                 goto status_fail;
2458
2459 #ifdef SUPPORT_SD_LOCK
2460 SD_UNLOCK_ENTRY:
2461         retval = sd_update_lock_status(chip);
2462         if (retval != STATUS_SUCCESS)
2463                 goto status_fail;
2464
2465         if (sd_card->sd_lock_status & SD_LOCKED) {
2466                 sd_card->sd_lock_status |= (SD_LOCK_1BIT_MODE | SD_PWD_EXIST);
2467                 return STATUS_SUCCESS;
2468         } else if (!(sd_card->sd_lock_status & SD_UNLOCK_POW_ON)) {
2469                 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
2470         }
2471 #endif
2472
2473         retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2474                                      SD_RSP_TYPE_R1, NULL, 0);
2475         if (retval != STATUS_SUCCESS)
2476                 goto status_fail;
2477
2478         retval = sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0,
2479                                      SD_RSP_TYPE_R1, NULL, 0);
2480         if (retval != STATUS_SUCCESS)
2481                 goto status_fail;
2482
2483         if (support_1v8) {
2484                 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2485                                              SD_RSP_TYPE_R1, NULL, 0);
2486                 if (retval != STATUS_SUCCESS)
2487                         goto status_fail;
2488
2489                 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2,
2490                                              SD_RSP_TYPE_R1, NULL, 0);
2491                 if (retval != STATUS_SUCCESS)
2492                         goto status_fail;
2493
2494                 switch_bus_width = SD_BUS_WIDTH_4;
2495         } else {
2496                 switch_bus_width = SD_BUS_WIDTH_1;
2497         }
2498
2499         retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1,
2500                                      NULL, 0);
2501         if (retval != STATUS_SUCCESS)
2502                 goto status_fail;
2503
2504         retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2505         if (retval != STATUS_SUCCESS)
2506                 goto status_fail;
2507
2508         if (!(sd_card->raw_csd[4] & 0x40))
2509                 sd_dont_switch = true;
2510
2511         if (!sd_dont_switch) {
2512                 if (sd20_mode) {
2513                         /* Set sd_switch_fail here, because we needn't
2514                          * switch to UHS mode
2515                          */
2516                         sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
2517                                 DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;
2518                 }
2519
2520                 /* Check the card whether follow SD1.1 spec or higher */
2521                 retval = sd_check_spec(chip, switch_bus_width);
2522                 if (retval == STATUS_SUCCESS) {
2523                         retval = sd_switch_function(chip, switch_bus_width);
2524                         if (retval != STATUS_SUCCESS) {
2525                                 sd_init_power(chip);
2526                                 sd_dont_switch = true;
2527                                 try_sdio = false;
2528
2529                                 goto switch_fail;
2530                         }
2531                 } else {
2532                         if (support_1v8) {
2533                                 sd_init_power(chip);
2534                                 sd_dont_switch = true;
2535                                 try_sdio = false;
2536
2537                                 goto switch_fail;
2538                         }
2539                 }
2540         }
2541
2542         if (!support_1v8) {
2543                 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2544                                              SD_RSP_TYPE_R1, NULL, 0);
2545                 if (retval != STATUS_SUCCESS)
2546                         goto status_fail;
2547
2548                 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2,
2549                                              SD_RSP_TYPE_R1, NULL, 0);
2550                 if (retval != STATUS_SUCCESS)
2551                         goto status_fail;
2552         }
2553
2554 #ifdef SUPPORT_SD_LOCK
2555         sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2556 #endif
2557
2558         if (!sd20_mode && CHK_SD30_SPEED(sd_card)) {
2559                 int read_lba0 = 1;
2560
2561                 retval = rtsx_write_register(chip, SD30_DRIVE_SEL, 0x07,
2562                                              chip->sd30_drive_sel_1v8);
2563                 if (retval)
2564                         return retval;
2565
2566                 retval = sd_set_init_para(chip);
2567                 if (retval != STATUS_SUCCESS)
2568                         goto status_fail;
2569
2570                 if (CHK_SD_DDR50(sd_card))
2571                         retval = sd_ddr_tuning(chip);
2572                 else
2573                         retval = sd_sdr_tuning(chip);
2574
2575                 if (retval != STATUS_SUCCESS) {
2576                         if (sd20_mode) {
2577                                 goto status_fail;
2578                         } else {
2579                                 retval = sd_init_power(chip);
2580                                 if (retval != STATUS_SUCCESS)
2581                                         goto status_fail;
2582
2583                                 try_sdio = false;
2584                                 sd20_mode = true;
2585                                 goto switch_fail;
2586                         }
2587                 }
2588
2589                 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2590                                     SD_RSP_TYPE_R1, NULL, 0);
2591
2592                 if (CHK_SD_DDR50(sd_card)) {
2593                         retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
2594                         if (retval != STATUS_SUCCESS)
2595                                 read_lba0 = 0;
2596                 }
2597
2598                 if (read_lba0) {
2599                         retval = sd_read_lba0(chip);
2600                         if (retval != STATUS_SUCCESS) {
2601                                 if (sd20_mode) {
2602                                         goto status_fail;
2603                                 } else {
2604                                         retval = sd_init_power(chip);
2605                                         if (retval != STATUS_SUCCESS)
2606                                                 goto status_fail;
2607
2608                                         try_sdio = false;
2609                                         sd20_mode = true;
2610                                         goto switch_fail;
2611                                 }
2612                         }
2613                 }
2614         }
2615
2616         retval = sd_check_wp_state(chip);
2617         if (retval != STATUS_SUCCESS)
2618                 goto status_fail;
2619
2620         chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2621
2622 #ifdef SUPPORT_SD_LOCK
2623         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
2624                 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF,
2625                                              0x02);
2626                 if (retval)
2627                         return retval;
2628                 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF,
2629                                              0x00);
2630                 if (retval)
2631                         return retval;
2632         }
2633 #endif
2634
2635         return STATUS_SUCCESS;
2636
2637 status_fail:
2638         return STATUS_FAIL;
2639 }
2640
2641 static int mmc_test_switch_bus(struct rtsx_chip *chip, u8 width)
2642 {
2643         struct sd_info *sd_card = &chip->sd_card;
2644         int retval;
2645         u8 buf[8] = {0}, bus_width, *ptr;
2646         u16 byte_cnt;
2647         int len;
2648
2649         retval = sd_send_cmd_get_rsp(chip, BUSTEST_W, 0, SD_RSP_TYPE_R1, NULL,
2650                                      0);
2651         if (retval != STATUS_SUCCESS)
2652                 return SWITCH_FAIL;
2653
2654         if (width == MMC_8BIT_BUS) {
2655                 buf[0] = 0x55;
2656                 buf[1] = 0xAA;
2657                 len = 8;
2658                 byte_cnt = 8;
2659                 bus_width = SD_BUS_WIDTH_8;
2660         } else {
2661                 buf[0] = 0x5A;
2662                 len = 4;
2663                 byte_cnt = 4;
2664                 bus_width = SD_BUS_WIDTH_4;
2665         }
2666
2667         retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0x02);
2668         if (retval != STATUS_SUCCESS)
2669                 return SWITCH_ERR;
2670
2671         retval = sd_write_data(chip, SD_TM_AUTO_WRITE_3, NULL, 0, byte_cnt, 1,
2672                                bus_width, buf, len, 100);
2673         if (retval != STATUS_SUCCESS) {
2674                 rtsx_clear_sd_error(chip);
2675                 rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2676                 return SWITCH_ERR;
2677         }
2678
2679         retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2680         if (retval != STATUS_SUCCESS)
2681                 return SWITCH_ERR;
2682
2683         dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", BUSTEST_R);
2684
2685         rtsx_init_cmd(chip);
2686
2687         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | BUSTEST_R);
2688
2689         if (width == MMC_8BIT_BUS)
2690                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L,
2691                              0xFF, 0x08);
2692         else
2693                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L,
2694                              0xFF, 0x04);
2695
2696         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2697         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2698
2699         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, SD_CALCULATE_CRC7 |
2700                      SD_NO_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
2701                      SD_CHECK_CRC7 | SD_RSP_LEN_6);
2702         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
2703                      PINGPONG_BUFFER);
2704         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
2705                      SD_TM_NORMAL_READ | SD_TRANSFER_START);
2706         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
2707                      SD_TRANSFER_END);
2708
2709         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0);
2710         if (width == MMC_8BIT_BUS)
2711                 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0);
2712
2713         retval = rtsx_send_cmd(chip, SD_CARD, 100);
2714         if (retval < 0) {
2715                 rtsx_clear_sd_error(chip);
2716                 return SWITCH_ERR;
2717         }
2718
2719         ptr = rtsx_get_cmd_data(chip) + 1;
2720
2721         if (width == MMC_8BIT_BUS) {
2722                 dev_dbg(rtsx_dev(chip), "BUSTEST_R [8bits]: 0x%02x 0x%02x\n",
2723                         ptr[0], ptr[1]);
2724                 if ((ptr[0] == 0xAA) && (ptr[1] == 0x55)) {
2725                         u8 rsp[5];
2726                         u32 arg;
2727
2728                         if (CHK_MMC_DDR52(sd_card))
2729                                 arg = 0x03B70600;
2730                         else
2731                                 arg = 0x03B70200;
2732
2733                         retval = sd_send_cmd_get_rsp(chip, SWITCH, arg,
2734                                                      SD_RSP_TYPE_R1b, rsp, 5);
2735                         if ((retval == STATUS_SUCCESS) &&
2736                             !(rsp[4] & MMC_SWITCH_ERR))
2737                                 return SWITCH_SUCCESS;
2738                 }
2739         } else {
2740                 dev_dbg(rtsx_dev(chip), "BUSTEST_R [4bits]: 0x%02x\n", ptr[0]);
2741                 if (ptr[0] == 0xA5) {
2742                         u8 rsp[5];
2743                         u32 arg;
2744
2745                         if (CHK_MMC_DDR52(sd_card))
2746                                 arg = 0x03B70500;
2747                         else
2748                                 arg = 0x03B70100;
2749
2750                         retval = sd_send_cmd_get_rsp(chip, SWITCH, arg,
2751                                                      SD_RSP_TYPE_R1b, rsp, 5);
2752                         if ((retval == STATUS_SUCCESS) &&
2753                             !(rsp[4] & MMC_SWITCH_ERR))
2754                                 return SWITCH_SUCCESS;
2755                 }
2756         }
2757
2758         return SWITCH_FAIL;
2759 }
2760
2761 static int mmc_switch_timing_bus(struct rtsx_chip *chip, bool switch_ddr)
2762 {
2763         struct sd_info *sd_card = &chip->sd_card;
2764         int retval;
2765         u8 *ptr, card_type, card_type_mask = 0;
2766
2767         CLR_MMC_HS(sd_card);
2768
2769         dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", SEND_EXT_CSD);
2770
2771         rtsx_init_cmd(chip);
2772
2773         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
2774                      0x40 | SEND_EXT_CSD);
2775         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 0);
2776         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 0);
2777         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 0);
2778         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 0);
2779
2780         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0);
2781         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 2);
2782         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2783         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2784
2785         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
2786                      SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
2787                      SD_CHECK_CRC7 | SD_RSP_LEN_6);
2788         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
2789                      PINGPONG_BUFFER);
2790         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
2791                      SD_TM_NORMAL_READ | SD_TRANSFER_START);
2792         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
2793                      SD_TRANSFER_END);
2794
2795         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0);
2796         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0);
2797         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0);
2798         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0);
2799         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0);
2800
2801         retval = rtsx_send_cmd(chip, SD_CARD, 1000);
2802         if (retval < 0) {
2803                 if (retval == -ETIMEDOUT) {
2804                         rtsx_clear_sd_error(chip);
2805                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2806                                             SD_RSP_TYPE_R1, NULL, 0);
2807                 }
2808                 return STATUS_FAIL;
2809         }
2810
2811         ptr = rtsx_get_cmd_data(chip);
2812         if (ptr[0] & SD_TRANSFER_ERR) {
2813                 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2814                                     SD_RSP_TYPE_R1, NULL, 0);
2815                 return STATUS_FAIL;
2816         }
2817
2818         if (CHK_MMC_SECTOR_MODE(sd_card)) {
2819                 sd_card->capacity = ((u32)ptr[5] << 24) | ((u32)ptr[4] << 16) |
2820                         ((u32)ptr[3] << 8) | ((u32)ptr[2]);
2821         }
2822
2823         card_type_mask = 0x03;
2824         card_type = ptr[1] & card_type_mask;
2825         if (card_type) {
2826                 u8 rsp[5];
2827
2828                 if (card_type & 0x04) {
2829                         if (switch_ddr)
2830                                 SET_MMC_DDR52(sd_card);
2831                         else
2832                                 SET_MMC_52M(sd_card);
2833                 } else if (card_type & 0x02) {
2834                         SET_MMC_52M(sd_card);
2835                 } else {
2836                         SET_MMC_26M(sd_card);
2837                 }
2838
2839                 retval = sd_send_cmd_get_rsp(chip, SWITCH, 0x03B90100,
2840                                              SD_RSP_TYPE_R1b, rsp, 5);
2841                 if ((retval != STATUS_SUCCESS) || (rsp[4] & MMC_SWITCH_ERR))
2842                         CLR_MMC_HS(sd_card);
2843         }
2844
2845         sd_choose_proper_clock(chip);
2846         retval = switch_clock(chip, sd_card->sd_clock);
2847         if (retval != STATUS_SUCCESS)
2848                 return STATUS_FAIL;
2849
2850         /* Test Bus Procedure */
2851         retval = mmc_test_switch_bus(chip, MMC_8BIT_BUS);
2852         if (retval == SWITCH_SUCCESS) {
2853                 SET_MMC_8BIT(sd_card);
2854                 chip->card_bus_width[chip->card2lun[SD_CARD]] = 8;
2855 #ifdef SUPPORT_SD_LOCK
2856                 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2857 #endif
2858         } else if (retval == SWITCH_FAIL) {
2859                 retval = mmc_test_switch_bus(chip, MMC_4BIT_BUS);
2860                 if (retval == SWITCH_SUCCESS) {
2861                         SET_MMC_4BIT(sd_card);
2862                         chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2863 #ifdef SUPPORT_SD_LOCK
2864                         sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2865 #endif
2866                 } else if (retval == SWITCH_FAIL) {
2867                         CLR_MMC_8BIT(sd_card);
2868                         CLR_MMC_4BIT(sd_card);
2869                 } else {
2870                         return STATUS_FAIL;
2871                 }
2872         } else {
2873                 return STATUS_FAIL;
2874         }
2875
2876         return STATUS_SUCCESS;
2877 }
2878
2879 static int reset_mmc(struct rtsx_chip *chip)
2880 {
2881         struct sd_info *sd_card = &chip->sd_card;
2882         int retval, i = 0, j = 0, k = 0;
2883         bool switch_ddr = true;
2884         u8 rsp[16];
2885         u8 spec_ver = 0;
2886         u32 temp;
2887
2888 #ifdef SUPPORT_SD_LOCK
2889         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2890                 goto MMC_UNLOCK_ENTRY;
2891 #endif
2892
2893 switch_fail:
2894         retval = sd_prepare_reset(chip);
2895         if (retval != STATUS_SUCCESS)
2896                 return retval;
2897
2898         SET_MMC(sd_card);
2899
2900 RTY_MMC_RST:
2901         retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0,
2902                                      NULL, 0);
2903         if (retval != STATUS_SUCCESS)
2904                 return STATUS_FAIL;
2905
2906         do {
2907                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2908                         sd_set_err_code(chip, SD_NO_CARD);
2909                         return STATUS_FAIL;
2910                 }
2911
2912                 retval = sd_send_cmd_get_rsp(chip, SEND_OP_COND,
2913                                              (SUPPORT_VOLTAGE | 0x40000000),
2914                                              SD_RSP_TYPE_R3, rsp, 5);
2915                 if (retval != STATUS_SUCCESS) {
2916                         if (sd_check_err_code(chip, SD_BUSY) ||
2917                             sd_check_err_code(chip, SD_TO_ERR)) {
2918                                 k++;
2919                                 if (k < 20) {
2920                                         sd_clr_err_code(chip);
2921                                         goto RTY_MMC_RST;
2922                                 } else {
2923                                         return STATUS_FAIL;
2924                                 }
2925                         } else {
2926                                 j++;
2927                                 if (j < 100) {
2928                                         sd_clr_err_code(chip);
2929                                         goto RTY_MMC_RST;
2930                                 } else {
2931                                         return STATUS_FAIL;
2932                                 }
2933                         }
2934                 }
2935
2936                 wait_timeout(20);
2937                 i++;
2938         } while (!(rsp[1] & 0x80) && (i < 255));
2939
2940         if (i == 255)
2941                 return STATUS_FAIL;
2942
2943         if ((rsp[1] & 0x60) == 0x40)
2944                 SET_MMC_SECTOR_MODE(sd_card);
2945         else
2946                 CLR_MMC_SECTOR_MODE(sd_card);
2947
2948         retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2,
2949                                      NULL, 0);
2950         if (retval != STATUS_SUCCESS)
2951                 return STATUS_FAIL;
2952
2953         sd_card->sd_addr = 0x00100000;
2954         retval = sd_send_cmd_get_rsp(chip, SET_RELATIVE_ADDR, sd_card->sd_addr,
2955                                      SD_RSP_TYPE_R6, rsp, 5);
2956         if (retval != STATUS_SUCCESS)
2957                 return STATUS_FAIL;
2958
2959         retval = sd_check_csd(chip, 1);
2960         if (retval != STATUS_SUCCESS)
2961                 return STATUS_FAIL;
2962
2963         spec_ver = (sd_card->raw_csd[0] & 0x3C) >> 2;
2964
2965         retval = sd_select_card(chip, 1);
2966         if (retval != STATUS_SUCCESS)
2967                 return STATUS_FAIL;
2968
2969         retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1,
2970                                      NULL, 0);
2971         if (retval != STATUS_SUCCESS)
2972                 return STATUS_FAIL;
2973
2974 #ifdef SUPPORT_SD_LOCK
2975 MMC_UNLOCK_ENTRY:
2976         retval = sd_update_lock_status(chip);
2977         if (retval != STATUS_SUCCESS)
2978                 return STATUS_FAIL;
2979 #endif
2980
2981         retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2982         if (retval != STATUS_SUCCESS)
2983                 return STATUS_FAIL;
2984
2985         chip->card_bus_width[chip->card2lun[SD_CARD]] = 1;
2986
2987         if (!sd_card->mmc_dont_switch_bus) {
2988                 if (spec_ver == 4) {
2989                         /* MMC 4.x Cards */
2990                         retval = mmc_switch_timing_bus(chip, switch_ddr);
2991                         if (retval != STATUS_SUCCESS) {
2992                                 retval = sd_init_power(chip);
2993                                 if (retval != STATUS_SUCCESS)
2994                                         return STATUS_FAIL;
2995                                 sd_card->mmc_dont_switch_bus = 1;
2996                                 goto switch_fail;
2997                         }
2998                 }
2999
3000                 if (CHK_MMC_SECTOR_MODE(sd_card) && (sd_card->capacity == 0))
3001                         return STATUS_FAIL;
3002
3003                 if (switch_ddr && CHK_MMC_DDR52(sd_card)) {
3004                         retval = sd_set_init_para(chip);
3005                         if (retval != STATUS_SUCCESS)
3006                                 return STATUS_FAIL;
3007
3008                         retval = mmc_ddr_tuning(chip);
3009                         if (retval != STATUS_SUCCESS) {
3010                                 retval = sd_init_power(chip);
3011                                 if (retval != STATUS_SUCCESS)
3012                                         return STATUS_FAIL;
3013
3014                                 switch_ddr = false;
3015                                 goto switch_fail;
3016                         }
3017
3018                         retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3019                         if (retval == STATUS_SUCCESS) {
3020                                 retval = sd_read_lba0(chip);
3021                                 if (retval != STATUS_SUCCESS) {
3022                                         retval = sd_init_power(chip);
3023                                         if (retval != STATUS_SUCCESS)
3024                                                 return STATUS_FAIL;
3025
3026                                         switch_ddr = false;
3027                                         goto switch_fail;
3028                                 }
3029                         }
3030                 }
3031         }
3032
3033 #ifdef SUPPORT_SD_LOCK
3034         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
3035                 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF,
3036                                              0x02);
3037                 if (retval)
3038                         return retval;
3039                 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF,
3040                                              0x00);
3041                 if (retval)
3042                         return retval;
3043         }
3044 #endif
3045
3046         temp = rtsx_readl(chip, RTSX_BIPR);
3047         if (temp & SD_WRITE_PROTECT)
3048                 chip->card_wp |= SD_CARD;
3049
3050         return STATUS_SUCCESS;
3051 }
3052
3053 int reset_sd_card(struct rtsx_chip *chip)
3054 {
3055         struct sd_info *sd_card = &chip->sd_card;
3056         int retval;
3057
3058         sd_init_reg_addr(chip);
3059
3060         memset(sd_card, 0, sizeof(struct sd_info));
3061         chip->capacity[chip->card2lun[SD_CARD]] = 0;
3062
3063         retval = enable_card_clock(chip, SD_CARD);
3064         if (retval != STATUS_SUCCESS)
3065                 return STATUS_FAIL;
3066
3067         if (chip->ignore_sd && CHK_SDIO_EXIST(chip) &&
3068             !CHK_SDIO_IGNORED(chip)) {
3069                 if (chip->asic_code) {
3070                         retval = sd_pull_ctl_enable(chip);
3071                         if (retval != STATUS_SUCCESS)
3072                                 return STATUS_FAIL;
3073                 } else {
3074                         retval = rtsx_write_register(chip, FPGA_PULL_CTL,
3075                                                      FPGA_SD_PULL_CTL_BIT |
3076                                                      0x20, 0);
3077                         if (retval != STATUS_SUCCESS)
3078                                 return STATUS_FAIL;
3079                 }
3080                 retval = card_share_mode(chip, SD_CARD);
3081                 if (retval != STATUS_SUCCESS)
3082                         return STATUS_FAIL;
3083
3084                 chip->sd_io = 1;
3085                 return STATUS_FAIL;
3086         }
3087
3088         retval = sd_init_power(chip);
3089         if (retval != STATUS_SUCCESS)
3090                 return STATUS_FAIL;
3091
3092         if (chip->sd_ctl & RESET_MMC_FIRST) {
3093                 retval = reset_mmc(chip);
3094                 if (retval != STATUS_SUCCESS) {
3095                         if (sd_check_err_code(chip, SD_NO_CARD))
3096                                 return STATUS_FAIL;
3097
3098                         retval = reset_sd(chip);
3099                         if (retval != STATUS_SUCCESS)
3100                                 return STATUS_FAIL;
3101                 }
3102         } else {
3103                 retval = reset_sd(chip);
3104                 if (retval != STATUS_SUCCESS) {
3105                         if (sd_check_err_code(chip, SD_NO_CARD))
3106                                 return STATUS_FAIL;
3107
3108                         if (chip->sd_io)
3109                                 return STATUS_FAIL;
3110                         retval = reset_mmc(chip);
3111                         if (retval != STATUS_SUCCESS)
3112                                 return STATUS_FAIL;
3113                 }
3114         }
3115
3116         retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3117         if (retval != STATUS_SUCCESS)
3118                 return STATUS_FAIL;
3119
3120         retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3121         if (retval)
3122                 return retval;
3123         retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3124         if (retval)
3125                 return retval;
3126
3127         chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3128
3129         retval = sd_set_init_para(chip);
3130         if (retval != STATUS_SUCCESS)
3131                 return STATUS_FAIL;
3132
3133         dev_dbg(rtsx_dev(chip), "sd_card->sd_type = 0x%x\n", sd_card->sd_type);
3134
3135         return STATUS_SUCCESS;
3136 }
3137
3138 static int reset_mmc_only(struct rtsx_chip *chip)
3139 {
3140         struct sd_info *sd_card = &chip->sd_card;
3141         int retval;
3142
3143         sd_card->sd_type = 0;
3144         sd_card->seq_mode = 0;
3145         sd_card->sd_data_buf_ready = 0;
3146         sd_card->capacity = 0;
3147         sd_card->sd_switch_fail = 0;
3148
3149 #ifdef SUPPORT_SD_LOCK
3150         sd_card->sd_lock_status = 0;
3151         sd_card->sd_erase_status = 0;
3152 #endif
3153
3154         chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0;
3155
3156         retval = enable_card_clock(chip, SD_CARD);
3157         if (retval != STATUS_SUCCESS)
3158                 return STATUS_FAIL;
3159
3160         retval = sd_init_power(chip);
3161         if (retval != STATUS_SUCCESS)
3162                 return STATUS_FAIL;
3163
3164         retval = reset_mmc(chip);
3165         if (retval != STATUS_SUCCESS)
3166                 return STATUS_FAIL;
3167
3168         retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3169         if (retval != STATUS_SUCCESS)
3170                 return STATUS_FAIL;
3171
3172         retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3173         if (retval)
3174                 return retval;
3175         retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3176         if (retval)
3177                 return retval;
3178
3179         chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3180
3181         retval = sd_set_init_para(chip);
3182         if (retval != STATUS_SUCCESS)
3183                 return STATUS_FAIL;
3184
3185         dev_dbg(rtsx_dev(chip), "In %s, sd_card->sd_type = 0x%x\n",
3186                 __func__, sd_card->sd_type);
3187
3188         return STATUS_SUCCESS;
3189 }
3190
3191 #define WAIT_DATA_READY_RTY_CNT         255
3192
3193 static int wait_data_buf_ready(struct rtsx_chip *chip)
3194 {
3195         struct sd_info *sd_card = &chip->sd_card;
3196         int i, retval;
3197
3198         for (i = 0; i < WAIT_DATA_READY_RTY_CNT; i++) {
3199                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3200                         sd_set_err_code(chip, SD_NO_CARD);
3201                         return STATUS_FAIL;
3202                 }
3203
3204                 sd_card->sd_data_buf_ready = 0;
3205
3206                 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
3207                                              sd_card->sd_addr, SD_RSP_TYPE_R1,
3208                                              NULL, 0);
3209                 if (retval != STATUS_SUCCESS)
3210                         return STATUS_FAIL;
3211
3212                 if (sd_card->sd_data_buf_ready) {
3213                         return sd_send_cmd_get_rsp(chip, SEND_STATUS,
3214                                 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3215                 }
3216         }
3217
3218         sd_set_err_code(chip, SD_TO_ERR);
3219
3220         return STATUS_FAIL;
3221 }
3222
3223 void sd_stop_seq_mode(struct rtsx_chip *chip)
3224 {
3225         struct sd_info *sd_card = &chip->sd_card;
3226         int retval;
3227
3228         if (sd_card->seq_mode) {
3229                 retval = sd_switch_clock(chip);
3230                 if (retval != STATUS_SUCCESS)
3231                         return;
3232
3233                 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3234                                              SD_RSP_TYPE_R1b, NULL, 0);
3235                 if (retval != STATUS_SUCCESS)
3236                         sd_set_err_code(chip, SD_STS_ERR);
3237
3238                 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3239                 if (retval != STATUS_SUCCESS)
3240                         sd_set_err_code(chip, SD_STS_ERR);
3241
3242                 sd_card->seq_mode = 0;
3243
3244                 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3245         }
3246 }
3247
3248 static inline int sd_auto_tune_clock(struct rtsx_chip *chip)
3249 {
3250         struct sd_info *sd_card = &chip->sd_card;
3251         int retval;
3252
3253         if (chip->asic_code) {
3254                 if (sd_card->sd_clock > 30)
3255                         sd_card->sd_clock -= 20;
3256         } else {
3257                 switch (sd_card->sd_clock) {
3258                 case CLK_200:
3259                         sd_card->sd_clock = CLK_150;
3260                         break;
3261
3262                 case CLK_150:
3263                         sd_card->sd_clock = CLK_120;
3264                         break;
3265
3266                 case CLK_120:
3267                         sd_card->sd_clock = CLK_100;
3268                         break;
3269
3270                 case CLK_100:
3271                         sd_card->sd_clock = CLK_80;
3272                         break;
3273
3274                 case CLK_80:
3275                         sd_card->sd_clock = CLK_60;
3276                         break;
3277
3278                 case CLK_60:
3279                         sd_card->sd_clock = CLK_50;
3280                         break;
3281
3282                 default:
3283                         break;
3284                 }
3285         }
3286
3287         retval = sd_switch_clock(chip);
3288         if (retval != STATUS_SUCCESS)
3289                 return STATUS_FAIL;
3290
3291         return STATUS_SUCCESS;
3292 }
3293
3294 int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector,
3295           u16 sector_cnt)
3296 {
3297         struct sd_info *sd_card = &chip->sd_card;
3298         u32 data_addr;
3299         u8 cfg2;
3300         int retval;
3301
3302         if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3303                 dev_dbg(rtsx_dev(chip), "%s: Read %d %s from 0x%x\n", __func__,
3304                         sector_cnt, (sector_cnt > 1) ? "sectors" : "sector",
3305                         start_sector);
3306         } else {
3307                 dev_dbg(rtsx_dev(chip), "%s: Write %d %s to 0x%x\n", __func__,
3308                         sector_cnt, (sector_cnt > 1) ? "sectors" : "sector",
3309                         start_sector);
3310         }
3311
3312         sd_card->cleanup_counter = 0;
3313
3314         if (!(chip->card_ready & SD_CARD)) {
3315                 sd_card->seq_mode = 0;
3316
3317                 retval = reset_sd_card(chip);
3318                 if (retval == STATUS_SUCCESS) {
3319                         chip->card_ready |= SD_CARD;
3320                         chip->card_fail &= ~SD_CARD;
3321                 } else {
3322                         chip->card_ready &= ~SD_CARD;
3323                         chip->card_fail |= SD_CARD;
3324                         chip->capacity[chip->card2lun[SD_CARD]] = 0;
3325                         chip->rw_need_retry = 1;
3326                         return STATUS_FAIL;
3327                 }
3328         }
3329
3330         if (!CHK_SD_HCXC(sd_card) && !CHK_MMC_SECTOR_MODE(sd_card))
3331                 data_addr = start_sector << 9;
3332         else
3333                 data_addr = start_sector;
3334
3335         sd_clr_err_code(chip);
3336
3337         retval = sd_switch_clock(chip);
3338         if (retval != STATUS_SUCCESS) {
3339                 sd_set_err_code(chip, SD_IO_ERR);
3340                 goto RW_FAIL;
3341         }
3342
3343         if (sd_card->seq_mode &&
3344             ((sd_card->pre_dir != srb->sc_data_direction) ||
3345             ((sd_card->pre_sec_addr + sd_card->pre_sec_cnt) !=
3346             start_sector))) {
3347                 if ((sd_card->pre_sec_cnt < 0x80) &&
3348                     (sd_card->pre_dir == DMA_FROM_DEVICE) &&
3349                     !CHK_SD30_SPEED(sd_card) &&
3350                     !CHK_SD_HS(sd_card) &&
3351                     !CHK_MMC_HS(sd_card)) {
3352                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
3353                                             SD_RSP_TYPE_R1, NULL, 0);
3354                 }
3355
3356                 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3357                                              SD_RSP_TYPE_R1b, NULL, 0);
3358                 if (retval != STATUS_SUCCESS) {
3359                         chip->rw_need_retry = 1;
3360                         sd_set_err_code(chip, SD_STS_ERR);
3361                         goto RW_FAIL;
3362                 }
3363
3364                 sd_card->seq_mode = 0;
3365
3366                 retval = rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3367                 if (retval != STATUS_SUCCESS) {
3368                         sd_set_err_code(chip, SD_IO_ERR);
3369                         goto RW_FAIL;
3370                 }
3371
3372                 if ((sd_card->pre_sec_cnt < 0x80) &&
3373                     !CHK_SD30_SPEED(sd_card) &&
3374                     !CHK_SD_HS(sd_card) &&
3375                     !CHK_MMC_HS(sd_card)) {
3376                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
3377                                             SD_RSP_TYPE_R1, NULL, 0);
3378                 }
3379         }
3380
3381         rtsx_init_cmd(chip);
3382
3383         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
3384         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
3385         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
3386                      (u8)sector_cnt);
3387         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
3388                      (u8)(sector_cnt >> 8));
3389
3390         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
3391
3392         if (CHK_MMC_8BIT(sd_card))
3393                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3394                              0x03, SD_BUS_WIDTH_8);
3395         else if (CHK_MMC_4BIT(sd_card) || CHK_SD(sd_card))
3396                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3397                              0x03, SD_BUS_WIDTH_4);
3398         else
3399                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3400                              0x03, SD_BUS_WIDTH_1);
3401
3402         if (sd_card->seq_mode) {
3403                 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3404                         SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 |
3405                         SD_RSP_LEN_0;
3406                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3407
3408                 trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512,
3409                                  DMA_512);
3410
3411                 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3412                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3413                                      SD_TM_AUTO_READ_3 | SD_TRANSFER_START);
3414                 } else {
3415                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3416                                      SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3417                 }
3418
3419                 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3420                              SD_TRANSFER_END, SD_TRANSFER_END);
3421
3422                 rtsx_send_cmd_no_wait(chip);
3423         } else {
3424                 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3425                         dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n",
3426                                 READ_MULTIPLE_BLOCK);
3427                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
3428                                      0x40 | READ_MULTIPLE_BLOCK);
3429                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF,
3430                                      (u8)(data_addr >> 24));
3431                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF,
3432                                      (u8)(data_addr >> 16));
3433                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF,
3434                                      (u8)(data_addr >> 8));
3435                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF,
3436                                      (u8)data_addr);
3437
3438                         cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3439                                 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 |
3440                                 SD_RSP_LEN_6;
3441                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
3442                                      cfg2);
3443
3444                         trans_dma_enable(srb->sc_data_direction, chip,
3445                                          sector_cnt * 512, DMA_512);
3446
3447                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3448                                      SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
3449                         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3450                                      SD_TRANSFER_END, SD_TRANSFER_END);
3451
3452                         rtsx_send_cmd_no_wait(chip);
3453                 } else {
3454                         retval = rtsx_send_cmd(chip, SD_CARD, 50);
3455                         if (retval < 0) {
3456                                 rtsx_clear_sd_error(chip);
3457
3458                                 chip->rw_need_retry = 1;
3459                                 sd_set_err_code(chip, SD_TO_ERR);
3460                                 goto RW_FAIL;
3461                         }
3462
3463                         retval = wait_data_buf_ready(chip);
3464                         if (retval != STATUS_SUCCESS) {
3465                                 chip->rw_need_retry = 1;
3466                                 sd_set_err_code(chip, SD_TO_ERR);
3467                                 goto RW_FAIL;
3468                         }
3469
3470                         retval = sd_send_cmd_get_rsp(chip, WRITE_MULTIPLE_BLOCK,
3471                                                      data_addr, SD_RSP_TYPE_R1,
3472                                                      NULL, 0);
3473                         if (retval != STATUS_SUCCESS) {
3474                                 chip->rw_need_retry = 1;
3475                                 goto RW_FAIL;
3476                         }
3477
3478                         rtsx_init_cmd(chip);
3479
3480                         cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3481                                 SD_NO_WAIT_BUSY_END |
3482                                 SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
3483                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
3484                                      cfg2);
3485
3486                         trans_dma_enable(srb->sc_data_direction, chip,
3487                                          sector_cnt * 512, DMA_512);
3488
3489                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3490                                      SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3491                         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3492                                      SD_TRANSFER_END, SD_TRANSFER_END);
3493
3494                         rtsx_send_cmd_no_wait(chip);
3495                 }
3496
3497                 sd_card->seq_mode = 1;
3498         }
3499
3500         retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
3501                                     scsi_bufflen(srb), scsi_sg_count(srb),
3502                                 srb->sc_data_direction, chip->sd_timeout);
3503         if (retval < 0) {
3504                 u8 stat = 0;
3505                 int err;
3506
3507                 sd_card->seq_mode = 0;
3508
3509                 if (retval == -ETIMEDOUT)
3510                         err = STATUS_TIMEDOUT;
3511                 else
3512                         err = STATUS_FAIL;
3513
3514                 rtsx_read_register(chip, REG_SD_STAT1, &stat);
3515                 rtsx_clear_sd_error(chip);
3516                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3517                         chip->rw_need_retry = 0;
3518                         dev_dbg(rtsx_dev(chip), "No card exist, exit %s\n",
3519                                 __func__);
3520                         return STATUS_FAIL;
3521                 }
3522
3523                 chip->rw_need_retry = 1;
3524
3525                 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3526                                              SD_RSP_TYPE_R1b, NULL, 0);
3527                 if (retval != STATUS_SUCCESS) {
3528                         sd_set_err_code(chip, SD_STS_ERR);
3529                         goto RW_FAIL;
3530                 }
3531
3532                 if (stat & (SD_CRC7_ERR | SD_CRC16_ERR | SD_CRC_WRITE_ERR)) {
3533                         dev_dbg(rtsx_dev(chip), "SD CRC error, tune clock!\n");
3534                         sd_set_err_code(chip, SD_CRC_ERR);
3535                         goto RW_FAIL;
3536                 }
3537
3538                 if (err == STATUS_TIMEDOUT) {
3539                         sd_set_err_code(chip, SD_TO_ERR);
3540                         goto RW_FAIL;
3541                 }
3542
3543                 return err;
3544         }
3545
3546         sd_card->pre_sec_addr = start_sector;
3547         sd_card->pre_sec_cnt = sector_cnt;
3548         sd_card->pre_dir = srb->sc_data_direction;
3549
3550         return STATUS_SUCCESS;
3551
3552 RW_FAIL:
3553         sd_card->seq_mode = 0;
3554
3555         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3556                 chip->rw_need_retry = 0;
3557                 dev_dbg(rtsx_dev(chip), "No card exist, exit %s\n", __func__);
3558                 return STATUS_FAIL;
3559         }
3560
3561         if (sd_check_err_code(chip, SD_CRC_ERR)) {
3562                 if (CHK_MMC_4BIT(sd_card) || CHK_MMC_8BIT(sd_card)) {
3563                         sd_card->mmc_dont_switch_bus = 1;
3564                         reset_mmc_only(chip);
3565                         sd_card->mmc_dont_switch_bus = 0;
3566                 } else {
3567                         sd_card->need_retune = 1;
3568                         sd_auto_tune_clock(chip);
3569                 }
3570         } else if (sd_check_err_code(chip, SD_TO_ERR | SD_STS_ERR)) {
3571                 retval = reset_sd_card(chip);
3572                 if (retval != STATUS_SUCCESS) {
3573                         chip->card_ready &= ~SD_CARD;
3574                         chip->card_fail |= SD_CARD;
3575                         chip->capacity[chip->card2lun[SD_CARD]] = 0;
3576                 }
3577         }
3578
3579         return STATUS_FAIL;
3580 }
3581
3582 #ifdef SUPPORT_CPRM
3583 int soft_reset_sd_card(struct rtsx_chip *chip)
3584 {
3585         return reset_sd(chip);
3586 }
3587
3588 int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx, u32 arg,
3589                             u8 rsp_type, u8 *rsp, int rsp_len,
3590                             bool special_check)
3591 {
3592         int retval;
3593         int timeout = 100;
3594         u16 reg_addr;
3595         u8 *ptr;
3596         int stat_idx = 0;
3597         int rty_cnt = 0;
3598
3599         dev_dbg(rtsx_dev(chip), "EXT SD/MMC CMD %d\n", cmd_idx);
3600
3601         if (rsp_type == SD_RSP_TYPE_R1b)
3602                 timeout = 3000;
3603
3604 RTY_SEND_CMD:
3605
3606         rtsx_init_cmd(chip);
3607
3608         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
3609         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
3610         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
3611         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
3612         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
3613
3614         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
3615         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
3616                      0x01, PINGPONG_BUFFER);
3617         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
3618                      0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
3619         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
3620                      SD_TRANSFER_END);
3621
3622         if (rsp_type == SD_RSP_TYPE_R2) {
3623                 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
3624                      reg_addr++)
3625                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3626
3627                 stat_idx = 17;
3628         } else if (rsp_type != SD_RSP_TYPE_R0) {
3629                 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
3630                      reg_addr++)
3631                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3632
3633                 stat_idx = 6;
3634         }
3635         rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0, 0);
3636
3637         rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
3638
3639         retval = rtsx_send_cmd(chip, SD_CARD, timeout);
3640         if (retval < 0) {
3641                 if (retval == -ETIMEDOUT) {
3642                         rtsx_clear_sd_error(chip);
3643
3644                         if (rsp_type & SD_WAIT_BUSY_END) {
3645                                 retval = sd_check_data0_status(chip);
3646                                 if (retval != STATUS_SUCCESS)
3647                                         return retval;
3648                         } else {
3649                                 sd_set_err_code(chip, SD_TO_ERR);
3650                         }
3651                 }
3652                 return STATUS_FAIL;
3653         }
3654
3655         if (rsp_type == SD_RSP_TYPE_R0)
3656                 return STATUS_SUCCESS;
3657
3658         ptr = rtsx_get_cmd_data(chip) + 1;
3659
3660         if ((ptr[0] & 0xC0) != 0) {
3661                 sd_set_err_code(chip, SD_STS_ERR);
3662                 return STATUS_FAIL;
3663         }
3664
3665         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
3666                 if (ptr[stat_idx] & SD_CRC7_ERR) {
3667                         if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
3668                                 sd_set_err_code(chip, SD_CRC_ERR);
3669                                 return STATUS_FAIL;
3670                         }
3671                         if (rty_cnt < SD_MAX_RETRY_COUNT) {
3672                                 wait_timeout(20);
3673                                 rty_cnt++;
3674                                 goto RTY_SEND_CMD;
3675                         } else {
3676                                 sd_set_err_code(chip, SD_CRC_ERR);
3677                                 return STATUS_FAIL;
3678                         }
3679                 }
3680         }
3681
3682         if ((cmd_idx == SELECT_CARD) || (cmd_idx == APP_CMD) ||
3683             (cmd_idx == SEND_STATUS) || (cmd_idx == STOP_TRANSMISSION)) {
3684                 if ((cmd_idx != STOP_TRANSMISSION) && !special_check) {
3685                         if (ptr[1] & 0x80)
3686                                 return STATUS_FAIL;
3687                 }
3688 #ifdef SUPPORT_SD_LOCK
3689                 if (ptr[1] & 0x7D) {
3690 #else
3691                 if (ptr[1] & 0x7F) {
3692 #endif
3693                         return STATUS_FAIL;
3694                 }
3695                 if (ptr[2] & 0xF8)
3696                         return STATUS_FAIL;
3697
3698                 if (cmd_idx == SELECT_CARD) {
3699                         if (rsp_type == SD_RSP_TYPE_R2) {
3700                                 if ((ptr[3] & 0x1E) != 0x04)
3701                                         return STATUS_FAIL;
3702                         }
3703                 }
3704         }
3705
3706         if (rsp && rsp_len)
3707                 memcpy(rsp, ptr, rsp_len);
3708
3709         return STATUS_SUCCESS;
3710 }
3711
3712 int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type)
3713 {
3714         int retval, rsp_len;
3715         u16 reg_addr;
3716
3717         if (rsp_type == SD_RSP_TYPE_R0)
3718                 return STATUS_SUCCESS;
3719
3720         rtsx_init_cmd(chip);
3721
3722         if (rsp_type == SD_RSP_TYPE_R2) {
3723                 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
3724                      reg_addr++)
3725                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3726
3727                 rsp_len = 17;
3728         } else if (rsp_type != SD_RSP_TYPE_R0) {
3729                 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
3730                      reg_addr++)
3731                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3732
3733                 rsp_len = 6;
3734         }
3735         rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0xFF, 0);
3736
3737         retval = rtsx_send_cmd(chip, SD_CARD, 100);
3738         if (retval != STATUS_SUCCESS)
3739                 return STATUS_FAIL;
3740
3741         if (rsp) {
3742                 int min_len = (rsp_len < len) ? rsp_len : len;
3743
3744                 memcpy(rsp, rtsx_get_cmd_data(chip), min_len);
3745
3746                 dev_dbg(rtsx_dev(chip), "min_len = %d\n", min_len);
3747                 dev_dbg(rtsx_dev(chip), "Response in cmd buf: 0x%x 0x%x 0x%x 0x%x\n",
3748                         rsp[0], rsp[1], rsp[2], rsp[3]);
3749         }
3750
3751         return STATUS_SUCCESS;
3752 }
3753
3754 int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3755 {
3756         struct sd_info *sd_card = &chip->sd_card;
3757         unsigned int lun = SCSI_LUN(srb);
3758         int len;
3759         u8 buf[18] = {
3760                 0x00,
3761                 0x00,
3762                 0x00,
3763                 0x0E,
3764                 0x00,
3765                 0x00,
3766                 0x00,
3767                 0x00,
3768                 0x53,
3769                 0x44,
3770                 0x20,
3771                 0x43,
3772                 0x61,
3773                 0x72,
3774                 0x64,
3775                 0x00,
3776                 0x00,
3777                 0x00,
3778         };
3779
3780         sd_card->pre_cmd_err = 0;
3781
3782         if (!(CHK_BIT(chip->lun_mc, lun))) {
3783                 SET_BIT(chip->lun_mc, lun);
3784                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3785                 return TRANSPORT_FAILED;
3786         }
3787
3788         if ((srb->cmnd[2] != 0x53) || (srb->cmnd[3] != 0x44) ||
3789             (srb->cmnd[4] != 0x20) || (srb->cmnd[5] != 0x43) ||
3790             (srb->cmnd[6] != 0x61) || (srb->cmnd[7] != 0x72) ||
3791             (srb->cmnd[8] != 0x64)) {
3792                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3793                 return TRANSPORT_FAILED;
3794         }
3795
3796         switch (srb->cmnd[1] & 0x0F) {
3797         case 0:
3798                 sd_card->sd_pass_thru_en = 0;
3799                 break;
3800
3801         case 1:
3802                 sd_card->sd_pass_thru_en = 1;
3803                 break;
3804
3805         default:
3806                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3807                 return TRANSPORT_FAILED;
3808         }
3809
3810         buf[5] = (CHK_SD(sd_card) == 1) ? 0x01 : 0x02;
3811         if (chip->card_wp & SD_CARD)
3812                 buf[5] |= 0x80;
3813
3814         buf[6] = (u8)(sd_card->sd_addr >> 16);
3815         buf[7] = (u8)(sd_card->sd_addr >> 24);
3816
3817         buf[15] = chip->max_lun;
3818
3819         len = min_t(int, 18, scsi_bufflen(srb));
3820         rtsx_stor_set_xfer_buf(buf, len, srb);
3821
3822         return TRANSPORT_GOOD;
3823 }
3824
3825 static inline int get_rsp_type(struct scsi_cmnd *srb, u8 *rsp_type,
3826                                int *rsp_len)
3827 {
3828         if (!rsp_type || !rsp_len)
3829                 return STATUS_FAIL;
3830
3831         switch (srb->cmnd[10]) {
3832         case 0x03:
3833                 *rsp_type = SD_RSP_TYPE_R0;
3834                 *rsp_len = 0;
3835                 break;
3836
3837         case 0x04:
3838                 *rsp_type = SD_RSP_TYPE_R1;
3839                 *rsp_len = 6;
3840                 break;
3841
3842         case 0x05:
3843                 *rsp_type = SD_RSP_TYPE_R1b;
3844                 *rsp_len = 6;
3845                 break;
3846
3847         case 0x06:
3848                 *rsp_type = SD_RSP_TYPE_R2;
3849                 *rsp_len = 17;
3850                 break;
3851
3852         case 0x07:
3853                 *rsp_type = SD_RSP_TYPE_R3;
3854                 *rsp_len = 6;
3855                 break;
3856
3857         default:
3858                 return STATUS_FAIL;
3859         }
3860
3861         return STATUS_SUCCESS;
3862 }
3863
3864 int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3865 {
3866         struct sd_info *sd_card = &chip->sd_card;
3867         unsigned int lun = SCSI_LUN(srb);
3868         int retval, rsp_len;
3869         u8 cmd_idx, rsp_type;
3870         bool standby = false, acmd = false;
3871         u32 arg;
3872
3873         if (!sd_card->sd_pass_thru_en) {
3874                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3875                 return TRANSPORT_FAILED;
3876         }
3877
3878         retval = sd_switch_clock(chip);
3879         if (retval != STATUS_SUCCESS)
3880                 return TRANSPORT_FAILED;
3881
3882         if (sd_card->pre_cmd_err) {
3883                 sd_card->pre_cmd_err = 0;
3884                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3885                 return TRANSPORT_FAILED;
3886         }
3887
3888         cmd_idx = srb->cmnd[2] & 0x3F;
3889         if (srb->cmnd[1] & 0x02)
3890                 standby = true;
3891
3892         if (srb->cmnd[1] & 0x01)
3893                 acmd = true;
3894
3895         arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
3896                 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
3897
3898         retval = get_rsp_type(srb, &rsp_type, &rsp_len);
3899         if (retval != STATUS_SUCCESS) {
3900                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3901                 return TRANSPORT_FAILED;
3902         }
3903         sd_card->last_rsp_type = rsp_type;
3904
3905         retval = sd_switch_clock(chip);
3906         if (retval != STATUS_SUCCESS)
3907                 return TRANSPORT_FAILED;
3908
3909 #ifdef SUPPORT_SD_LOCK
3910         if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
3911                 if (CHK_MMC_8BIT(sd_card)) {
3912                         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
3913                                                      SD_BUS_WIDTH_8);
3914                         if (retval != STATUS_SUCCESS)
3915                                 return TRANSPORT_FAILED;
3916
3917                 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
3918                         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
3919                                                      SD_BUS_WIDTH_4);
3920                         if (retval != STATUS_SUCCESS)
3921                                 return TRANSPORT_FAILED;
3922                 }
3923         }
3924 #else
3925         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3926         if (retval != STATUS_SUCCESS)
3927                 return TRANSPORT_FAILED;
3928 #endif
3929
3930         if (standby) {
3931                 retval = sd_select_card(chip, 0);
3932                 if (retval != STATUS_SUCCESS)
3933                         goto sd_execute_cmd_failed;
3934         }
3935
3936         if (acmd) {
3937                 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
3938                                                  sd_card->sd_addr,
3939                                                  SD_RSP_TYPE_R1, NULL, 0,
3940                                                  false);
3941                 if (retval != STATUS_SUCCESS)
3942                         goto sd_execute_cmd_failed;
3943         }
3944
3945         retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
3946                                          sd_card->rsp, rsp_len, false);
3947         if (retval != STATUS_SUCCESS)
3948                 goto sd_execute_cmd_failed;
3949
3950         if (standby) {
3951                 retval = sd_select_card(chip, 1);
3952                 if (retval != STATUS_SUCCESS)
3953                         goto sd_execute_cmd_failed;
3954         }
3955
3956 #ifdef SUPPORT_SD_LOCK
3957         retval = sd_update_lock_status(chip);
3958         if (retval != STATUS_SUCCESS)
3959                 goto sd_execute_cmd_failed;
3960 #endif
3961
3962         scsi_set_resid(srb, 0);
3963         return TRANSPORT_GOOD;
3964
3965 sd_execute_cmd_failed:
3966         sd_card->pre_cmd_err = 1;
3967         set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
3968         release_sd_card(chip);
3969         do_reset_sd_card(chip);
3970         if (!(chip->card_ready & SD_CARD))
3971                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3972
3973         return TRANSPORT_FAILED;
3974 }
3975
3976 int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3977 {
3978         struct sd_info *sd_card = &chip->sd_card;
3979         unsigned int lun = SCSI_LUN(srb);
3980         int retval, rsp_len, i;
3981         bool read_err = false, cmd13_checkbit = false;
3982         u8 cmd_idx, rsp_type, bus_width;
3983         bool standby = false, send_cmd12 = false, acmd = false;
3984         u32 data_len;
3985
3986         if (!sd_card->sd_pass_thru_en) {
3987                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3988                 return TRANSPORT_FAILED;
3989         }
3990
3991         if (sd_card->pre_cmd_err) {
3992                 sd_card->pre_cmd_err = 0;
3993                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3994                 return TRANSPORT_FAILED;
3995         }
3996
3997         retval = sd_switch_clock(chip);
3998         if (retval != STATUS_SUCCESS)
3999                 return TRANSPORT_FAILED;
4000
4001         cmd_idx = srb->cmnd[2] & 0x3F;
4002         if (srb->cmnd[1] & 0x04)
4003                 send_cmd12 = true;
4004
4005         if (srb->cmnd[1] & 0x02)
4006                 standby = true;
4007
4008         if (srb->cmnd[1] & 0x01)
4009                 acmd = true;
4010
4011         data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8]
4012                                                 << 8) | srb->cmnd[9];
4013
4014         retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4015         if (retval != STATUS_SUCCESS) {
4016                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4017                 return TRANSPORT_FAILED;
4018         }
4019         sd_card->last_rsp_type = rsp_type;
4020
4021         retval = sd_switch_clock(chip);
4022         if (retval != STATUS_SUCCESS)
4023                 return TRANSPORT_FAILED;
4024
4025 #ifdef SUPPORT_SD_LOCK
4026         if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4027                 if (CHK_MMC_8BIT(sd_card))
4028                         bus_width = SD_BUS_WIDTH_8;
4029                 else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card))
4030                         bus_width = SD_BUS_WIDTH_4;
4031                 else
4032                         bus_width = SD_BUS_WIDTH_1;
4033         } else {
4034                 bus_width = SD_BUS_WIDTH_4;
4035         }
4036         dev_dbg(rtsx_dev(chip), "bus_width = %d\n", bus_width);
4037 #else
4038         bus_width = SD_BUS_WIDTH_4;
4039 #endif
4040
4041         if (data_len < 512) {
4042                 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4043                                                  SD_RSP_TYPE_R1, NULL, 0,
4044                                                  false);
4045                 if (retval != STATUS_SUCCESS)
4046                         goto sd_execute_read_cmd_failed;
4047         }
4048
4049         if (standby) {
4050                 retval = sd_select_card(chip, 0);
4051                 if (retval != STATUS_SUCCESS)
4052                         goto sd_execute_read_cmd_failed;
4053         }
4054
4055         if (acmd) {
4056                 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
4057                                                  sd_card->sd_addr,
4058                                                  SD_RSP_TYPE_R1, NULL, 0,
4059                                                  false);
4060                 if (retval != STATUS_SUCCESS)
4061                         goto sd_execute_read_cmd_failed;
4062         }
4063
4064         if (data_len <= 512) {
4065                 int min_len;
4066                 u8 *buf;
4067                 u16 byte_cnt, blk_cnt;
4068                 u8 cmd[5];
4069
4070                 byte_cnt = ((u16)(srb->cmnd[8] & 0x03) << 8) | srb->cmnd[9];
4071                 blk_cnt = 1;
4072
4073                 cmd[0] = 0x40 | cmd_idx;
4074                 cmd[1] = srb->cmnd[3];
4075                 cmd[2] = srb->cmnd[4];
4076                 cmd[3] = srb->cmnd[5];
4077                 cmd[4] = srb->cmnd[6];
4078
4079                 buf = kmalloc(data_len, GFP_KERNEL);
4080                 if (!buf)
4081                         return TRANSPORT_ERROR;
4082
4083                 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, byte_cnt,
4084                                       blk_cnt, bus_width, buf, data_len, 2000);
4085                 if (retval != STATUS_SUCCESS) {
4086                         read_err = true;
4087                         kfree(buf);
4088                         rtsx_clear_sd_error(chip);
4089                         goto sd_execute_read_cmd_failed;
4090                 }
4091
4092                 min_len = min(data_len, scsi_bufflen(srb));
4093                 rtsx_stor_set_xfer_buf(buf, min_len, srb);
4094
4095                 kfree(buf);
4096         } else if (!(data_len & 0x1FF)) {
4097                 rtsx_init_cmd(chip);
4098
4099                 trans_dma_enable(DMA_FROM_DEVICE, chip, data_len, DMA_512);
4100
4101                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4102                              0x02);
4103                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4104                              0x00);
4105                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4106                              0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4107                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4108                              0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4109
4110                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
4111                              0x40 | cmd_idx);
4112                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF,
4113                              srb->cmnd[3]);
4114                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF,
4115                              srb->cmnd[4]);
4116                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF,
4117                              srb->cmnd[5]);
4118                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF,
4119                              srb->cmnd[6]);
4120
4121                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
4122                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
4123
4124                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
4125                              0xFF, SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
4126                 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4127                              SD_TRANSFER_END, SD_TRANSFER_END);
4128
4129                 rtsx_send_cmd_no_wait(chip);
4130
4131                 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
4132                                             scsi_bufflen(srb),
4133                                             scsi_sg_count(srb),
4134                                             DMA_FROM_DEVICE, 10000);
4135                 if (retval < 0) {
4136                         read_err = true;
4137                         rtsx_clear_sd_error(chip);
4138                         goto sd_execute_read_cmd_failed;
4139                 }
4140
4141         } else {
4142                 goto sd_execute_read_cmd_failed;
4143         }
4144
4145         retval = ext_sd_get_rsp(chip, rsp_len, sd_card->rsp, rsp_type);
4146         if (retval != STATUS_SUCCESS)
4147                 goto sd_execute_read_cmd_failed;
4148
4149         if (standby) {
4150                 retval = sd_select_card(chip, 1);
4151                 if (retval != STATUS_SUCCESS)
4152                         goto sd_execute_read_cmd_failed;
4153         }
4154
4155         if (send_cmd12) {
4156                 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
4157                                                  SD_RSP_TYPE_R1b, NULL, 0,
4158                                                  false);
4159                 if (retval != STATUS_SUCCESS)
4160                         goto sd_execute_read_cmd_failed;
4161         }
4162
4163         if (data_len < 512) {
4164                 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4165                                                  SD_RSP_TYPE_R1, NULL, 0,
4166                                                  false);
4167                 if (retval != STATUS_SUCCESS)
4168                         goto sd_execute_read_cmd_failed;
4169
4170                 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4171                 if (retval != STATUS_SUCCESS)
4172                         goto sd_execute_read_cmd_failed;
4173
4174                 retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4175                 if (retval != STATUS_SUCCESS)
4176                         goto sd_execute_read_cmd_failed;
4177         }
4178
4179         if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04))
4180                 cmd13_checkbit = true;
4181
4182         for (i = 0; i < 3; i++) {
4183                 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS,
4184                                                  sd_card->sd_addr,
4185                                                 SD_RSP_TYPE_R1, NULL, 0,
4186                                                 cmd13_checkbit);
4187                 if (retval == STATUS_SUCCESS)
4188                         break;
4189         }
4190         if (retval != STATUS_SUCCESS)
4191                 goto sd_execute_read_cmd_failed;
4192
4193         scsi_set_resid(srb, 0);
4194         return TRANSPORT_GOOD;
4195
4196 sd_execute_read_cmd_failed:
4197         sd_card->pre_cmd_err = 1;
4198         set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4199         if (read_err)
4200                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4201
4202         release_sd_card(chip);
4203         do_reset_sd_card(chip);
4204         if (!(chip->card_ready & SD_CARD))
4205                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4206
4207         return TRANSPORT_FAILED;
4208 }
4209
4210 int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4211 {
4212         struct sd_info *sd_card = &chip->sd_card;
4213         unsigned int lun = SCSI_LUN(srb);
4214         int retval, rsp_len, i;
4215         bool write_err = false, cmd13_checkbit = false;
4216         u8 cmd_idx, rsp_type;
4217         bool standby = false, send_cmd12 = false, acmd = false;
4218         u32 data_len, arg;
4219 #ifdef SUPPORT_SD_LOCK
4220         int lock_cmd_fail = 0;
4221         u8 sd_lock_state = 0;
4222         u8 lock_cmd_type = 0;
4223 #endif
4224
4225         if (!sd_card->sd_pass_thru_en) {
4226                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4227                 return TRANSPORT_FAILED;
4228         }
4229
4230         if (sd_card->pre_cmd_err) {
4231                 sd_card->pre_cmd_err = 0;
4232                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4233                 return TRANSPORT_FAILED;
4234         }
4235
4236         retval = sd_switch_clock(chip);
4237         if (retval != STATUS_SUCCESS)
4238                 return TRANSPORT_FAILED;
4239
4240         cmd_idx = srb->cmnd[2] & 0x3F;
4241         if (srb->cmnd[1] & 0x04)
4242                 send_cmd12 = true;
4243
4244         if (srb->cmnd[1] & 0x02)
4245                 standby = true;
4246
4247         if (srb->cmnd[1] & 0x01)
4248                 acmd = true;
4249
4250         data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8]
4251                                                 << 8) | srb->cmnd[9];
4252         arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
4253                 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
4254
4255 #ifdef SUPPORT_SD_LOCK
4256         if (cmd_idx == LOCK_UNLOCK) {
4257                 sd_lock_state = sd_card->sd_lock_status;
4258                 sd_lock_state &= SD_LOCKED;
4259         }
4260 #endif
4261
4262         retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4263         if (retval != STATUS_SUCCESS) {
4264                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4265                 return TRANSPORT_FAILED;
4266         }
4267         sd_card->last_rsp_type = rsp_type;
4268
4269         retval = sd_switch_clock(chip);
4270         if (retval != STATUS_SUCCESS)
4271                 return TRANSPORT_FAILED;
4272
4273 #ifdef SUPPORT_SD_LOCK
4274         if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4275                 if (CHK_MMC_8BIT(sd_card)) {
4276                         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
4277                                                      SD_BUS_WIDTH_8);
4278                         if (retval != STATUS_SUCCESS)
4279                                 return TRANSPORT_FAILED;
4280
4281                 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
4282                         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
4283                                                      SD_BUS_WIDTH_4);
4284                         if (retval != STATUS_SUCCESS)
4285                                 return TRANSPORT_FAILED;
4286                 }
4287         }
4288 #else
4289         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4290         if (retval != STATUS_SUCCESS)
4291                 return TRANSPORT_FAILED;
4292 #endif
4293
4294         if (data_len < 512) {
4295                 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4296                                                  SD_RSP_TYPE_R1, NULL, 0,
4297                                                  false);
4298                 if (retval != STATUS_SUCCESS)
4299                         goto sd_execute_write_cmd_failed;
4300         }
4301
4302         if (standby) {
4303                 retval = sd_select_card(chip, 0);
4304                 if (retval != STATUS_SUCCESS)
4305                         goto sd_execute_write_cmd_failed;
4306         }
4307
4308         if (acmd) {
4309                 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
4310                                                  sd_card->sd_addr,
4311                                                  SD_RSP_TYPE_R1, NULL, 0,
4312                                                  false);
4313                 if (retval != STATUS_SUCCESS)
4314                         goto sd_execute_write_cmd_failed;
4315         }
4316
4317         retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
4318                                          sd_card->rsp, rsp_len, false);
4319         if (retval != STATUS_SUCCESS)
4320                 goto sd_execute_write_cmd_failed;
4321
4322         if (data_len <= 512) {
4323                 u16 i;
4324                 u8 *buf;
4325
4326                 buf = kmalloc(data_len, GFP_KERNEL);
4327                 if (!buf)
4328                         return TRANSPORT_ERROR;
4329
4330                 rtsx_stor_get_xfer_buf(buf, data_len, srb);
4331
4332 #ifdef SUPPORT_SD_LOCK
4333                 if (cmd_idx == LOCK_UNLOCK)
4334                         lock_cmd_type = buf[0] & 0x0F;
4335 #endif
4336
4337                 if (data_len > 256) {
4338                         rtsx_init_cmd(chip);
4339                         for (i = 0; i < 256; i++) {
4340                                 rtsx_add_cmd(chip, WRITE_REG_CMD,
4341                                              PPBUF_BASE2 + i, 0xFF, buf[i]);
4342                         }
4343                         retval = rtsx_send_cmd(chip, 0, 250);
4344                         if (retval != STATUS_SUCCESS) {
4345                                 kfree(buf);
4346                                 goto sd_execute_write_cmd_failed;
4347                         }
4348
4349                         rtsx_init_cmd(chip);
4350                         for (i = 256; i < data_len; i++) {
4351                                 rtsx_add_cmd(chip, WRITE_REG_CMD,
4352                                              PPBUF_BASE2 + i, 0xFF, buf[i]);
4353                         }
4354                         retval = rtsx_send_cmd(chip, 0, 250);
4355                         if (retval != STATUS_SUCCESS) {
4356                                 kfree(buf);
4357                                 goto sd_execute_write_cmd_failed;
4358                         }
4359                 } else {
4360                         rtsx_init_cmd(chip);
4361                         for (i = 0; i < data_len; i++) {
4362                                 rtsx_add_cmd(chip, WRITE_REG_CMD,
4363                                              PPBUF_BASE2 + i, 0xFF, buf[i]);
4364                         }
4365                         retval = rtsx_send_cmd(chip, 0, 250);
4366                         if (retval != STATUS_SUCCESS) {
4367                                 kfree(buf);
4368                                 goto sd_execute_write_cmd_failed;
4369                         }
4370                 }
4371
4372                 kfree(buf);
4373
4374                 rtsx_init_cmd(chip);
4375
4376                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4377                              srb->cmnd[8] & 0x03);
4378                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4379                              srb->cmnd[9]);
4380                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
4381                              0x00);
4382                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
4383                              0x01);
4384                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
4385                              PINGPONG_BUFFER);
4386
4387                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4388                              SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4389                 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4390                              SD_TRANSFER_END, SD_TRANSFER_END);
4391
4392                 retval = rtsx_send_cmd(chip, SD_CARD, 250);
4393         } else if (!(data_len & 0x1FF)) {
4394                 rtsx_init_cmd(chip);
4395
4396                 trans_dma_enable(DMA_TO_DEVICE, chip, data_len, DMA_512);
4397
4398                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4399                              0x02);
4400                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4401                              0x00);
4402                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4403                              0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4404                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4405                              0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4406
4407                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4408                              SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4409                 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4410                              SD_TRANSFER_END, SD_TRANSFER_END);
4411
4412                 rtsx_send_cmd_no_wait(chip);
4413
4414                 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
4415                                             scsi_bufflen(srb),
4416                                             scsi_sg_count(srb),
4417                                             DMA_TO_DEVICE, 10000);
4418
4419         } else {
4420                 goto sd_execute_write_cmd_failed;
4421         }
4422
4423         if (retval < 0) {
4424                 write_err = true;
4425                 rtsx_clear_sd_error(chip);
4426                 goto sd_execute_write_cmd_failed;
4427         }
4428
4429 #ifdef SUPPORT_SD_LOCK
4430         if (cmd_idx == LOCK_UNLOCK) {
4431                 if (lock_cmd_type == SD_ERASE) {
4432                         sd_card->sd_erase_status = SD_UNDER_ERASING;
4433                         scsi_set_resid(srb, 0);
4434                         return TRANSPORT_GOOD;
4435                 }
4436
4437                 rtsx_init_cmd(chip);
4438                 rtsx_add_cmd(chip, CHECK_REG_CMD, 0xFD30, 0x02, 0x02);
4439
4440                 retval = rtsx_send_cmd(chip, SD_CARD, 250);
4441                 if (retval < 0) {
4442                         write_err = true;
4443                         rtsx_clear_sd_error(chip);
4444                         goto sd_execute_write_cmd_failed;
4445                 }
4446
4447                 retval = sd_update_lock_status(chip);
4448                 if (retval != STATUS_SUCCESS) {
4449                         dev_dbg(rtsx_dev(chip), "Lock command fail!\n");
4450                         lock_cmd_fail = 1;
4451                 }
4452         }
4453 #endif /* SUPPORT_SD_LOCK */
4454
4455         if (standby) {
4456                 retval = sd_select_card(chip, 1);
4457                 if (retval != STATUS_SUCCESS)
4458                         goto sd_execute_write_cmd_failed;
4459         }
4460
4461         if (send_cmd12) {
4462                 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
4463                                                  SD_RSP_TYPE_R1b, NULL, 0,
4464                                                  false);
4465                 if (retval != STATUS_SUCCESS)
4466                         goto sd_execute_write_cmd_failed;
4467         }
4468
4469         if (data_len < 512) {
4470                 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4471                                                  SD_RSP_TYPE_R1, NULL, 0,
4472                                                  false);
4473                 if (retval != STATUS_SUCCESS)
4474                         goto sd_execute_write_cmd_failed;
4475
4476                 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4477                 if (retval != STATUS_SUCCESS)
4478                         goto sd_execute_write_cmd_failed;
4479
4480                 retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4481                 if (retval != STATUS_SUCCESS)
4482                         goto sd_execute_write_cmd_failed;
4483         }
4484
4485         if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04))
4486                 cmd13_checkbit = true;
4487
4488         for (i = 0; i < 3; i++) {
4489                 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS,
4490                                                  sd_card->sd_addr,
4491                                                  SD_RSP_TYPE_R1, NULL, 0,
4492                                                  cmd13_checkbit);
4493                 if (retval == STATUS_SUCCESS)
4494                         break;
4495         }
4496         if (retval != STATUS_SUCCESS)
4497                 goto sd_execute_write_cmd_failed;
4498
4499 #ifdef SUPPORT_SD_LOCK
4500         if (cmd_idx == LOCK_UNLOCK) {
4501                 if (!lock_cmd_fail) {
4502                         dev_dbg(rtsx_dev(chip), "lock_cmd_type = 0x%x\n",
4503                                 lock_cmd_type);
4504                         if (lock_cmd_type & SD_CLR_PWD)
4505                                 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
4506
4507                         if (lock_cmd_type & SD_SET_PWD)
4508                                 sd_card->sd_lock_status |= SD_PWD_EXIST;
4509                 }
4510
4511                 dev_dbg(rtsx_dev(chip), "sd_lock_state = 0x%x, sd_card->sd_lock_status = 0x%x\n",
4512                         sd_lock_state, sd_card->sd_lock_status);
4513                 if (sd_lock_state ^ (sd_card->sd_lock_status & SD_LOCKED)) {
4514                         sd_card->sd_lock_notify = 1;
4515                         if (sd_lock_state) {
4516                                 if (sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) {
4517                                         sd_card->sd_lock_status |= (
4518                                                 SD_UNLOCK_POW_ON | SD_SDR_RST);
4519                                         if (CHK_SD(sd_card)) {
4520                                                 retval = reset_sd(chip);
4521                                                 if (retval != STATUS_SUCCESS) {
4522                                                         sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4523                                                         goto sd_execute_write_cmd_failed;
4524                                                 }
4525                                         }
4526
4527                                         sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4528                                 }
4529                         }
4530                 }
4531         }
4532
4533         if (lock_cmd_fail) {
4534                 scsi_set_resid(srb, 0);
4535                 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4536                 return TRANSPORT_FAILED;
4537         }
4538 #endif  /* SUPPORT_SD_LOCK */
4539
4540         scsi_set_resid(srb, 0);
4541         return TRANSPORT_GOOD;
4542
4543 sd_execute_write_cmd_failed:
4544         sd_card->pre_cmd_err = 1;
4545         set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4546         if (write_err)
4547                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
4548
4549         release_sd_card(chip);
4550         do_reset_sd_card(chip);
4551         if (!(chip->card_ready & SD_CARD))
4552                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4553
4554         return TRANSPORT_FAILED;
4555 }
4556
4557 int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4558 {
4559         struct sd_info *sd_card = &chip->sd_card;
4560         unsigned int lun = SCSI_LUN(srb);
4561         int count;
4562         u16 data_len;
4563
4564         if (!sd_card->sd_pass_thru_en) {
4565                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4566                 return TRANSPORT_FAILED;
4567         }
4568
4569         if (sd_card->pre_cmd_err) {
4570                 sd_card->pre_cmd_err = 0;
4571                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4572                 return TRANSPORT_FAILED;
4573         }
4574
4575         data_len = ((u16)srb->cmnd[7] << 8) | srb->cmnd[8];
4576
4577         if (sd_card->last_rsp_type == SD_RSP_TYPE_R0) {
4578                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4579                 return TRANSPORT_FAILED;
4580         } else if (sd_card->last_rsp_type == SD_RSP_TYPE_R2) {
4581                 count = (data_len < 17) ? data_len : 17;
4582         } else {
4583                 count = (data_len < 6) ? data_len : 6;
4584         }
4585         rtsx_stor_set_xfer_buf(sd_card->rsp, count, srb);
4586
4587         dev_dbg(rtsx_dev(chip), "Response length: %d\n", data_len);
4588         dev_dbg(rtsx_dev(chip), "Response: 0x%x 0x%x 0x%x 0x%x\n",
4589                 sd_card->rsp[0], sd_card->rsp[1],
4590                 sd_card->rsp[2], sd_card->rsp[3]);
4591
4592         scsi_set_resid(srb, 0);
4593         return TRANSPORT_GOOD;
4594 }
4595
4596 int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4597 {
4598         struct sd_info *sd_card = &chip->sd_card;
4599         unsigned int lun = SCSI_LUN(srb);
4600         int retval;
4601
4602         if (!sd_card->sd_pass_thru_en) {
4603                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4604                 return TRANSPORT_FAILED;
4605         }
4606
4607         if (sd_card->pre_cmd_err) {
4608                 sd_card->pre_cmd_err = 0;
4609                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4610                 return TRANSPORT_FAILED;
4611         }
4612
4613         if ((srb->cmnd[2] != 0x53) || (srb->cmnd[3] != 0x44) ||
4614             (srb->cmnd[4] != 0x20) || (srb->cmnd[5] != 0x43) ||
4615             (srb->cmnd[6] != 0x61) || (srb->cmnd[7] != 0x72) ||
4616             (srb->cmnd[8] != 0x64)) {
4617                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4618                 return TRANSPORT_FAILED;
4619         }
4620
4621         switch (srb->cmnd[1] & 0x0F) {
4622         case 0:
4623 #ifdef SUPPORT_SD_LOCK
4624                 if (srb->cmnd[9] == 0x64)
4625                         sd_card->sd_lock_status |= SD_SDR_RST;
4626 #endif
4627                 retval = reset_sd_card(chip);
4628                 if (retval != STATUS_SUCCESS) {
4629 #ifdef SUPPORT_SD_LOCK
4630                         sd_card->sd_lock_status &= ~SD_SDR_RST;
4631 #endif
4632                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4633                         sd_card->pre_cmd_err = 1;
4634                         return TRANSPORT_FAILED;
4635                 }
4636 #ifdef SUPPORT_SD_LOCK
4637                 sd_card->sd_lock_status &= ~SD_SDR_RST;
4638 #endif
4639                 break;
4640
4641         case 1:
4642                 retval = soft_reset_sd_card(chip);
4643                 if (retval != STATUS_SUCCESS) {
4644                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4645                         sd_card->pre_cmd_err = 1;
4646                         return TRANSPORT_FAILED;
4647                 }
4648                 break;
4649
4650         default:
4651                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4652                 return TRANSPORT_FAILED;
4653         }
4654
4655         scsi_set_resid(srb, 0);
4656         return TRANSPORT_GOOD;
4657 }
4658 #endif
4659
4660 void sd_cleanup_work(struct rtsx_chip *chip)
4661 {
4662         struct sd_info *sd_card = &chip->sd_card;
4663
4664         if (sd_card->seq_mode) {
4665                 dev_dbg(rtsx_dev(chip), "SD: stop transmission\n");
4666                 sd_stop_seq_mode(chip);
4667                 sd_card->cleanup_counter = 0;
4668         }
4669 }
4670
4671 int sd_power_off_card3v3(struct rtsx_chip *chip)
4672 {
4673         int retval;
4674
4675         retval = disable_card_clock(chip, SD_CARD);
4676         if (retval != STATUS_SUCCESS)
4677                 return STATUS_FAIL;
4678
4679         retval = rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
4680         if (retval)
4681                 return retval;
4682
4683         if (!chip->ft2_fast_mode) {
4684                 retval = card_power_off(chip, SD_CARD);
4685                 if (retval != STATUS_SUCCESS)
4686                         return STATUS_FAIL;
4687
4688                 mdelay(50);
4689         }
4690
4691         if (chip->asic_code) {
4692                 retval = sd_pull_ctl_disable(chip);
4693                 if (retval != STATUS_SUCCESS)
4694                         return STATUS_FAIL;
4695         } else {
4696                 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
4697                                              FPGA_SD_PULL_CTL_BIT | 0x20,
4698                                              FPGA_SD_PULL_CTL_BIT);
4699                 if (retval)
4700                         return retval;
4701         }
4702
4703         return STATUS_SUCCESS;
4704 }
4705
4706 int release_sd_card(struct rtsx_chip *chip)
4707 {
4708         struct sd_info *sd_card = &chip->sd_card;
4709         int retval;
4710
4711         chip->card_ready &= ~SD_CARD;
4712         chip->card_fail &= ~SD_CARD;
4713         chip->card_wp &= ~SD_CARD;
4714
4715         chip->sd_io = 0;
4716         chip->sd_int = 0;
4717
4718 #ifdef SUPPORT_SD_LOCK
4719         sd_card->sd_lock_status = 0;
4720         sd_card->sd_erase_status = 0;
4721 #endif
4722
4723         memset(sd_card->raw_csd, 0, 16);
4724         memset(sd_card->raw_scr, 0, 8);
4725
4726         retval = sd_power_off_card3v3(chip);
4727         if (retval != STATUS_SUCCESS)
4728                 return STATUS_FAIL;
4729
4730         return STATUS_SUCCESS;
4731 }