drivers/spi/spi-rockchip.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  * Author: Addy Ke <[email protected]>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/dmaengine.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/pinctrl/consumer.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/spi/spi.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/scatterlist.h>
  26
  27 #define DRIVER_NAME "rockchip-spi"
  28
  29 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
  30                 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
  31 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \
  32                 writel_relaxed(readl_relaxed(reg) | (bits), reg)
  33
  34 /* SPI register offsets */
  35 #define ROCKCHIP_SPI_CTRLR0                     0x0000
  36 #define ROCKCHIP_SPI_CTRLR1                     0x0004
  37 #define ROCKCHIP_SPI_SSIENR                     0x0008
  38 #define ROCKCHIP_SPI_SER                        0x000c
  39 #define ROCKCHIP_SPI_BAUDR                      0x0010
  40 #define ROCKCHIP_SPI_TXFTLR                     0x0014
  41 #define ROCKCHIP_SPI_RXFTLR                     0x0018
  42 #define ROCKCHIP_SPI_TXFLR                      0x001c
  43 #define ROCKCHIP_SPI_RXFLR                      0x0020
  44 #define ROCKCHIP_SPI_SR                         0x0024
  45 #define ROCKCHIP_SPI_IPR                        0x0028
  46 #define ROCKCHIP_SPI_IMR                        0x002c
  47 #define ROCKCHIP_SPI_ISR                        0x0030
  48 #define ROCKCHIP_SPI_RISR                       0x0034
  49 #define ROCKCHIP_SPI_ICR                        0x0038
  50 #define ROCKCHIP_SPI_DMACR                      0x003c
  51 #define ROCKCHIP_SPI_DMATDLR            0x0040
  52 #define ROCKCHIP_SPI_DMARDLR            0x0044
  53 #define ROCKCHIP_SPI_TXDR                       0x0400
  54 #define ROCKCHIP_SPI_RXDR                       0x0800
  55
  56 /* Bit fields in CTRLR0 */
  57 #define CR0_DFS_OFFSET                          0
  58 #define CR0_DFS_4BIT                            0x0
  59 #define CR0_DFS_8BIT                            0x1
  60 #define CR0_DFS_16BIT                           0x2
  61
  62 #define CR0_CFS_OFFSET                          2
  63
  64 #define CR0_SCPH_OFFSET                         6
  65
  66 #define CR0_SCPOL_OFFSET                        7
  67
  68 #define CR0_CSM_OFFSET                          8
  69 #define CR0_CSM_KEEP                            0x0
  70 /* ss_n be high for half sclk_out cycles */
  71 #define CR0_CSM_HALF                            0X1
  72 /* ss_n be high for one sclk_out cycle */
  73 #define CR0_CSM_ONE                                     0x2
  74
  75 /* ss_n to sclk_out delay */
  76 #define CR0_SSD_OFFSET                          10
  77 /*
  78  * The period between ss_n active and
  79  * sclk_out active is half sclk_out cycles
  80  */
  81 #define CR0_SSD_HALF                            0x0
  82 /*
  83  * The period between ss_n active and
  84  * sclk_out active is one sclk_out cycle
  85  */
  86 #define CR0_SSD_ONE                                     0x1
  87
  88 #define CR0_EM_OFFSET                           11
  89 #define CR0_EM_LITTLE                           0x0
  90 #define CR0_EM_BIG                                      0x1
  91
  92 #define CR0_FBM_OFFSET                          12
  93 #define CR0_FBM_MSB                                     0x0
  94 #define CR0_FBM_LSB                                     0x1
  95
  96 #define CR0_BHT_OFFSET                          13
  97 #define CR0_BHT_16BIT                           0x0
  98 #define CR0_BHT_8BIT                            0x1
  99
 100 #define CR0_RSD_OFFSET                          14
 101 #define CR0_RSD_MAX                             0x3
 102
 103 #define CR0_FRF_OFFSET                          16
 104 #define CR0_FRF_SPI                                     0x0
 105 #define CR0_FRF_SSP                                     0x1
 106 #define CR0_FRF_MICROWIRE                       0x2
 107
 108 #define CR0_XFM_OFFSET                          18
 109 #define CR0_XFM_MASK                            (0x03 << SPI_XFM_OFFSET)
 110 #define CR0_XFM_TR                                      0x0
 111 #define CR0_XFM_TO                                      0x1
 112 #define CR0_XFM_RO                                      0x2
 113
 114 #define CR0_OPM_OFFSET                          20
 115 #define CR0_OPM_MASTER                          0x0
 116 #define CR0_OPM_SLAVE                           0x1
 117
 118 #define CR0_MTM_OFFSET                          0x21
 119
 120 /* Bit fields in SER, 2bit */
 121 #define SER_MASK                                        0x3
 122
 123 /* Bit fields in BAUDR */
 124 #define BAUDR_SCKDV_MIN                         2
 125 #define BAUDR_SCKDV_MAX                         65534
 126
 127 /* Bit fields in SR, 5bit */
 128 #define SR_MASK                                         0x1f
 129 #define SR_BUSY                                         (1 << 0)
 130 #define SR_TF_FULL                                      (1 << 1)
 131 #define SR_TF_EMPTY                                     (1 << 2)
 132 #define SR_RF_EMPTY                                     (1 << 3)
 133 #define SR_RF_FULL                                      (1 << 4)
 134
 135 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
 136 #define INT_MASK                                        0x1f
 137 #define INT_TF_EMPTY                            (1 << 0)
 138 #define INT_TF_OVERFLOW                         (1 << 1)
 139 #define INT_RF_UNDERFLOW                        (1 << 2)
 140 #define INT_RF_OVERFLOW                         (1 << 3)
 141 #define INT_RF_FULL                                     (1 << 4)
 142
 143 /* Bit fields in ICR, 4bit */
 144 #define ICR_MASK                                        0x0f
 145 #define ICR_ALL                                         (1 << 0)
 146 #define ICR_RF_UNDERFLOW                        (1 << 1)
 147 #define ICR_RF_OVERFLOW                         (1 << 2)
 148 #define ICR_TF_OVERFLOW                         (1 << 3)
 149
 150 /* Bit fields in DMACR */
 151 #define RF_DMA_EN                                       (1 << 0)
 152 #define TF_DMA_EN                                       (1 << 1)
 153
 154 /* Driver state flags */
 155 #define RXDMA                                   (1 << 0)
 156 #define TXDMA                                   (1 << 1)
 157
 158 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
 159 #define MAX_SCLK_OUT                            50000000U
 160
 161 /*
 162  * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
 163  * the controller seems to hang when given 0x10000, so stick with this for now.
 164  */
 165 #define ROCKCHIP_SPI_MAX_TRANLEN                0xffff
 166
 167 #define ROCKCHIP_SPI_MAX_CS_NUM                 2
 168
 169 struct rockchip_spi {
 170         struct device *dev;
 171
 172         struct clk *spiclk;
 173         struct clk *apb_pclk;
 174
 175         void __iomem *regs;
 176         dma_addr_t dma_addr_rx;
 177         dma_addr_t dma_addr_tx;
 178
 179         const void *tx;
 180         void *rx;
 181         unsigned int tx_left;
 182         unsigned int rx_left;
 183
 184         atomic_t state;
 185
 186         /*depth of the FIFO buffer */
 187         u32 fifo_len;
 188         /* frequency of spiclk */
 189         u32 freq;
 190
 191         u8 n_bytes;
 192         u8 rsd;
 193
 194         bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
 195 };
 196
 197 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
 198 {
 199         writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
 200 }
 201
 202 static inline void wait_for_idle(struct rockchip_spi *rs)
 203 {
 204         unsigned long timeout = jiffies + msecs_to_jiffies(5);
 205
 206         do {
 207                 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
 208                         return;
 209         } while (!time_after(jiffies, timeout));
 210
 211         dev_warn(rs->dev, "spi controller is in busy state!\n");
 212 }
 213
 214 static u32 get_fifo_len(struct rockchip_spi *rs)
 215 {
 216         u32 fifo;
 217
 218         for (fifo = 2; fifo < 32; fifo++) {
 219                 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
 220                 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
 221                         break;
 222         }
 223
 224         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
 225
 226         return (fifo == 31) ? 0 : fifo;
 227 }
 228
 229 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
 230 {
 231         struct spi_master *master = spi->master;
 232         struct rockchip_spi *rs = spi_master_get_devdata(master);
 233         bool cs_asserted = !enable;
 234
 235         /* Return immediately for no-op */
 236         if (cs_asserted == rs->cs_asserted[spi->chip_select])
 237                 return;
 238
 239         if (cs_asserted) {
 240                 /* Keep things powered as long as CS is asserted */
 241                 pm_runtime_get_sync(rs->dev);
 242
 243                 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER,
 244                                       BIT(spi->chip_select));
 245         } else {
 246                 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER,
 247                                       BIT(spi->chip_select));
 248
 249                 /* Drop reference from when we first asserted CS */
 250                 pm_runtime_put(rs->dev);
 251         }
 252
 253         rs->cs_asserted[spi->chip_select] = cs_asserted;
 254 }
 255
 256 static void rockchip_spi_handle_err(struct spi_master *master,
 257                                     struct spi_message *msg)
 258 {
 259         struct rockchip_spi *rs = spi_master_get_devdata(master);
 260
 261         /* stop running spi transfer
 262          * this also flushes both rx and tx fifos
 263          */
 264         spi_enable_chip(rs, false);
 265
 266         /* make sure all interrupts are masked */
 267         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 268
 269         if (atomic_read(&rs->state) & TXDMA)
 270                 dmaengine_terminate_async(master->dma_tx);
 271
 272         if (atomic_read(&rs->state) & RXDMA)
 273                 dmaengine_terminate_async(master->dma_rx);
 274 }
 275
 276 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
 277 {
 278         u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
 279         u32 words = min(rs->tx_left, tx_free);
 280
 281         rs->tx_left -= words;
 282         for (; words; words--) {
 283                 u32 txw;
 284
 285                 if (rs->n_bytes == 1)
 286                         txw = *(u8 *)rs->tx;
 287                 else
 288                         txw = *(u16 *)rs->tx;
 289
 290                 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
 291                 rs->tx += rs->n_bytes;
 292         }
 293 }
 294
 295 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
 296 {
 297         u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 298         u32 rx_left = rs->rx_left - words;
 299
 300         /* the hardware doesn't allow us to change fifo threshold
 301          * level while spi is enabled, so instead make sure to leave
 302          * enough words in the rx fifo to get the last interrupt
 303          * exactly when all words have been received
 304          */
 305         if (rx_left) {
 306                 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1;
 307
 308                 if (rx_left < ftl) {
 309                         rx_left = ftl;
 310                         words = rs->rx_left - rx_left;
 311                 }
 312         }
 313
 314         rs->rx_left = rx_left;
 315         for (; words; words--) {
 316                 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 317
 318                 if (!rs->rx)
 319                         continue;
 320
 321                 if (rs->n_bytes == 1)
 322                         *(u8 *)rs->rx = (u8)rxw;
 323                 else
 324                         *(u16 *)rs->rx = (u16)rxw;
 325                 rs->rx += rs->n_bytes;
 326         }
 327 }
 328
 329 static irqreturn_t rockchip_spi_isr(int irq, void *dev_id)
 330 {
 331         struct spi_master *master = dev_id;
 332         struct rockchip_spi *rs = spi_master_get_devdata(master);
 333
 334         if (rs->tx_left)
 335                 rockchip_spi_pio_writer(rs);
 336
 337         rockchip_spi_pio_reader(rs);
 338         if (!rs->rx_left) {
 339                 spi_enable_chip(rs, false);
 340                 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 341                 spi_finalize_current_transfer(master);
 342         }
 343
 344         return IRQ_HANDLED;
 345 }
 346
 347 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs,
 348                 struct spi_transfer *xfer)
 349 {
 350         rs->tx = xfer->tx_buf;
 351         rs->rx = xfer->rx_buf;
 352         rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
 353         rs->rx_left = xfer->len / rs->n_bytes;
 354
 355         writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
 356         spi_enable_chip(rs, true);
 357
 358         if (rs->tx_left)
 359                 rockchip_spi_pio_writer(rs);
 360
 361         /* 1 means the transfer is in progress */
 362         return 1;
 363 }
 364
 365 static void rockchip_spi_dma_rxcb(void *data)
 366 {
 367         struct spi_master *master = data;
 368         struct rockchip_spi *rs = spi_master_get_devdata(master);
 369         int state = atomic_fetch_andnot(RXDMA, &rs->state);
 370
 371         if (state & TXDMA)
 372                 return;
 373
 374         spi_enable_chip(rs, false);
 375         spi_finalize_current_transfer(master);
 376 }
 377
 378 static void rockchip_spi_dma_txcb(void *data)
 379 {
 380         struct spi_master *master = data;
 381         struct rockchip_spi *rs = spi_master_get_devdata(master);
 382         int state = atomic_fetch_andnot(TXDMA, &rs->state);
 383
 384         if (state & RXDMA)
 385                 return;
 386
 387         /* Wait until the FIFO data completely. */
 388         wait_for_idle(rs);
 389
 390         spi_enable_chip(rs, false);
 391         spi_finalize_current_transfer(master);
 392 }
 393
 394 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
 395                 struct spi_master *master, struct spi_transfer *xfer)
 396 {
 397         struct dma_async_tx_descriptor *rxdesc, *txdesc;
 398
 399         atomic_set(&rs->state, 0);
 400
 401         rxdesc = NULL;
 402         if (xfer->rx_buf) {
 403                 struct dma_slave_config rxconf = {
 404                         .direction = DMA_DEV_TO_MEM,
 405                         .src_addr = rs->dma_addr_rx,
 406                         .src_addr_width = rs->n_bytes,
 407                         .src_maxburst = 1,
 408                 };
 409
 410                 dmaengine_slave_config(master->dma_rx, &rxconf);
 411
 412                 rxdesc = dmaengine_prep_slave_sg(
 413                                 master->dma_rx,
 414                                 xfer->rx_sg.sgl, xfer->rx_sg.nents,
 415                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
 416                 if (!rxdesc)
 417                         return -EINVAL;
 418
 419                 rxdesc->callback = rockchip_spi_dma_rxcb;
 420                 rxdesc->callback_param = master;
 421         }
 422
 423         txdesc = NULL;
 424         if (xfer->tx_buf) {
 425                 struct dma_slave_config txconf = {
 426                         .direction = DMA_MEM_TO_DEV,
 427                         .dst_addr = rs->dma_addr_tx,
 428                         .dst_addr_width = rs->n_bytes,
 429                         .dst_maxburst = rs->fifo_len / 2,
 430                 };
 431
 432                 dmaengine_slave_config(master->dma_tx, &txconf);
 433
 434                 txdesc = dmaengine_prep_slave_sg(
 435                                 master->dma_tx,
 436                                 xfer->tx_sg.sgl, xfer->tx_sg.nents,
 437                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 438                 if (!txdesc) {
 439                         if (rxdesc)
 440                                 dmaengine_terminate_sync(master->dma_rx);
 441                         return -EINVAL;
 442                 }
 443
 444                 txdesc->callback = rockchip_spi_dma_txcb;
 445                 txdesc->callback_param = master;
 446         }
 447
 448         /* rx must be started before tx due to spi instinct */
 449         if (rxdesc) {
 450                 atomic_or(RXDMA, &rs->state);
 451                 dmaengine_submit(rxdesc);
 452                 dma_async_issue_pending(master->dma_rx);
 453         }
 454
 455         spi_enable_chip(rs, true);
 456
 457         if (txdesc) {
 458                 atomic_or(TXDMA, &rs->state);
 459                 dmaengine_submit(txdesc);
 460                 dma_async_issue_pending(master->dma_tx);
 461         }
 462
 463         /* 1 means the transfer is in progress */
 464         return 1;
 465 }
 466
 467 static void rockchip_spi_config(struct rockchip_spi *rs,
 468                 struct spi_device *spi, struct spi_transfer *xfer,
 469                 bool use_dma)
 470 {
 471         u32 cr0 = CR0_FRF_SPI  << CR0_FRF_OFFSET
 472                 | CR0_BHT_8BIT << CR0_BHT_OFFSET
 473                 | CR0_SSD_ONE  << CR0_SSD_OFFSET
 474                 | CR0_EM_BIG   << CR0_EM_OFFSET;
 475         u32 cr1;
 476         u32 dmacr = 0;
 477
 478         cr0 |= rs->rsd << CR0_RSD_OFFSET;
 479         cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
 480         if (spi->mode & SPI_LSB_FIRST)
 481                 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
 482
 483         if (xfer->rx_buf && xfer->tx_buf)
 484                 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
 485         else if (xfer->rx_buf)
 486                 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
 487         else if (use_dma)
 488                 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
 489
 490         switch (xfer->bits_per_word) {
 491         case 4:
 492                 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET;
 493                 cr1 = xfer->len - 1;
 494                 break;
 495         case 8:
 496                 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET;
 497                 cr1 = xfer->len - 1;
 498                 break;
 499         case 16:
 500                 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET;
 501                 cr1 = xfer->len / 2 - 1;
 502                 break;
 503         default:
 504                 /* we only whitelist 4, 8 and 16 bit words in
 505                  * master->bits_per_word_mask, so this shouldn't
 506                  * happen
 507                  */
 508                 unreachable();
 509         }
 510
 511         if (use_dma) {
 512                 if (xfer->tx_buf)
 513                         dmacr |= TF_DMA_EN;
 514                 if (xfer->rx_buf)
 515                         dmacr |= RF_DMA_EN;
 516         }
 517
 518         writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
 519         writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 520
 521         /* unfortunately setting the fifo threshold level to generate an
 522          * interrupt exactly when the fifo is full doesn't seem to work,
 523          * so we need the strict inequality here
 524          */
 525         if (xfer->len < rs->fifo_len)
 526                 writel_relaxed(xfer->len - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 527         else
 528                 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 529
 530         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
 531         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
 532         writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
 533
 534         /* the hardware only supports an even clock divisor, so
 535          * round divisor = spiclk / speed up to nearest even number
 536          * so that the resulting speed is <= the requested speed
 537          */
 538         writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
 539                         rs->regs + ROCKCHIP_SPI_BAUDR);
 540 }
 541
 542 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
 543 {
 544         return ROCKCHIP_SPI_MAX_TRANLEN;
 545 }
 546
 547 static int rockchip_spi_transfer_one(
 548                 struct spi_master *master,
 549                 struct spi_device *spi,
 550                 struct spi_transfer *xfer)
 551 {
 552         struct rockchip_spi *rs = spi_master_get_devdata(master);
 553         bool use_dma;
 554
 555         WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
 556                 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
 557
 558         if (!xfer->tx_buf && !xfer->rx_buf) {
 559                 dev_err(rs->dev, "No buffer for transfer\n");
 560                 return -EINVAL;
 561         }
 562
 563         if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
 564                 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
 565                 return -EINVAL;
 566         }
 567
 568         rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
 569
 570         use_dma = master->can_dma ? master->can_dma(master, spi, xfer) : false;
 571
 572         rockchip_spi_config(rs, spi, xfer, use_dma);
 573
 574         if (use_dma)
 575                 return rockchip_spi_prepare_dma(rs, master, xfer);
 576
 577         return rockchip_spi_prepare_irq(rs, xfer);
 578 }
 579
 580 static bool rockchip_spi_can_dma(struct spi_master *master,
 581                                  struct spi_device *spi,
 582                                  struct spi_transfer *xfer)
 583 {
 584         struct rockchip_spi *rs = spi_master_get_devdata(master);
 585         unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2;
 586
 587         /* if the numbor of spi words to transfer is less than the fifo
 588          * length we can just fill the fifo and wait for a single irq,
 589          * so don't bother setting up dma
 590          */
 591         return xfer->len / bytes_per_word >= rs->fifo_len;
 592 }
 593
 594 static int rockchip_spi_probe(struct platform_device *pdev)
 595 {
 596         int ret;
 597         struct rockchip_spi *rs;
 598         struct spi_master *master;
 599         struct resource *mem;
 600         u32 rsd_nsecs;
 601
 602         master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
 603         if (!master)
 604                 return -ENOMEM;
 605
 606         platform_set_drvdata(pdev, master);
 607
 608         rs = spi_master_get_devdata(master);
 609
 610         /* Get basic io resource and map it */
 611         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 612         rs->regs = devm_ioremap_resource(&pdev->dev, mem);
 613         if (IS_ERR(rs->regs)) {
 614                 ret =  PTR_ERR(rs->regs);
 615                 goto err_put_master;
 616         }
 617
 618         rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
 619         if (IS_ERR(rs->apb_pclk)) {
 620                 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
 621                 ret = PTR_ERR(rs->apb_pclk);
 622                 goto err_put_master;
 623         }
 624
 625         rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
 626         if (IS_ERR(rs->spiclk)) {
 627                 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
 628                 ret = PTR_ERR(rs->spiclk);
 629                 goto err_put_master;
 630         }
 631
 632         ret = clk_prepare_enable(rs->apb_pclk);
 633         if (ret < 0) {
 634                 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
 635                 goto err_put_master;
 636         }
 637
 638         ret = clk_prepare_enable(rs->spiclk);
 639         if (ret < 0) {
 640                 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
 641                 goto err_disable_apbclk;
 642         }
 643
 644         spi_enable_chip(rs, false);
 645
 646         ret = platform_get_irq(pdev, 0);
 647         if (ret < 0)
 648                 goto err_disable_spiclk;
 649
 650         ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
 651                         IRQF_ONESHOT, dev_name(&pdev->dev), master);
 652         if (ret)
 653                 goto err_disable_spiclk;
 654
 655         rs->dev = &pdev->dev;
 656         rs->freq = clk_get_rate(rs->spiclk);
 657
 658         if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
 659                                   &rsd_nsecs)) {
 660                 /* rx sample delay is expressed in parent clock cycles (max 3) */
 661                 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8),
 662                                 1000000000 >> 8);
 663                 if (!rsd) {
 664                         dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n",
 665                                         rs->freq, rsd_nsecs);
 666                 } else if (rsd > CR0_RSD_MAX) {
 667                         rsd = CR0_RSD_MAX;
 668                         dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n",
 669                                         rs->freq, rsd_nsecs,
 670                                         CR0_RSD_MAX * 1000000000U / rs->freq);
 671                 }
 672                 rs->rsd = rsd;
 673         }
 674
 675         rs->fifo_len = get_fifo_len(rs);
 676         if (!rs->fifo_len) {
 677                 dev_err(&pdev->dev, "Failed to get fifo length\n");
 678                 ret = -EINVAL;
 679                 goto err_disable_spiclk;
 680         }
 681
 682         pm_runtime_set_active(&pdev->dev);
 683         pm_runtime_enable(&pdev->dev);
 684
 685         master->auto_runtime_pm = true;
 686         master->bus_num = pdev->id;
 687         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
 688         master->num_chipselect = ROCKCHIP_SPI_MAX_CS_NUM;
 689         master->dev.of_node = pdev->dev.of_node;
 690         master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
 691         master->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
 692         master->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
 693
 694         master->set_cs = rockchip_spi_set_cs;
 695         master->transfer_one = rockchip_spi_transfer_one;
 696         master->max_transfer_size = rockchip_spi_max_transfer_size;
 697         master->handle_err = rockchip_spi_handle_err;
 698         master->flags = SPI_MASTER_GPIO_SS;
 699
 700         master->dma_tx = dma_request_chan(rs->dev, "tx");
 701         if (IS_ERR(master->dma_tx)) {
 702                 /* Check tx to see if we need defer probing driver */
 703                 if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) {
 704                         ret = -EPROBE_DEFER;
 705                         goto err_disable_pm_runtime;
 706                 }
 707                 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
 708                 master->dma_tx = NULL;
 709         }
 710
 711         master->dma_rx = dma_request_chan(rs->dev, "rx");
 712         if (IS_ERR(master->dma_rx)) {
 713                 if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) {
 714                         ret = -EPROBE_DEFER;
 715                         goto err_free_dma_tx;
 716                 }
 717                 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
 718                 master->dma_rx = NULL;
 719         }
 720
 721         if (master->dma_tx && master->dma_rx) {
 722                 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
 723                 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
 724                 master->can_dma = rockchip_spi_can_dma;
 725         }
 726
 727         ret = devm_spi_register_master(&pdev->dev, master);
 728         if (ret < 0) {
 729                 dev_err(&pdev->dev, "Failed to register master\n");
 730                 goto err_free_dma_rx;
 731         }
 732
 733         return 0;
 734
 735 err_free_dma_rx:
 736         if (master->dma_rx)
 737                 dma_release_channel(master->dma_rx);
 738 err_free_dma_tx:
 739         if (master->dma_tx)
 740                 dma_release_channel(master->dma_tx);
 741 err_disable_pm_runtime:
 742         pm_runtime_disable(&pdev->dev);
 743 err_disable_spiclk:
 744         clk_disable_unprepare(rs->spiclk);
 745 err_disable_apbclk:
 746         clk_disable_unprepare(rs->apb_pclk);
 747 err_put_master:
 748         spi_master_put(master);
 749
 750         return ret;
 751 }
 752
 753 static int rockchip_spi_remove(struct platform_device *pdev)
 754 {
 755         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
 756         struct rockchip_spi *rs = spi_master_get_devdata(master);
 757
 758         pm_runtime_get_sync(&pdev->dev);
 759
 760         clk_disable_unprepare(rs->spiclk);
 761         clk_disable_unprepare(rs->apb_pclk);
 762
 763         pm_runtime_put_noidle(&pdev->dev);
 764         pm_runtime_disable(&pdev->dev);
 765         pm_runtime_set_suspended(&pdev->dev);
 766
 767         if (master->dma_tx)
 768                 dma_release_channel(master->dma_tx);
 769         if (master->dma_rx)
 770                 dma_release_channel(master->dma_rx);
 771
 772         spi_master_put(master);
 773
 774         return 0;
 775 }
 776
 777 #ifdef CONFIG_PM_SLEEP
 778 static int rockchip_spi_suspend(struct device *dev)
 779 {
 780         int ret;
 781         struct spi_master *master = dev_get_drvdata(dev);
 782
 783         ret = spi_master_suspend(master);
 784         if (ret < 0)
 785                 return ret;
 786
 787         ret = pm_runtime_force_suspend(dev);
 788         if (ret < 0)
 789                 return ret;
 790
 791         pinctrl_pm_select_sleep_state(dev);
 792
 793         return 0;
 794 }
 795
 796 static int rockchip_spi_resume(struct device *dev)
 797 {
 798         int ret;
 799         struct spi_master *master = dev_get_drvdata(dev);
 800         struct rockchip_spi *rs = spi_master_get_devdata(master);
 801
 802         pinctrl_pm_select_default_state(dev);
 803
 804         ret = pm_runtime_force_resume(dev);
 805         if (ret < 0)
 806                 return ret;
 807
 808         ret = spi_master_resume(master);
 809         if (ret < 0) {
 810                 clk_disable_unprepare(rs->spiclk);
 811                 clk_disable_unprepare(rs->apb_pclk);
 812         }
 813
 814         return 0;
 815 }
 816 #endif /* CONFIG_PM_SLEEP */
 817
 818 #ifdef CONFIG_PM
 819 static int rockchip_spi_runtime_suspend(struct device *dev)
 820 {
 821         struct spi_master *master = dev_get_drvdata(dev);
 822         struct rockchip_spi *rs = spi_master_get_devdata(master);
 823
 824         clk_disable_unprepare(rs->spiclk);
 825         clk_disable_unprepare(rs->apb_pclk);
 826
 827         return 0;
 828 }
 829
 830 static int rockchip_spi_runtime_resume(struct device *dev)
 831 {
 832         int ret;
 833         struct spi_master *master = dev_get_drvdata(dev);
 834         struct rockchip_spi *rs = spi_master_get_devdata(master);
 835
 836         ret = clk_prepare_enable(rs->apb_pclk);
 837         if (ret < 0)
 838                 return ret;
 839
 840         ret = clk_prepare_enable(rs->spiclk);
 841         if (ret < 0)
 842                 clk_disable_unprepare(rs->apb_pclk);
 843
 844         return 0;
 845 }
 846 #endif /* CONFIG_PM */
 847
 848 static const struct dev_pm_ops rockchip_spi_pm = {
 849         SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
 850         SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
 851                            rockchip_spi_runtime_resume, NULL)
 852 };
 853
 854 static const struct of_device_id rockchip_spi_dt_match[] = {
 855         { .compatible = "rockchip,rv1108-spi", },
 856         { .compatible = "rockchip,rk3036-spi", },
 857         { .compatible = "rockchip,rk3066-spi", },
 858         { .compatible = "rockchip,rk3188-spi", },
 859         { .compatible = "rockchip,rk3228-spi", },
 860         { .compatible = "rockchip,rk3288-spi", },
 861         { .compatible = "rockchip,rk3368-spi", },
 862         { .compatible = "rockchip,rk3399-spi", },
 863         { },
 864 };
 865 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
 866
 867 static struct platform_driver rockchip_spi_driver = {
 868         .driver = {
 869                 .name   = DRIVER_NAME,
 870                 .pm = &rockchip_spi_pm,
 871                 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
 872         },
 873         .probe = rockchip_spi_probe,
 874         .remove = rockchip_spi_remove,
 875 };
 876
 877 module_platform_driver(rockchip_spi_driver);
 878
 879 MODULE_AUTHOR("Addy Ke <[email protected]>");
 880 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
 881 MODULE_LICENSE("GPL v2");