drivers/net/phy/dp83867.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Driver for the Texas Instruments DP83867 PHY
   3  *
   4  * Copyright (C) 2015 Texas Instruments Inc.
   5  */
   6
   7 #include <linux/ethtool.h>
   8 #include <linux/kernel.h>
   9 #include <linux/mii.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/phy.h>
  13 #include <linux/delay.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/bitfield.h>
  17
  18 #include <dt-bindings/net/ti-dp83867.h>
  19
  20 #define DP83867_PHY_ID          0x2000a231
  21 #define DP83867_DEVADDR         0x1f
  22
  23 #define MII_DP83867_PHYCTRL     0x10
  24 #define MII_DP83867_PHYSTS      0x11
  25 #define MII_DP83867_MICR        0x12
  26 #define MII_DP83867_ISR         0x13
  27 #define DP83867_CFG2            0x14
  28 #define DP83867_CFG3            0x1e
  29 #define DP83867_CTRL            0x1f
  30
  31 /* Extended Registers */
  32 #define DP83867_FLD_THR_CFG     0x002e
  33 #define DP83867_CFG4            0x0031
  34 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
  35 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS   (3 << 5)
  36 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US  (2 << 5)
  37 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US    (1 << 5)
  38 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS   (0 << 5)
  39
  40 #define DP83867_RGMIICTL        0x0032
  41 #define DP83867_STRAP_STS1      0x006E
  42 #define DP83867_STRAP_STS2      0x006f
  43 #define DP83867_RGMIIDCTL       0x0086
  44 #define DP83867_RXFCFG          0x0134
  45 #define DP83867_RXFPMD1 0x0136
  46 #define DP83867_RXFPMD2 0x0137
  47 #define DP83867_RXFPMD3 0x0138
  48 #define DP83867_RXFSOP1 0x0139
  49 #define DP83867_RXFSOP2 0x013A
  50 #define DP83867_RXFSOP3 0x013B
  51 #define DP83867_IO_MUX_CFG      0x0170
  52 #define DP83867_SGMIICTL        0x00D3
  53 #define DP83867_10M_SGMII_CFG   0x016F
  54 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
  55
  56 #define DP83867_SW_RESET        BIT(15)
  57 #define DP83867_SW_RESTART      BIT(14)
  58
  59 /* MICR Interrupt bits */
  60 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  61 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  62 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  63 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  64 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  65 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  66 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  67 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  68 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  69 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  70 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  71 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  72
  73 /* RGMIICTL bits */
  74 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  75 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  76
  77 /* SGMIICTL bits */
  78 #define DP83867_SGMII_TYPE              BIT(14)
  79
  80 /* RXFCFG bits*/
  81 #define DP83867_WOL_MAGIC_EN            BIT(0)
  82 #define DP83867_WOL_BCAST_EN            BIT(2)
  83 #define DP83867_WOL_UCAST_EN            BIT(4)
  84 #define DP83867_WOL_SEC_EN              BIT(5)
  85 #define DP83867_WOL_ENH_MAC             BIT(7)
  86
  87 /* STRAP_STS1 bits */
  88 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  89
  90 /* STRAP_STS2 bits */
  91 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK     GENMASK(6, 4)
  92 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT    4
  93 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK     GENMASK(2, 0)
  94 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT    0
  95 #define DP83867_STRAP_STS2_CLK_SKEW_NONE        BIT(2)
  96 #define DP83867_STRAP_STS2_STRAP_FLD            BIT(10)
  97
  98 /* PHY CTRL bits */
  99 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT       14
 100 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT       12
 101 #define DP83867_PHYCR_FIFO_DEPTH_MAX            0x03
 102 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK        GENMASK(15, 14)
 103 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK        GENMASK(13, 12)
 104 #define DP83867_PHYCR_RESERVED_MASK             BIT(11)
 105 #define DP83867_PHYCR_FORCE_LINK_GOOD           BIT(10)
 106
 107 /* RGMIIDCTL bits */
 108 #define DP83867_RGMII_TX_CLK_DELAY_MAX          0xf
 109 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
 110 #define DP83867_RGMII_TX_CLK_DELAY_INV  (DP83867_RGMII_TX_CLK_DELAY_MAX + 1)
 111 #define DP83867_RGMII_RX_CLK_DELAY_MAX          0xf
 112 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT        0
 113 #define DP83867_RGMII_RX_CLK_DELAY_INV  (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
 114
 115 /* IO_MUX_CFG bits */
 116 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK    0x1f
 117 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
 118 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
 119 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE        BIT(6)
 120 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK       (0x1f << 8)
 121 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
 122
 123 /* PHY STS bits */
 124 #define DP83867_PHYSTS_1000                     BIT(15)
 125 #define DP83867_PHYSTS_100                      BIT(14)
 126 #define DP83867_PHYSTS_DUPLEX                   BIT(13)
 127 #define DP83867_PHYSTS_LINK                     BIT(10)
 128
 129 /* CFG2 bits */
 130 #define DP83867_DOWNSHIFT_EN            (BIT(8) | BIT(9))
 131 #define DP83867_DOWNSHIFT_ATTEMPT_MASK  (BIT(10) | BIT(11))
 132 #define DP83867_DOWNSHIFT_1_COUNT_VAL   0
 133 #define DP83867_DOWNSHIFT_2_COUNT_VAL   1
 134 #define DP83867_DOWNSHIFT_4_COUNT_VAL   2
 135 #define DP83867_DOWNSHIFT_8_COUNT_VAL   3
 136 #define DP83867_DOWNSHIFT_1_COUNT       1
 137 #define DP83867_DOWNSHIFT_2_COUNT       2
 138 #define DP83867_DOWNSHIFT_4_COUNT       4
 139 #define DP83867_DOWNSHIFT_8_COUNT       8
 140
 141 /* CFG3 bits */
 142 #define DP83867_CFG3_INT_OE                     BIT(7)
 143 #define DP83867_CFG3_ROBUST_AUTO_MDIX           BIT(9)
 144
 145 /* CFG4 bits */
 146 #define DP83867_CFG4_PORT_MIRROR_EN              BIT(0)
 147
 148 /* FLD_THR_CFG */
 149 #define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK        0x7
 150
 151 enum {
 152         DP83867_PORT_MIRROING_KEEP,
 153         DP83867_PORT_MIRROING_EN,
 154         DP83867_PORT_MIRROING_DIS,
 155 };
 156
 157 struct dp83867_private {
 158         u32 rx_id_delay;
 159         u32 tx_id_delay;
 160         u32 tx_fifo_depth;
 161         u32 rx_fifo_depth;
 162         int io_impedance;
 163         int port_mirroring;
 164         bool rxctrl_strap_quirk;
 165         bool set_clk_output;
 166         u32 clk_output_sel;
 167         bool sgmii_ref_clk_en;
 168 };
 169
 170 static int dp83867_ack_interrupt(struct phy_device *phydev)
 171 {
 172         int err = phy_read(phydev, MII_DP83867_ISR);
 173
 174         if (err < 0)
 175                 return err;
 176
 177         return 0;
 178 }
 179
 180 static int dp83867_set_wol(struct phy_device *phydev,
 181                            struct ethtool_wolinfo *wol)
 182 {
 183         struct net_device *ndev = phydev->attached_dev;
 184         u16 val_rxcfg, val_micr;
 185         u8 *mac;
 186
 187         val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
 188         val_micr = phy_read(phydev, MII_DP83867_MICR);
 189
 190         if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
 191                             WAKE_BCAST)) {
 192                 val_rxcfg |= DP83867_WOL_ENH_MAC;
 193                 val_micr |= MII_DP83867_MICR_WOL_INT_EN;
 194
 195                 if (wol->wolopts & WAKE_MAGIC) {
 196                         mac = (u8 *)ndev->dev_addr;
 197
 198                         if (!is_valid_ether_addr(mac))
 199                                 return -EINVAL;
 200
 201                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
 202                                       (mac[1] << 8 | mac[0]));
 203                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
 204                                       (mac[3] << 8 | mac[2]));
 205                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
 206                                       (mac[5] << 8 | mac[4]));
 207
 208                         val_rxcfg |= DP83867_WOL_MAGIC_EN;
 209                 } else {
 210                         val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
 211                 }
 212
 213                 if (wol->wolopts & WAKE_MAGICSECURE) {
 214                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
 215                                       (wol->sopass[1] << 8) | wol->sopass[0]);
 216                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,
 217                                       (wol->sopass[3] << 8) | wol->sopass[2]);
 218                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,
 219                                       (wol->sopass[5] << 8) | wol->sopass[4]);
 220
 221                         val_rxcfg |= DP83867_WOL_SEC_EN;
 222                 } else {
 223                         val_rxcfg &= ~DP83867_WOL_SEC_EN;
 224                 }
 225
 226                 if (wol->wolopts & WAKE_UCAST)
 227                         val_rxcfg |= DP83867_WOL_UCAST_EN;
 228                 else
 229                         val_rxcfg &= ~DP83867_WOL_UCAST_EN;
 230
 231                 if (wol->wolopts & WAKE_BCAST)
 232                         val_rxcfg |= DP83867_WOL_BCAST_EN;
 233                 else
 234                         val_rxcfg &= ~DP83867_WOL_BCAST_EN;
 235         } else {
 236                 val_rxcfg &= ~DP83867_WOL_ENH_MAC;
 237                 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
 238         }
 239
 240         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
 241         phy_write(phydev, MII_DP83867_MICR, val_micr);
 242
 243         return 0;
 244 }
 245
 246 static void dp83867_get_wol(struct phy_device *phydev,
 247                             struct ethtool_wolinfo *wol)
 248 {
 249         u16 value, sopass_val;
 250
 251         wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
 252                         WAKE_MAGICSECURE);
 253         wol->wolopts = 0;
 254
 255         value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
 256
 257         if (value & DP83867_WOL_UCAST_EN)
 258                 wol->wolopts |= WAKE_UCAST;
 259
 260         if (value & DP83867_WOL_BCAST_EN)
 261                 wol->wolopts |= WAKE_BCAST;
 262
 263         if (value & DP83867_WOL_MAGIC_EN)
 264                 wol->wolopts |= WAKE_MAGIC;
 265
 266         if (value & DP83867_WOL_SEC_EN) {
 267                 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
 268                                           DP83867_RXFSOP1);
 269                 wol->sopass[0] = (sopass_val & 0xff);
 270                 wol->sopass[1] = (sopass_val >> 8);
 271
 272                 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
 273                                           DP83867_RXFSOP2);
 274                 wol->sopass[2] = (sopass_val & 0xff);
 275                 wol->sopass[3] = (sopass_val >> 8);
 276
 277                 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
 278                                           DP83867_RXFSOP3);
 279                 wol->sopass[4] = (sopass_val & 0xff);
 280                 wol->sopass[5] = (sopass_val >> 8);
 281
 282                 wol->wolopts |= WAKE_MAGICSECURE;
 283         }
 284
 285         if (!(value & DP83867_WOL_ENH_MAC))
 286                 wol->wolopts = 0;
 287 }
 288
 289 static int dp83867_config_intr(struct phy_device *phydev)
 290 {
 291         int micr_status, err;
 292
 293         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 294                 err = dp83867_ack_interrupt(phydev);
 295                 if (err)
 296                         return err;
 297
 298                 micr_status = phy_read(phydev, MII_DP83867_MICR);
 299                 if (micr_status < 0)
 300                         return micr_status;
 301
 302                 micr_status |=
 303                         (MII_DP83867_MICR_AN_ERR_INT_EN |
 304                         MII_DP83867_MICR_SPEED_CHNG_INT_EN |
 305                         MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
 306                         MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
 307                         MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
 308                         MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
 309
 310                 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
 311         } else {
 312                 micr_status = 0x0;
 313                 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
 314                 if (err)
 315                         return err;
 316
 317                 err = dp83867_ack_interrupt(phydev);
 318         }
 319
 320         return err;
 321 }
 322
 323 static irqreturn_t dp83867_handle_interrupt(struct phy_device *phydev)
 324 {
 325         int irq_status, irq_enabled;
 326
 327         irq_status = phy_read(phydev, MII_DP83867_ISR);
 328         if (irq_status < 0) {
 329                 phy_error(phydev);
 330                 return IRQ_NONE;
 331         }
 332
 333         irq_enabled = phy_read(phydev, MII_DP83867_MICR);
 334         if (irq_enabled < 0) {
 335                 phy_error(phydev);
 336                 return IRQ_NONE;
 337         }
 338
 339         if (!(irq_status & irq_enabled))
 340                 return IRQ_NONE;
 341
 342         phy_trigger_machine(phydev);
 343
 344         return IRQ_HANDLED;
 345 }
 346
 347 static int dp83867_read_status(struct phy_device *phydev)
 348 {
 349         int status = phy_read(phydev, MII_DP83867_PHYSTS);
 350         int ret;
 351
 352         ret = genphy_read_status(phydev);
 353         if (ret)
 354                 return ret;
 355
 356         if (status < 0)
 357                 return status;
 358
 359         if (status & DP83867_PHYSTS_DUPLEX)
 360                 phydev->duplex = DUPLEX_FULL;
 361         else
 362                 phydev->duplex = DUPLEX_HALF;
 363
 364         if (status & DP83867_PHYSTS_1000)
 365                 phydev->speed = SPEED_1000;
 366         else if (status & DP83867_PHYSTS_100)
 367                 phydev->speed = SPEED_100;
 368         else
 369                 phydev->speed = SPEED_10;
 370
 371         return 0;
 372 }
 373
 374 static int dp83867_get_downshift(struct phy_device *phydev, u8 *data)
 375 {
 376         int val, cnt, enable, count;
 377
 378         val = phy_read(phydev, DP83867_CFG2);
 379         if (val < 0)
 380                 return val;
 381
 382         enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val);
 383         cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val);
 384
 385         switch (cnt) {
 386         case DP83867_DOWNSHIFT_1_COUNT_VAL:
 387                 count = DP83867_DOWNSHIFT_1_COUNT;
 388                 break;
 389         case DP83867_DOWNSHIFT_2_COUNT_VAL:
 390                 count = DP83867_DOWNSHIFT_2_COUNT;
 391                 break;
 392         case DP83867_DOWNSHIFT_4_COUNT_VAL:
 393                 count = DP83867_DOWNSHIFT_4_COUNT;
 394                 break;
 395         case DP83867_DOWNSHIFT_8_COUNT_VAL:
 396                 count = DP83867_DOWNSHIFT_8_COUNT;
 397                 break;
 398         default:
 399                 return -EINVAL;
 400         }
 401
 402         *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
 403
 404         return 0;
 405 }
 406
 407 static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt)
 408 {
 409         int val, count;
 410
 411         if (cnt > DP83867_DOWNSHIFT_8_COUNT)
 412                 return -E2BIG;
 413
 414         if (!cnt)
 415                 return phy_clear_bits(phydev, DP83867_CFG2,
 416                                       DP83867_DOWNSHIFT_EN);
 417
 418         switch (cnt) {
 419         case DP83867_DOWNSHIFT_1_COUNT:
 420                 count = DP83867_DOWNSHIFT_1_COUNT_VAL;
 421                 break;
 422         case DP83867_DOWNSHIFT_2_COUNT:
 423                 count = DP83867_DOWNSHIFT_2_COUNT_VAL;
 424                 break;
 425         case DP83867_DOWNSHIFT_4_COUNT:
 426                 count = DP83867_DOWNSHIFT_4_COUNT_VAL;
 427                 break;
 428         case DP83867_DOWNSHIFT_8_COUNT:
 429                 count = DP83867_DOWNSHIFT_8_COUNT_VAL;
 430                 break;
 431         default:
 432                 phydev_err(phydev,
 433                            "Downshift count must be 1, 2, 4 or 8\n");
 434                 return -EINVAL;
 435         }
 436
 437         val = DP83867_DOWNSHIFT_EN;
 438         val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count);
 439
 440         return phy_modify(phydev, DP83867_CFG2,
 441                           DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK,
 442                           val);
 443 }
 444
 445 static int dp83867_get_tunable(struct phy_device *phydev,
 446                                struct ethtool_tunable *tuna, void *data)
 447 {
 448         switch (tuna->id) {
 449         case ETHTOOL_PHY_DOWNSHIFT:
 450                 return dp83867_get_downshift(phydev, data);
 451         default:
 452                 return -EOPNOTSUPP;
 453         }
 454 }
 455
 456 static int dp83867_set_tunable(struct phy_device *phydev,
 457                                struct ethtool_tunable *tuna, const void *data)
 458 {
 459         switch (tuna->id) {
 460         case ETHTOOL_PHY_DOWNSHIFT:
 461                 return dp83867_set_downshift(phydev, *(const u8 *)data);
 462         default:
 463                 return -EOPNOTSUPP;
 464         }
 465 }
 466
 467 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 468 {
 469         struct dp83867_private *dp83867 =
 470                 (struct dp83867_private *)phydev->priv;
 471
 472         if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
 473                 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 474                                  DP83867_CFG4_PORT_MIRROR_EN);
 475         else
 476                 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 477                                    DP83867_CFG4_PORT_MIRROR_EN);
 478         return 0;
 479 }
 480
 481 static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
 482 {
 483         struct dp83867_private *dp83867 = phydev->priv;
 484
 485         /* Existing behavior was to use default pin strapping delay in rgmii
 486          * mode, but rgmii should have meant no delay.  Warn existing users.
 487          */
 488         if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
 489                 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 490                                              DP83867_STRAP_STS2);
 491                 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
 492                                    DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
 493                 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
 494                                    DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
 495
 496                 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
 497                     rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
 498                         phydev_warn(phydev,
 499                                     "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
 500                                     "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n",
 501                                     txskew, rxskew);
 502         }
 503
 504         /* RX delay *must* be specified if internal delay of RX is used. */
 505         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 506              phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
 507              dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) {
 508                 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
 509                 return -EINVAL;
 510         }
 511
 512         /* TX delay *must* be specified if internal delay of TX is used. */
 513         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 514              phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
 515              dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) {
 516                 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
 517                 return -EINVAL;
 518         }
 519
 520         return 0;
 521 }
 522
 523 #if IS_ENABLED(CONFIG_OF_MDIO)
 524 static int dp83867_of_init(struct phy_device *phydev)
 525 {
 526         struct dp83867_private *dp83867 = phydev->priv;
 527         struct device *dev = &phydev->mdio.dev;
 528         struct device_node *of_node = dev->of_node;
 529         int ret;
 530
 531         if (!of_node)
 532                 return -ENODEV;
 533
 534         /* Optional configuration */
 535         ret = of_property_read_u32(of_node, "ti,clk-output-sel",
 536                                    &dp83867->clk_output_sel);
 537         /* If not set, keep default */
 538         if (!ret) {
 539                 dp83867->set_clk_output = true;
 540                 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
 541                  * DP83867_CLK_O_SEL_OFF.
 542                  */
 543                 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
 544                     dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
 545                         phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
 546                                    dp83867->clk_output_sel);
 547                         return -EINVAL;
 548                 }
 549         }
 550
 551         if (of_property_read_bool(of_node, "ti,max-output-impedance"))
 552                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 553         else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
 554                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 555         else
 556                 dp83867->io_impedance = -1; /* leave at default */
 557
 558         dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
 559                                                             "ti,dp83867-rxctrl-strap-quirk");
 560
 561         dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
 562                                                           "ti,sgmii-ref-clock-output-enable");
 563
 564         dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
 565         ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
 566                                    &dp83867->rx_id_delay);
 567         if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
 568                 phydev_err(phydev,
 569                            "ti,rx-internal-delay value of %u out of range\n",
 570                            dp83867->rx_id_delay);
 571                 return -EINVAL;
 572         }
 573
 574         dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV;
 575         ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
 576                                    &dp83867->tx_id_delay);
 577         if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
 578                 phydev_err(phydev,
 579                            "ti,tx-internal-delay value of %u out of range\n",
 580                            dp83867->tx_id_delay);
 581                 return -EINVAL;
 582         }
 583
 584         if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
 585                 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
 586
 587         if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
 588                 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
 589
 590         ret = of_property_read_u32(of_node, "ti,fifo-depth",
 591                                    &dp83867->tx_fifo_depth);
 592         if (ret) {
 593                 ret = of_property_read_u32(of_node, "tx-fifo-depth",
 594                                            &dp83867->tx_fifo_depth);
 595                 if (ret)
 596                         dp83867->tx_fifo_depth =
 597                                         DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
 598         }
 599
 600         if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
 601                 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
 602                            dp83867->tx_fifo_depth);
 603                 return -EINVAL;
 604         }
 605
 606         ret = of_property_read_u32(of_node, "rx-fifo-depth",
 607                                    &dp83867->rx_fifo_depth);
 608         if (ret)
 609                 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
 610
 611         if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
 612                 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
 613                            dp83867->rx_fifo_depth);
 614                 return -EINVAL;
 615         }
 616
 617         return 0;
 618 }
 619 #else
 620 static int dp83867_of_init(struct phy_device *phydev)
 621 {
 622         return 0;
 623 }
 624 #endif /* CONFIG_OF_MDIO */
 625
 626 static int dp83867_probe(struct phy_device *phydev)
 627 {
 628         struct dp83867_private *dp83867;
 629
 630         dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
 631                                GFP_KERNEL);
 632         if (!dp83867)
 633                 return -ENOMEM;
 634
 635         phydev->priv = dp83867;
 636
 637         return dp83867_of_init(phydev);
 638 }
 639
 640 static int dp83867_config_init(struct phy_device *phydev)
 641 {
 642         struct dp83867_private *dp83867 = phydev->priv;
 643         int ret, val, bs;
 644         u16 delay;
 645
 646         /* Force speed optimization for the PHY even if it strapped */
 647         ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
 648                          DP83867_DOWNSHIFT_EN);
 649         if (ret)
 650                 return ret;
 651
 652         ret = dp83867_verify_rgmii_cfg(phydev);
 653         if (ret)
 654                 return ret;
 655
 656         /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
 657         if (dp83867->rxctrl_strap_quirk)
 658                 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 659                                    BIT(7));
 660
 661         bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
 662         if (bs & DP83867_STRAP_STS2_STRAP_FLD) {
 663                 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
 664                  * be set to 0x2. This may causes the PHY link to be unstable -
 665                  * the default value 0x1 need to be restored.
 666                  */
 667                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 668                                      DP83867_FLD_THR_CFG,
 669                                      DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK,
 670                                      0x1);
 671                 if (ret)
 672                         return ret;
 673         }
 674
 675         if (phy_interface_is_rgmii(phydev) ||
 676             phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 677                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 678                 if (val < 0)
 679                         return val;
 680
 681                 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
 682                 val |= (dp83867->tx_fifo_depth <<
 683                         DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
 684
 685                 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 686                         val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
 687                         val |= (dp83867->rx_fifo_depth <<
 688                                 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
 689                 }
 690
 691                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 692                 if (ret)
 693                         return ret;
 694         }
 695
 696         if (phy_interface_is_rgmii(phydev)) {
 697                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 698                 if (val < 0)
 699                         return val;
 700
 701                 /* The code below checks if "port mirroring" N/A MODE4 has been
 702                  * enabled during power on bootstrap.
 703                  *
 704                  * Such N/A mode enabled by mistake can put PHY IC in some
 705                  * internal testing mode and disable RGMII transmission.
 706                  *
 707                  * In this particular case one needs to check STRAP_STS1
 708                  * register's bit 11 (marked as RESERVED).
 709                  */
 710
 711                 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
 712                 if (bs & DP83867_STRAP_STS1_RESERVED)
 713                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 714
 715                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 716                 if (ret)
 717                         return ret;
 718
 719                 /* If rgmii mode with no internal delay is selected, we do NOT use
 720                  * aligned mode as one might expect.  Instead we use the PHY's default
 721                  * based on pin strapping.  And the "mode 0" default is to *use*
 722                  * internal delay with a value of 7 (2.00 ns).
 723                  *
 724                  * Set up RGMII delays
 725                  */
 726                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
 727
 728                 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 729                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 730                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 731
 732                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 733                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 734
 735                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 736                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 737
 738                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
 739
 740                 delay = 0;
 741                 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV)
 742                         delay |= dp83867->rx_id_delay;
 743                 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV)
 744                         delay |= dp83867->tx_id_delay <<
 745                                  DP83867_RGMII_TX_CLK_DELAY_SHIFT;
 746
 747                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
 748                               delay);
 749         }
 750
 751         /* If specified, set io impedance */
 752         if (dp83867->io_impedance >= 0)
 753                 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 754                                DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
 755                                dp83867->io_impedance);
 756
 757         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 758                 /* For support SPEED_10 in SGMII mode
 759                  * DP83867_10M_SGMII_RATE_ADAPT bit
 760                  * has to be cleared by software. That
 761                  * does not affect SPEED_100 and
 762                  * SPEED_1000.
 763                  */
 764                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 765                                      DP83867_10M_SGMII_CFG,
 766                                      DP83867_10M_SGMII_RATE_ADAPT_MASK,
 767                                      0);
 768                 if (ret)
 769                         return ret;
 770
 771                 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
 772                  * are 01). That is not enough to finalize autoneg on some
 773                  * devices. Increase this timer duration to maximum 16ms.
 774                  */
 775                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 776                                      DP83867_CFG4,
 777                                      DP83867_CFG4_SGMII_ANEG_MASK,
 778                                      DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
 779
 780                 if (ret)
 781                         return ret;
 782
 783                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
 784                 /* SGMII type is set to 4-wire mode by default.
 785                  * If we place appropriate property in dts (see above)
 786                  * switch on 6-wire mode.
 787                  */
 788                 if (dp83867->sgmii_ref_clk_en)
 789                         val |= DP83867_SGMII_TYPE;
 790                 else
 791                         val &= ~DP83867_SGMII_TYPE;
 792                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
 793         }
 794
 795         val = phy_read(phydev, DP83867_CFG3);
 796         /* Enable Interrupt output INT_OE in CFG3 register */
 797         if (phy_interrupt_is_valid(phydev))
 798                 val |= DP83867_CFG3_INT_OE;
 799
 800         val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
 801         phy_write(phydev, DP83867_CFG3, val);
 802
 803         if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
 804                 dp83867_config_port_mirroring(phydev);
 805
 806         /* Clock output selection if muxing property is set */
 807         if (dp83867->set_clk_output) {
 808                 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
 809
 810                 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
 811                         val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
 812                 } else {
 813                         mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
 814                         val = dp83867->clk_output_sel <<
 815                               DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
 816                 }
 817
 818                 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 819                                mask, val);
 820         }
 821
 822         return 0;
 823 }
 824
 825 static int dp83867_phy_reset(struct phy_device *phydev)
 826 {
 827         int err;
 828
 829         err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART);
 830         if (err < 0)
 831                 return err;
 832
 833         usleep_range(10, 20);
 834
 835         return phy_modify(phydev, MII_DP83867_PHYCTRL,
 836                          DP83867_PHYCR_FORCE_LINK_GOOD, 0);
 837 }
 838
 839 static struct phy_driver dp83867_driver[] = {
 840         {
 841                 .phy_id         = DP83867_PHY_ID,
 842                 .phy_id_mask    = 0xfffffff0,
 843                 .name           = "TI DP83867",
 844                 /* PHY_GBIT_FEATURES */
 845
 846                 .probe          = dp83867_probe,
 847                 .config_init    = dp83867_config_init,
 848                 .soft_reset     = dp83867_phy_reset,
 849
 850                 .read_status    = dp83867_read_status,
 851                 .get_tunable    = dp83867_get_tunable,
 852                 .set_tunable    = dp83867_set_tunable,
 853
 854                 .get_wol        = dp83867_get_wol,
 855                 .set_wol        = dp83867_set_wol,
 856
 857                 /* IRQ related */
 858                 .config_intr    = dp83867_config_intr,
 859                 .handle_interrupt = dp83867_handle_interrupt,
 860
 861                 .suspend        = genphy_suspend,
 862                 .resume         = genphy_resume,
 863         },
 864 };
 865 module_phy_driver(dp83867_driver);
 866
 867 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
 868         { DP83867_PHY_ID, 0xfffffff0 },
 869         { }
 870 };
 871
 872 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
 873
 874 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
 875 MODULE_AUTHOR("Dan Murphy <[email protected]");
 876 MODULE_LICENSE("GPL v2");