5 #include <linux/init.h>
6 #include <linux/kernel.h>
7 #include <linux/sched.h>
10 #include <asm/mipsregs.h>
11 #include <asm/bcache.h>
12 #include <asm/cacheops.h>
14 #include <asm/pgtable.h>
15 #include <asm/mmu_context.h>
16 #include <asm/r4kcache.h>
18 /* Secondary cache size in bytes, if present. */
19 static unsigned long scache_size;
22 #define SC_PAGE (128*SC_LINE)
24 static inline void blast_r5000_scache(void)
26 unsigned long start = INDEX_BASE;
27 unsigned long end = start + scache_size;
30 cache_op(R5K_Page_Invalidate_S, start);
35 static void r5k_dma_cache_inv_sc(unsigned long addr, unsigned long size)
39 /* Catch bad driver code */
42 if (size >= scache_size) {
47 /* On the R5000 secondary cache we cannot
48 * invalidate less than a page at a time.
49 * The secondary cache is physically indexed, write-through.
51 a = addr & ~(SC_PAGE - 1);
52 end = (addr + size - 1) & ~(SC_PAGE - 1);
54 cache_op(R5K_Page_Invalidate_S, a);
59 static void r5k_sc_enable(void)
63 local_irq_save(flags);
64 set_c0_config(R5K_CONF_SE);
66 local_irq_restore(flags);
69 static void r5k_sc_disable(void)
73 local_irq_save(flags);
75 clear_c0_config(R5K_CONF_SE);
76 local_irq_restore(flags);
79 static inline int __init r5k_sc_probe(void)
81 unsigned long config = read_c0_config();
86 scache_size = (512 * 1024) << ((config & R5K_CONF_SS) >> 20);
88 printk("R5000 SCACHE size %ldkB, linesize 32 bytes.\n",
94 static struct bcache_ops r5k_sc_ops = {
95 .bc_enable = r5k_sc_enable,
96 .bc_disable = r5k_sc_disable,
97 .bc_wback_inv = r5k_dma_cache_inv_sc,
98 .bc_inv = r5k_dma_cache_inv_sc
101 void r5k_sc_init(void)
103 if (r5k_sc_probe()) {