drivers/gpu/drm/omapdrm/dss/omapdss.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
   4  * Author: Tomi Valkeinen <[email protected]>
   5  */
   6
   7 #ifndef __OMAP_DRM_DSS_H
   8 #define __OMAP_DRM_DSS_H
   9
  10 #include <drm/drm_color_mgmt.h>
  11 #include <drm/drm_crtc.h>
  12 #include <drm/drm_mode.h>
  13 #include <linux/device.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/platform_data/omapdss.h>
  17 #include <video/videomode.h>
  18
  19 #define DISPC_IRQ_FRAMEDONE             (1 << 0)
  20 #define DISPC_IRQ_VSYNC                 (1 << 1)
  21 #define DISPC_IRQ_EVSYNC_EVEN           (1 << 2)
  22 #define DISPC_IRQ_EVSYNC_ODD            (1 << 3)
  23 #define DISPC_IRQ_ACBIAS_COUNT_STAT     (1 << 4)
  24 #define DISPC_IRQ_PROG_LINE_NUM         (1 << 5)
  25 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW    (1 << 6)
  26 #define DISPC_IRQ_GFX_END_WIN           (1 << 7)
  27 #define DISPC_IRQ_PAL_GAMMA_MASK        (1 << 8)
  28 #define DISPC_IRQ_OCP_ERR               (1 << 9)
  29 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW   (1 << 10)
  30 #define DISPC_IRQ_VID1_END_WIN          (1 << 11)
  31 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW   (1 << 12)
  32 #define DISPC_IRQ_VID2_END_WIN          (1 << 13)
  33 #define DISPC_IRQ_SYNC_LOST             (1 << 14)
  34 #define DISPC_IRQ_SYNC_LOST_DIGIT       (1 << 15)
  35 #define DISPC_IRQ_WAKEUP                (1 << 16)
  36 #define DISPC_IRQ_SYNC_LOST2            (1 << 17)
  37 #define DISPC_IRQ_VSYNC2                (1 << 18)
  38 #define DISPC_IRQ_VID3_END_WIN          (1 << 19)
  39 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW   (1 << 20)
  40 #define DISPC_IRQ_ACBIAS_COUNT_STAT2    (1 << 21)
  41 #define DISPC_IRQ_FRAMEDONE2            (1 << 22)
  42 #define DISPC_IRQ_FRAMEDONEWB           (1 << 23)
  43 #define DISPC_IRQ_FRAMEDONETV           (1 << 24)
  44 #define DISPC_IRQ_WBBUFFEROVERFLOW      (1 << 25)
  45 #define DISPC_IRQ_WBUNCOMPLETEERROR     (1 << 26)
  46 #define DISPC_IRQ_SYNC_LOST3            (1 << 27)
  47 #define DISPC_IRQ_VSYNC3                (1 << 28)
  48 #define DISPC_IRQ_ACBIAS_COUNT_STAT3    (1 << 29)
  49 #define DISPC_IRQ_FRAMEDONE3            (1 << 30)
  50
  51 struct dispc_device;
  52 struct drm_connector;
  53 struct dss_device;
  54 struct dss_lcd_mgr_config;
  55 struct hdmi_avi_infoframe;
  56 struct omap_drm_private;
  57 struct omap_dss_device;
  58 struct snd_aes_iec958;
  59 struct snd_cea_861_aud_if;
  60
  61 enum omap_display_type {
  62         OMAP_DISPLAY_TYPE_NONE          = 0,
  63         OMAP_DISPLAY_TYPE_DPI           = 1 << 0,
  64         OMAP_DISPLAY_TYPE_DBI           = 1 << 1,
  65         OMAP_DISPLAY_TYPE_SDI           = 1 << 2,
  66         OMAP_DISPLAY_TYPE_DSI           = 1 << 3,
  67         OMAP_DISPLAY_TYPE_VENC          = 1 << 4,
  68         OMAP_DISPLAY_TYPE_HDMI          = 1 << 5,
  69         OMAP_DISPLAY_TYPE_DVI           = 1 << 6,
  70 };
  71
  72 enum omap_plane_id {
  73         OMAP_DSS_GFX    = 0,
  74         OMAP_DSS_VIDEO1 = 1,
  75         OMAP_DSS_VIDEO2 = 2,
  76         OMAP_DSS_VIDEO3 = 3,
  77         OMAP_DSS_WB     = 4,
  78 };
  79
  80 enum omap_channel {
  81         OMAP_DSS_CHANNEL_LCD    = 0,
  82         OMAP_DSS_CHANNEL_DIGIT  = 1,
  83         OMAP_DSS_CHANNEL_LCD2   = 2,
  84         OMAP_DSS_CHANNEL_LCD3   = 3,
  85         OMAP_DSS_CHANNEL_WB     = 4,
  86 };
  87
  88 enum omap_color_mode {
  89         _UNUSED_,
  90 };
  91
  92 enum omap_dss_load_mode {
  93         OMAP_DSS_LOAD_CLUT_AND_FRAME    = 0,
  94         OMAP_DSS_LOAD_CLUT_ONLY         = 1,
  95         OMAP_DSS_LOAD_FRAME_ONLY        = 2,
  96         OMAP_DSS_LOAD_CLUT_ONCE_FRAME   = 3,
  97 };
  98
  99 enum omap_dss_trans_key_type {
 100         OMAP_DSS_COLOR_KEY_GFX_DST = 0,
 101         OMAP_DSS_COLOR_KEY_VID_SRC = 1,
 102 };
 103
 104 enum omap_dss_signal_level {
 105         OMAPDSS_SIG_ACTIVE_LOW,
 106         OMAPDSS_SIG_ACTIVE_HIGH,
 107 };
 108
 109 enum omap_dss_signal_edge {
 110         OMAPDSS_DRIVE_SIG_FALLING_EDGE,
 111         OMAPDSS_DRIVE_SIG_RISING_EDGE,
 112 };
 113
 114 enum omap_dss_venc_type {
 115         OMAP_DSS_VENC_TYPE_COMPOSITE,
 116         OMAP_DSS_VENC_TYPE_SVIDEO,
 117 };
 118
 119 enum omap_dss_rotation_type {
 120         OMAP_DSS_ROT_NONE       = 0,
 121         OMAP_DSS_ROT_TILER      = 1 << 0,
 122 };
 123
 124 enum omap_overlay_caps {
 125         OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
 126         OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
 127         OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
 128         OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
 129         OMAP_DSS_OVL_CAP_POS = 1 << 4,
 130         OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
 131 };
 132
 133 enum omap_dss_output_id {
 134         OMAP_DSS_OUTPUT_DPI     = 1 << 0,
 135         OMAP_DSS_OUTPUT_DBI     = 1 << 1,
 136         OMAP_DSS_OUTPUT_SDI     = 1 << 2,
 137         OMAP_DSS_OUTPUT_DSI1    = 1 << 3,
 138         OMAP_DSS_OUTPUT_DSI2    = 1 << 4,
 139         OMAP_DSS_OUTPUT_VENC    = 1 << 5,
 140         OMAP_DSS_OUTPUT_HDMI    = 1 << 6,
 141 };
 142
 143 struct omap_dss_cpr_coefs {
 144         s16 rr, rg, rb;
 145         s16 gr, gg, gb;
 146         s16 br, bg, bb;
 147 };
 148
 149 struct omap_overlay_info {
 150         dma_addr_t paddr;
 151         dma_addr_t p_uv_addr;  /* for NV12 format */
 152         u16 screen_width;
 153         u16 width;
 154         u16 height;
 155         u32 fourcc;
 156         u8 rotation;
 157         enum omap_dss_rotation_type rotation_type;
 158
 159         u16 pos_x;
 160         u16 pos_y;
 161         u16 out_width;  /* if 0, out_width == width */
 162         u16 out_height; /* if 0, out_height == height */
 163         u8 global_alpha;
 164         u8 pre_mult_alpha;
 165         u8 zorder;
 166
 167         enum drm_color_encoding color_encoding;
 168         enum drm_color_range color_range;
 169 };
 170
 171 struct omap_overlay_manager_info {
 172         u32 default_color;
 173
 174         enum omap_dss_trans_key_type trans_key_type;
 175         u32 trans_key;
 176         bool trans_enabled;
 177
 178         bool partial_alpha_enabled;
 179
 180         bool cpr_enable;
 181         struct omap_dss_cpr_coefs cpr_coefs;
 182 };
 183
 184 struct omap_dss_writeback_info {
 185         u32 paddr;
 186         u32 p_uv_addr;
 187         u16 buf_width;
 188         u16 width;
 189         u16 height;
 190         u32 fourcc;
 191         u8 rotation;
 192         enum omap_dss_rotation_type rotation_type;
 193         u8 pre_mult_alpha;
 194 };
 195
 196 struct omapdss_dsi_ops {
 197         int (*update)(struct omap_dss_device *dssdev);
 198         bool (*is_video_mode)(struct omap_dss_device *dssdev);
 199 };
 200
 201 struct omap_dss_device {
 202         struct device *dev;
 203
 204         struct dss_device *dss;
 205         struct drm_bridge *bridge;
 206         struct drm_bridge *next_bridge;
 207         struct drm_panel *panel;
 208
 209         struct list_head list;
 210
 211         /*
 212          * DSS type that this device generates (for DSS internal devices) or
 213          * requires (for external encoders, connectors and panels). Must be a
 214          * non-zero (different than OMAP_DISPLAY_TYPE_NONE) value.
 215          */
 216         enum omap_display_type type;
 217
 218         const char *name;
 219
 220         const struct omapdss_dsi_ops *dsi_ops;
 221         u32 bus_flags;
 222
 223         /* OMAP DSS output specific fields */
 224
 225         /* DISPC channel for this output */
 226         enum omap_channel dispc_channel;
 227
 228         /* output instance */
 229         enum omap_dss_output_id id;
 230
 231         /* port number in DT */
 232         unsigned int of_port;
 233 };
 234
 235 struct dss_pdata {
 236         struct dss_device *dss;
 237 };
 238
 239 void omapdss_device_register(struct omap_dss_device *dssdev);
 240 void omapdss_device_unregister(struct omap_dss_device *dssdev);
 241 struct omap_dss_device *omapdss_device_get(struct omap_dss_device *dssdev);
 242 void omapdss_device_put(struct omap_dss_device *dssdev);
 243 struct omap_dss_device *omapdss_find_device_by_node(struct device_node *node);
 244 int omapdss_device_connect(struct dss_device *dss,
 245                            struct omap_dss_device *dst);
 246 void omapdss_device_disconnect(struct dss_device *dss,
 247                                struct omap_dss_device *dst);
 248
 249 int omap_dss_get_num_overlay_managers(void);
 250
 251 int omap_dss_get_num_overlays(void);
 252
 253 #define for_each_dss_output(d) \
 254         while ((d = omapdss_device_next_output(d)) != NULL)
 255 struct omap_dss_device *omapdss_device_next_output(struct omap_dss_device *from);
 256 int omapdss_device_init_output(struct omap_dss_device *out,
 257                                struct drm_bridge *local_bridge);
 258 void omapdss_device_cleanup_output(struct omap_dss_device *out);
 259
 260 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
 261 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 262 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 263
 264 int omapdss_compat_init(void);
 265 void omapdss_compat_uninit(void);
 266
 267 enum dss_writeback_channel {
 268         DSS_WB_LCD1_MGR =       0,
 269         DSS_WB_LCD2_MGR =       1,
 270         DSS_WB_TV_MGR =         2,
 271         DSS_WB_OVL0 =           3,
 272         DSS_WB_OVL1 =           4,
 273         DSS_WB_OVL2 =           5,
 274         DSS_WB_OVL3 =           6,
 275         DSS_WB_LCD3_MGR =       7,
 276 };
 277
 278 void omap_crtc_dss_start_update(struct omap_drm_private *priv,
 279                                        enum omap_channel channel);
 280 void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable);
 281 int omap_crtc_dss_enable(struct omap_drm_private *priv, enum omap_channel channel);
 282 void omap_crtc_dss_disable(struct omap_drm_private *priv, enum omap_channel channel);
 283 void omap_crtc_dss_set_timings(struct omap_drm_private *priv,
 284                 enum omap_channel channel,
 285                 const struct videomode *vm);
 286 void omap_crtc_dss_set_lcd_config(struct omap_drm_private *priv,
 287                 enum omap_channel channel,
 288                 const struct dss_lcd_mgr_config *config);
 289 int omap_crtc_dss_register_framedone(
 290                 struct omap_drm_private *priv, enum omap_channel channel,
 291                 void (*handler)(void *), void *data);
 292 void omap_crtc_dss_unregister_framedone(
 293                 struct omap_drm_private *priv, enum omap_channel channel,
 294                 void (*handler)(void *), void *data);
 295
 296 void dss_mgr_set_timings(struct omap_dss_device *dssdev,
 297                 const struct videomode *vm);
 298 void dss_mgr_set_lcd_config(struct omap_dss_device *dssdev,
 299                 const struct dss_lcd_mgr_config *config);
 300 int dss_mgr_enable(struct omap_dss_device *dssdev);
 301 void dss_mgr_disable(struct omap_dss_device *dssdev);
 302 void dss_mgr_start_update(struct omap_dss_device *dssdev);
 303 int dss_mgr_register_framedone_handler(struct omap_dss_device *dssdev,
 304                 void (*handler)(void *), void *data);
 305 void dss_mgr_unregister_framedone_handler(struct omap_dss_device *dssdev,
 306                 void (*handler)(void *), void *data);
 307
 308 struct dispc_device *dispc_get_dispc(struct dss_device *dss);
 309
 310 bool omapdss_stack_is_ready(void);
 311 void omapdss_gather_components(struct device *dev);
 312
 313 int omap_dss_init(void);
 314 void omap_dss_exit(void);
 315
 316 #endif /* __OMAP_DRM_DSS_H */