drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/drm_cache.h>
  29 #include "amdgpu.h"
  30 #include "gmc_v6_0.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_gem.h"
  33
  34 #include "bif/bif_3_0_d.h"
  35 #include "bif/bif_3_0_sh_mask.h"
  36 #include "oss/oss_1_0_d.h"
  37 #include "oss/oss_1_0_sh_mask.h"
  38 #include "gmc/gmc_6_0_d.h"
  39 #include "gmc/gmc_6_0_sh_mask.h"
  40 #include "dce/dce_6_0_d.h"
  41 #include "dce/dce_6_0_sh_mask.h"
  42 #include "si_enums.h"
  43
  44 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev);
  45 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  46 static int gmc_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block);
  47
  48 MODULE_FIRMWARE("amdgpu/tahiti_mc.bin");
  49 MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin");
  50 MODULE_FIRMWARE("amdgpu/verde_mc.bin");
  51 MODULE_FIRMWARE("amdgpu/oland_mc.bin");
  52 MODULE_FIRMWARE("amdgpu/hainan_mc.bin");
  53 MODULE_FIRMWARE("amdgpu/si58_mc.bin");
  54
  55 #define MC_SEQ_MISC0__MT__MASK   0xf0000000
  56 #define MC_SEQ_MISC0__MT__GDDR1  0x10000000
  57 #define MC_SEQ_MISC0__MT__DDR2   0x20000000
  58 #define MC_SEQ_MISC0__MT__GDDR3  0x30000000
  59 #define MC_SEQ_MISC0__MT__GDDR4  0x40000000
  60 #define MC_SEQ_MISC0__MT__GDDR5  0x50000000
  61 #define MC_SEQ_MISC0__MT__HBM    0x60000000
  62 #define MC_SEQ_MISC0__MT__DDR3   0xB0000000
  63
  64 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)
  65 {
  66         u32 blackout;
  67         struct amdgpu_ip_block *ip_block;
  68
  69         ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC);
  70         if (!ip_block)
  71                 return;
  72
  73         gmc_v6_0_wait_for_idle(ip_block);
  74
  75         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  76         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  77                 /* Block CPU access */
  78                 WREG32(mmBIF_FB_EN, 0);
  79                 /* blackout the MC */
  80                 blackout = REG_SET_FIELD(blackout,
  81                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  82                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  83         }
  84         /* wait for the MC to settle */
  85         udelay(100);
  86
  87 }
  88
  89 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev)
  90 {
  91         u32 tmp;
  92
  93         /* unblackout the MC */
  94         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  95         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  96         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
  97         /* allow CPU access */
  98         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
  99         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 100         WREG32(mmBIF_FB_EN, tmp);
 101 }
 102
 103 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
 104 {
 105         const char *chip_name;
 106         int err;
 107
 108         DRM_DEBUG("\n");
 109
 110         switch (adev->asic_type) {
 111         case CHIP_TAHITI:
 112                 chip_name = "tahiti";
 113                 break;
 114         case CHIP_PITCAIRN:
 115                 chip_name = "pitcairn";
 116                 break;
 117         case CHIP_VERDE:
 118                 chip_name = "verde";
 119                 break;
 120         case CHIP_OLAND:
 121                 chip_name = "oland";
 122                 break;
 123         case CHIP_HAINAN:
 124                 chip_name = "hainan";
 125                 break;
 126         default:
 127                 BUG();
 128         }
 129
 130         /* this memory configuration requires special firmware */
 131         if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
 132                 chip_name = "si58";
 133
 134         err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED,
 135                                    "amdgpu/%s_mc.bin", chip_name);
 136         if (err) {
 137                 dev_err(adev->dev,
 138                        "si_mc: Failed to load firmware \"%s_mc.bin\"\n",
 139                        chip_name);
 140                 amdgpu_ucode_release(&adev->gmc.fw);
 141         }
 142         return err;
 143 }
 144
 145 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
 146 {
 147         const __le32 *new_fw_data = NULL;
 148         u32 running;
 149         const __le32 *new_io_mc_regs = NULL;
 150         int i, regs_size, ucode_size;
 151         const struct mc_firmware_header_v1_0 *hdr;
 152
 153         if (!adev->gmc.fw)
 154                 return -EINVAL;
 155
 156         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 157
 158         amdgpu_ucode_print_mc_hdr(&hdr->header);
 159
 160         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 161         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 162         new_io_mc_regs = (const __le32 *)
 163                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 164         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 165         new_fw_data = (const __le32 *)
 166                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 167
 168         running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
 169
 170         if (running == 0) {
 171
 172                 /* reset the engine and set to writable */
 173                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 174                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 175
 176                 /* load mc io regs */
 177                 for (i = 0; i < regs_size; i++) {
 178                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
 179                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
 180                 }
 181                 /* load the MC ucode */
 182                 for (i = 0; i < ucode_size; i++)
 183                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
 184
 185                 /* put the engine back into the active state */
 186                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 187                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 188                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 189
 190                 /* wait for training to complete */
 191                 for (i = 0; i < adev->usec_timeout; i++) {
 192                         if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
 193                                 break;
 194                         udelay(1);
 195                 }
 196                 for (i = 0; i < adev->usec_timeout; i++) {
 197                         if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
 198                                 break;
 199                         udelay(1);
 200                 }
 201
 202         }
 203
 204         return 0;
 205 }
 206
 207 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
 208                                        struct amdgpu_gmc *mc)
 209 {
 210         u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 211
 212         base <<= 24;
 213
 214         amdgpu_gmc_set_agp_default(adev, mc);
 215         amdgpu_gmc_vram_location(adev, mc, base);
 216         amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT);
 217 }
 218
 219 static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
 220 {
 221         int i, j;
 222         struct amdgpu_ip_block *ip_block;
 223
 224
 225         /* Initialize HDP */
 226         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 227                 WREG32((0xb05 + j), 0x00000000);
 228                 WREG32((0xb06 + j), 0x00000000);
 229                 WREG32((0xb07 + j), 0x00000000);
 230                 WREG32((0xb08 + j), 0x00000000);
 231                 WREG32((0xb09 + j), 0x00000000);
 232         }
 233         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 234
 235         ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC);
 236         if (!ip_block)
 237                 return;
 238
 239         if (gmc_v6_0_wait_for_idle(ip_block))
 240                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 241
 242         if (adev->mode_info.num_crtc) {
 243                 u32 tmp;
 244
 245                 /* Lockout access through VGA aperture*/
 246                 tmp = RREG32(mmVGA_HDP_CONTROL);
 247                 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
 248                 WREG32(mmVGA_HDP_CONTROL, tmp);
 249
 250                 /* disable VGA render */
 251                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 252                 tmp &= ~VGA_VSTATUS_CNTL;
 253                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 254         }
 255         /* Update configuration */
 256         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 257                adev->gmc.vram_start >> 12);
 258         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 259                adev->gmc.vram_end >> 12);
 260         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 261                adev->mem_scratch.gpu_addr >> 12);
 262         WREG32(mmMC_VM_AGP_BASE, 0);
 263         WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22);
 264         WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22);
 265
 266         if (gmc_v6_0_wait_for_idle(ip_block))
 267                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 268 }
 269
 270 static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
 271 {
 272
 273         u32 tmp;
 274         int chansize, numchan;
 275         int r;
 276
 277         tmp = RREG32(mmMC_ARB_RAMCFG);
 278         if (tmp & (1 << 11))
 279                 chansize = 16;
 280         else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK)
 281                 chansize = 64;
 282         else
 283                 chansize = 32;
 284
 285         tmp = RREG32(mmMC_SHARED_CHMAP);
 286         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 287         case 0:
 288         default:
 289                 numchan = 1;
 290                 break;
 291         case 1:
 292                 numchan = 2;
 293                 break;
 294         case 2:
 295                 numchan = 4;
 296                 break;
 297         case 3:
 298                 numchan = 8;
 299                 break;
 300         case 4:
 301                 numchan = 3;
 302                 break;
 303         case 5:
 304                 numchan = 6;
 305                 break;
 306         case 6:
 307                 numchan = 10;
 308                 break;
 309         case 7:
 310                 numchan = 12;
 311                 break;
 312         case 8:
 313                 numchan = 16;
 314                 break;
 315         }
 316         adev->gmc.vram_width = numchan * chansize;
 317         /* size in MB on si */
 318         adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 319         adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 320
 321         if (!(adev->flags & AMD_IS_APU)) {
 322                 r = amdgpu_device_resize_fb_bar(adev);
 323                 if (r)
 324                         return r;
 325         }
 326         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 327         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 328         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 329
 330         /* set the gart size */
 331         if (amdgpu_gart_size == -1) {
 332                 switch (adev->asic_type) {
 333                 case CHIP_HAINAN:    /* no MM engines */
 334                 default:
 335                         adev->gmc.gart_size = 256ULL << 20;
 336                         break;
 337                 case CHIP_VERDE:    /* UVD, VCE do not support GPUVM */
 338                 case CHIP_TAHITI:   /* UVD, VCE do not support GPUVM */
 339                 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
 340                 case CHIP_OLAND:    /* UVD, VCE do not support GPUVM */
 341                         adev->gmc.gart_size = 1024ULL << 20;
 342                         break;
 343                 }
 344         } else {
 345                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 346         }
 347
 348         adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
 349         gmc_v6_0_vram_gtt_location(adev, &adev->gmc);
 350
 351         return 0;
 352 }
 353
 354 static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 355                                         uint32_t vmhub, uint32_t flush_type)
 356 {
 357         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 358 }
 359
 360 static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 361                                             unsigned int vmid, uint64_t pd_addr)
 362 {
 363         uint32_t reg;
 364
 365         /* write new base address */
 366         if (vmid < 8)
 367                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
 368         else
 369                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8);
 370         amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
 371
 372         /* bits 0-15 are the VM contexts0-15 */
 373         amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
 374
 375         return pd_addr;
 376 }
 377
 378 static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level,
 379                                 uint64_t *addr, uint64_t *flags)
 380 {
 381         BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
 382 }
 383
 384 static void gmc_v6_0_get_vm_pte(struct amdgpu_device *adev,
 385                                 struct amdgpu_bo_va_mapping *mapping,
 386                                 uint64_t *flags)
 387 {
 388         *flags &= ~AMDGPU_PTE_EXECUTABLE;
 389         *flags &= ~AMDGPU_PTE_PRT;
 390 }
 391
 392 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
 393                                               bool value)
 394 {
 395         u32 tmp;
 396
 397         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 398         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 399                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 400         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 401                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 402         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 403                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 404         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 405                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 406         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 407                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 408         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 409                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 410         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 411 }
 412
 413  /**
 414   * gmc_v8_0_set_prt() - set PRT VM fault
 415   *
 416   * @adev: amdgpu_device pointer
 417   * @enable: enable/disable VM fault handling for PRT
 418   */
 419 static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
 420 {
 421         u32 tmp;
 422
 423         if (enable && !adev->gmc.prt_warning) {
 424                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 425                 adev->gmc.prt_warning = true;
 426         }
 427
 428         tmp = RREG32(mmVM_PRT_CNTL);
 429         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 430                             CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
 431                             enable);
 432         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 433                             TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
 434                             enable);
 435         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 436                             L2_CACHE_STORE_INVALID_ENTRIES,
 437                             enable);
 438         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 439                             L1_TLB_STORE_INVALID_ENTRIES,
 440                             enable);
 441         WREG32(mmVM_PRT_CNTL, tmp);
 442
 443         if (enable) {
 444                 uint32_t low = AMDGPU_VA_RESERVED_BOTTOM >>
 445                         AMDGPU_GPU_PAGE_SHIFT;
 446                 uint32_t high = adev->vm_manager.max_pfn -
 447                         (AMDGPU_VA_RESERVED_TOP >> AMDGPU_GPU_PAGE_SHIFT);
 448
 449                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 450                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 451                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 452                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 453                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 454                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 455                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 456                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 457         } else {
 458                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 459                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 460                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 461                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 462                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 463                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 464                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 465                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 466         }
 467 }
 468
 469 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 470 {
 471         uint64_t table_addr;
 472         u32 field;
 473         int i;
 474
 475         if (adev->gart.bo == NULL) {
 476                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 477                 return -EINVAL;
 478         }
 479         amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
 480
 481         table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 482
 483         /* Setup TLB control */
 484         WREG32(mmMC_VM_MX_L1_TLB_CNTL,
 485                (0xA << 7) |
 486                MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
 487                MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
 488                MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
 489                MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
 490                (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
 491         /* Setup L2 cache */
 492         WREG32(mmVM_L2_CNTL,
 493                VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
 494                VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
 495                VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 496                VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 497                (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
 498                (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
 499         WREG32(mmVM_L2_CNTL2,
 500                VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
 501                VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
 502
 503         field = adev->vm_manager.fragment_size;
 504         WREG32(mmVM_L2_CNTL3,
 505                VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
 506                (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
 507                (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
 508         /* setup context0 */
 509         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
 510         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
 511         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
 512         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 513                         (u32)(adev->dummy_page_addr >> 12));
 514         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 515         WREG32(mmVM_CONTEXT0_CNTL,
 516                VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
 517                (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
 518                VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
 519
 520         WREG32(0x575, 0);
 521         WREG32(0x576, 0);
 522         WREG32(0x577, 0);
 523
 524         /* empty context1-15 */
 525         /* set vm size, must be a multiple of 4 */
 526         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 527         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 528         /* Assign the pt base to something valid for now; the pts used for
 529          * the VMs are determined by the application and setup and assigned
 530          * on the fly in the vm part of radeon_gart.c
 531          */
 532         for (i = 1; i < AMDGPU_NUM_VMID; i++) {
 533                 if (i < 8)
 534                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 535                                table_addr >> 12);
 536                 else
 537                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 538                                table_addr >> 12);
 539         }
 540
 541         /* enable context1-15 */
 542         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 543                (u32)(adev->dummy_page_addr >> 12));
 544         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 545         WREG32(mmVM_CONTEXT1_CNTL,
 546                VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
 547                (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
 548                ((adev->vm_manager.block_size - 9)
 549                << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
 550         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 551                 gmc_v6_0_set_fault_enable_default(adev, false);
 552         else
 553                 gmc_v6_0_set_fault_enable_default(adev, true);
 554
 555         gmc_v6_0_flush_gpu_tlb(adev, 0, 0, 0);
 556         dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
 557                  (unsigned int)(adev->gmc.gart_size >> 20),
 558                  (unsigned long long)table_addr);
 559         return 0;
 560 }
 561
 562 static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
 563 {
 564         int r;
 565
 566         if (adev->gart.bo) {
 567                 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
 568                 return 0;
 569         }
 570         r = amdgpu_gart_init(adev);
 571         if (r)
 572                 return r;
 573         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 574         adev->gart.gart_pte_flags = 0;
 575         return amdgpu_gart_table_vram_alloc(adev);
 576 }
 577
 578 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
 579 {
 580         /*unsigned i;
 581
 582         for (i = 1; i < 16; ++i) {
 583                 uint32_t reg;
 584                 if (i < 8)
 585                         reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
 586                 else
 587                         reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
 588                 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
 589         }*/
 590
 591         /* Disable all tables */
 592         WREG32(mmVM_CONTEXT0_CNTL, 0);
 593         WREG32(mmVM_CONTEXT1_CNTL, 0);
 594         /* Setup TLB control */
 595         WREG32(mmMC_VM_MX_L1_TLB_CNTL,
 596                MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
 597                (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
 598         /* Setup L2 cache */
 599         WREG32(mmVM_L2_CNTL,
 600                VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 601                VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 602                (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
 603                (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
 604         WREG32(mmVM_L2_CNTL2, 0);
 605         WREG32(mmVM_L2_CNTL3,
 606                VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
 607                (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
 608 }
 609
 610 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
 611                                      u32 status, u32 addr, u32 mc_client)
 612 {
 613         u32 mc_id;
 614         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 615         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 616                                         PROTECTIONS);
 617         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 618                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 619
 620         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 621                               MEMORY_CLIENT_ID);
 622
 623         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 624                protections, vmid, addr,
 625                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 626                              MEMORY_CLIENT_RW) ?
 627                "write" : "read", block, mc_client, mc_id);
 628 }
 629
 630 /*
 631 static const u32 mc_cg_registers[] = {
 632         MC_HUB_MISC_HUB_CG,
 633         MC_HUB_MISC_SIP_CG,
 634         MC_HUB_MISC_VM_CG,
 635         MC_XPB_CLK_GAT,
 636         ATC_MISC_CG,
 637         MC_CITF_MISC_WR_CG,
 638         MC_CITF_MISC_RD_CG,
 639         MC_CITF_MISC_VM_CG,
 640         VM_L2_CG,
 641 };
 642
 643 static const u32 mc_cg_ls_en[] = {
 644         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 645         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 646         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 647         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 648         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 649         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 650         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 651         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 652         VM_L2_CG__MEM_LS_ENABLE_MASK,
 653 };
 654
 655 static const u32 mc_cg_en[] = {
 656         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 657         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 658         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 659         MC_XPB_CLK_GAT__ENABLE_MASK,
 660         ATC_MISC_CG__ENABLE_MASK,
 661         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 662         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 663         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 664         VM_L2_CG__ENABLE_MASK,
 665 };
 666
 667 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
 668                                   bool enable)
 669 {
 670         int i;
 671         u32 orig, data;
 672
 673         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 674                 orig = data = RREG32(mc_cg_registers[i]);
 675                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
 676                         data |= mc_cg_ls_en[i];
 677                 else
 678                         data &= ~mc_cg_ls_en[i];
 679                 if (data != orig)
 680                         WREG32(mc_cg_registers[i], data);
 681         }
 682 }
 683
 684 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
 685                                     bool enable)
 686 {
 687         int i;
 688         u32 orig, data;
 689
 690         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 691                 orig = data = RREG32(mc_cg_registers[i]);
 692                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
 693                         data |= mc_cg_en[i];
 694                 else
 695                         data &= ~mc_cg_en[i];
 696                 if (data != orig)
 697                         WREG32(mc_cg_registers[i], data);
 698         }
 699 }
 700
 701 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
 702                                      bool enable)
 703 {
 704         u32 orig, data;
 705
 706         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 707
 708         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
 709                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 710                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 711                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 712                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 713         } else {
 714                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 715                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 716                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 717                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 718         }
 719
 720         if (orig != data)
 721                 WREG32_PCIE(ixPCIE_CNTL2, data);
 722 }
 723
 724 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 725                                      bool enable)
 726 {
 727         u32 orig, data;
 728
 729         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 730
 731         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
 732                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 733         else
 734                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 735
 736         if (orig != data)
 737                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 738 }
 739
 740 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
 741                                    bool enable)
 742 {
 743         u32 orig, data;
 744
 745         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 746
 747         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
 748                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 749         else
 750                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 751
 752         if (orig != data)
 753                 WREG32(mmHDP_MEM_POWER_LS, data);
 754 }
 755 */
 756
 757 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
 758 {
 759         switch (mc_seq_vram_type) {
 760         case MC_SEQ_MISC0__MT__GDDR1:
 761                 return AMDGPU_VRAM_TYPE_GDDR1;
 762         case MC_SEQ_MISC0__MT__DDR2:
 763                 return AMDGPU_VRAM_TYPE_DDR2;
 764         case MC_SEQ_MISC0__MT__GDDR3:
 765                 return AMDGPU_VRAM_TYPE_GDDR3;
 766         case MC_SEQ_MISC0__MT__GDDR4:
 767                 return AMDGPU_VRAM_TYPE_GDDR4;
 768         case MC_SEQ_MISC0__MT__GDDR5:
 769                 return AMDGPU_VRAM_TYPE_GDDR5;
 770         case MC_SEQ_MISC0__MT__DDR3:
 771                 return AMDGPU_VRAM_TYPE_DDR3;
 772         default:
 773                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 774         }
 775 }
 776
 777 static int gmc_v6_0_early_init(struct amdgpu_ip_block *ip_block)
 778 {
 779         struct amdgpu_device *adev = ip_block->adev;
 780
 781         gmc_v6_0_set_gmc_funcs(adev);
 782         gmc_v6_0_set_irq_funcs(adev);
 783
 784         return 0;
 785 }
 786
 787 static int gmc_v6_0_late_init(struct amdgpu_ip_block *ip_block)
 788 {
 789         struct amdgpu_device *adev = ip_block->adev;
 790
 791         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 792                 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 793         else
 794                 return 0;
 795 }
 796
 797 static unsigned int gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev)
 798 {
 799         u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
 800         unsigned int size;
 801
 802         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 803                 size = AMDGPU_VBIOS_VGA_ALLOCATION;
 804         } else {
 805                 u32 viewport = RREG32(mmVIEWPORT_SIZE);
 806
 807                 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
 808                         REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
 809                         4);
 810         }
 811         return size;
 812 }
 813
 814 static int gmc_v6_0_sw_init(struct amdgpu_ip_block *ip_block)
 815 {
 816         int r;
 817         struct amdgpu_device *adev = ip_block->adev;
 818
 819         set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
 820
 821         if (adev->flags & AMD_IS_APU) {
 822                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 823         } else {
 824                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 825
 826                 tmp &= MC_SEQ_MISC0__MT__MASK;
 827                 adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp);
 828         }
 829
 830         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
 831         if (r)
 832                 return r;
 833
 834         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
 835         if (r)
 836                 return r;
 837
 838         amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
 839
 840         adev->gmc.mc_mask = 0xffffffffffULL;
 841
 842         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
 843         if (r) {
 844                 dev_warn(adev->dev, "No suitable DMA available.\n");
 845                 return r;
 846         }
 847         adev->need_swiotlb = drm_need_swiotlb(40);
 848
 849         r = gmc_v6_0_init_microcode(adev);
 850         if (r) {
 851                 dev_err(adev->dev, "Failed to load mc firmware!\n");
 852                 return r;
 853         }
 854
 855         r = gmc_v6_0_mc_init(adev);
 856         if (r)
 857                 return r;
 858
 859         amdgpu_gmc_get_vbios_allocations(adev);
 860
 861         r = amdgpu_bo_init(adev);
 862         if (r)
 863                 return r;
 864
 865         r = gmc_v6_0_gart_init(adev);
 866         if (r)
 867                 return r;
 868
 869         /*
 870          * number of VMs
 871          * VMID 0 is reserved for System
 872          * amdgpu graphics/compute will use VMIDs 1-7
 873          * amdkfd will use VMIDs 8-15
 874          */
 875         adev->vm_manager.first_kfd_vmid = 8;
 876         amdgpu_vm_manager_init(adev);
 877
 878         /* base offset of vram pages */
 879         if (adev->flags & AMD_IS_APU) {
 880                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 881
 882                 tmp <<= 22;
 883                 adev->vm_manager.vram_base_offset = tmp;
 884         } else {
 885                 adev->vm_manager.vram_base_offset = 0;
 886         }
 887
 888         return 0;
 889 }
 890
 891 static int gmc_v6_0_sw_fini(struct amdgpu_ip_block *ip_block)
 892 {
 893         struct amdgpu_device *adev = ip_block->adev;
 894
 895         amdgpu_gem_force_release(adev);
 896         amdgpu_vm_manager_fini(adev);
 897         amdgpu_gart_table_vram_free(adev);
 898         amdgpu_bo_fini(adev);
 899         amdgpu_ucode_release(&adev->gmc.fw);
 900
 901         return 0;
 902 }
 903
 904 static int gmc_v6_0_hw_init(struct amdgpu_ip_block *ip_block)
 905 {
 906         int r;
 907         struct amdgpu_device *adev = ip_block->adev;
 908
 909         gmc_v6_0_mc_program(adev);
 910
 911         if (!(adev->flags & AMD_IS_APU)) {
 912                 r = gmc_v6_0_mc_load_microcode(adev);
 913                 if (r) {
 914                         dev_err(adev->dev, "Failed to load MC firmware!\n");
 915                         return r;
 916                 }
 917         }
 918
 919         r = gmc_v6_0_gart_enable(adev);
 920         if (r)
 921                 return r;
 922
 923         if (amdgpu_emu_mode == 1)
 924                 return amdgpu_gmc_vram_checking(adev);
 925
 926         return 0;
 927 }
 928
 929 static int gmc_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)
 930 {
 931         struct amdgpu_device *adev = ip_block->adev;
 932
 933         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
 934         gmc_v6_0_gart_disable(adev);
 935
 936         return 0;
 937 }
 938
 939 static int gmc_v6_0_suspend(struct amdgpu_ip_block *ip_block)
 940 {
 941         gmc_v6_0_hw_fini(ip_block);
 942
 943         return 0;
 944 }
 945
 946 static int gmc_v6_0_resume(struct amdgpu_ip_block *ip_block)
 947 {
 948         int r;
 949         struct amdgpu_device *adev = ip_block->adev;
 950
 951         r = gmc_v6_0_hw_init(ip_block);
 952         if (r)
 953                 return r;
 954
 955         amdgpu_vmid_reset_all(adev);
 956
 957         return 0;
 958 }
 959
 960 static bool gmc_v6_0_is_idle(void *handle)
 961 {
 962         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 963
 964         u32 tmp = RREG32(mmSRBM_STATUS);
 965
 966         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 967                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
 968                 return false;
 969
 970         return true;
 971 }
 972
 973 static int gmc_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
 974 {
 975         unsigned int i;
 976         struct amdgpu_device *adev = ip_block->adev;
 977
 978         for (i = 0; i < adev->usec_timeout; i++) {
 979                 if (gmc_v6_0_is_idle(adev))
 980                         return 0;
 981                 udelay(1);
 982         }
 983         return -ETIMEDOUT;
 984
 985 }
 986
 987 static int gmc_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)
 988 {
 989         struct amdgpu_device *adev = ip_block->adev;
 990
 991         u32 srbm_soft_reset = 0;
 992         u32 tmp = RREG32(mmSRBM_STATUS);
 993
 994         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
 995                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
 996                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
 997
 998         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 999                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1000                 if (!(adev->flags & AMD_IS_APU))
1001                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1002                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1003         }
1004
1005         if (srbm_soft_reset) {
1006                 gmc_v6_0_mc_stop(adev);
1007
1008                 if (gmc_v6_0_wait_for_idle(ip_block))
1009                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1010
1011                 tmp = RREG32(mmSRBM_SOFT_RESET);
1012                 tmp |= srbm_soft_reset;
1013                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1014                 WREG32(mmSRBM_SOFT_RESET, tmp);
1015                 tmp = RREG32(mmSRBM_SOFT_RESET);
1016
1017                 udelay(50);
1018
1019                 tmp &= ~srbm_soft_reset;
1020                 WREG32(mmSRBM_SOFT_RESET, tmp);
1021                 tmp = RREG32(mmSRBM_SOFT_RESET);
1022
1023                 udelay(50);
1024
1025                 gmc_v6_0_mc_resume(adev);
1026                 udelay(50);
1027         }
1028
1029         return 0;
1030 }
1031
1032 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1033                                              struct amdgpu_irq_src *src,
1034                                              unsigned int type,
1035                                              enum amdgpu_interrupt_state state)
1036 {
1037         u32 tmp;
1038         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1039                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1040                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1041                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1042                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1043                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1044
1045         switch (state) {
1046         case AMDGPU_IRQ_STATE_DISABLE:
1047                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1048                 tmp &= ~bits;
1049                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1050                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1051                 tmp &= ~bits;
1052                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1053                 break;
1054         case AMDGPU_IRQ_STATE_ENABLE:
1055                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1056                 tmp |= bits;
1057                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1058                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1059                 tmp |= bits;
1060                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1061                 break;
1062         default:
1063                 break;
1064         }
1065
1066         return 0;
1067 }
1068
1069 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1070                                       struct amdgpu_irq_src *source,
1071                                       struct amdgpu_iv_entry *entry)
1072 {
1073         u32 addr, status;
1074
1075         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1076         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1077         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1078
1079         if (!addr && !status)
1080                 return 0;
1081
1082         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1083                 gmc_v6_0_set_fault_enable_default(adev, false);
1084
1085         if (printk_ratelimit()) {
1086                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1087                         entry->src_id, entry->src_data[0]);
1088                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1089                         addr);
1090                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1091                         status);
1092                 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1093         }
1094
1095         return 0;
1096 }
1097
1098 static int gmc_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1099                                           enum amd_clockgating_state state)
1100 {
1101         return 0;
1102 }
1103
1104 static int gmc_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
1105                                           enum amd_powergating_state state)
1106 {
1107         return 0;
1108 }
1109
1110 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1111         .name = "gmc_v6_0",
1112         .early_init = gmc_v6_0_early_init,
1113         .late_init = gmc_v6_0_late_init,
1114         .sw_init = gmc_v6_0_sw_init,
1115         .sw_fini = gmc_v6_0_sw_fini,
1116         .hw_init = gmc_v6_0_hw_init,
1117         .hw_fini = gmc_v6_0_hw_fini,
1118         .suspend = gmc_v6_0_suspend,
1119         .resume = gmc_v6_0_resume,
1120         .is_idle = gmc_v6_0_is_idle,
1121         .wait_for_idle = gmc_v6_0_wait_for_idle,
1122         .soft_reset = gmc_v6_0_soft_reset,
1123         .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1124         .set_powergating_state = gmc_v6_0_set_powergating_state,
1125 };
1126
1127 static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
1128         .flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb,
1129         .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb,
1130         .set_prt = gmc_v6_0_set_prt,
1131         .get_vm_pde = gmc_v6_0_get_vm_pde,
1132         .get_vm_pte = gmc_v6_0_get_vm_pte,
1133         .get_vbios_fb_size = gmc_v6_0_get_vbios_fb_size,
1134 };
1135
1136 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1137         .set = gmc_v6_0_vm_fault_interrupt_state,
1138         .process = gmc_v6_0_process_interrupt,
1139 };
1140
1141 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev)
1142 {
1143         adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;
1144 }
1145
1146 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1147 {
1148         adev->gmc.vm_fault.num_types = 1;
1149         adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1150 }
1151
1152 const struct amdgpu_ip_block_version gmc_v6_0_ip_block = {
1153         .type = AMD_IP_BLOCK_TYPE_GMC,
1154         .major = 6,
1155         .minor = 0,
1156         .rev = 0,
1157         .funcs = &gmc_v6_0_ip_funcs,
1158 };