drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/string_helpers.h>
  27 #include <linux/uaccess.h>
  28
  29 #include "dc.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_dm.h"
  32 #include "amdgpu_dm_debugfs.h"
  33 #include "dm_helpers.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "resource.h"
  36 #include "dsc.h"
  37 #include "dc_link_dp.h"
  38 #include "link_hwss.h"
  39 #include "dc/dc_dmub_srv.h"
  40
  41 struct dmub_debugfs_trace_header {
  42         uint32_t entry_count;
  43         uint32_t reserved[3];
  44 };
  45
  46 struct dmub_debugfs_trace_entry {
  47         uint32_t trace_code;
  48         uint32_t tick_count;
  49         uint32_t param0;
  50         uint32_t param1;
  51 };
  52
  53 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
  54  *
  55  * Function takes in attributes passed to debugfs write entry
  56  * and writes into param array.
  57  * The user passes max_param_num to identify maximum number of
  58  * parameters that could be parsed.
  59  *
  60  */
  61 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,
  62                                           long *param, const char __user *buf,
  63                                           int max_param_num,
  64                                           uint8_t *param_nums)
  65 {
  66         char *wr_buf_ptr = NULL;
  67         uint32_t wr_buf_count = 0;
  68         int r;
  69         char *sub_str = NULL;
  70         const char delimiter[3] = {' ', '\n', '\0'};
  71         uint8_t param_index = 0;
  72
  73         *param_nums = 0;
  74
  75         wr_buf_ptr = wr_buf;
  76
  77         /* r is bytes not be copied */
  78         if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) {
  79                 DRM_DEBUG_DRIVER("user data could not be read successfully\n");
  80                 return -EFAULT;
  81         }
  82
  83         /* check number of parameters. isspace could not differ space and \n */
  84         while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
  85                 /* skip space*/
  86                 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
  87                         wr_buf_ptr++;
  88                         wr_buf_count++;
  89                         }
  90
  91                 if (wr_buf_count == wr_buf_size)
  92                         break;
  93
  94                 /* skip non-space*/
  95                 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
  96                         wr_buf_ptr++;
  97                         wr_buf_count++;
  98                 }
  99
 100                 (*param_nums)++;
 101
 102                 if (wr_buf_count == wr_buf_size)
 103                         break;
 104         }
 105
 106         if (*param_nums > max_param_num)
 107                 *param_nums = max_param_num;
 108
 109         wr_buf_ptr = wr_buf; /* reset buf pointer */
 110         wr_buf_count = 0; /* number of char already checked */
 111
 112         while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
 113                 wr_buf_ptr++;
 114                 wr_buf_count++;
 115         }
 116
 117         while (param_index < *param_nums) {
 118                 /* after strsep, wr_buf_ptr will be moved to after space */
 119                 sub_str = strsep(&wr_buf_ptr, delimiter);
 120
 121                 r = kstrtol(sub_str, 16, &(param[param_index]));
 122
 123                 if (r)
 124                         DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
 125
 126                 param_index++;
 127         }
 128
 129         return 0;
 130 }
 131
 132 /* function description
 133  * get/ set DP configuration: lane_count, link_rate, spread_spectrum
 134  *
 135  * valid lane count value: 1, 2, 4
 136  * valid link rate value:
 137  * 06h = 1.62Gbps per lane
 138  * 0Ah = 2.7Gbps per lane
 139  * 0Ch = 3.24Gbps per lane
 140  * 14h = 5.4Gbps per lane
 141  * 1Eh = 8.1Gbps per lane
 142  *
 143  * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
 144  *
 145  * --- to get dp configuration
 146  *
 147  * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 148  *
 149  * It will list current, verified, reported, preferred dp configuration.
 150  * current -- for current video mode
 151  * verified --- maximum configuration which pass link training
 152  * reported --- DP rx report caps (DPCD register offset 0, 1 2)
 153  * preferred --- user force settings
 154  *
 155  * --- set (or force) dp configuration
 156  *
 157  * echo <lane_count>  <link_rate> > link_settings
 158  *
 159  * for example, to force to  2 lane, 2.7GHz,
 160  * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings
 161  *
 162  * spread_spectrum could not be changed dynamically.
 163  *
 164  * in case invalid lane count, link rate are force, no hw programming will be
 165  * done. please check link settings after force operation to see if HW get
 166  * programming.
 167  *
 168  * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 169  *
 170  * check current and preferred settings.
 171  *
 172  */
 173 static ssize_t dp_link_settings_read(struct file *f, char __user *buf,
 174                                  size_t size, loff_t *pos)
 175 {
 176         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 177         struct dc_link *link = connector->dc_link;
 178         char *rd_buf = NULL;
 179         char *rd_buf_ptr = NULL;
 180         const uint32_t rd_buf_size = 100;
 181         uint32_t result = 0;
 182         uint8_t str_len = 0;
 183         int r;
 184
 185         if (*pos & 3 || size & 3)
 186                 return -EINVAL;
 187
 188         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 189         if (!rd_buf)
 190                 return 0;
 191
 192         rd_buf_ptr = rd_buf;
 193
 194         str_len = strlen("Current:  %d  0x%x  %d  ");
 195         snprintf(rd_buf_ptr, str_len, "Current:  %d  0x%x  %d  ",
 196                         link->cur_link_settings.lane_count,
 197                         link->cur_link_settings.link_rate,
 198                         link->cur_link_settings.link_spread);
 199         rd_buf_ptr += str_len;
 200
 201         str_len = strlen("Verified:  %d  0x%x  %d  ");
 202         snprintf(rd_buf_ptr, str_len, "Verified:  %d  0x%x  %d  ",
 203                         link->verified_link_cap.lane_count,
 204                         link->verified_link_cap.link_rate,
 205                         link->verified_link_cap.link_spread);
 206         rd_buf_ptr += str_len;
 207
 208         str_len = strlen("Reported:  %d  0x%x  %d  ");
 209         snprintf(rd_buf_ptr, str_len, "Reported:  %d  0x%x  %d  ",
 210                         link->reported_link_cap.lane_count,
 211                         link->reported_link_cap.link_rate,
 212                         link->reported_link_cap.link_spread);
 213         rd_buf_ptr += str_len;
 214
 215         str_len = strlen("Preferred:  %d  0x%x  %d  ");
 216         snprintf(rd_buf_ptr, str_len, "Preferred:  %d  0x%x  %d\n",
 217                         link->preferred_link_setting.lane_count,
 218                         link->preferred_link_setting.link_rate,
 219                         link->preferred_link_setting.link_spread);
 220
 221         while (size) {
 222                 if (*pos >= rd_buf_size)
 223                         break;
 224
 225                 r = put_user(*(rd_buf + result), buf);
 226                 if (r) {
 227                         kfree(rd_buf);
 228                         return r; /* r = -EFAULT */
 229                 }
 230
 231                 buf += 1;
 232                 size -= 1;
 233                 *pos += 1;
 234                 result += 1;
 235         }
 236
 237         kfree(rd_buf);
 238         return result;
 239 }
 240
 241 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
 242                                  size_t size, loff_t *pos)
 243 {
 244         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 245         struct dc_link *link = connector->dc_link;
 246         struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
 247         struct dc *dc = (struct dc *)link->dc;
 248         struct dc_link_settings prefer_link_settings;
 249         char *wr_buf = NULL;
 250         const uint32_t wr_buf_size = 40;
 251         /* 0: lane_count; 1: link_rate */
 252         int max_param_num = 2;
 253         uint8_t param_nums = 0;
 254         long param[2];
 255         bool valid_input = true;
 256
 257         if (size == 0)
 258                 return -EINVAL;
 259
 260         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 261         if (!wr_buf)
 262                 return -ENOSPC;
 263
 264         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 265                                            (long *)param, buf,
 266                                            max_param_num,
 267                                            &param_nums)) {
 268                 kfree(wr_buf);
 269                 return -EINVAL;
 270         }
 271
 272         if (param_nums <= 0) {
 273                 kfree(wr_buf);
 274                 DRM_DEBUG_DRIVER("user data not be read\n");
 275                 return -EINVAL;
 276         }
 277
 278         switch (param[0]) {
 279         case LANE_COUNT_ONE:
 280         case LANE_COUNT_TWO:
 281         case LANE_COUNT_FOUR:
 282                 break;
 283         default:
 284                 valid_input = false;
 285                 break;
 286         }
 287
 288         switch (param[1]) {
 289         case LINK_RATE_LOW:
 290         case LINK_RATE_HIGH:
 291         case LINK_RATE_RBR2:
 292         case LINK_RATE_HIGH2:
 293         case LINK_RATE_HIGH3:
 294         case LINK_RATE_UHBR10:
 295                 break;
 296         default:
 297                 valid_input = false;
 298                 break;
 299         }
 300
 301         if (!valid_input) {
 302                 kfree(wr_buf);
 303                 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
 304                 mutex_lock(&adev->dm.dc_lock);
 305                 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
 306                 mutex_unlock(&adev->dm.dc_lock);
 307                 return size;
 308         }
 309
 310         /* save user force lane_count, link_rate to preferred settings
 311          * spread spectrum will not be changed
 312          */
 313         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
 314         prefer_link_settings.use_link_rate_set = false;
 315         prefer_link_settings.lane_count = param[0];
 316         prefer_link_settings.link_rate = param[1];
 317
 318         mutex_lock(&adev->dm.dc_lock);
 319         dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false);
 320         mutex_unlock(&adev->dm.dc_lock);
 321
 322         kfree(wr_buf);
 323         return size;
 324 }
 325
 326 /* function: get current DP PHY settings: voltage swing, pre-emphasis,
 327  * post-cursor2 (defined by VESA DP specification)
 328  *
 329  * valid values
 330  * voltage swing: 0,1,2,3
 331  * pre-emphasis : 0,1,2,3
 332  * post cursor2 : 0,1,2,3
 333  *
 334  *
 335  * how to use this debugfs
 336  *
 337  * debugfs is located at /sys/kernel/debug/dri/0/DP-x
 338  *
 339  * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display
 340  *
 341  * To figure out which DP-x is the display for DP to be check,
 342  * cd DP-x
 343  * ls -ll
 344  * There should be debugfs file, like link_settings, phy_settings.
 345  * cat link_settings
 346  * from lane_count, link_rate to figure which DP-x is for display to be worked
 347  * on
 348  *
 349  * To get current DP PHY settings,
 350  * cat phy_settings
 351  *
 352  * To change DP PHY settings,
 353  * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings
 354  * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to
 355  * 0,
 356  * echo 2 3 0 > phy_settings
 357  *
 358  * To check if change be applied, get current phy settings by
 359  * cat phy_settings
 360  *
 361  * In case invalid values are set by user, like
 362  * echo 1 4 0 > phy_settings
 363  *
 364  * HW will NOT be programmed by these settings.
 365  * cat phy_settings will show the previous valid settings.
 366  */
 367 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,
 368                                  size_t size, loff_t *pos)
 369 {
 370         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 371         struct dc_link *link = connector->dc_link;
 372         char *rd_buf = NULL;
 373         const uint32_t rd_buf_size = 20;
 374         uint32_t result = 0;
 375         int r;
 376
 377         if (*pos & 3 || size & 3)
 378                 return -EINVAL;
 379
 380         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 381         if (!rd_buf)
 382                 return -EINVAL;
 383
 384         snprintf(rd_buf, rd_buf_size, "  %d  %d  %d\n",
 385                         link->cur_lane_setting[0].VOLTAGE_SWING,
 386                         link->cur_lane_setting[0].PRE_EMPHASIS,
 387                         link->cur_lane_setting[0].POST_CURSOR2);
 388
 389         while (size) {
 390                 if (*pos >= rd_buf_size)
 391                         break;
 392
 393                 r = put_user((*(rd_buf + result)), buf);
 394                 if (r) {
 395                         kfree(rd_buf);
 396                         return r; /* r = -EFAULT */
 397                 }
 398
 399                 buf += 1;
 400                 size -= 1;
 401                 *pos += 1;
 402                 result += 1;
 403         }
 404
 405         kfree(rd_buf);
 406         return result;
 407 }
 408
 409 static int dp_lttpr_status_show(struct seq_file *m, void *d)
 410 {
 411         char *data;
 412         struct amdgpu_dm_connector *connector = file_inode(m->file)->i_private;
 413         struct dc_link *link = connector->dc_link;
 414         uint32_t read_size = 1;
 415         uint8_t repeater_count = 0;
 416
 417         data = kzalloc(read_size, GFP_KERNEL);
 418         if (!data)
 419                 return 0;
 420
 421         dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0002, data, read_size);
 422
 423         switch ((uint8_t)*data) {
 424         case 0x80:
 425                 repeater_count = 1;
 426                 break;
 427         case 0x40:
 428                 repeater_count = 2;
 429                 break;
 430         case 0x20:
 431                 repeater_count = 3;
 432                 break;
 433         case 0x10:
 434                 repeater_count = 4;
 435                 break;
 436         case 0x8:
 437                 repeater_count = 5;
 438                 break;
 439         case 0x4:
 440                 repeater_count = 6;
 441                 break;
 442         case 0x2:
 443                 repeater_count = 7;
 444                 break;
 445         case 0x1:
 446                 repeater_count = 8;
 447                 break;
 448         case 0x0:
 449                 repeater_count = 0;
 450                 break;
 451         default:
 452                 repeater_count = (uint8_t)*data;
 453                 break;
 454         }
 455
 456         seq_printf(m, "phy repeater count: %d\n", repeater_count);
 457
 458         dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0003, data, read_size);
 459
 460         if ((uint8_t)*data == 0x55)
 461                 seq_printf(m, "phy repeater mode: transparent\n");
 462         else if ((uint8_t)*data == 0xAA)
 463                 seq_printf(m, "phy repeater mode: non-transparent\n");
 464         else if ((uint8_t)*data == 0x00)
 465                 seq_printf(m, "phy repeater mode: non lttpr\n");
 466         else
 467                 seq_printf(m, "phy repeater mode: read error\n");
 468
 469         kfree(data);
 470         return 0;
 471 }
 472
 473 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
 474                                  size_t size, loff_t *pos)
 475 {
 476         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 477         struct dc_link *link = connector->dc_link;
 478         struct dc *dc = (struct dc *)link->dc;
 479         char *wr_buf = NULL;
 480         uint32_t wr_buf_size = 40;
 481         long param[3];
 482         bool use_prefer_link_setting;
 483         struct link_training_settings link_lane_settings;
 484         int max_param_num = 3;
 485         uint8_t param_nums = 0;
 486         int r = 0;
 487
 488
 489         if (size == 0)
 490                 return -EINVAL;
 491
 492         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 493         if (!wr_buf)
 494                 return -ENOSPC;
 495
 496         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 497                                            (long *)param, buf,
 498                                            max_param_num,
 499                                            &param_nums)) {
 500                 kfree(wr_buf);
 501                 return -EINVAL;
 502         }
 503
 504         if (param_nums <= 0) {
 505                 kfree(wr_buf);
 506                 DRM_DEBUG_DRIVER("user data not be read\n");
 507                 return -EINVAL;
 508         }
 509
 510         if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) ||
 511                         (param[1] > PRE_EMPHASIS_MAX_LEVEL) ||
 512                         (param[2] > POST_CURSOR2_MAX_LEVEL)) {
 513                 kfree(wr_buf);
 514                 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n");
 515                 return size;
 516         }
 517
 518         /* get link settings: lane count, link rate */
 519         use_prefer_link_setting =
 520                 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) &&
 521                 (link->test_pattern_enabled));
 522
 523         memset(&link_lane_settings, 0, sizeof(link_lane_settings));
 524
 525         if (use_prefer_link_setting) {
 526                 link_lane_settings.link_settings.lane_count =
 527                                 link->preferred_link_setting.lane_count;
 528                 link_lane_settings.link_settings.link_rate =
 529                                 link->preferred_link_setting.link_rate;
 530                 link_lane_settings.link_settings.link_spread =
 531                                 link->preferred_link_setting.link_spread;
 532         } else {
 533                 link_lane_settings.link_settings.lane_count =
 534                                 link->cur_link_settings.lane_count;
 535                 link_lane_settings.link_settings.link_rate =
 536                                 link->cur_link_settings.link_rate;
 537                 link_lane_settings.link_settings.link_spread =
 538                                 link->cur_link_settings.link_spread;
 539         }
 540
 541         /* apply phy settings from user */
 542         for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
 543                 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING =
 544                                 (enum dc_voltage_swing) (param[0]);
 545                 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS =
 546                                 (enum dc_pre_emphasis) (param[1]);
 547                 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 =
 548                                 (enum dc_post_cursor2) (param[2]);
 549         }
 550
 551         /* program ASIC registers and DPCD registers */
 552         dc_link_set_drive_settings(dc, &link_lane_settings, link);
 553
 554         kfree(wr_buf);
 555         return size;
 556 }
 557
 558 /* function description
 559  *
 560  * set PHY layer or Link layer test pattern
 561  * PHY test pattern is used for PHY SI check.
 562  * Link layer test will not affect PHY SI.
 563  *
 564  * Reset Test Pattern:
 565  * 0 = DP_TEST_PATTERN_VIDEO_MODE
 566  *
 567  * PHY test pattern supported:
 568  * 1 = DP_TEST_PATTERN_D102
 569  * 2 = DP_TEST_PATTERN_SYMBOL_ERROR
 570  * 3 = DP_TEST_PATTERN_PRBS7
 571  * 4 = DP_TEST_PATTERN_80BIT_CUSTOM
 572  * 5 = DP_TEST_PATTERN_CP2520_1
 573  * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
 574  * 7 = DP_TEST_PATTERN_CP2520_3
 575  *
 576  * DP PHY Link Training Patterns
 577  * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1
 578  * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2
 579  * a = DP_TEST_PATTERN_TRAINING_PATTERN3
 580  * b = DP_TEST_PATTERN_TRAINING_PATTERN4
 581  *
 582  * DP Link Layer Test pattern
 583  * c = DP_TEST_PATTERN_COLOR_SQUARES
 584  * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA
 585  * e = DP_TEST_PATTERN_VERTICAL_BARS
 586  * f = DP_TEST_PATTERN_HORIZONTAL_BARS
 587  * 10= DP_TEST_PATTERN_COLOR_RAMP
 588  *
 589  * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x
 590  *
 591  * --- set test pattern
 592  * echo <test pattern #> > test_pattern
 593  *
 594  * If test pattern # is not supported, NO HW programming will be done.
 595  * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
 596  * for the user pattern. input 10 bytes data are separated by space
 597  *
 598  * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern
 599  *
 600  * --- reset test pattern
 601  * echo 0 > test_pattern
 602  *
 603  * --- HPD detection is disabled when set PHY test pattern
 604  *
 605  * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC
 606  * is disable. User could unplug DP display from DP connected and plug scope to
 607  * check test pattern PHY SI.
 608  * If there is need unplug scope and plug DP display back, do steps below:
 609  * echo 0 > phy_test_pattern
 610  * unplug scope
 611  * plug DP display.
 612  *
 613  * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw
 614  * driver could detect "unplug scope" and "plug DP display"
 615  */
 616 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf,
 617                                  size_t size, loff_t *pos)
 618 {
 619         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 620         struct dc_link *link = connector->dc_link;
 621         char *wr_buf = NULL;
 622         uint32_t wr_buf_size = 100;
 623         long param[11] = {0x0};
 624         int max_param_num = 11;
 625         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 626         bool disable_hpd = false;
 627         bool valid_test_pattern = false;
 628         uint8_t param_nums = 0;
 629         /* init with default 80bit custom pattern */
 630         uint8_t custom_pattern[10] = {
 631                         0x1f, 0x7c, 0xf0, 0xc1, 0x07,
 632                         0x1f, 0x7c, 0xf0, 0xc1, 0x07
 633                         };
 634         struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN,
 635                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 636         struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN,
 637                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 638         struct link_training_settings link_training_settings;
 639         int i;
 640
 641         if (size == 0)
 642                 return -EINVAL;
 643
 644         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 645         if (!wr_buf)
 646                 return -ENOSPC;
 647
 648         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 649                                            (long *)param, buf,
 650                                            max_param_num,
 651                                            &param_nums)) {
 652                 kfree(wr_buf);
 653                 return -EINVAL;
 654         }
 655
 656         if (param_nums <= 0) {
 657                 kfree(wr_buf);
 658                 DRM_DEBUG_DRIVER("user data not be read\n");
 659                 return -EINVAL;
 660         }
 661
 662
 663         test_pattern = param[0];
 664
 665         switch (test_pattern) {
 666         case DP_TEST_PATTERN_VIDEO_MODE:
 667         case DP_TEST_PATTERN_COLOR_SQUARES:
 668         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
 669         case DP_TEST_PATTERN_VERTICAL_BARS:
 670         case DP_TEST_PATTERN_HORIZONTAL_BARS:
 671         case DP_TEST_PATTERN_COLOR_RAMP:
 672                 valid_test_pattern = true;
 673                 break;
 674
 675         case DP_TEST_PATTERN_D102:
 676         case DP_TEST_PATTERN_SYMBOL_ERROR:
 677         case DP_TEST_PATTERN_PRBS7:
 678         case DP_TEST_PATTERN_80BIT_CUSTOM:
 679         case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
 680         case DP_TEST_PATTERN_TRAINING_PATTERN4:
 681                 disable_hpd = true;
 682                 valid_test_pattern = true;
 683                 break;
 684
 685         default:
 686                 valid_test_pattern = false;
 687                 test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 688                 break;
 689         }
 690
 691         if (!valid_test_pattern) {
 692                 kfree(wr_buf);
 693                 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n");
 694                 return size;
 695         }
 696
 697         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
 698                 for (i = 0; i < 10; i++) {
 699                         if ((uint8_t) param[i + 1] != 0x0)
 700                                 break;
 701                 }
 702
 703                 if (i < 10) {
 704                         /* not use default value */
 705                         for (i = 0; i < 10; i++)
 706                                 custom_pattern[i] = (uint8_t) param[i + 1];
 707                 }
 708         }
 709
 710         /* Usage: set DP physical test pattern using debugfs with normal DP
 711          * panel. Then plug out DP panel and connect a scope to measure
 712          * For normal video mode and test pattern generated from CRCT,
 713          * they are visibile to user. So do not disable HPD.
 714          * Video Mode is also set to clear the test pattern, so enable HPD
 715          * because it might have been disabled after a test pattern was set.
 716          * AUX depends on HPD * sequence dependent, do not move!
 717          */
 718         if (!disable_hpd)
 719                 dc_link_enable_hpd(link);
 720
 721         prefer_link_settings.lane_count = link->verified_link_cap.lane_count;
 722         prefer_link_settings.link_rate = link->verified_link_cap.link_rate;
 723         prefer_link_settings.link_spread = link->verified_link_cap.link_spread;
 724
 725         cur_link_settings.lane_count = link->cur_link_settings.lane_count;
 726         cur_link_settings.link_rate = link->cur_link_settings.link_rate;
 727         cur_link_settings.link_spread = link->cur_link_settings.link_spread;
 728
 729         link_training_settings.link_settings = cur_link_settings;
 730
 731
 732         if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
 733                 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN &&
 734                         prefer_link_settings.link_rate !=  LINK_RATE_UNKNOWN &&
 735                         (prefer_link_settings.lane_count != cur_link_settings.lane_count ||
 736                         prefer_link_settings.link_rate != cur_link_settings.link_rate))
 737                         link_training_settings.link_settings = prefer_link_settings;
 738         }
 739
 740         for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
 741                 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i];
 742
 743         dc_link_set_test_pattern(
 744                 link,
 745                 test_pattern,
 746                 DP_TEST_PATTERN_COLOR_SPACE_RGB,
 747                 &link_training_settings,
 748                 custom_pattern,
 749                 10);
 750
 751         /* Usage: Set DP physical test pattern using AMDDP with normal DP panel
 752          * Then plug out DP panel and connect a scope to measure DP PHY signal.
 753          * Need disable interrupt to avoid SW driver disable DP output. This is
 754          * done after the test pattern is set.
 755          */
 756         if (valid_test_pattern && disable_hpd)
 757                 dc_link_disable_hpd(link);
 758
 759         kfree(wr_buf);
 760
 761         return size;
 762 }
 763
 764 /*
 765  * Returns the DMCUB tracebuffer contents.
 766  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
 767  */
 768 static int dmub_tracebuffer_show(struct seq_file *m, void *data)
 769 {
 770         struct amdgpu_device *adev = m->private;
 771         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 772         struct dmub_debugfs_trace_entry *entries;
 773         uint8_t *tbuf_base;
 774         uint32_t tbuf_size, max_entries, num_entries, i;
 775
 776         if (!fb_info)
 777                 return 0;
 778
 779         tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;
 780         if (!tbuf_base)
 781                 return 0;
 782
 783         tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size;
 784         max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /
 785                       sizeof(struct dmub_debugfs_trace_entry);
 786
 787         num_entries =
 788                 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count;
 789
 790         num_entries = min(num_entries, max_entries);
 791
 792         entries = (struct dmub_debugfs_trace_entry
 793                            *)(tbuf_base +
 794                               sizeof(struct dmub_debugfs_trace_header));
 795
 796         for (i = 0; i < num_entries; ++i) {
 797                 struct dmub_debugfs_trace_entry *entry = &entries[i];
 798
 799                 seq_printf(m,
 800                            "trace_code=%u tick_count=%u param0=%u param1=%u\n",
 801                            entry->trace_code, entry->tick_count, entry->param0,
 802                            entry->param1);
 803         }
 804
 805         return 0;
 806 }
 807
 808 /*
 809  * Returns the DMCUB firmware state contents.
 810  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state
 811  */
 812 static int dmub_fw_state_show(struct seq_file *m, void *data)
 813 {
 814         struct amdgpu_device *adev = m->private;
 815         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 816         uint8_t *state_base;
 817         uint32_t state_size;
 818
 819         if (!fb_info)
 820                 return 0;
 821
 822         state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr;
 823         if (!state_base)
 824                 return 0;
 825
 826         state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size;
 827
 828         return seq_write(m, state_base, state_size);
 829 }
 830
 831 /* psr_capability_show() - show eDP panel PSR capability
 832  *
 833  * The read function: sink_psr_capability_show
 834  * Shows if sink has PSR capability or not.
 835  * If yes - the PSR version is appended
 836  *
 837  *      cat /sys/kernel/debug/dri/0/eDP-X/psr_capability
 838  *
 839  * Expected output:
 840  * "Sink support: no\n" - if panel doesn't support PSR
 841  * "Sink support: yes [0x01]\n" - if panel supports PSR1
 842  * "Driver support: no\n" - if driver doesn't support PSR
 843  * "Driver support: yes [0x01]\n" - if driver supports PSR1
 844  */
 845 static int psr_capability_show(struct seq_file *m, void *data)
 846 {
 847         struct drm_connector *connector = m->private;
 848         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 849         struct dc_link *link = aconnector->dc_link;
 850
 851         if (!link)
 852                 return -ENODEV;
 853
 854         if (link->type == dc_connection_none)
 855                 return -ENODEV;
 856
 857         if (!(link->connector_signal & SIGNAL_TYPE_EDP))
 858                 return -ENODEV;
 859
 860         seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0));
 861         if (link->dpcd_caps.psr_info.psr_version)
 862                 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version);
 863         seq_puts(m, "\n");
 864
 865         seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled));
 866         if (link->psr_settings.psr_version)
 867                 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version);
 868         seq_puts(m, "\n");
 869
 870         return 0;
 871 }
 872
 873 /*
 874  * Returns the current bpc for the crtc.
 875  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc
 876  */
 877 static int amdgpu_current_bpc_show(struct seq_file *m, void *data)
 878 {
 879         struct drm_crtc *crtc = m->private;
 880         struct drm_device *dev = crtc->dev;
 881         struct dm_crtc_state *dm_crtc_state = NULL;
 882         int res = -ENODEV;
 883         unsigned int bpc;
 884
 885         mutex_lock(&dev->mode_config.mutex);
 886         drm_modeset_lock(&crtc->mutex, NULL);
 887         if (crtc->state == NULL)
 888                 goto unlock;
 889
 890         dm_crtc_state = to_dm_crtc_state(crtc->state);
 891         if (dm_crtc_state->stream == NULL)
 892                 goto unlock;
 893
 894         switch (dm_crtc_state->stream->timing.display_color_depth) {
 895         case COLOR_DEPTH_666:
 896                 bpc = 6;
 897                 break;
 898         case COLOR_DEPTH_888:
 899                 bpc = 8;
 900                 break;
 901         case COLOR_DEPTH_101010:
 902                 bpc = 10;
 903                 break;
 904         case COLOR_DEPTH_121212:
 905                 bpc = 12;
 906                 break;
 907         case COLOR_DEPTH_161616:
 908                 bpc = 16;
 909                 break;
 910         default:
 911                 goto unlock;
 912         }
 913
 914         seq_printf(m, "Current: %u\n", bpc);
 915         res = 0;
 916
 917 unlock:
 918         drm_modeset_unlock(&crtc->mutex);
 919         mutex_unlock(&dev->mode_config.mutex);
 920
 921         return res;
 922 }
 923 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc);
 924
 925 /*
 926  * Example usage:
 927  * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
 928  *   echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
 929  * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
 930  *   echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
 931  */
 932 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf,
 933                                  size_t size, loff_t *pos)
 934 {
 935         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
 936         char *wr_buf = NULL;
 937         uint32_t wr_buf_size = 42;
 938         int max_param_num = 1;
 939         long param;
 940         uint8_t param_nums = 0;
 941
 942         if (size == 0)
 943                 return -EINVAL;
 944
 945         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 946
 947         if (!wr_buf) {
 948                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
 949                 return -ENOSPC;
 950         }
 951
 952         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 953                                            &param, buf,
 954                                            max_param_num,
 955                                            &param_nums)) {
 956                 kfree(wr_buf);
 957                 return -EINVAL;
 958         }
 959
 960         aconnector->dsc_settings.dsc_force_disable_passthrough = param;
 961
 962         kfree(wr_buf);
 963         return 0;
 964 }
 965
 966 #ifdef CONFIG_DRM_AMD_DC_HDCP
 967 /*
 968  * Returns the HDCP capability of the Display (1.4 for now).
 969  *
 970  * NOTE* Not all HDMI displays report their HDCP caps even when they are capable.
 971  * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable.
 972  *
 973  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability
 974  *              or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability
 975  */
 976 static int hdcp_sink_capability_show(struct seq_file *m, void *data)
 977 {
 978         struct drm_connector *connector = m->private;
 979         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 980         bool hdcp_cap, hdcp2_cap;
 981
 982         if (connector->status != connector_status_connected)
 983                 return -ENODEV;
 984
 985         seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id);
 986
 987         hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal);
 988         hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal);
 989
 990
 991         if (hdcp_cap)
 992                 seq_printf(m, "%s ", "HDCP1.4");
 993         if (hdcp2_cap)
 994                 seq_printf(m, "%s ", "HDCP2.2");
 995
 996         if (!hdcp_cap && !hdcp2_cap)
 997                 seq_printf(m, "%s ", "None");
 998
 999         seq_puts(m, "\n");
1000
1001         return 0;
1002 }
1003 #endif
1004
1005 /*
1006  * Returns whether the connected display is internal and not hotpluggable.
1007  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display
1008  */
1009 static int internal_display_show(struct seq_file *m, void *data)
1010 {
1011         struct drm_connector *connector = m->private;
1012         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1013         struct dc_link *link = aconnector->dc_link;
1014
1015         seq_printf(m, "Internal: %u\n", link->is_internal_display);
1016
1017         return 0;
1018 }
1019
1020 /* function description
1021  *
1022  * generic SDP message access for testing
1023  *
1024  * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x
1025  *
1026  * SDP header
1027  * Hb0 : Secondary-Data Packet ID
1028  * Hb1 : Secondary-Data Packet type
1029  * Hb2 : Secondary-Data-packet-specific header, Byte 0
1030  * Hb3 : Secondary-Data-packet-specific header, Byte 1
1031  *
1032  * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data
1033  */
1034 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf,
1035                                  size_t size, loff_t *pos)
1036 {
1037         int r;
1038         uint8_t data[36];
1039         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1040         struct dm_crtc_state *acrtc_state;
1041         uint32_t write_size = 36;
1042
1043         if (connector->base.status != connector_status_connected)
1044                 return -ENODEV;
1045
1046         if (size == 0)
1047                 return 0;
1048
1049         acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state);
1050
1051         r = copy_from_user(data, buf, write_size);
1052
1053         write_size -= r;
1054
1055         dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size);
1056
1057         return write_size;
1058 }
1059
1060 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf,
1061                                  size_t size, loff_t *pos)
1062 {
1063         int r;
1064         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1065
1066         if (size < sizeof(connector->debugfs_dpcd_address))
1067                 return -EINVAL;
1068
1069         r = copy_from_user(&connector->debugfs_dpcd_address,
1070                         buf, sizeof(connector->debugfs_dpcd_address));
1071
1072         return size - r;
1073 }
1074
1075 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf,
1076                                  size_t size, loff_t *pos)
1077 {
1078         int r;
1079         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1080
1081         if (size < sizeof(connector->debugfs_dpcd_size))
1082                 return -EINVAL;
1083
1084         r = copy_from_user(&connector->debugfs_dpcd_size,
1085                         buf, sizeof(connector->debugfs_dpcd_size));
1086
1087         if (connector->debugfs_dpcd_size > 256)
1088                 connector->debugfs_dpcd_size = 0;
1089
1090         return size - r;
1091 }
1092
1093 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf,
1094                                  size_t size, loff_t *pos)
1095 {
1096         int r;
1097         char *data;
1098         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1099         struct dc_link *link = connector->dc_link;
1100         uint32_t write_size = connector->debugfs_dpcd_size;
1101
1102         if (!write_size || size < write_size)
1103                 return -EINVAL;
1104
1105         data = kzalloc(write_size, GFP_KERNEL);
1106         if (!data)
1107                 return 0;
1108
1109         r = copy_from_user(data, buf, write_size);
1110
1111         dm_helpers_dp_write_dpcd(link->ctx, link,
1112                         connector->debugfs_dpcd_address, data, write_size - r);
1113         kfree(data);
1114         return write_size - r;
1115 }
1116
1117 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf,
1118                                  size_t size, loff_t *pos)
1119 {
1120         int r;
1121         char *data;
1122         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1123         struct dc_link *link = connector->dc_link;
1124         uint32_t read_size = connector->debugfs_dpcd_size;
1125
1126         if (!read_size || size < read_size)
1127                 return 0;
1128
1129         data = kzalloc(read_size, GFP_KERNEL);
1130         if (!data)
1131                 return 0;
1132
1133         dm_helpers_dp_read_dpcd(link->ctx, link,
1134                         connector->debugfs_dpcd_address, data, read_size);
1135
1136         r = copy_to_user(buf, data, read_size);
1137
1138         kfree(data);
1139         return read_size - r;
1140 }
1141
1142 /* function: Read link's DSC & FEC capabilities
1143  *
1144  *
1145  * Access it with the following command (you need to specify
1146  * connector like DP-1):
1147  *
1148  *      cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support
1149  *
1150  */
1151 static int dp_dsc_fec_support_show(struct seq_file *m, void *data)
1152 {
1153         struct drm_connector *connector = m->private;
1154         struct drm_modeset_acquire_ctx ctx;
1155         struct drm_device *dev = connector->dev;
1156         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1157         int ret = 0;
1158         bool try_again = false;
1159         bool is_fec_supported = false;
1160         bool is_dsc_supported = false;
1161         struct dpcd_caps dpcd_caps;
1162
1163         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1164         do {
1165                 try_again = false;
1166                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
1167                 if (ret) {
1168                         if (ret == -EDEADLK) {
1169                                 ret = drm_modeset_backoff(&ctx);
1170                                 if (!ret) {
1171                                         try_again = true;
1172                                         continue;
1173                                 }
1174                         }
1175                         break;
1176                 }
1177                 if (connector->status != connector_status_connected) {
1178                         ret = -ENODEV;
1179                         break;
1180                 }
1181                 dpcd_caps = aconnector->dc_link->dpcd_caps;
1182                 if (aconnector->port) {
1183                         /* aconnector sets dsc_aux during get_modes call
1184                          * if MST connector has it means it can either
1185                          * enable DSC on the sink device or on MST branch
1186                          * its connected to.
1187                          */
1188                         if (aconnector->dsc_aux) {
1189                                 is_fec_supported = true;
1190                                 is_dsc_supported = true;
1191                         }
1192                 } else {
1193                         is_fec_supported = dpcd_caps.fec_cap.raw & 0x1;
1194                         is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1;
1195                 }
1196         } while (try_again);
1197
1198         drm_modeset_drop_locks(&ctx);
1199         drm_modeset_acquire_fini(&ctx);
1200
1201         seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported));
1202         seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported));
1203
1204         return ret;
1205 }
1206
1207 /* function: Trigger virtual HPD redetection on connector
1208  *
1209  * This function will perform link rediscovery, link disable
1210  * and enable, and dm connector state update.
1211  *
1212  * Retrigger HPD on an existing connector by echoing 1 into
1213  * its respectful "trigger_hotplug" debugfs entry:
1214  *
1215  *      echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1216  *
1217  * This function can perform HPD unplug:
1218  *
1219  *      echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1220  *
1221  */
1222 static ssize_t trigger_hotplug(struct file *f, const char __user *buf,
1223                                                         size_t size, loff_t *pos)
1224 {
1225         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1226         struct drm_connector *connector = &aconnector->base;
1227         struct dc_link *link = NULL;
1228         struct drm_device *dev = connector->dev;
1229         enum dc_connection_type new_connection_type = dc_connection_none;
1230         char *wr_buf = NULL;
1231         uint32_t wr_buf_size = 42;
1232         int max_param_num = 1;
1233         long param[1] = {0};
1234         uint8_t param_nums = 0;
1235
1236         if (!aconnector || !aconnector->dc_link)
1237                 return -EINVAL;
1238
1239         if (size == 0)
1240                 return -EINVAL;
1241
1242         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1243
1244         if (!wr_buf) {
1245                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1246                 return -ENOSPC;
1247         }
1248
1249         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1250                                                 (long *)param, buf,
1251                                                 max_param_num,
1252                                                 &param_nums)) {
1253                 kfree(wr_buf);
1254                 return -EINVAL;
1255         }
1256
1257         if (param_nums <= 0) {
1258                 DRM_DEBUG_DRIVER("user data not be read\n");
1259                 kfree(wr_buf);
1260                 return -EINVAL;
1261         }
1262
1263         if (param[0] == 1) {
1264                 mutex_lock(&aconnector->hpd_lock);
1265
1266                 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type) &&
1267                         new_connection_type != dc_connection_none)
1268                         goto unlock;
1269
1270                 if (!dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD))
1271                         goto unlock;
1272
1273                 amdgpu_dm_update_connector_after_detect(aconnector);
1274
1275                 drm_modeset_lock_all(dev);
1276                 dm_restore_drm_connector_state(dev, connector);
1277                 drm_modeset_unlock_all(dev);
1278
1279                 drm_kms_helper_connector_hotplug_event(connector);
1280         } else if (param[0] == 0) {
1281                 if (!aconnector->dc_link)
1282                         goto unlock;
1283
1284                 link = aconnector->dc_link;
1285
1286                 if (link->local_sink) {
1287                         dc_sink_release(link->local_sink);
1288                         link->local_sink = NULL;
1289                 }
1290
1291                 link->dpcd_sink_count = 0;
1292                 link->type = dc_connection_none;
1293                 link->dongle_max_pix_clk = 0;
1294
1295                 amdgpu_dm_update_connector_after_detect(aconnector);
1296
1297                 drm_modeset_lock_all(dev);
1298                 dm_restore_drm_connector_state(dev, connector);
1299                 drm_modeset_unlock_all(dev);
1300
1301                 drm_kms_helper_connector_hotplug_event(connector);
1302         }
1303
1304 unlock:
1305         mutex_unlock(&aconnector->hpd_lock);
1306
1307         kfree(wr_buf);
1308         return size;
1309 }
1310
1311 /* function: read DSC status on the connector
1312  *
1313  * The read function: dp_dsc_clock_en_read
1314  * returns current status of DSC clock on the connector.
1315  * The return is a boolean flag: 1 or 0.
1316  *
1317  * Access it with the following command (you need to specify
1318  * connector like DP-1):
1319  *
1320  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1321  *
1322  * Expected output:
1323  * 1 - means that DSC is currently enabled
1324  * 0 - means that DSC is disabled
1325  */
1326 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
1327                                     size_t size, loff_t *pos)
1328 {
1329         char *rd_buf = NULL;
1330         char *rd_buf_ptr = NULL;
1331         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1332         struct display_stream_compressor *dsc;
1333         struct dcn_dsc_state dsc_state = {0};
1334         const uint32_t rd_buf_size = 10;
1335         struct pipe_ctx *pipe_ctx;
1336         ssize_t result = 0;
1337         int i, r, str_len = 30;
1338
1339         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1340
1341         if (!rd_buf)
1342                 return -ENOMEM;
1343
1344         rd_buf_ptr = rd_buf;
1345
1346         for (i = 0; i < MAX_PIPES; i++) {
1347                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1348                         if (pipe_ctx && pipe_ctx->stream &&
1349                             pipe_ctx->stream->link == aconnector->dc_link)
1350                                 break;
1351         }
1352
1353         if (!pipe_ctx) {
1354                 kfree(rd_buf);
1355                 return -ENXIO;
1356         }
1357
1358         dsc = pipe_ctx->stream_res.dsc;
1359         if (dsc)
1360                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1361
1362         snprintf(rd_buf_ptr, str_len,
1363                 "%d\n",
1364                 dsc_state.dsc_clock_en);
1365         rd_buf_ptr += str_len;
1366
1367         while (size) {
1368                 if (*pos >= rd_buf_size)
1369                         break;
1370
1371                 r = put_user(*(rd_buf + result), buf);
1372                 if (r) {
1373                         kfree(rd_buf);
1374                         return r; /* r = -EFAULT */
1375                 }
1376
1377                 buf += 1;
1378                 size -= 1;
1379                 *pos += 1;
1380                 result += 1;
1381         }
1382
1383         kfree(rd_buf);
1384         return result;
1385 }
1386
1387 /* function: write force DSC on the connector
1388  *
1389  * The write function: dp_dsc_clock_en_write
1390  * enables to force DSC on the connector.
1391  * User can write to either force enable or force disable DSC
1392  * on the next modeset or set it to driver default
1393  *
1394  * Accepted inputs:
1395  * 0 - default DSC enablement policy
1396  * 1 - force enable DSC on the connector
1397  * 2 - force disable DSC on the connector (might cause fail in atomic_check)
1398  *
1399  * Writing DSC settings is done with the following command:
1400  * - To force enable DSC (you need to specify
1401  * connector like DP-1):
1402  *
1403  *      echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1404  *
1405  * - To return to default state set the flag to zero and
1406  * let driver deal with DSC automatically
1407  * (you need to specify connector like DP-1):
1408  *
1409  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1410  *
1411  */
1412 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
1413                                      size_t size, loff_t *pos)
1414 {
1415         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1416         struct drm_connector *connector = &aconnector->base;
1417         struct drm_device *dev = connector->dev;
1418         struct drm_crtc *crtc = NULL;
1419         struct dm_crtc_state *dm_crtc_state = NULL;
1420         struct pipe_ctx *pipe_ctx;
1421         int i;
1422         char *wr_buf = NULL;
1423         uint32_t wr_buf_size = 42;
1424         int max_param_num = 1;
1425         long param[1] = {0};
1426         uint8_t param_nums = 0;
1427
1428         if (size == 0)
1429                 return -EINVAL;
1430
1431         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1432
1433         if (!wr_buf) {
1434                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1435                 return -ENOSPC;
1436         }
1437
1438         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1439                                             (long *)param, buf,
1440                                             max_param_num,
1441                                             &param_nums)) {
1442                 kfree(wr_buf);
1443                 return -EINVAL;
1444         }
1445
1446         if (param_nums <= 0) {
1447                 DRM_DEBUG_DRIVER("user data not be read\n");
1448                 kfree(wr_buf);
1449                 return -EINVAL;
1450         }
1451
1452         for (i = 0; i < MAX_PIPES; i++) {
1453                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1454                         if (pipe_ctx && pipe_ctx->stream &&
1455                             pipe_ctx->stream->link == aconnector->dc_link)
1456                                 break;
1457         }
1458
1459         if (!pipe_ctx || !pipe_ctx->stream)
1460                 goto done;
1461
1462         // Get CRTC state
1463         mutex_lock(&dev->mode_config.mutex);
1464         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1465
1466         if (connector->state == NULL)
1467                 goto unlock;
1468
1469         crtc = connector->state->crtc;
1470         if (crtc == NULL)
1471                 goto unlock;
1472
1473         drm_modeset_lock(&crtc->mutex, NULL);
1474         if (crtc->state == NULL)
1475                 goto unlock;
1476
1477         dm_crtc_state = to_dm_crtc_state(crtc->state);
1478         if (dm_crtc_state->stream == NULL)
1479                 goto unlock;
1480
1481         if (param[0] == 1)
1482                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE;
1483         else if (param[0] == 2)
1484                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE;
1485         else
1486                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT;
1487
1488         dm_crtc_state->dsc_force_changed = true;
1489
1490 unlock:
1491         if (crtc)
1492                 drm_modeset_unlock(&crtc->mutex);
1493         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1494         mutex_unlock(&dev->mode_config.mutex);
1495
1496 done:
1497         kfree(wr_buf);
1498         return size;
1499 }
1500
1501 /* function: read DSC slice width parameter on the connector
1502  *
1503  * The read function: dp_dsc_slice_width_read
1504  * returns dsc slice width used in the current configuration
1505  * The return is an integer: 0 or other positive number
1506  *
1507  * Access the status with the following command:
1508  *
1509  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1510  *
1511  * 0 - means that DSC is disabled
1512  *
1513  * Any other number more than zero represents the
1514  * slice width currently used by DSC in pixels
1515  *
1516  */
1517 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
1518                                     size_t size, loff_t *pos)
1519 {
1520         char *rd_buf = NULL;
1521         char *rd_buf_ptr = NULL;
1522         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1523         struct display_stream_compressor *dsc;
1524         struct dcn_dsc_state dsc_state = {0};
1525         const uint32_t rd_buf_size = 100;
1526         struct pipe_ctx *pipe_ctx;
1527         ssize_t result = 0;
1528         int i, r, str_len = 30;
1529
1530         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1531
1532         if (!rd_buf)
1533                 return -ENOMEM;
1534
1535         rd_buf_ptr = rd_buf;
1536
1537         for (i = 0; i < MAX_PIPES; i++) {
1538                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1539                         if (pipe_ctx && pipe_ctx->stream &&
1540                             pipe_ctx->stream->link == aconnector->dc_link)
1541                                 break;
1542         }
1543
1544         if (!pipe_ctx) {
1545                 kfree(rd_buf);
1546                 return -ENXIO;
1547         }
1548
1549         dsc = pipe_ctx->stream_res.dsc;
1550         if (dsc)
1551                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1552
1553         snprintf(rd_buf_ptr, str_len,
1554                 "%d\n",
1555                 dsc_state.dsc_slice_width);
1556         rd_buf_ptr += str_len;
1557
1558         while (size) {
1559                 if (*pos >= rd_buf_size)
1560                         break;
1561
1562                 r = put_user(*(rd_buf + result), buf);
1563                 if (r) {
1564                         kfree(rd_buf);
1565                         return r; /* r = -EFAULT */
1566                 }
1567
1568                 buf += 1;
1569                 size -= 1;
1570                 *pos += 1;
1571                 result += 1;
1572         }
1573
1574         kfree(rd_buf);
1575         return result;
1576 }
1577
1578 /* function: write DSC slice width parameter
1579  *
1580  * The write function: dp_dsc_slice_width_write
1581  * overwrites automatically generated DSC configuration
1582  * of slice width.
1583  *
1584  * The user has to write the slice width divisible by the
1585  * picture width.
1586  *
1587  * Also the user has to write width in hexidecimal
1588  * rather than in decimal.
1589  *
1590  * Writing DSC settings is done with the following command:
1591  * - To force overwrite slice width: (example sets to 1920 pixels)
1592  *
1593  *      echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1594  *
1595  *  - To stop overwriting and let driver find the optimal size,
1596  * set the width to zero:
1597  *
1598  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1599  *
1600  */
1601 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
1602                                      size_t size, loff_t *pos)
1603 {
1604         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1605         struct pipe_ctx *pipe_ctx;
1606         struct drm_connector *connector = &aconnector->base;
1607         struct drm_device *dev = connector->dev;
1608         struct drm_crtc *crtc = NULL;
1609         struct dm_crtc_state *dm_crtc_state = NULL;
1610         int i;
1611         char *wr_buf = NULL;
1612         uint32_t wr_buf_size = 42;
1613         int max_param_num = 1;
1614         long param[1] = {0};
1615         uint8_t param_nums = 0;
1616
1617         if (size == 0)
1618                 return -EINVAL;
1619
1620         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1621
1622         if (!wr_buf) {
1623                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1624                 return -ENOSPC;
1625         }
1626
1627         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1628                                             (long *)param, buf,
1629                                             max_param_num,
1630                                             &param_nums)) {
1631                 kfree(wr_buf);
1632                 return -EINVAL;
1633         }
1634
1635         if (param_nums <= 0) {
1636                 DRM_DEBUG_DRIVER("user data not be read\n");
1637                 kfree(wr_buf);
1638                 return -EINVAL;
1639         }
1640
1641         for (i = 0; i < MAX_PIPES; i++) {
1642                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1643                         if (pipe_ctx && pipe_ctx->stream &&
1644                             pipe_ctx->stream->link == aconnector->dc_link)
1645                                 break;
1646         }
1647
1648         if (!pipe_ctx || !pipe_ctx->stream)
1649                 goto done;
1650
1651         // Safely get CRTC state
1652         mutex_lock(&dev->mode_config.mutex);
1653         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1654
1655         if (connector->state == NULL)
1656                 goto unlock;
1657
1658         crtc = connector->state->crtc;
1659         if (crtc == NULL)
1660                 goto unlock;
1661
1662         drm_modeset_lock(&crtc->mutex, NULL);
1663         if (crtc->state == NULL)
1664                 goto unlock;
1665
1666         dm_crtc_state = to_dm_crtc_state(crtc->state);
1667         if (dm_crtc_state->stream == NULL)
1668                 goto unlock;
1669
1670         if (param[0] > 0)
1671                 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(
1672                                         pipe_ctx->stream->timing.h_addressable,
1673                                         param[0]);
1674         else
1675                 aconnector->dsc_settings.dsc_num_slices_h = 0;
1676
1677         dm_crtc_state->dsc_force_changed = true;
1678
1679 unlock:
1680         if (crtc)
1681                 drm_modeset_unlock(&crtc->mutex);
1682         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1683         mutex_unlock(&dev->mode_config.mutex);
1684
1685 done:
1686         kfree(wr_buf);
1687         return size;
1688 }
1689
1690 /* function: read DSC slice height parameter on the connector
1691  *
1692  * The read function: dp_dsc_slice_height_read
1693  * returns dsc slice height used in the current configuration
1694  * The return is an integer: 0 or other positive number
1695  *
1696  * Access the status with the following command:
1697  *
1698  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1699  *
1700  * 0 - means that DSC is disabled
1701  *
1702  * Any other number more than zero represents the
1703  * slice height currently used by DSC in pixels
1704  *
1705  */
1706 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
1707                                     size_t size, loff_t *pos)
1708 {
1709         char *rd_buf = NULL;
1710         char *rd_buf_ptr = NULL;
1711         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1712         struct display_stream_compressor *dsc;
1713         struct dcn_dsc_state dsc_state = {0};
1714         const uint32_t rd_buf_size = 100;
1715         struct pipe_ctx *pipe_ctx;
1716         ssize_t result = 0;
1717         int i, r, str_len = 30;
1718
1719         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1720
1721         if (!rd_buf)
1722                 return -ENOMEM;
1723
1724         rd_buf_ptr = rd_buf;
1725
1726         for (i = 0; i < MAX_PIPES; i++) {
1727                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1728                         if (pipe_ctx && pipe_ctx->stream &&
1729                             pipe_ctx->stream->link == aconnector->dc_link)
1730                                 break;
1731         }
1732
1733         if (!pipe_ctx) {
1734                 kfree(rd_buf);
1735                 return -ENXIO;
1736         }
1737
1738         dsc = pipe_ctx->stream_res.dsc;
1739         if (dsc)
1740                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1741
1742         snprintf(rd_buf_ptr, str_len,
1743                 "%d\n",
1744                 dsc_state.dsc_slice_height);
1745         rd_buf_ptr += str_len;
1746
1747         while (size) {
1748                 if (*pos >= rd_buf_size)
1749                         break;
1750
1751                 r = put_user(*(rd_buf + result), buf);
1752                 if (r) {
1753                         kfree(rd_buf);
1754                         return r; /* r = -EFAULT */
1755                 }
1756
1757                 buf += 1;
1758                 size -= 1;
1759                 *pos += 1;
1760                 result += 1;
1761         }
1762
1763         kfree(rd_buf);
1764         return result;
1765 }
1766
1767 /* function: write DSC slice height parameter
1768  *
1769  * The write function: dp_dsc_slice_height_write
1770  * overwrites automatically generated DSC configuration
1771  * of slice height.
1772  *
1773  * The user has to write the slice height divisible by the
1774  * picture height.
1775  *
1776  * Also the user has to write height in hexidecimal
1777  * rather than in decimal.
1778  *
1779  * Writing DSC settings is done with the following command:
1780  * - To force overwrite slice height (example sets to 128 pixels):
1781  *
1782  *      echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1783  *
1784  *  - To stop overwriting and let driver find the optimal size,
1785  * set the height to zero:
1786  *
1787  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1788  *
1789  */
1790 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
1791                                      size_t size, loff_t *pos)
1792 {
1793         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1794         struct drm_connector *connector = &aconnector->base;
1795         struct drm_device *dev = connector->dev;
1796         struct drm_crtc *crtc = NULL;
1797         struct dm_crtc_state *dm_crtc_state = NULL;
1798         struct pipe_ctx *pipe_ctx;
1799         int i;
1800         char *wr_buf = NULL;
1801         uint32_t wr_buf_size = 42;
1802         int max_param_num = 1;
1803         uint8_t param_nums = 0;
1804         long param[1] = {0};
1805
1806         if (size == 0)
1807                 return -EINVAL;
1808
1809         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1810
1811         if (!wr_buf) {
1812                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1813                 return -ENOSPC;
1814         }
1815
1816         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1817                                             (long *)param, buf,
1818                                             max_param_num,
1819                                             &param_nums)) {
1820                 kfree(wr_buf);
1821                 return -EINVAL;
1822         }
1823
1824         if (param_nums <= 0) {
1825                 DRM_DEBUG_DRIVER("user data not be read\n");
1826                 kfree(wr_buf);
1827                 return -EINVAL;
1828         }
1829
1830         for (i = 0; i < MAX_PIPES; i++) {
1831                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1832                         if (pipe_ctx && pipe_ctx->stream &&
1833                             pipe_ctx->stream->link == aconnector->dc_link)
1834                                 break;
1835         }
1836
1837         if (!pipe_ctx || !pipe_ctx->stream)
1838                 goto done;
1839
1840         // Get CRTC state
1841         mutex_lock(&dev->mode_config.mutex);
1842         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1843
1844         if (connector->state == NULL)
1845                 goto unlock;
1846
1847         crtc = connector->state->crtc;
1848         if (crtc == NULL)
1849                 goto unlock;
1850
1851         drm_modeset_lock(&crtc->mutex, NULL);
1852         if (crtc->state == NULL)
1853                 goto unlock;
1854
1855         dm_crtc_state = to_dm_crtc_state(crtc->state);
1856         if (dm_crtc_state->stream == NULL)
1857                 goto unlock;
1858
1859         if (param[0] > 0)
1860                 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(
1861                                         pipe_ctx->stream->timing.v_addressable,
1862                                         param[0]);
1863         else
1864                 aconnector->dsc_settings.dsc_num_slices_v = 0;
1865
1866         dm_crtc_state->dsc_force_changed = true;
1867
1868 unlock:
1869         if (crtc)
1870                 drm_modeset_unlock(&crtc->mutex);
1871         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1872         mutex_unlock(&dev->mode_config.mutex);
1873
1874 done:
1875         kfree(wr_buf);
1876         return size;
1877 }
1878
1879 /* function: read DSC target rate on the connector in bits per pixel
1880  *
1881  * The read function: dp_dsc_bits_per_pixel_read
1882  * returns target rate of compression in bits per pixel
1883  * The return is an integer: 0 or other positive integer
1884  *
1885  * Access it with the following command:
1886  *
1887  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1888  *
1889  *  0 - means that DSC is disabled
1890  */
1891 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
1892                                     size_t size, loff_t *pos)
1893 {
1894         char *rd_buf = NULL;
1895         char *rd_buf_ptr = NULL;
1896         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1897         struct display_stream_compressor *dsc;
1898         struct dcn_dsc_state dsc_state = {0};
1899         const uint32_t rd_buf_size = 100;
1900         struct pipe_ctx *pipe_ctx;
1901         ssize_t result = 0;
1902         int i, r, str_len = 30;
1903
1904         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1905
1906         if (!rd_buf)
1907                 return -ENOMEM;
1908
1909         rd_buf_ptr = rd_buf;
1910
1911         for (i = 0; i < MAX_PIPES; i++) {
1912                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1913                         if (pipe_ctx && pipe_ctx->stream &&
1914                             pipe_ctx->stream->link == aconnector->dc_link)
1915                                 break;
1916         }
1917
1918         if (!pipe_ctx) {
1919                 kfree(rd_buf);
1920                 return -ENXIO;
1921         }
1922
1923         dsc = pipe_ctx->stream_res.dsc;
1924         if (dsc)
1925                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1926
1927         snprintf(rd_buf_ptr, str_len,
1928                 "%d\n",
1929                 dsc_state.dsc_bits_per_pixel);
1930         rd_buf_ptr += str_len;
1931
1932         while (size) {
1933                 if (*pos >= rd_buf_size)
1934                         break;
1935
1936                 r = put_user(*(rd_buf + result), buf);
1937                 if (r) {
1938                         kfree(rd_buf);
1939                         return r; /* r = -EFAULT */
1940                 }
1941
1942                 buf += 1;
1943                 size -= 1;
1944                 *pos += 1;
1945                 result += 1;
1946         }
1947
1948         kfree(rd_buf);
1949         return result;
1950 }
1951
1952 /* function: write DSC target rate in bits per pixel
1953  *
1954  * The write function: dp_dsc_bits_per_pixel_write
1955  * overwrites automatically generated DSC configuration
1956  * of DSC target bit rate.
1957  *
1958  * Also the user has to write bpp in hexidecimal
1959  * rather than in decimal.
1960  *
1961  * Writing DSC settings is done with the following command:
1962  * - To force overwrite rate (example sets to 256 bpp x 1/16):
1963  *
1964  *      echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1965  *
1966  *  - To stop overwriting and let driver find the optimal rate,
1967  * set the rate to zero:
1968  *
1969  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1970  *
1971  */
1972 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf,
1973                                      size_t size, loff_t *pos)
1974 {
1975         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1976         struct drm_connector *connector = &aconnector->base;
1977         struct drm_device *dev = connector->dev;
1978         struct drm_crtc *crtc = NULL;
1979         struct dm_crtc_state *dm_crtc_state = NULL;
1980         struct pipe_ctx *pipe_ctx;
1981         int i;
1982         char *wr_buf = NULL;
1983         uint32_t wr_buf_size = 42;
1984         int max_param_num = 1;
1985         uint8_t param_nums = 0;
1986         long param[1] = {0};
1987
1988         if (size == 0)
1989                 return -EINVAL;
1990
1991         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1992
1993         if (!wr_buf) {
1994                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1995                 return -ENOSPC;
1996         }
1997
1998         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1999                                             (long *)param, buf,
2000                                             max_param_num,
2001                                             &param_nums)) {
2002                 kfree(wr_buf);
2003                 return -EINVAL;
2004         }
2005
2006         if (param_nums <= 0) {
2007                 DRM_DEBUG_DRIVER("user data not be read\n");
2008                 kfree(wr_buf);
2009                 return -EINVAL;
2010         }
2011
2012         for (i = 0; i < MAX_PIPES; i++) {
2013                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2014                         if (pipe_ctx && pipe_ctx->stream &&
2015                             pipe_ctx->stream->link == aconnector->dc_link)
2016                                 break;
2017         }
2018
2019         if (!pipe_ctx || !pipe_ctx->stream)
2020                 goto done;
2021
2022         // Get CRTC state
2023         mutex_lock(&dev->mode_config.mutex);
2024         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2025
2026         if (connector->state == NULL)
2027                 goto unlock;
2028
2029         crtc = connector->state->crtc;
2030         if (crtc == NULL)
2031                 goto unlock;
2032
2033         drm_modeset_lock(&crtc->mutex, NULL);
2034         if (crtc->state == NULL)
2035                 goto unlock;
2036
2037         dm_crtc_state = to_dm_crtc_state(crtc->state);
2038         if (dm_crtc_state->stream == NULL)
2039                 goto unlock;
2040
2041         aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
2042
2043         dm_crtc_state->dsc_force_changed = true;
2044
2045 unlock:
2046         if (crtc)
2047                 drm_modeset_unlock(&crtc->mutex);
2048         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2049         mutex_unlock(&dev->mode_config.mutex);
2050
2051 done:
2052         kfree(wr_buf);
2053         return size;
2054 }
2055
2056 /* function: read DSC picture width parameter on the connector
2057  *
2058  * The read function: dp_dsc_pic_width_read
2059  * returns dsc picture width used in the current configuration
2060  * It is the same as h_addressable of the current
2061  * display's timing
2062  * The return is an integer: 0 or other positive integer
2063  * If 0 then DSC is disabled.
2064  *
2065  * Access it with the following command:
2066  *
2067  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width
2068  *
2069  * 0 - means that DSC is disabled
2070  */
2071 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
2072                                     size_t size, loff_t *pos)
2073 {
2074         char *rd_buf = NULL;
2075         char *rd_buf_ptr = NULL;
2076         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2077         struct display_stream_compressor *dsc;
2078         struct dcn_dsc_state dsc_state = {0};
2079         const uint32_t rd_buf_size = 100;
2080         struct pipe_ctx *pipe_ctx;
2081         ssize_t result = 0;
2082         int i, r, str_len = 30;
2083
2084         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2085
2086         if (!rd_buf)
2087                 return -ENOMEM;
2088
2089         rd_buf_ptr = rd_buf;
2090
2091         for (i = 0; i < MAX_PIPES; i++) {
2092                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2093                         if (pipe_ctx && pipe_ctx->stream &&
2094                             pipe_ctx->stream->link == aconnector->dc_link)
2095                                 break;
2096         }
2097
2098         if (!pipe_ctx) {
2099                 kfree(rd_buf);
2100                 return -ENXIO;
2101         }
2102
2103         dsc = pipe_ctx->stream_res.dsc;
2104         if (dsc)
2105                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2106
2107         snprintf(rd_buf_ptr, str_len,
2108                 "%d\n",
2109                 dsc_state.dsc_pic_width);
2110         rd_buf_ptr += str_len;
2111
2112         while (size) {
2113                 if (*pos >= rd_buf_size)
2114                         break;
2115
2116                 r = put_user(*(rd_buf + result), buf);
2117                 if (r) {
2118                         kfree(rd_buf);
2119                         return r; /* r = -EFAULT */
2120                 }
2121
2122                 buf += 1;
2123                 size -= 1;
2124                 *pos += 1;
2125                 result += 1;
2126         }
2127
2128         kfree(rd_buf);
2129         return result;
2130 }
2131
2132 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
2133                                     size_t size, loff_t *pos)
2134 {
2135         char *rd_buf = NULL;
2136         char *rd_buf_ptr = NULL;
2137         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2138         struct display_stream_compressor *dsc;
2139         struct dcn_dsc_state dsc_state = {0};
2140         const uint32_t rd_buf_size = 100;
2141         struct pipe_ctx *pipe_ctx;
2142         ssize_t result = 0;
2143         int i, r, str_len = 30;
2144
2145         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2146
2147         if (!rd_buf)
2148                 return -ENOMEM;
2149
2150         rd_buf_ptr = rd_buf;
2151
2152         for (i = 0; i < MAX_PIPES; i++) {
2153                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2154                         if (pipe_ctx && pipe_ctx->stream &&
2155                             pipe_ctx->stream->link == aconnector->dc_link)
2156                                 break;
2157         }
2158
2159         if (!pipe_ctx) {
2160                 kfree(rd_buf);
2161                 return -ENXIO;
2162         }
2163
2164         dsc = pipe_ctx->stream_res.dsc;
2165         if (dsc)
2166                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2167
2168         snprintf(rd_buf_ptr, str_len,
2169                 "%d\n",
2170                 dsc_state.dsc_pic_height);
2171         rd_buf_ptr += str_len;
2172
2173         while (size) {
2174                 if (*pos >= rd_buf_size)
2175                         break;
2176
2177                 r = put_user(*(rd_buf + result), buf);
2178                 if (r) {
2179                         kfree(rd_buf);
2180                         return r; /* r = -EFAULT */
2181                 }
2182
2183                 buf += 1;
2184                 size -= 1;
2185                 *pos += 1;
2186                 result += 1;
2187         }
2188
2189         kfree(rd_buf);
2190         return result;
2191 }
2192
2193 /* function: read DSC chunk size parameter on the connector
2194  *
2195  * The read function: dp_dsc_chunk_size_read
2196  * returns dsc chunk size set in the current configuration
2197  * The value is calculated automatically by DSC code
2198  * and depends on slice parameters and bpp target rate
2199  * The return is an integer: 0 or other positive integer
2200  * If 0 then DSC is disabled.
2201  *
2202  * Access it with the following command:
2203  *
2204  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size
2205  *
2206  * 0 - means that DSC is disabled
2207  */
2208 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
2209                                     size_t size, loff_t *pos)
2210 {
2211         char *rd_buf = NULL;
2212         char *rd_buf_ptr = NULL;
2213         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2214         struct display_stream_compressor *dsc;
2215         struct dcn_dsc_state dsc_state = {0};
2216         const uint32_t rd_buf_size = 100;
2217         struct pipe_ctx *pipe_ctx;
2218         ssize_t result = 0;
2219         int i, r, str_len = 30;
2220
2221         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2222
2223         if (!rd_buf)
2224                 return -ENOMEM;
2225
2226         rd_buf_ptr = rd_buf;
2227
2228         for (i = 0; i < MAX_PIPES; i++) {
2229                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2230                         if (pipe_ctx && pipe_ctx->stream &&
2231                             pipe_ctx->stream->link == aconnector->dc_link)
2232                                 break;
2233         }
2234
2235         if (!pipe_ctx) {
2236                 kfree(rd_buf);
2237                 return -ENXIO;
2238         }
2239
2240         dsc = pipe_ctx->stream_res.dsc;
2241         if (dsc)
2242                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2243
2244         snprintf(rd_buf_ptr, str_len,
2245                 "%d\n",
2246                 dsc_state.dsc_chunk_size);
2247         rd_buf_ptr += str_len;
2248
2249         while (size) {
2250                 if (*pos >= rd_buf_size)
2251                         break;
2252
2253                 r = put_user(*(rd_buf + result), buf);
2254                 if (r) {
2255                         kfree(rd_buf);
2256                         return r; /* r = -EFAULT */
2257                 }
2258
2259                 buf += 1;
2260                 size -= 1;
2261                 *pos += 1;
2262                 result += 1;
2263         }
2264
2265         kfree(rd_buf);
2266         return result;
2267 }
2268
2269 /* function: read DSC slice bpg offset on the connector
2270  *
2271  * The read function: dp_dsc_slice_bpg_offset_read
2272  * returns dsc bpg slice offset set in the current configuration
2273  * The value is calculated automatically by DSC code
2274  * and depends on slice parameters and bpp target rate
2275  * The return is an integer: 0 or other positive integer
2276  * If 0 then DSC is disabled.
2277  *
2278  * Access it with the following command:
2279  *
2280  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset
2281  *
2282  * 0 - means that DSC is disabled
2283  */
2284 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
2285                                     size_t size, loff_t *pos)
2286 {
2287         char *rd_buf = NULL;
2288         char *rd_buf_ptr = NULL;
2289         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2290         struct display_stream_compressor *dsc;
2291         struct dcn_dsc_state dsc_state = {0};
2292         const uint32_t rd_buf_size = 100;
2293         struct pipe_ctx *pipe_ctx;
2294         ssize_t result = 0;
2295         int i, r, str_len = 30;
2296
2297         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2298
2299         if (!rd_buf)
2300                 return -ENOMEM;
2301
2302         rd_buf_ptr = rd_buf;
2303
2304         for (i = 0; i < MAX_PIPES; i++) {
2305                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2306                         if (pipe_ctx && pipe_ctx->stream &&
2307                             pipe_ctx->stream->link == aconnector->dc_link)
2308                                 break;
2309         }
2310
2311         if (!pipe_ctx) {
2312                 kfree(rd_buf);
2313                 return -ENXIO;
2314         }
2315
2316         dsc = pipe_ctx->stream_res.dsc;
2317         if (dsc)
2318                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2319
2320         snprintf(rd_buf_ptr, str_len,
2321                 "%d\n",
2322                 dsc_state.dsc_slice_bpg_offset);
2323         rd_buf_ptr += str_len;
2324
2325         while (size) {
2326                 if (*pos >= rd_buf_size)
2327                         break;
2328
2329                 r = put_user(*(rd_buf + result), buf);
2330                 if (r) {
2331                         kfree(rd_buf);
2332                         return r; /* r = -EFAULT */
2333                 }
2334
2335                 buf += 1;
2336                 size -= 1;
2337                 *pos += 1;
2338                 result += 1;
2339         }
2340
2341         kfree(rd_buf);
2342         return result;
2343 }
2344
2345
2346 /*
2347  * function description: Read max_requested_bpc property from the connector
2348  *
2349  * Access it with the following command:
2350  *
2351  *      cat /sys/kernel/debug/dri/0/DP-X/max_bpc
2352  *
2353  */
2354 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf,
2355                 size_t size, loff_t *pos)
2356 {
2357         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2358         struct drm_connector *connector = &aconnector->base;
2359         struct drm_device *dev = connector->dev;
2360         struct dm_connector_state *state;
2361         ssize_t result = 0;
2362         char *rd_buf = NULL;
2363         char *rd_buf_ptr = NULL;
2364         const uint32_t rd_buf_size = 10;
2365         int r;
2366
2367         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2368
2369         if (!rd_buf)
2370                 return -ENOMEM;
2371
2372         mutex_lock(&dev->mode_config.mutex);
2373         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2374
2375         if (connector->state == NULL)
2376                 goto unlock;
2377
2378         state = to_dm_connector_state(connector->state);
2379
2380         rd_buf_ptr = rd_buf;
2381         snprintf(rd_buf_ptr, rd_buf_size,
2382                 "%u\n",
2383                 state->base.max_requested_bpc);
2384
2385         while (size) {
2386                 if (*pos >= rd_buf_size)
2387                         break;
2388
2389                 r = put_user(*(rd_buf + result), buf);
2390                 if (r) {
2391                         result = r; /* r = -EFAULT */
2392                         goto unlock;
2393                 }
2394                 buf += 1;
2395                 size -= 1;
2396                 *pos += 1;
2397                 result += 1;
2398         }
2399 unlock:
2400         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2401         mutex_unlock(&dev->mode_config.mutex);
2402         kfree(rd_buf);
2403         return result;
2404 }
2405
2406
2407 /*
2408  * function description: Set max_requested_bpc property on the connector
2409  *
2410  * This function will not force the input BPC on connector, it will only
2411  * change the max value. This is equivalent to setting max_bpc through
2412  * xrandr.
2413  *
2414  * The BPC value written must be >= 6 and <= 16. Values outside of this
2415  * range will result in errors.
2416  *
2417  * BPC values:
2418  *      0x6 - 6 BPC
2419  *      0x8 - 8 BPC
2420  *      0xa - 10 BPC
2421  *      0xc - 12 BPC
2422  *      0x10 - 16 BPC
2423  *
2424  * Write the max_bpc in the following way:
2425  *
2426  * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc
2427  *
2428  */
2429 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf,
2430                                      size_t size, loff_t *pos)
2431 {
2432         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2433         struct drm_connector *connector = &aconnector->base;
2434         struct dm_connector_state *state;
2435         struct drm_device *dev = connector->dev;
2436         char *wr_buf = NULL;
2437         uint32_t wr_buf_size = 42;
2438         int max_param_num = 1;
2439         long param[1] = {0};
2440         uint8_t param_nums = 0;
2441
2442         if (size == 0)
2443                 return -EINVAL;
2444
2445         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2446
2447         if (!wr_buf) {
2448                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2449                 return -ENOSPC;
2450         }
2451
2452         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2453                                            (long *)param, buf,
2454                                            max_param_num,
2455                                            &param_nums)) {
2456                 kfree(wr_buf);
2457                 return -EINVAL;
2458         }
2459
2460         if (param_nums <= 0) {
2461                 DRM_DEBUG_DRIVER("user data not be read\n");
2462                 kfree(wr_buf);
2463                 return -EINVAL;
2464         }
2465
2466         if (param[0] < 6 || param[0] > 16) {
2467                 DRM_DEBUG_DRIVER("bad max_bpc value\n");
2468                 kfree(wr_buf);
2469                 return -EINVAL;
2470         }
2471
2472         mutex_lock(&dev->mode_config.mutex);
2473         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2474
2475         if (connector->state == NULL)
2476                 goto unlock;
2477
2478         state = to_dm_connector_state(connector->state);
2479         state->base.max_requested_bpc = param[0];
2480 unlock:
2481         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2482         mutex_unlock(&dev->mode_config.mutex);
2483
2484         kfree(wr_buf);
2485         return size;
2486 }
2487
2488 /*
2489  * Backlight at this moment.  Read only.
2490  * As written to display, taking ABM and backlight lut into account.
2491  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2492  *
2493  * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight
2494  */
2495 static int current_backlight_show(struct seq_file *m, void *unused)
2496 {
2497         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2498         struct dc_link *link = aconnector->dc_link;
2499         unsigned int backlight;
2500
2501         backlight = dc_link_get_backlight_level(link);
2502         seq_printf(m, "0x%x\n", backlight);
2503
2504         return 0;
2505 }
2506
2507 /*
2508  * Backlight value that is being approached.  Read only.
2509  * As written to display, taking ABM and backlight lut into account.
2510  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2511  *
2512  * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight
2513  */
2514 static int target_backlight_show(struct seq_file *m, void *unused)
2515 {
2516         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2517         struct dc_link *link = aconnector->dc_link;
2518         unsigned int backlight;
2519
2520         backlight = dc_link_get_target_backlight_pwm(link);
2521         seq_printf(m, "0x%x\n", backlight);
2522
2523         return 0;
2524 }
2525
2526 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
2527 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
2528 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
2529 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
2530 #ifdef CONFIG_DRM_AMD_DC_HDCP
2531 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
2532 #endif
2533 DEFINE_SHOW_ATTRIBUTE(internal_display);
2534 DEFINE_SHOW_ATTRIBUTE(psr_capability);
2535
2536 static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
2537         .owner = THIS_MODULE,
2538         .read = dp_dsc_clock_en_read,
2539         .write = dp_dsc_clock_en_write,
2540         .llseek = default_llseek
2541 };
2542
2543 static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
2544         .owner = THIS_MODULE,
2545         .read = dp_dsc_slice_width_read,
2546         .write = dp_dsc_slice_width_write,
2547         .llseek = default_llseek
2548 };
2549
2550 static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
2551         .owner = THIS_MODULE,
2552         .read = dp_dsc_slice_height_read,
2553         .write = dp_dsc_slice_height_write,
2554         .llseek = default_llseek
2555 };
2556
2557 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = {
2558         .owner = THIS_MODULE,
2559         .read = dp_dsc_bits_per_pixel_read,
2560         .write = dp_dsc_bits_per_pixel_write,
2561         .llseek = default_llseek
2562 };
2563
2564 static const struct file_operations dp_dsc_pic_width_debugfs_fops = {
2565         .owner = THIS_MODULE,
2566         .read = dp_dsc_pic_width_read,
2567         .llseek = default_llseek
2568 };
2569
2570 static const struct file_operations dp_dsc_pic_height_debugfs_fops = {
2571         .owner = THIS_MODULE,
2572         .read = dp_dsc_pic_height_read,
2573         .llseek = default_llseek
2574 };
2575
2576 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = {
2577         .owner = THIS_MODULE,
2578         .read = dp_dsc_chunk_size_read,
2579         .llseek = default_llseek
2580 };
2581
2582 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = {
2583         .owner = THIS_MODULE,
2584         .read = dp_dsc_slice_bpg_offset_read,
2585         .llseek = default_llseek
2586 };
2587
2588 static const struct file_operations trigger_hotplug_debugfs_fops = {
2589         .owner = THIS_MODULE,
2590         .write = trigger_hotplug,
2591         .llseek = default_llseek
2592 };
2593
2594 static const struct file_operations dp_link_settings_debugfs_fops = {
2595         .owner = THIS_MODULE,
2596         .read = dp_link_settings_read,
2597         .write = dp_link_settings_write,
2598         .llseek = default_llseek
2599 };
2600
2601 static const struct file_operations dp_phy_settings_debugfs_fop = {
2602         .owner = THIS_MODULE,
2603         .read = dp_phy_settings_read,
2604         .write = dp_phy_settings_write,
2605         .llseek = default_llseek
2606 };
2607
2608 static const struct file_operations dp_phy_test_pattern_fops = {
2609         .owner = THIS_MODULE,
2610         .write = dp_phy_test_pattern_debugfs_write,
2611         .llseek = default_llseek
2612 };
2613
2614 static const struct file_operations sdp_message_fops = {
2615         .owner = THIS_MODULE,
2616         .write = dp_sdp_message_debugfs_write,
2617         .llseek = default_llseek
2618 };
2619
2620 static const struct file_operations dp_dpcd_address_debugfs_fops = {
2621         .owner = THIS_MODULE,
2622         .write = dp_dpcd_address_write,
2623         .llseek = default_llseek
2624 };
2625
2626 static const struct file_operations dp_dpcd_size_debugfs_fops = {
2627         .owner = THIS_MODULE,
2628         .write = dp_dpcd_size_write,
2629         .llseek = default_llseek
2630 };
2631
2632 static const struct file_operations dp_dpcd_data_debugfs_fops = {
2633         .owner = THIS_MODULE,
2634         .read = dp_dpcd_data_read,
2635         .write = dp_dpcd_data_write,
2636         .llseek = default_llseek
2637 };
2638
2639 static const struct file_operations dp_max_bpc_debugfs_fops = {
2640         .owner = THIS_MODULE,
2641         .read = dp_max_bpc_read,
2642         .write = dp_max_bpc_write,
2643         .llseek = default_llseek
2644 };
2645
2646 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = {
2647         .owner = THIS_MODULE,
2648         .write = dp_dsc_passthrough_set,
2649         .llseek = default_llseek
2650 };
2651
2652 static const struct {
2653         char *name;
2654         const struct file_operations *fops;
2655 } dp_debugfs_entries[] = {
2656                 {"link_settings", &dp_link_settings_debugfs_fops},
2657                 {"phy_settings", &dp_phy_settings_debugfs_fop},
2658                 {"lttpr_status", &dp_lttpr_status_fops},
2659                 {"test_pattern", &dp_phy_test_pattern_fops},
2660 #ifdef CONFIG_DRM_AMD_DC_HDCP
2661                 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
2662 #endif
2663                 {"sdp_message", &sdp_message_fops},
2664                 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops},
2665                 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops},
2666                 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops},
2667                 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops},
2668                 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops},
2669                 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops},
2670                 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops},
2671                 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops},
2672                 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops},
2673                 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
2674                 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
2675                 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
2676                 {"max_bpc", &dp_max_bpc_debugfs_fops},
2677                 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops},
2678 };
2679
2680 #ifdef CONFIG_DRM_AMD_DC_HDCP
2681 static const struct {
2682         char *name;
2683         const struct file_operations *fops;
2684 } hdmi_debugfs_entries[] = {
2685                 {"hdcp_sink_capability", &hdcp_sink_capability_fops}
2686 };
2687 #endif
2688 /*
2689  * Force YUV420 output if available from the given mode
2690  */
2691 static int force_yuv420_output_set(void *data, u64 val)
2692 {
2693         struct amdgpu_dm_connector *connector = data;
2694
2695         connector->force_yuv420_output = (bool)val;
2696
2697         return 0;
2698 }
2699
2700 /*
2701  * Check if YUV420 is forced when available from the given mode
2702  */
2703 static int force_yuv420_output_get(void *data, u64 *val)
2704 {
2705         struct amdgpu_dm_connector *connector = data;
2706
2707         *val = connector->force_yuv420_output;
2708
2709         return 0;
2710 }
2711
2712 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
2713                          force_yuv420_output_set, "%llu\n");
2714
2715 /*
2716  *  Read PSR state
2717  */
2718 static int psr_get(void *data, u64 *val)
2719 {
2720         struct amdgpu_dm_connector *connector = data;
2721         struct dc_link *link = connector->dc_link;
2722         enum dc_psr_state state = PSR_STATE0;
2723
2724         dc_link_get_psr_state(link, &state);
2725
2726         *val = state;
2727
2728         return 0;
2729 }
2730
2731 /*
2732  * Set dmcub trace event IRQ enable or disable.
2733  * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2734  * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2735  */
2736 static int dmcub_trace_event_state_set(void *data, u64 val)
2737 {
2738         struct amdgpu_device *adev = data;
2739
2740         if (val == 1 || val == 0) {
2741                 dc_dmub_trace_event_control(adev->dm.dc, val);
2742                 adev->dm.dmcub_trace_event_en = (bool)val;
2743         } else
2744                 return 0;
2745
2746         return 0;
2747 }
2748
2749 /*
2750  * The interface doesn't need get function, so it will return the
2751  * value of zero
2752  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2753  */
2754 static int dmcub_trace_event_state_get(void *data, u64 *val)
2755 {
2756         struct amdgpu_device *adev = data;
2757
2758         *val = adev->dm.dmcub_trace_event_en;
2759         return 0;
2760 }
2761
2762 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get,
2763                          dmcub_trace_event_state_set, "%llu\n");
2764
2765 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
2766
2767 DEFINE_SHOW_ATTRIBUTE(current_backlight);
2768 DEFINE_SHOW_ATTRIBUTE(target_backlight);
2769
2770 static const struct {
2771         char *name;
2772         const struct file_operations *fops;
2773 } connector_debugfs_entries[] = {
2774                 {"force_yuv420_output", &force_yuv420_output_fops},
2775                 {"trigger_hotplug", &trigger_hotplug_debugfs_fops},
2776                 {"internal_display", &internal_display_fops}
2777 };
2778
2779 /*
2780  * Returns supported customized link rates by this eDP panel.
2781  * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting
2782  */
2783 static int edp_ilr_show(struct seq_file *m, void *unused)
2784 {
2785         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2786         struct dc_link *link = aconnector->dc_link;
2787         uint8_t supported_link_rates[16];
2788         uint32_t link_rate_in_khz;
2789         uint32_t entry = 0;
2790         uint8_t dpcd_rev;
2791
2792         memset(supported_link_rates, 0, sizeof(supported_link_rates));
2793         dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES,
2794                 supported_link_rates, sizeof(supported_link_rates));
2795
2796         dpcd_rev = link->dpcd_caps.dpcd_rev.raw;
2797
2798         if (dpcd_rev >= DP_DPCD_REV_13 &&
2799                 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) {
2800
2801                 for (entry = 0; entry < 16; entry += 2) {
2802                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
2803                                                                                 supported_link_rates[entry]) * 200;
2804                         seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz);
2805                 }
2806         } else {
2807                 seq_printf(m, "ILR is not supported by this eDP panel.\n");
2808         }
2809
2810         return 0;
2811 }
2812
2813 /*
2814  * Set supported customized link rate to eDP panel.
2815  *
2816  * echo <lane_count>  <link_rate option> > ilr_setting
2817  *
2818  * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ...
2819  * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting
2820  * to set 4 lanes and 2.16 GHz
2821  */
2822 static ssize_t edp_ilr_write(struct file *f, const char __user *buf,
2823                                  size_t size, loff_t *pos)
2824 {
2825         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
2826         struct dc_link *link = connector->dc_link;
2827         struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
2828         struct dc *dc = (struct dc *)link->dc;
2829         struct dc_link_settings prefer_link_settings;
2830         char *wr_buf = NULL;
2831         const uint32_t wr_buf_size = 40;
2832         /* 0: lane_count; 1: link_rate */
2833         int max_param_num = 2;
2834         uint8_t param_nums = 0;
2835         long param[2];
2836         bool valid_input = true;
2837
2838         if (size == 0)
2839                 return -EINVAL;
2840
2841         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2842         if (!wr_buf)
2843                 return -ENOMEM;
2844
2845         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2846                                            (long *)param, buf,
2847                                            max_param_num,
2848                                            &param_nums)) {
2849                 kfree(wr_buf);
2850                 return -EINVAL;
2851         }
2852
2853         if (param_nums <= 0) {
2854                 kfree(wr_buf);
2855                 return -EINVAL;
2856         }
2857
2858         switch (param[0]) {
2859         case LANE_COUNT_ONE:
2860         case LANE_COUNT_TWO:
2861         case LANE_COUNT_FOUR:
2862                 break;
2863         default:
2864                 valid_input = false;
2865                 break;
2866         }
2867
2868         if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count)
2869                 valid_input = false;
2870
2871         if (!valid_input) {
2872                 kfree(wr_buf);
2873                 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n");
2874                 prefer_link_settings.use_link_rate_set = false;
2875                 mutex_lock(&adev->dm.dc_lock);
2876                 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
2877                 mutex_unlock(&adev->dm.dc_lock);
2878                 return size;
2879         }
2880
2881         /* save user force lane_count, link_rate to preferred settings
2882          * spread spectrum will not be changed
2883          */
2884         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
2885         prefer_link_settings.lane_count = param[0];
2886         prefer_link_settings.use_link_rate_set = true;
2887         prefer_link_settings.link_rate_set = param[1];
2888         prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]];
2889
2890         mutex_lock(&adev->dm.dc_lock);
2891         dc_link_set_preferred_training_settings(dc, &prefer_link_settings,
2892                                                 NULL, link, false);
2893         mutex_unlock(&adev->dm.dc_lock);
2894
2895         kfree(wr_buf);
2896         return size;
2897 }
2898
2899 static int edp_ilr_open(struct inode *inode, struct file *file)
2900 {
2901         return single_open(file, edp_ilr_show, inode->i_private);
2902 }
2903
2904 static const struct file_operations edp_ilr_debugfs_fops = {
2905         .owner = THIS_MODULE,
2906         .open = edp_ilr_open,
2907         .read = seq_read,
2908         .llseek = seq_lseek,
2909         .release = single_release,
2910         .write = edp_ilr_write
2911 };
2912
2913 void connector_debugfs_init(struct amdgpu_dm_connector *connector)
2914 {
2915         int i;
2916         struct dentry *dir = connector->base.debugfs_entry;
2917
2918         if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2919             connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
2920                 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
2921                         debugfs_create_file(dp_debugfs_entries[i].name,
2922                                             0644, dir, connector,
2923                                             dp_debugfs_entries[i].fops);
2924                 }
2925         }
2926         if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
2927                 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops);
2928                 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
2929                 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector,
2930                                     &current_backlight_fops);
2931                 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector,
2932                                     &target_backlight_fops);
2933                 debugfs_create_file("ilr_setting", 0644, dir, connector,
2934                                         &edp_ilr_debugfs_fops);
2935         }
2936
2937         for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
2938                 debugfs_create_file(connector_debugfs_entries[i].name,
2939                                     0644, dir, connector,
2940                                     connector_debugfs_entries[i].fops);
2941         }
2942
2943         connector->debugfs_dpcd_address = 0;
2944         connector->debugfs_dpcd_size = 0;
2945
2946 #ifdef CONFIG_DRM_AMD_DC_HDCP
2947         if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
2948                 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) {
2949                         debugfs_create_file(hdmi_debugfs_entries[i].name,
2950                                             0644, dir, connector,
2951                                             hdmi_debugfs_entries[i].fops);
2952                 }
2953         }
2954 #endif
2955 }
2956
2957 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
2958 /*
2959  * Set crc window coordinate x start
2960  */
2961 static int crc_win_x_start_set(void *data, u64 val)
2962 {
2963         struct drm_crtc *crtc = data;
2964         struct drm_device *drm_dev = crtc->dev;
2965         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2966
2967         spin_lock_irq(&drm_dev->event_lock);
2968         acrtc->dm_irq_params.crc_window.x_start = (uint16_t) val;
2969         acrtc->dm_irq_params.crc_window.update_win = false;
2970         spin_unlock_irq(&drm_dev->event_lock);
2971
2972         return 0;
2973 }
2974
2975 /*
2976  * Get crc window coordinate x start
2977  */
2978 static int crc_win_x_start_get(void *data, u64 *val)
2979 {
2980         struct drm_crtc *crtc = data;
2981         struct drm_device *drm_dev = crtc->dev;
2982         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2983
2984         spin_lock_irq(&drm_dev->event_lock);
2985         *val = acrtc->dm_irq_params.crc_window.x_start;
2986         spin_unlock_irq(&drm_dev->event_lock);
2987
2988         return 0;
2989 }
2990
2991 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get,
2992                          crc_win_x_start_set, "%llu\n");
2993
2994
2995 /*
2996  * Set crc window coordinate y start
2997  */
2998 static int crc_win_y_start_set(void *data, u64 val)
2999 {
3000         struct drm_crtc *crtc = data;
3001         struct drm_device *drm_dev = crtc->dev;
3002         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3003
3004         spin_lock_irq(&drm_dev->event_lock);
3005         acrtc->dm_irq_params.crc_window.y_start = (uint16_t) val;
3006         acrtc->dm_irq_params.crc_window.update_win = false;
3007         spin_unlock_irq(&drm_dev->event_lock);
3008
3009         return 0;
3010 }
3011
3012 /*
3013  * Get crc window coordinate y start
3014  */
3015 static int crc_win_y_start_get(void *data, u64 *val)
3016 {
3017         struct drm_crtc *crtc = data;
3018         struct drm_device *drm_dev = crtc->dev;
3019         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3020
3021         spin_lock_irq(&drm_dev->event_lock);
3022         *val = acrtc->dm_irq_params.crc_window.y_start;
3023         spin_unlock_irq(&drm_dev->event_lock);
3024
3025         return 0;
3026 }
3027
3028 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get,
3029                          crc_win_y_start_set, "%llu\n");
3030
3031 /*
3032  * Set crc window coordinate x end
3033  */
3034 static int crc_win_x_end_set(void *data, u64 val)
3035 {
3036         struct drm_crtc *crtc = data;
3037         struct drm_device *drm_dev = crtc->dev;
3038         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3039
3040         spin_lock_irq(&drm_dev->event_lock);
3041         acrtc->dm_irq_params.crc_window.x_end = (uint16_t) val;
3042         acrtc->dm_irq_params.crc_window.update_win = false;
3043         spin_unlock_irq(&drm_dev->event_lock);
3044
3045         return 0;
3046 }
3047
3048 /*
3049  * Get crc window coordinate x end
3050  */
3051 static int crc_win_x_end_get(void *data, u64 *val)
3052 {
3053         struct drm_crtc *crtc = data;
3054         struct drm_device *drm_dev = crtc->dev;
3055         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3056
3057         spin_lock_irq(&drm_dev->event_lock);
3058         *val = acrtc->dm_irq_params.crc_window.x_end;
3059         spin_unlock_irq(&drm_dev->event_lock);
3060
3061         return 0;
3062 }
3063
3064 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get,
3065                          crc_win_x_end_set, "%llu\n");
3066
3067 /*
3068  * Set crc window coordinate y end
3069  */
3070 static int crc_win_y_end_set(void *data, u64 val)
3071 {
3072         struct drm_crtc *crtc = data;
3073         struct drm_device *drm_dev = crtc->dev;
3074         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3075
3076         spin_lock_irq(&drm_dev->event_lock);
3077         acrtc->dm_irq_params.crc_window.y_end = (uint16_t) val;
3078         acrtc->dm_irq_params.crc_window.update_win = false;
3079         spin_unlock_irq(&drm_dev->event_lock);
3080
3081         return 0;
3082 }
3083
3084 /*
3085  * Get crc window coordinate y end
3086  */
3087 static int crc_win_y_end_get(void *data, u64 *val)
3088 {
3089         struct drm_crtc *crtc = data;
3090         struct drm_device *drm_dev = crtc->dev;
3091         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3092
3093         spin_lock_irq(&drm_dev->event_lock);
3094         *val = acrtc->dm_irq_params.crc_window.y_end;
3095         spin_unlock_irq(&drm_dev->event_lock);
3096
3097         return 0;
3098 }
3099
3100 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get,
3101                          crc_win_y_end_set, "%llu\n");
3102 /*
3103  * Trigger to commit crc window
3104  */
3105 static int crc_win_update_set(void *data, u64 val)
3106 {
3107         struct drm_crtc *new_crtc = data;
3108         struct drm_crtc *old_crtc = NULL;
3109         struct amdgpu_crtc *new_acrtc, *old_acrtc;
3110         struct amdgpu_device *adev = drm_to_adev(new_crtc->dev);
3111         struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk;
3112
3113         if (!crc_rd_wrk)
3114                 return 0;
3115
3116         if (val) {
3117                 spin_lock_irq(&adev_to_drm(adev)->event_lock);
3118                 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);
3119                 if (crc_rd_wrk->crtc) {
3120                         old_crtc = crc_rd_wrk->crtc;
3121                         old_acrtc = to_amdgpu_crtc(old_crtc);
3122                 }
3123                 new_acrtc = to_amdgpu_crtc(new_crtc);
3124
3125                 if (old_crtc && old_crtc != new_crtc) {
3126                         old_acrtc->dm_irq_params.crc_window.activated = false;
3127                         old_acrtc->dm_irq_params.crc_window.update_win = false;
3128                         old_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
3129
3130                         new_acrtc->dm_irq_params.crc_window.activated = true;
3131                         new_acrtc->dm_irq_params.crc_window.update_win = true;
3132                         new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
3133                         crc_rd_wrk->crtc = new_crtc;
3134                 } else {
3135                         new_acrtc->dm_irq_params.crc_window.activated = true;
3136                         new_acrtc->dm_irq_params.crc_window.update_win = true;
3137                         new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
3138                         crc_rd_wrk->crtc = new_crtc;
3139                 }
3140                 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
3141                 spin_unlock_irq(&adev_to_drm(adev)->event_lock);
3142         }
3143
3144         return 0;
3145 }
3146
3147 /*
3148  * Get crc window update flag
3149  */
3150 static int crc_win_update_get(void *data, u64 *val)
3151 {
3152         *val = 0;
3153         return 0;
3154 }
3155
3156 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get,
3157                          crc_win_update_set, "%llu\n");
3158 #endif
3159 void crtc_debugfs_init(struct drm_crtc *crtc)
3160 {
3161 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3162         struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry);
3163
3164         if (!dir)
3165                 return;
3166
3167         debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc,
3168                                    &crc_win_x_start_fops);
3169         debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc,
3170                                    &crc_win_y_start_fops);
3171         debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc,
3172                                    &crc_win_x_end_fops);
3173         debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc,
3174                                    &crc_win_y_end_fops);
3175         debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc,
3176                                    &crc_win_update_fops);
3177 #endif
3178         debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry,
3179                             crtc, &amdgpu_current_bpc_fops);
3180 }
3181
3182 /*
3183  * Writes DTN log state to the user supplied buffer.
3184  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3185  */
3186 static ssize_t dtn_log_read(
3187         struct file *f,
3188         char __user *buf,
3189         size_t size,
3190         loff_t *pos)
3191 {
3192         struct amdgpu_device *adev = file_inode(f)->i_private;
3193         struct dc *dc = adev->dm.dc;
3194         struct dc_log_buffer_ctx log_ctx = { 0 };
3195         ssize_t result = 0;
3196
3197         if (!buf || !size)
3198                 return -EINVAL;
3199
3200         if (!dc->hwss.log_hw_state)
3201                 return 0;
3202
3203         dc->hwss.log_hw_state(dc, &log_ctx);
3204
3205         if (*pos < log_ctx.pos) {
3206                 size_t to_copy = log_ctx.pos - *pos;
3207
3208                 to_copy = min(to_copy, size);
3209
3210                 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) {
3211                         *pos += to_copy;
3212                         result = to_copy;
3213                 }
3214         }
3215
3216         kfree(log_ctx.buf);
3217
3218         return result;
3219 }
3220
3221 /*
3222  * Writes DTN log state to dmesg when triggered via a write.
3223  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3224  */
3225 static ssize_t dtn_log_write(
3226         struct file *f,
3227         const char __user *buf,
3228         size_t size,
3229         loff_t *pos)
3230 {
3231         struct amdgpu_device *adev = file_inode(f)->i_private;
3232         struct dc *dc = adev->dm.dc;
3233
3234         /* Write triggers log output via dmesg. */
3235         if (size == 0)
3236                 return 0;
3237
3238         if (dc->hwss.log_hw_state)
3239                 dc->hwss.log_hw_state(dc, NULL);
3240
3241         return size;
3242 }
3243
3244 static int mst_topo_show(struct seq_file *m, void *unused)
3245 {
3246         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3247         struct drm_device *dev = adev_to_drm(adev);
3248         struct drm_connector *connector;
3249         struct drm_connector_list_iter conn_iter;
3250         struct amdgpu_dm_connector *aconnector;
3251
3252         drm_connector_list_iter_begin(dev, &conn_iter);
3253         drm_for_each_connector_iter(connector, &conn_iter) {
3254                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3255                         continue;
3256
3257                 aconnector = to_amdgpu_dm_connector(connector);
3258
3259                 /* Ensure we're only dumping the topology of a root mst node */
3260                 if (!aconnector->mst_mgr.mst_state)
3261                         continue;
3262
3263                 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
3264                 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
3265         }
3266         drm_connector_list_iter_end(&conn_iter);
3267
3268         return 0;
3269 }
3270
3271 /*
3272  * Sets trigger hpd for MST topologies.
3273  * All connected connectors will be rediscovered and re started as needed if val of 1 is sent.
3274  * All topologies will be disconnected if val of 0 is set .
3275  * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3276  * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3277  */
3278 static int trigger_hpd_mst_set(void *data, u64 val)
3279 {
3280         struct amdgpu_device *adev = data;
3281         struct drm_device *dev = adev_to_drm(adev);
3282         struct drm_connector_list_iter iter;
3283         struct amdgpu_dm_connector *aconnector;
3284         struct drm_connector *connector;
3285         struct dc_link *link = NULL;
3286
3287         if (val == 1) {
3288                 drm_connector_list_iter_begin(dev, &iter);
3289                 drm_for_each_connector_iter(connector, &iter) {
3290                         aconnector = to_amdgpu_dm_connector(connector);
3291                         if (aconnector->dc_link->type == dc_connection_mst_branch &&
3292                             aconnector->mst_mgr.aux) {
3293                                 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3294                                 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
3295                         }
3296                 }
3297         } else if (val == 0) {
3298                 drm_connector_list_iter_begin(dev, &iter);
3299                 drm_for_each_connector_iter(connector, &iter) {
3300                         aconnector = to_amdgpu_dm_connector(connector);
3301                         if (!aconnector->dc_link)
3302                                 continue;
3303
3304                         if (!aconnector->mst_port)
3305                                 continue;
3306
3307                         link = aconnector->dc_link;
3308                         dp_receiver_power_ctrl(link, false);
3309                         drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_port->mst_mgr, false);
3310                         link->mst_stream_alloc_table.stream_count = 0;
3311                         memset(link->mst_stream_alloc_table.stream_allocations, 0,
3312                                         sizeof(link->mst_stream_alloc_table.stream_allocations));
3313                 }
3314         } else {
3315                 return 0;
3316         }
3317         drm_kms_helper_hotplug_event(dev);
3318
3319         return 0;
3320 }
3321
3322 /*
3323  * The interface doesn't need get function, so it will return the
3324  * value of zero
3325  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3326  */
3327 static int trigger_hpd_mst_get(void *data, u64 *val)
3328 {
3329         *val = 0;
3330         return 0;
3331 }
3332
3333 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get,
3334                          trigger_hpd_mst_set, "%llu\n");
3335
3336
3337 /*
3338  * Sets the force_timing_sync debug option from the given string.
3339  * All connected displays will be force synchronized immediately.
3340  * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3341  */
3342 static int force_timing_sync_set(void *data, u64 val)
3343 {
3344         struct amdgpu_device *adev = data;
3345
3346         adev->dm.force_timing_sync = (bool)val;
3347
3348         amdgpu_dm_trigger_timing_sync(adev_to_drm(adev));
3349
3350         return 0;
3351 }
3352
3353 /*
3354  * Gets the force_timing_sync debug option value into the given buffer.
3355  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3356  */
3357 static int force_timing_sync_get(void *data, u64 *val)
3358 {
3359         struct amdgpu_device *adev = data;
3360
3361         *val = adev->dm.force_timing_sync;
3362
3363         return 0;
3364 }
3365
3366 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get,
3367                          force_timing_sync_set, "%llu\n");
3368
3369
3370 /*
3371  * Disables all HPD and HPD RX interrupt handling in the
3372  * driver when set to 1. Default is 0.
3373  */
3374 static int disable_hpd_set(void *data, u64 val)
3375 {
3376         struct amdgpu_device *adev = data;
3377
3378         adev->dm.disable_hpd_irq = (bool)val;
3379
3380         return 0;
3381 }
3382
3383
3384 /*
3385  * Returns 1 if HPD and HPRX interrupt handling is disabled,
3386  * 0 otherwise.
3387  */
3388 static int disable_hpd_get(void *data, u64 *val)
3389 {
3390         struct amdgpu_device *adev = data;
3391
3392         *val = adev->dm.disable_hpd_irq;
3393
3394         return 0;
3395 }
3396
3397 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
3398                          disable_hpd_set, "%llu\n");
3399
3400 /*
3401  * Temporary w/a to force sst sequence in M42D DP2 mst receiver
3402  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst
3403  */
3404 static int dp_force_sst_set(void *data, u64 val)
3405 {
3406         struct amdgpu_device *adev = data;
3407
3408         adev->dm.dc->debug.set_mst_en_for_sst = val;
3409
3410         return 0;
3411 }
3412
3413 static int dp_force_sst_get(void *data, u64 *val)
3414 {
3415         struct amdgpu_device *adev = data;
3416
3417         *val = adev->dm.dc->debug.set_mst_en_for_sst;
3418
3419         return 0;
3420 }
3421 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get,
3422                          dp_force_sst_set, "%llu\n");
3423
3424 /*
3425  * Force DP2 sequence without VESA certified cable.
3426  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id
3427  */
3428 static int dp_ignore_cable_id_set(void *data, u64 val)
3429 {
3430         struct amdgpu_device *adev = data;
3431
3432         adev->dm.dc->debug.ignore_cable_id = val;
3433
3434         return 0;
3435 }
3436
3437 static int dp_ignore_cable_id_get(void *data, u64 *val)
3438 {
3439         struct amdgpu_device *adev = data;
3440
3441         *val = adev->dm.dc->debug.ignore_cable_id;
3442
3443         return 0;
3444 }
3445 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get,
3446                          dp_ignore_cable_id_set, "%llu\n");
3447
3448 /*
3449  * Sets the DC visual confirm debug option from the given string.
3450  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm
3451  */
3452 static int visual_confirm_set(void *data, u64 val)
3453 {
3454         struct amdgpu_device *adev = data;
3455
3456         adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
3457
3458         return 0;
3459 }
3460
3461 /*
3462  * Reads the DC visual confirm debug option value into the given buffer.
3463  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
3464  */
3465 static int visual_confirm_get(void *data, u64 *val)
3466 {
3467         struct amdgpu_device *adev = data;
3468
3469         *val = adev->dm.dc->debug.visual_confirm;
3470
3471         return 0;
3472 }
3473
3474 DEFINE_SHOW_ATTRIBUTE(mst_topo);
3475 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
3476                          visual_confirm_set, "%llu\n");
3477
3478
3479 /*
3480  * Sets the DC skip_detection_link_training debug option from the given string.
3481  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training
3482  */
3483 static int skip_detection_link_training_set(void *data, u64 val)
3484 {
3485         struct amdgpu_device *adev = data;
3486
3487         if (val == 0)
3488                 adev->dm.dc->debug.skip_detection_link_training = false;
3489         else
3490                 adev->dm.dc->debug.skip_detection_link_training = true;
3491
3492         return 0;
3493 }
3494
3495 /*
3496  * Reads the DC skip_detection_link_training debug option value into the given buffer.
3497  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training
3498  */
3499 static int skip_detection_link_training_get(void *data, u64 *val)
3500 {
3501         struct amdgpu_device *adev = data;
3502
3503         *val = adev->dm.dc->debug.skip_detection_link_training;
3504
3505         return 0;
3506 }
3507
3508 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops,
3509                          skip_detection_link_training_get,
3510                          skip_detection_link_training_set, "%llu\n");
3511
3512 /*
3513  * Dumps the DCC_EN bit for each pipe.
3514  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
3515  */
3516 static ssize_t dcc_en_bits_read(
3517         struct file *f,
3518         char __user *buf,
3519         size_t size,
3520         loff_t *pos)
3521 {
3522         struct amdgpu_device *adev = file_inode(f)->i_private;
3523         struct dc *dc = adev->dm.dc;
3524         char *rd_buf = NULL;
3525         const uint32_t rd_buf_size = 32;
3526         uint32_t result = 0;
3527         int offset = 0;
3528         int num_pipes = dc->res_pool->pipe_count;
3529         int *dcc_en_bits;
3530         int i, r;
3531
3532         dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL);
3533         if (!dcc_en_bits)
3534                 return -ENOMEM;
3535
3536         if (!dc->hwss.get_dcc_en_bits) {
3537                 kfree(dcc_en_bits);
3538                 return 0;
3539         }
3540
3541         dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
3542
3543         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
3544         if (!rd_buf) {
3545                 kfree(dcc_en_bits);
3546                 return -ENOMEM;
3547         }
3548
3549         for (i = 0; i < num_pipes; i++)
3550                 offset += snprintf(rd_buf + offset, rd_buf_size - offset,
3551                                    "%d  ", dcc_en_bits[i]);
3552         rd_buf[strlen(rd_buf)] = '\n';
3553
3554         kfree(dcc_en_bits);
3555
3556         while (size) {
3557                 if (*pos >= rd_buf_size)
3558                         break;
3559                 r = put_user(*(rd_buf + result), buf);
3560                 if (r) {
3561                         kfree(rd_buf);
3562                         return r; /* r = -EFAULT */
3563                 }
3564                 buf += 1;
3565                 size -= 1;
3566                 *pos += 1;
3567                 result += 1;
3568         }
3569
3570         kfree(rd_buf);
3571         return result;
3572 }
3573
3574 void dtn_debugfs_init(struct amdgpu_device *adev)
3575 {
3576         static const struct file_operations dtn_log_fops = {
3577                 .owner = THIS_MODULE,
3578                 .read = dtn_log_read,
3579                 .write = dtn_log_write,
3580                 .llseek = default_llseek
3581         };
3582         static const struct file_operations dcc_en_bits_fops = {
3583                 .owner = THIS_MODULE,
3584                 .read = dcc_en_bits_read,
3585                 .llseek = default_llseek
3586         };
3587
3588         struct drm_minor *minor = adev_to_drm(adev)->primary;
3589         struct dentry *root = minor->debugfs_root;
3590
3591         debugfs_create_file("amdgpu_mst_topology", 0444, root,
3592                             adev, &mst_topo_fops);
3593         debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
3594                             &dtn_log_fops);
3595         debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev,
3596                                 &dp_set_mst_en_for_sst_ops);
3597         debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev,
3598                                 &dp_ignore_cable_id_ops);
3599
3600         debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
3601                                    &visual_confirm_fops);
3602
3603         debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev,
3604                                    &skip_detection_link_training_fops);
3605
3606         debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root,
3607                                    adev, &dmub_tracebuffer_fops);
3608
3609         debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root,
3610                                    adev, &dmub_fw_state_fops);
3611
3612         debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,
3613                                    adev, &force_timing_sync_ops);
3614
3615         debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
3616                                    adev, &dmcub_trace_event_state_fops);
3617
3618         debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root,
3619                                    adev, &trigger_hpd_mst_ops);
3620
3621         debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev,
3622                                    &dcc_en_bits_fops);
3623
3624         debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
3625                                    &disable_hpd_ops);
3626
3627 }