drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/fdtable.h>
  24 #include <linux/uaccess.h>
  25 #include <linux/firmware.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_amdkfd.h"
  29 #include "cikd.h"
  30 #include "cik_sdma.h"
  31 #include "amdgpu_ucode.h"
  32 #include "gfx_v7_0.h"
  33 #include "gca/gfx_7_2_d.h"
  34 #include "gca/gfx_7_2_enum.h"
  35 #include "gca/gfx_7_2_sh_mask.h"
  36 #include "oss/oss_2_0_d.h"
  37 #include "oss/oss_2_0_sh_mask.h"
  38 #include "gmc/gmc_7_1_d.h"
  39 #include "gmc/gmc_7_1_sh_mask.h"
  40 #include "cik_structs.h"
  41
  42 enum hqd_dequeue_request_type {
  43         NO_ACTION = 0,
  44         DRAIN_PIPE,
  45         RESET_WAVES
  46 };
  47
  48 enum {
  49         MAX_TRAPID = 8,         /* 3 bits in the bitfield. */
  50         MAX_WATCH_ADDRESSES = 4
  51 };
  52
  53 enum {
  54         ADDRESS_WATCH_REG_ADDR_HI = 0,
  55         ADDRESS_WATCH_REG_ADDR_LO,
  56         ADDRESS_WATCH_REG_CNTL,
  57         ADDRESS_WATCH_REG_MAX
  58 };
  59
  60 /*  not defined in the CI/KV reg file  */
  61 enum {
  62         ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,
  63         ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,
  64         ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,
  65         /* extend the mask to 26 bits to match the low address field */
  66         ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,
  67         ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF
  68 };
  69
  70 static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = {
  71         mmTCP_WATCH0_ADDR_H, mmTCP_WATCH0_ADDR_L, mmTCP_WATCH0_CNTL,
  72         mmTCP_WATCH1_ADDR_H, mmTCP_WATCH1_ADDR_L, mmTCP_WATCH1_CNTL,
  73         mmTCP_WATCH2_ADDR_H, mmTCP_WATCH2_ADDR_L, mmTCP_WATCH2_CNTL,
  74         mmTCP_WATCH3_ADDR_H, mmTCP_WATCH3_ADDR_L, mmTCP_WATCH3_CNTL
  75 };
  76
  77 union TCP_WATCH_CNTL_BITS {
  78         struct {
  79                 uint32_t mask:24;
  80                 uint32_t vmid:4;
  81                 uint32_t atc:1;
  82                 uint32_t mode:2;
  83                 uint32_t valid:1;
  84         } bitfields, bits;
  85         uint32_t u32All;
  86         signed int i32All;
  87         float f32All;
  88 };
  89
  90 /*
  91  * Register access functions
  92  */
  93
  94 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
  95                 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
  96                 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
  97
  98 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
  99                                         unsigned int vmid);
 100
 101 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
 102                                 uint32_t hpd_size, uint64_t hpd_gpu_addr);
 103 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
 104 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 105                         uint32_t queue_id, uint32_t __user *wptr,
 106                         uint32_t wptr_shift, uint32_t wptr_mask,
 107                         struct mm_struct *mm);
 108 static int kgd_hqd_dump(struct kgd_dev *kgd,
 109                         uint32_t pipe_id, uint32_t queue_id,
 110                         uint32_t (**dump)[2], uint32_t *n_regs);
 111 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 112                              uint32_t __user *wptr, struct mm_struct *mm);
 113 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
 114                              uint32_t engine_id, uint32_t queue_id,
 115                              uint32_t (**dump)[2], uint32_t *n_regs);
 116 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
 117                                 uint32_t pipe_id, uint32_t queue_id);
 118
 119 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
 120                                 enum kfd_preempt_type reset_type,
 121                                 unsigned int utimeout, uint32_t pipe_id,
 122                                 uint32_t queue_id);
 123 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
 124 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 125                                 unsigned int utimeout);
 126 static int kgd_address_watch_disable(struct kgd_dev *kgd);
 127 static int kgd_address_watch_execute(struct kgd_dev *kgd,
 128                                         unsigned int watch_point_id,
 129                                         uint32_t cntl_val,
 130                                         uint32_t addr_hi,
 131                                         uint32_t addr_lo);
 132 static int kgd_wave_control_execute(struct kgd_dev *kgd,
 133                                         uint32_t gfx_index_val,
 134                                         uint32_t sq_cmd);
 135 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
 136                                         unsigned int watch_point_id,
 137                                         unsigned int reg_offset);
 138
 139 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid);
 140 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
 141                                                         uint8_t vmid);
 142
 143 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
 144 static void set_scratch_backing_va(struct kgd_dev *kgd,
 145                                         uint64_t va, uint32_t vmid);
 146 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
 147                 uint32_t page_table_base);
 148 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
 149 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
 150
 151 /* Because of REG_GET_FIELD() being used, we put this function in the
 152  * asic specific file.
 153  */
 154 static int get_tile_config(struct kgd_dev *kgd,
 155                 struct tile_config *config)
 156 {
 157         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 158
 159         config->gb_addr_config = adev->gfx.config.gb_addr_config;
 160         config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
 161                                 MC_ARB_RAMCFG, NOOFBANK);
 162         config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
 163                                 MC_ARB_RAMCFG, NOOFRANKS);
 164
 165         config->tile_config_ptr = adev->gfx.config.tile_mode_array;
 166         config->num_tile_configs =
 167                         ARRAY_SIZE(adev->gfx.config.tile_mode_array);
 168         config->macro_tile_config_ptr =
 169                         adev->gfx.config.macrotile_mode_array;
 170         config->num_macro_tile_configs =
 171                         ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
 172
 173         return 0;
 174 }
 175
 176 static const struct kfd2kgd_calls kfd2kgd = {
 177         .init_gtt_mem_allocation = alloc_gtt_mem,
 178         .free_gtt_mem = free_gtt_mem,
 179         .get_local_mem_info = get_local_mem_info,
 180         .get_gpu_clock_counter = get_gpu_clock_counter,
 181         .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
 182         .alloc_pasid = amdgpu_pasid_alloc,
 183         .free_pasid = amdgpu_pasid_free,
 184         .program_sh_mem_settings = kgd_program_sh_mem_settings,
 185         .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
 186         .init_pipeline = kgd_init_pipeline,
 187         .init_interrupts = kgd_init_interrupts,
 188         .hqd_load = kgd_hqd_load,
 189         .hqd_sdma_load = kgd_hqd_sdma_load,
 190         .hqd_dump = kgd_hqd_dump,
 191         .hqd_sdma_dump = kgd_hqd_sdma_dump,
 192         .hqd_is_occupied = kgd_hqd_is_occupied,
 193         .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
 194         .hqd_destroy = kgd_hqd_destroy,
 195         .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
 196         .address_watch_disable = kgd_address_watch_disable,
 197         .address_watch_execute = kgd_address_watch_execute,
 198         .wave_control_execute = kgd_wave_control_execute,
 199         .address_watch_get_offset = kgd_address_watch_get_offset,
 200         .get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid,
 201         .get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid,
 202         .get_fw_version = get_fw_version,
 203         .set_scratch_backing_va = set_scratch_backing_va,
 204         .get_tile_config = get_tile_config,
 205         .get_cu_info = get_cu_info,
 206         .get_vram_usage = amdgpu_amdkfd_get_vram_usage,
 207         .create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
 208         .destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
 209         .get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
 210         .set_vm_context_page_table_base = set_vm_context_page_table_base,
 211         .alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu,
 212         .free_memory_of_gpu = amdgpu_amdkfd_gpuvm_free_memory_of_gpu,
 213         .map_memory_to_gpu = amdgpu_amdkfd_gpuvm_map_memory_to_gpu,
 214         .unmap_memory_to_gpu = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu,
 215         .sync_memory = amdgpu_amdkfd_gpuvm_sync_memory,
 216         .map_gtt_bo_to_kernel = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel,
 217         .restore_process_bos = amdgpu_amdkfd_gpuvm_restore_process_bos,
 218         .invalidate_tlbs = invalidate_tlbs,
 219         .invalidate_tlbs_vmid = invalidate_tlbs_vmid,
 220         .submit_ib = amdgpu_amdkfd_submit_ib,
 221 };
 222
 223 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
 224 {
 225         return (struct kfd2kgd_calls *)&kfd2kgd;
 226 }
 227
 228 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
 229 {
 230         return (struct amdgpu_device *)kgd;
 231 }
 232
 233 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
 234                         uint32_t queue, uint32_t vmid)
 235 {
 236         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 237         uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
 238
 239         mutex_lock(&adev->srbm_mutex);
 240         WREG32(mmSRBM_GFX_CNTL, value);
 241 }
 242
 243 static void unlock_srbm(struct kgd_dev *kgd)
 244 {
 245         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 246
 247         WREG32(mmSRBM_GFX_CNTL, 0);
 248         mutex_unlock(&adev->srbm_mutex);
 249 }
 250
 251 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
 252                                 uint32_t queue_id)
 253 {
 254         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 255
 256         uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 257         uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 258
 259         lock_srbm(kgd, mec, pipe, queue_id, 0);
 260 }
 261
 262 static void release_queue(struct kgd_dev *kgd)
 263 {
 264         unlock_srbm(kgd);
 265 }
 266
 267 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
 268                                         uint32_t sh_mem_config,
 269                                         uint32_t sh_mem_ape1_base,
 270                                         uint32_t sh_mem_ape1_limit,
 271                                         uint32_t sh_mem_bases)
 272 {
 273         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 274
 275         lock_srbm(kgd, 0, 0, 0, vmid);
 276
 277         WREG32(mmSH_MEM_CONFIG, sh_mem_config);
 278         WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
 279         WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
 280         WREG32(mmSH_MEM_BASES, sh_mem_bases);
 281
 282         unlock_srbm(kgd);
 283 }
 284
 285 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
 286                                         unsigned int vmid)
 287 {
 288         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 289
 290         /*
 291          * We have to assume that there is no outstanding mapping.
 292          * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
 293          * a mapping is in progress or because a mapping finished and the
 294          * SW cleared it. So the protocol is to always wait & clear.
 295          */
 296         uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
 297                         ATC_VMID0_PASID_MAPPING__VALID_MASK;
 298
 299         WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
 300
 301         while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
 302                 cpu_relax();
 303         WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
 304
 305         /* Mapping vmid to pasid also for IH block */
 306         WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
 307
 308         return 0;
 309 }
 310
 311 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
 312                                 uint32_t hpd_size, uint64_t hpd_gpu_addr)
 313 {
 314         /* amdgpu owns the per-pipe state */
 315         return 0;
 316 }
 317
 318 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
 319 {
 320         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 321         uint32_t mec;
 322         uint32_t pipe;
 323
 324         mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 325         pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 326
 327         lock_srbm(kgd, mec, pipe, 0, 0);
 328
 329         WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
 330                         CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
 331
 332         unlock_srbm(kgd);
 333
 334         return 0;
 335 }
 336
 337 static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
 338 {
 339         uint32_t retval;
 340
 341         retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
 342                         m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
 343
 344         pr_debug("kfd: sdma base address: 0x%x\n", retval);
 345
 346         return retval;
 347 }
 348
 349 static inline struct cik_mqd *get_mqd(void *mqd)
 350 {
 351         return (struct cik_mqd *)mqd;
 352 }
 353
 354 static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
 355 {
 356         return (struct cik_sdma_rlc_registers *)mqd;
 357 }
 358
 359 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 360                         uint32_t queue_id, uint32_t __user *wptr,
 361                         uint32_t wptr_shift, uint32_t wptr_mask,
 362                         struct mm_struct *mm)
 363 {
 364         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 365         struct cik_mqd *m;
 366         uint32_t *mqd_hqd;
 367         uint32_t reg, wptr_val, data;
 368         bool valid_wptr = false;
 369
 370         m = get_mqd(mqd);
 371
 372         acquire_queue(kgd, pipe_id, queue_id);
 373
 374         /* HQD registers extend from CP_MQD_BASE_ADDR to CP_MQD_CONTROL. */
 375         mqd_hqd = &m->cp_mqd_base_addr_lo;
 376
 377         for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
 378                 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
 379
 380         /* Copy userspace write pointer value to register.
 381          * Activate doorbell logic to monitor subsequent changes.
 382          */
 383         data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
 384                              CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
 385         WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
 386
 387         /* read_user_ptr may take the mm->mmap_sem.
 388          * release srbm_mutex to avoid circular dependency between
 389          * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex.
 390          */
 391         release_queue(kgd);
 392         valid_wptr = read_user_wptr(mm, wptr, wptr_val);
 393         acquire_queue(kgd, pipe_id, queue_id);
 394         if (valid_wptr)
 395                 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
 396
 397         data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
 398         WREG32(mmCP_HQD_ACTIVE, data);
 399
 400         release_queue(kgd);
 401
 402         return 0;
 403 }
 404
 405 static int kgd_hqd_dump(struct kgd_dev *kgd,
 406                         uint32_t pipe_id, uint32_t queue_id,
 407                         uint32_t (**dump)[2], uint32_t *n_regs)
 408 {
 409         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 410         uint32_t i = 0, reg;
 411 #define HQD_N_REGS (35+4)
 412 #define DUMP_REG(addr) do {                             \
 413                 if (WARN_ON_ONCE(i >= HQD_N_REGS))      \
 414                         break;                          \
 415                 (*dump)[i][0] = (addr) << 2;            \
 416                 (*dump)[i++][1] = RREG32(addr);         \
 417         } while (0)
 418
 419         *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
 420         if (*dump == NULL)
 421                 return -ENOMEM;
 422
 423         acquire_queue(kgd, pipe_id, queue_id);
 424
 425         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0);
 426         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1);
 427         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2);
 428         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3);
 429
 430         for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
 431                 DUMP_REG(reg);
 432
 433         release_queue(kgd);
 434
 435         WARN_ON_ONCE(i != HQD_N_REGS);
 436         *n_regs = i;
 437
 438         return 0;
 439 }
 440
 441 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 442                              uint32_t __user *wptr, struct mm_struct *mm)
 443 {
 444         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 445         struct cik_sdma_rlc_registers *m;
 446         unsigned long end_jiffies;
 447         uint32_t sdma_base_addr;
 448         uint32_t data;
 449
 450         m = get_sdma_mqd(mqd);
 451         sdma_base_addr = get_sdma_base_addr(m);
 452
 453         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
 454                 m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
 455
 456         end_jiffies = msecs_to_jiffies(2000) + jiffies;
 457         while (true) {
 458                 data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
 459                 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
 460                         break;
 461                 if (time_after(jiffies, end_jiffies))
 462                         return -ETIME;
 463                 usleep_range(500, 1000);
 464         }
 465         if (m->sdma_engine_id) {
 466                 data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
 467                 data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
 468                                 RESUME_CTX, 0);
 469                 WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
 470         } else {
 471                 data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
 472                 data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
 473                                 RESUME_CTX, 0);
 474                 WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
 475         }
 476
 477         data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,
 478                              ENABLE, 1);
 479         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
 480         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdma_rlc_rb_rptr);
 481
 482         if (read_user_wptr(mm, wptr, data))
 483                 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
 484         else
 485                 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
 486                        m->sdma_rlc_rb_rptr);
 487
 488         WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
 489                                 m->sdma_rlc_virtual_addr);
 490         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
 491         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
 492                         m->sdma_rlc_rb_base_hi);
 493         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
 494                         m->sdma_rlc_rb_rptr_addr_lo);
 495         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
 496                         m->sdma_rlc_rb_rptr_addr_hi);
 497
 498         data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL,
 499                              RB_ENABLE, 1);
 500         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
 501
 502         return 0;
 503 }
 504
 505 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
 506                              uint32_t engine_id, uint32_t queue_id,
 507                              uint32_t (**dump)[2], uint32_t *n_regs)
 508 {
 509         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 510         uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +
 511                 queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
 512         uint32_t i = 0, reg;
 513 #undef HQD_N_REGS
 514 #define HQD_N_REGS (19+4)
 515
 516         *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
 517         if (*dump == NULL)
 518                 return -ENOMEM;
 519
 520         for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
 521                 DUMP_REG(sdma_offset + reg);
 522         for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK;
 523              reg++)
 524                 DUMP_REG(sdma_offset + reg);
 525
 526         WARN_ON_ONCE(i != HQD_N_REGS);
 527         *n_regs = i;
 528
 529         return 0;
 530 }
 531
 532 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
 533                                 uint32_t pipe_id, uint32_t queue_id)
 534 {
 535         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 536         uint32_t act;
 537         bool retval = false;
 538         uint32_t low, high;
 539
 540         acquire_queue(kgd, pipe_id, queue_id);
 541         act = RREG32(mmCP_HQD_ACTIVE);
 542         if (act) {
 543                 low = lower_32_bits(queue_address >> 8);
 544                 high = upper_32_bits(queue_address >> 8);
 545
 546                 if (low == RREG32(mmCP_HQD_PQ_BASE) &&
 547                                 high == RREG32(mmCP_HQD_PQ_BASE_HI))
 548                         retval = true;
 549         }
 550         release_queue(kgd);
 551         return retval;
 552 }
 553
 554 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
 555 {
 556         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 557         struct cik_sdma_rlc_registers *m;
 558         uint32_t sdma_base_addr;
 559         uint32_t sdma_rlc_rb_cntl;
 560
 561         m = get_sdma_mqd(mqd);
 562         sdma_base_addr = get_sdma_base_addr(m);
 563
 564         sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
 565
 566         if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
 567                 return true;
 568
 569         return false;
 570 }
 571
 572 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
 573                                 enum kfd_preempt_type reset_type,
 574                                 unsigned int utimeout, uint32_t pipe_id,
 575                                 uint32_t queue_id)
 576 {
 577         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 578         uint32_t temp;
 579         enum hqd_dequeue_request_type type;
 580         unsigned long flags, end_jiffies;
 581         int retry;
 582
 583         acquire_queue(kgd, pipe_id, queue_id);
 584         WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
 585
 586         switch (reset_type) {
 587         case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
 588                 type = DRAIN_PIPE;
 589                 break;
 590         case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
 591                 type = RESET_WAVES;
 592                 break;
 593         default:
 594                 type = DRAIN_PIPE;
 595                 break;
 596         }
 597
 598         /* Workaround: If IQ timer is active and the wait time is close to or
 599          * equal to 0, dequeueing is not safe. Wait until either the wait time
 600          * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is
 601          * cleared before continuing. Also, ensure wait times are set to at
 602          * least 0x3.
 603          */
 604         local_irq_save(flags);
 605         preempt_disable();
 606         retry = 5000; /* wait for 500 usecs at maximum */
 607         while (true) {
 608                 temp = RREG32(mmCP_HQD_IQ_TIMER);
 609                 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
 610                         pr_debug("HW is processing IQ\n");
 611                         goto loop;
 612                 }
 613                 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
 614                         if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
 615                                         == 3) /* SEM-rearm is safe */
 616                                 break;
 617                         /* Wait time 3 is safe for CP, but our MMIO read/write
 618                          * time is close to 1 microsecond, so check for 10 to
 619                          * leave more buffer room
 620                          */
 621                         if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
 622                                         >= 10)
 623                                 break;
 624                         pr_debug("IQ timer is active\n");
 625                 } else
 626                         break;
 627 loop:
 628                 if (!retry) {
 629                         pr_err("CP HQD IQ timer status time out\n");
 630                         break;
 631                 }
 632                 ndelay(100);
 633                 --retry;
 634         }
 635         retry = 1000;
 636         while (true) {
 637                 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
 638                 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK))
 639                         break;
 640                 pr_debug("Dequeue request is pending\n");
 641
 642                 if (!retry) {
 643                         pr_err("CP HQD dequeue request time out\n");
 644                         break;
 645                 }
 646                 ndelay(100);
 647                 --retry;
 648         }
 649         local_irq_restore(flags);
 650         preempt_enable();
 651
 652         WREG32(mmCP_HQD_DEQUEUE_REQUEST, type);
 653
 654         end_jiffies = (utimeout * HZ / 1000) + jiffies;
 655         while (true) {
 656                 temp = RREG32(mmCP_HQD_ACTIVE);
 657                 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
 658                         break;
 659                 if (time_after(jiffies, end_jiffies)) {
 660                         pr_err("cp queue preemption time out\n");
 661                         release_queue(kgd);
 662                         return -ETIME;
 663                 }
 664                 usleep_range(500, 1000);
 665         }
 666
 667         release_queue(kgd);
 668         return 0;
 669 }
 670
 671 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 672                                 unsigned int utimeout)
 673 {
 674         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 675         struct cik_sdma_rlc_registers *m;
 676         uint32_t sdma_base_addr;
 677         uint32_t temp;
 678         unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
 679
 680         m = get_sdma_mqd(mqd);
 681         sdma_base_addr = get_sdma_base_addr(m);
 682
 683         temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
 684         temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
 685         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
 686
 687         while (true) {
 688                 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
 689                 if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
 690                         break;
 691                 if (time_after(jiffies, end_jiffies))
 692                         return -ETIME;
 693                 usleep_range(500, 1000);
 694         }
 695
 696         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
 697         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
 698                 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
 699                 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
 700
 701         m->sdma_rlc_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
 702
 703         return 0;
 704 }
 705
 706 static int kgd_address_watch_disable(struct kgd_dev *kgd)
 707 {
 708         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 709         union TCP_WATCH_CNTL_BITS cntl;
 710         unsigned int i;
 711
 712         cntl.u32All = 0;
 713
 714         cntl.bitfields.valid = 0;
 715         cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
 716         cntl.bitfields.atc = 1;
 717
 718         /* Turning off this address until we set all the registers */
 719         for (i = 0; i < MAX_WATCH_ADDRESSES; i++)
 720                 WREG32(watchRegs[i * ADDRESS_WATCH_REG_MAX +
 721                         ADDRESS_WATCH_REG_CNTL], cntl.u32All);
 722
 723         return 0;
 724 }
 725
 726 static int kgd_address_watch_execute(struct kgd_dev *kgd,
 727                                         unsigned int watch_point_id,
 728                                         uint32_t cntl_val,
 729                                         uint32_t addr_hi,
 730                                         uint32_t addr_lo)
 731 {
 732         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 733         union TCP_WATCH_CNTL_BITS cntl;
 734
 735         cntl.u32All = cntl_val;
 736
 737         /* Turning off this watch point until we set all the registers */
 738         cntl.bitfields.valid = 0;
 739         WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
 740                 ADDRESS_WATCH_REG_CNTL], cntl.u32All);
 741
 742         WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
 743                 ADDRESS_WATCH_REG_ADDR_HI], addr_hi);
 744
 745         WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
 746                 ADDRESS_WATCH_REG_ADDR_LO], addr_lo);
 747
 748         /* Enable the watch point */
 749         cntl.bitfields.valid = 1;
 750
 751         WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
 752                 ADDRESS_WATCH_REG_CNTL], cntl.u32All);
 753
 754         return 0;
 755 }
 756
 757 static int kgd_wave_control_execute(struct kgd_dev *kgd,
 758                                         uint32_t gfx_index_val,
 759                                         uint32_t sq_cmd)
 760 {
 761         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 762         uint32_t data;
 763
 764         mutex_lock(&adev->grbm_idx_mutex);
 765
 766         WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
 767         WREG32(mmSQ_CMD, sq_cmd);
 768
 769         /*  Restore the GRBM_GFX_INDEX register  */
 770
 771         data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK |
 772                 GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
 773                 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
 774
 775         WREG32(mmGRBM_GFX_INDEX, data);
 776
 777         mutex_unlock(&adev->grbm_idx_mutex);
 778
 779         return 0;
 780 }
 781
 782 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
 783                                         unsigned int watch_point_id,
 784                                         unsigned int reg_offset)
 785 {
 786         return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
 787 }
 788
 789 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
 790                                                         uint8_t vmid)
 791 {
 792         uint32_t reg;
 793         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 794
 795         reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 796         return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
 797 }
 798
 799 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
 800                                                                 uint8_t vmid)
 801 {
 802         uint32_t reg;
 803         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 804
 805         reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 806         return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 807 }
 808
 809 static void set_scratch_backing_va(struct kgd_dev *kgd,
 810                                         uint64_t va, uint32_t vmid)
 811 {
 812         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 813
 814         lock_srbm(kgd, 0, 0, 0, vmid);
 815         WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);
 816         unlock_srbm(kgd);
 817 }
 818
 819 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
 820 {
 821         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 822         const union amdgpu_firmware_header *hdr;
 823
 824         switch (type) {
 825         case KGD_ENGINE_PFP:
 826                 hdr = (const union amdgpu_firmware_header *)
 827                                                 adev->gfx.pfp_fw->data;
 828                 break;
 829
 830         case KGD_ENGINE_ME:
 831                 hdr = (const union amdgpu_firmware_header *)
 832                                                 adev->gfx.me_fw->data;
 833                 break;
 834
 835         case KGD_ENGINE_CE:
 836                 hdr = (const union amdgpu_firmware_header *)
 837                                                 adev->gfx.ce_fw->data;
 838                 break;
 839
 840         case KGD_ENGINE_MEC1:
 841                 hdr = (const union amdgpu_firmware_header *)
 842                                                 adev->gfx.mec_fw->data;
 843                 break;
 844
 845         case KGD_ENGINE_MEC2:
 846                 hdr = (const union amdgpu_firmware_header *)
 847                                                 adev->gfx.mec2_fw->data;
 848                 break;
 849
 850         case KGD_ENGINE_RLC:
 851                 hdr = (const union amdgpu_firmware_header *)
 852                                                 adev->gfx.rlc_fw->data;
 853                 break;
 854
 855         case KGD_ENGINE_SDMA1:
 856                 hdr = (const union amdgpu_firmware_header *)
 857                                                 adev->sdma.instance[0].fw->data;
 858                 break;
 859
 860         case KGD_ENGINE_SDMA2:
 861                 hdr = (const union amdgpu_firmware_header *)
 862                                                 adev->sdma.instance[1].fw->data;
 863                 break;
 864
 865         default:
 866                 return 0;
 867         }
 868
 869         if (hdr == NULL)
 870                 return 0;
 871
 872         /* Only 12 bit in use*/
 873         return hdr->common.ucode_version;
 874 }
 875
 876 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
 877                         uint32_t page_table_base)
 878 {
 879         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 880
 881         if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
 882                 pr_err("trying to set page table base for wrong VMID\n");
 883                 return;
 884         }
 885         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, page_table_base);
 886 }
 887
 888 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
 889 {
 890         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 891         int vmid;
 892         unsigned int tmp;
 893
 894         for (vmid = 0; vmid < 16; vmid++) {
 895                 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
 896                         continue;
 897
 898                 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 899                 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
 900                         (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
 901                         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 902                         RREG32(mmVM_INVALIDATE_RESPONSE);
 903                         break;
 904                 }
 905         }
 906
 907         return 0;
 908 }
 909
 910 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
 911 {
 912         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 913
 914         if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
 915                 pr_err("non kfd vmid\n");
 916                 return 0;
 917         }
 918
 919         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 920         RREG32(mmVM_INVALIDATE_RESPONSE);
 921         return 0;
 922 }