drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_VCN_H__
  25 #define __AMDGPU_VCN_H__
  26
  27 #define AMDGPU_VCN_STACK_SIZE           (128*1024)
  28 #define AMDGPU_VCN_CONTEXT_SIZE         (512*1024)
  29
  30 #define AMDGPU_VCN_FIRMWARE_OFFSET      256
  31 #define AMDGPU_VCN_MAX_ENC_RINGS        3
  32
  33 #define AMDGPU_MAX_VCN_INSTANCES        2
  34 #define AMDGPU_MAX_VCN_ENC_RINGS  AMDGPU_VCN_MAX_ENC_RINGS * AMDGPU_MAX_VCN_INSTANCES
  35
  36 #define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
  37 #define AMDGPU_VCN_HARVEST_VCN1 (1 << 1)
  38
  39 #define VCN_DEC_KMD_CMD                 0x80000000
  40 #define VCN_DEC_CMD_FENCE               0x00000000
  41 #define VCN_DEC_CMD_TRAP                0x00000001
  42 #define VCN_DEC_CMD_WRITE_REG           0x00000004
  43 #define VCN_DEC_CMD_REG_READ_COND_WAIT  0x00000006
  44 #define VCN_DEC_CMD_PACKET_START        0x0000000a
  45 #define VCN_DEC_CMD_PACKET_END          0x0000000b
  46
  47 #define VCN_ENC_CMD_NO_OP               0x00000000
  48 #define VCN_ENC_CMD_END                 0x00000001
  49 #define VCN_ENC_CMD_IB                  0x00000002
  50 #define VCN_ENC_CMD_FENCE               0x00000003
  51 #define VCN_ENC_CMD_TRAP                0x00000004
  52 #define VCN_ENC_CMD_REG_WRITE           0x0000000b
  53 #define VCN_ENC_CMD_REG_WAIT            0x0000000c
  54
  55 #define VCN_VID_SOC_ADDRESS_2_0         0x1fa00
  56 #define VCN_AON_SOC_ADDRESS_2_0         0x1f800
  57 #define VCN_VID_IP_ADDRESS_2_0          0x0
  58 #define VCN_AON_IP_ADDRESS_2_0          0x30000
  59
  60 #define mmUVD_RBC_XX_IB_REG_CHECK                                       0x026b
  61 #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX                              1
  62 #define mmUVD_REG_XX_MASK                                               0x026c
  63 #define mmUVD_REG_XX_MASK_BASE_IDX                                      1
  64
  65 /* 1 second timeout */
  66 #define VCN_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  67
  68 #define RREG32_SOC15_DPG_MODE(ip, inst_idx, reg, mask, sram_sel)                        \
  69         ({      WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask);                   \
  70                 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL,                           \
  71                         UVD_DPG_LMA_CTL__MASK_EN_MASK |                                 \
  72                         ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg)  \
  73                         << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) |                   \
  74                         (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT));                \
  75                 RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA);                         \
  76         })
  77
  78 #define WREG32_SOC15_DPG_MODE(ip, inst_idx, reg, value, mask, sram_sel)                 \
  79         do {                                                                            \
  80                 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value);                  \
  81                 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask);                   \
  82                 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL,                           \
  83                         UVD_DPG_LMA_CTL__READ_WRITE_MASK |                              \
  84                         ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg)  \
  85                         << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) |                   \
  86                         (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT));                \
  87         } while (0)
  88
  89 #define SOC15_DPG_MODE_OFFSET_2_0(ip, inst_idx, reg)                                            \
  90         ({                                                                                      \
  91                 uint32_t internal_reg_offset, addr;                                             \
  92                 bool video_range, aon_range;                                                    \
  93                                                                                                 \
  94                 addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg);           \
  95                 addr <<= 2;                                                                     \
  96                 video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) &&              \
  97                                 ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600)))));    \
  98                 aon_range   = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) &&              \
  99                                 ((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600)))));     \
 100                 if (video_range)                                                                \
 101                         internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) +   \
 102                                 (VCN_VID_IP_ADDRESS_2_0));                                      \
 103                 else if (aon_range)                                                             \
 104                         internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) +   \
 105                                 (VCN_AON_IP_ADDRESS_2_0));                                      \
 106                 else                                                                            \
 107                         internal_reg_offset = (0xFFFFF & addr);                                 \
 108                                                                                                 \
 109                 internal_reg_offset >>= 2;                                                      \
 110         })
 111
 112 #define RREG32_SOC15_DPG_MODE_2_0(inst_idx, offset, mask_en)                                    \
 113         ({                                                                                      \
 114                 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL,                                  \
 115                         (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT |                            \
 116                         mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT |                            \
 117                         offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT));                    \
 118                 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA);                                \
 119         })
 120
 121 #define WREG32_SOC15_DPG_MODE_2_0(inst_idx, offset, value, mask_en, indirect)                   \
 122         do {                                                                                    \
 123                 if (!indirect) {                                                                \
 124                         WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA, value);                 \
 125                         WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL,                          \
 126                                 (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT |                    \
 127                                  mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT |                   \
 128                                  offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT));           \
 129                 } else {                                                                        \
 130                         *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = offset;                \
 131                         *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = value;                 \
 132                 }                                                                               \
 133         } while (0)
 134
 135 #define AMDGPU_VCN_MULTI_QUEUE_FLAG     (1 << 8)
 136
 137 enum fw_queue_mode {
 138         FW_QUEUE_RING_RESET = 1,
 139         FW_QUEUE_DPG_HOLD_OFF = 2,
 140 };
 141
 142 enum engine_status_constants {
 143         UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
 144         UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0,
 145         UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
 146         UVD_STATUS__UVD_BUSY = 0x00000004,
 147         GB_ADDR_CONFIG_DEFAULT = 0x26010011,
 148         UVD_STATUS__IDLE = 0x2,
 149         UVD_STATUS__BUSY = 0x5,
 150         UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1,
 151         UVD_STATUS__RBC_BUSY = 0x1,
 152         UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0,
 153 };
 154
 155 enum internal_dpg_state {
 156         VCN_DPG_STATE__UNPAUSE = 0,
 157         VCN_DPG_STATE__PAUSE,
 158 };
 159
 160 struct dpg_pause_state {
 161         enum internal_dpg_state fw_based;
 162         enum internal_dpg_state jpeg;
 163 };
 164
 165 struct amdgpu_vcn_reg{
 166         unsigned        data0;
 167         unsigned        data1;
 168         unsigned        cmd;
 169         unsigned        nop;
 170         unsigned        context_id;
 171         unsigned        ib_vmid;
 172         unsigned        ib_bar_low;
 173         unsigned        ib_bar_high;
 174         unsigned        ib_size;
 175         unsigned        gp_scratch8;
 176         unsigned        scratch9;
 177 };
 178
 179 struct amdgpu_vcn_inst {
 180         struct amdgpu_bo        *vcpu_bo;
 181         void                    *cpu_addr;
 182         uint64_t                gpu_addr;
 183         void                    *saved_bo;
 184         struct amdgpu_ring      ring_dec;
 185         struct amdgpu_ring      ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
 186         struct amdgpu_irq_src   irq;
 187         struct amdgpu_vcn_reg   external;
 188         struct amdgpu_bo        *dpg_sram_bo;
 189         struct amdgpu_bo        *fw_shared_bo;
 190         struct dpg_pause_state  pause_state;
 191         void                    *dpg_sram_cpu_addr;
 192         uint64_t                dpg_sram_gpu_addr;
 193         uint32_t                *dpg_sram_curr_addr;
 194         atomic_t                dpg_enc_submission_cnt;
 195         void                    *fw_shared_cpu_addr;
 196         uint64_t                fw_shared_gpu_addr;
 197         void                    *saved_shm_bo;
 198 };
 199
 200 struct amdgpu_vcn {
 201         unsigned                fw_version;
 202         struct delayed_work     idle_work;
 203         const struct firmware   *fw;    /* VCN firmware */
 204         unsigned                num_enc_rings;
 205         enum amd_powergating_state cur_state;
 206         bool                    indirect_sram;
 207
 208         uint8_t num_vcn_inst;
 209         struct amdgpu_vcn_inst   inst[AMDGPU_MAX_VCN_INSTANCES];
 210         struct amdgpu_vcn_reg    internal;
 211         struct mutex             vcn_pg_lock;
 212         atomic_t                 total_submission_cnt;
 213
 214         unsigned        harvest_config;
 215         int (*pause_dpg_mode)(struct amdgpu_device *adev,
 216                 int inst_idx, struct dpg_pause_state *new_state);
 217 };
 218
 219 struct amdgpu_fw_shared_multi_queue {
 220         uint8_t decode_queue_mode;
 221         uint8_t encode_generalpurpose_queue_mode;
 222         uint8_t encode_lowlatency_queue_mode;
 223         uint8_t encode_realtime_queue_mode;
 224         uint8_t padding[4];
 225 };
 226
 227 struct amdgpu_fw_shared {
 228         uint32_t present_flag_0;
 229         uint8_t pad[53];
 230         struct amdgpu_fw_shared_multi_queue multi_queue;
 231 } __attribute__((__packed__));
 232
 233 int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
 234 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
 235 int amdgpu_vcn_suspend(struct amdgpu_device *adev);
 236 int amdgpu_vcn_resume(struct amdgpu_device *adev);
 237 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
 238 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
 239
 240 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
 241 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 242
 243 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
 244 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 245
 246 #endif