1 // SPDX-License-Identifier: GPL-2.0
3 * BPF Jit compiler for s390.
5 * Minimum build requirements:
7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
13 * Copyright IBM Corp. 2012,2015
19 #define KMSG_COMPONENT "bpf_jit"
20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
22 #include <linux/netdevice.h>
23 #include <linux/filter.h>
24 #include <linux/init.h>
25 #include <linux/bpf.h>
27 #include <linux/kernel.h>
28 #include <asm/cacheflush.h>
30 #include <asm/facility.h>
31 #include <asm/nospec-branch.h>
32 #include <asm/set_memory.h>
36 u32 seen; /* Flags to remember seen eBPF instructions */
37 u32 seen_reg[16]; /* Array to remember which registers are used */
38 u32 *addrs; /* Array with relative instruction addresses */
39 u8 *prg_buf; /* Start of program */
40 int size; /* Size of program and literal pool */
41 int size_prg; /* Size of program */
42 int prg; /* Current position in program */
43 int lit32_start; /* Start of 32-bit literal pool */
44 int lit32; /* Current position in 32-bit literal pool */
45 int lit64_start; /* Start of 64-bit literal pool */
46 int lit64; /* Current position in 64-bit literal pool */
47 int base_ip; /* Base address for literal pool */
48 int exit_ip; /* Address of exit */
49 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */
50 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */
51 int tail_call_start; /* Tail call start offset */
52 int labels[1]; /* Labels for local jumps */
55 #define SEEN_MEM BIT(0) /* use mem[] for temporary storage */
56 #define SEEN_LITERAL BIT(1) /* code uses literals */
57 #define SEEN_FUNC BIT(2) /* calls C functions */
58 #define SEEN_TAIL_CALL BIT(3) /* code uses tail calls */
59 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM)
64 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */
65 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */
66 #define REG_L (MAX_BPF_JIT_REG + 2) /* Literal pool register */
67 #define REG_15 (MAX_BPF_JIT_REG + 3) /* Register 15 */
68 #define REG_0 REG_W0 /* Register 0 */
69 #define REG_1 REG_W1 /* Register 1 */
70 #define REG_2 BPF_REG_1 /* Register 2 */
71 #define REG_14 BPF_REG_0 /* Register 14 */
74 * Mapping of BPF registers to s390 registers
76 static const int reg2hex[] = {
79 /* Function parameters */
85 /* Call saved registers */
90 /* BPF stack pointer */
92 /* Register for blinding */
94 /* Work registers for s390x backend */
101 static inline u32 reg(u32 dst_reg, u32 src_reg)
103 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
106 static inline u32 reg_high(u32 reg)
108 return reg2hex[reg] << 4;
111 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
113 u32 r1 = reg2hex[b1];
115 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15)
116 jit->seen_reg[r1] = 1;
119 #define REG_SET_SEEN(b1) \
121 reg_set_seen(jit, b1); \
124 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
127 * EMIT macros for code generation
133 *(u16 *) (jit->prg_buf + jit->prg) = (op); \
137 #define EMIT2(op, b1, b2) \
139 _EMIT2((op) | reg(b1, b2)); \
147 *(u32 *) (jit->prg_buf + jit->prg) = (op); \
151 #define EMIT4(op, b1, b2) \
153 _EMIT4((op) | reg(b1, b2)); \
158 #define EMIT4_RRF(op, b1, b2, b3) \
160 _EMIT4((op) | reg_high(b3) << 8 | reg(b1, b2)); \
166 #define _EMIT4_DISP(op, disp) \
168 unsigned int __disp = (disp) & 0xfff; \
169 _EMIT4((op) | __disp); \
172 #define EMIT4_DISP(op, b1, b2, disp) \
174 _EMIT4_DISP((op) | reg_high(b1) << 16 | \
175 reg_high(b2) << 8, (disp)); \
180 #define EMIT4_IMM(op, b1, imm) \
182 unsigned int __imm = (imm) & 0xffff; \
183 _EMIT4((op) | reg_high(b1) << 16 | __imm); \
187 #define EMIT4_PCREL(op, pcrel) \
189 long __pcrel = ((pcrel) >> 1) & 0xffff; \
190 _EMIT4((op) | __pcrel); \
193 #define EMIT4_PCREL_RIC(op, mask, target) \
195 int __rel = ((target) - jit->prg) / 2; \
196 _EMIT4((op) | (mask) << 20 | (__rel & 0xffff)); \
199 #define _EMIT6(op1, op2) \
201 if (jit->prg_buf) { \
202 *(u32 *) (jit->prg_buf + jit->prg) = (op1); \
203 *(u16 *) (jit->prg_buf + jit->prg + 4) = (op2); \
208 #define _EMIT6_DISP(op1, op2, disp) \
210 unsigned int __disp = (disp) & 0xfff; \
211 _EMIT6((op1) | __disp, op2); \
214 #define _EMIT6_DISP_LH(op1, op2, disp) \
216 u32 _disp = (u32) (disp); \
217 unsigned int __disp_h = _disp & 0xff000; \
218 unsigned int __disp_l = _disp & 0x00fff; \
219 _EMIT6((op1) | __disp_l, (op2) | __disp_h >> 4); \
222 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
224 _EMIT6_DISP_LH((op1) | reg(b1, b2) << 16 | \
225 reg_high(b3) << 8, op2, disp); \
231 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \
233 int rel = (jit->labels[label] - jit->prg) >> 1; \
234 _EMIT6((op1) | reg(b1, b2) << 16 | (rel & 0xffff), \
235 (op2) | (mask) << 12); \
240 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \
242 int rel = (jit->labels[label] - jit->prg) >> 1; \
243 _EMIT6((op1) | (reg_high(b1) | (mask)) << 16 | \
244 (rel & 0xffff), (op2) | ((imm) & 0xff) << 8); \
246 BUILD_BUG_ON(((unsigned long) (imm)) > 0xff); \
249 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
251 /* Branch instruction needs 6 bytes */ \
252 int rel = (addrs[(i) + (off) + 1] - (addrs[(i) + 1] - 6)) / 2;\
253 _EMIT6((op1) | reg(b1, b2) << 16 | (rel & 0xffff), (op2) | (mask));\
258 #define EMIT6_PCREL_RILB(op, b, target) \
260 unsigned int rel = (int)((target) - jit->prg) / 2; \
261 _EMIT6((op) | reg_high(b) << 16 | rel >> 16, rel & 0xffff);\
265 #define EMIT6_PCREL_RIL(op, target) \
267 unsigned int rel = (int)((target) - jit->prg) / 2; \
268 _EMIT6((op) | rel >> 16, rel & 0xffff); \
271 #define EMIT6_PCREL_RILC(op, mask, target) \
273 EMIT6_PCREL_RIL((op) | (mask) << 20, (target)); \
276 #define _EMIT6_IMM(op, imm) \
278 unsigned int __imm = (imm); \
279 _EMIT6((op) | (__imm >> 16), __imm & 0xffff); \
282 #define EMIT6_IMM(op, b1, imm) \
284 _EMIT6_IMM((op) | reg_high(b1) << 16, imm); \
288 #define _EMIT_CONST_U32(val) \
293 *(u32 *)(jit->prg_buf + jit->lit32) = (u32)(val);\
298 #define EMIT_CONST_U32(val) \
300 jit->seen |= SEEN_LITERAL; \
301 _EMIT_CONST_U32(val) - jit->base_ip; \
304 #define _EMIT_CONST_U64(val) \
309 *(u64 *)(jit->prg_buf + jit->lit64) = (u64)(val);\
314 #define EMIT_CONST_U64(val) \
316 jit->seen |= SEEN_LITERAL; \
317 _EMIT_CONST_U64(val) - jit->base_ip; \
320 #define EMIT_ZERO(b1) \
322 if (!fp->aux->verifier_zext) { \
323 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
324 EMIT4(0xb9160000, b1, b1); \
330 * Return whether this is the first pass. The first pass is special, since we
331 * don't know any sizes yet, and thus must be conservative.
333 static bool is_first_pass(struct bpf_jit *jit)
335 return jit->size == 0;
339 * Return whether this is the code generation pass. The code generation pass is
340 * special, since we should change as little as possible.
342 static bool is_codegen_pass(struct bpf_jit *jit)
348 * Return whether "rel" can be encoded as a short PC-relative offset
350 static bool is_valid_rel(int rel)
352 return rel >= -65536 && rel <= 65534;
356 * Return whether "off" can be reached using a short PC-relative offset
358 static bool can_use_rel(struct bpf_jit *jit, int off)
360 return is_valid_rel(off - jit->prg);
364 * Return whether given displacement can be encoded using
365 * Long-Displacement Facility
367 static bool is_valid_ldisp(int disp)
369 return disp >= -524288 && disp <= 524287;
373 * Return whether the next 32-bit literal pool entry can be referenced using
374 * Long-Displacement Facility
376 static bool can_use_ldisp_for_lit32(struct bpf_jit *jit)
378 return is_valid_ldisp(jit->lit32 - jit->base_ip);
382 * Return whether the next 64-bit literal pool entry can be referenced using
383 * Long-Displacement Facility
385 static bool can_use_ldisp_for_lit64(struct bpf_jit *jit)
387 return is_valid_ldisp(jit->lit64 - jit->base_ip);
391 * Fill whole space with illegal instructions
393 static void jit_fill_hole(void *area, unsigned int size)
395 memset(area, 0, size);
399 * Save registers from "rs" (register start) to "re" (register end) on stack
401 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
403 u32 off = STK_OFF_R6 + (rs - 6) * 8;
406 /* stg %rs,off(%r15) */
407 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
409 /* stmg %rs,%re,off(%r15) */
410 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
414 * Restore registers from "rs" (register start) to "re" (register end) on stack
416 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re, u32 stack_depth)
418 u32 off = STK_OFF_R6 + (rs - 6) * 8;
420 if (jit->seen & SEEN_STACK)
421 off += STK_OFF + stack_depth;
424 /* lg %rs,off(%r15) */
425 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
427 /* lmg %rs,%re,off(%r15) */
428 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
432 * Return first seen register (from start)
434 static int get_start(struct bpf_jit *jit, int start)
438 for (i = start; i <= 15; i++) {
439 if (jit->seen_reg[i])
446 * Return last seen register (from start) (gap >= 2)
448 static int get_end(struct bpf_jit *jit, int start)
452 for (i = start; i < 15; i++) {
453 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
456 return jit->seen_reg[15] ? 15 : 14;
460 #define REGS_RESTORE 0
462 * Save and restore clobbered registers (6-15) on stack.
463 * We save/restore registers in chunks with gap >= 2 registers.
465 static void save_restore_regs(struct bpf_jit *jit, int op, u32 stack_depth)
467 const int last = 15, save_restore_size = 6;
470 if (is_first_pass(jit)) {
472 * We don't know yet which registers are used. Reserve space
475 jit->prg += (last - re + 1) * save_restore_size;
480 rs = get_start(jit, re);
483 re = get_end(jit, rs + 1);
485 save_regs(jit, rs, re);
487 restore_regs(jit, rs, re, stack_depth);
489 } while (re <= last);
493 * Emit function prologue
495 * Save registers and create stack frame if necessary.
496 * See stack frame layout desription in "bpf_jit.h"!
498 static void bpf_jit_prologue(struct bpf_jit *jit, u32 stack_depth)
500 if (jit->seen & SEEN_TAIL_CALL) {
501 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
502 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT);
504 /* j tail_call_start: NOP if no tail calls are used */
505 EMIT4_PCREL(0xa7f40000, 6);
507 EMIT2(0x0700, 0, REG_0);
509 /* Tail calls have to skip above initialization */
510 jit->tail_call_start = jit->prg;
512 save_restore_regs(jit, REGS_SAVE, stack_depth);
513 /* Setup literal pool */
514 if (is_first_pass(jit) || (jit->seen & SEEN_LITERAL)) {
515 if (!is_first_pass(jit) &&
516 is_valid_ldisp(jit->size - (jit->prg + 2))) {
518 EMIT2(0x0d00, REG_L, REG_0);
519 jit->base_ip = jit->prg;
521 /* larl %l,lit32_start */
522 EMIT6_PCREL_RILB(0xc0000000, REG_L, jit->lit32_start);
523 jit->base_ip = jit->lit32_start;
526 /* Setup stack and backchain */
527 if (is_first_pass(jit) || (jit->seen & SEEN_STACK)) {
528 if (is_first_pass(jit) || (jit->seen & SEEN_FUNC))
529 /* lgr %w1,%r15 (backchain) */
530 EMIT4(0xb9040000, REG_W1, REG_15);
531 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
532 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED);
533 /* aghi %r15,-STK_OFF */
534 EMIT4_IMM(0xa70b0000, REG_15, -(STK_OFF + stack_depth));
535 if (is_first_pass(jit) || (jit->seen & SEEN_FUNC))
536 /* stg %w1,152(%r15) (backchain) */
537 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
545 static void bpf_jit_epilogue(struct bpf_jit *jit, u32 stack_depth)
547 jit->exit_ip = jit->prg;
548 /* Load exit code: lgr %r2,%b0 */
549 EMIT4(0xb9040000, REG_2, BPF_REG_0);
550 /* Restore registers */
551 save_restore_regs(jit, REGS_RESTORE, stack_depth);
552 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) {
553 jit->r14_thunk_ip = jit->prg;
554 /* Generate __s390_indirect_jump_r14 thunk */
555 if (test_facility(35)) {
557 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
560 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14);
562 EMIT4_DISP(0x44000000, REG_0, REG_1, 0);
565 EMIT4_PCREL(0xa7f40000, 0);
570 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable &&
571 (is_first_pass(jit) || (jit->seen & SEEN_FUNC))) {
572 jit->r1_thunk_ip = jit->prg;
573 /* Generate __s390_indirect_jump_r1 thunk */
574 if (test_facility(35)) {
576 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
578 EMIT4_PCREL(0xa7f40000, 0);
582 /* ex 0,S390_lowcore.br_r1_tampoline */
583 EMIT4_DISP(0x44000000, REG_0, REG_0,
584 offsetof(struct lowcore, br_r1_trampoline));
586 EMIT4_PCREL(0xa7f40000, 0);
592 * Compile one eBPF instruction into s390x code
594 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
595 * stack space for the large switch statement.
597 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp,
598 int i, bool extra_pass, u32 stack_depth)
600 struct bpf_insn *insn = &fp->insnsi[i];
601 u32 dst_reg = insn->dst_reg;
602 u32 src_reg = insn->src_reg;
603 int last, insn_count = 1;
604 u32 *addrs = jit->addrs;
609 switch (insn->code) {
613 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
614 /* llgfr %dst,%src */
615 EMIT4(0xb9160000, dst_reg, src_reg);
616 if (insn_is_zext(&insn[1]))
619 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
621 EMIT4(0xb9040000, dst_reg, src_reg);
623 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
625 EMIT6_IMM(0xc00f0000, dst_reg, imm);
626 if (insn_is_zext(&insn[1]))
629 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
631 EMIT6_IMM(0xc0010000, dst_reg, imm);
636 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
638 /* 16 byte instruction that uses two 'struct bpf_insn' */
641 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
643 EMIT6_PCREL_RILB(0xc4080000, dst_reg, _EMIT_CONST_U64(imm64));
650 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
652 EMIT2(0x1a00, dst_reg, src_reg);
655 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
657 EMIT4(0xb9080000, dst_reg, src_reg);
659 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
663 EMIT6_IMM(0xc20b0000, dst_reg, imm);
666 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
670 EMIT6_IMM(0xc2080000, dst_reg, imm);
675 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
677 EMIT2(0x1b00, dst_reg, src_reg);
680 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
682 EMIT4(0xb9090000, dst_reg, src_reg);
684 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
688 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
691 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
695 EMIT6_IMM(0xc2080000, dst_reg, -imm);
700 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
702 EMIT4(0xb2520000, dst_reg, src_reg);
705 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
707 EMIT4(0xb90c0000, dst_reg, src_reg);
709 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
713 EMIT6_IMM(0xc2010000, dst_reg, imm);
716 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
720 EMIT6_IMM(0xc2000000, dst_reg, imm);
725 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
726 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
728 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
731 EMIT4_IMM(0xa7080000, REG_W0, 0);
733 EMIT2(0x1800, REG_W1, dst_reg);
735 EMIT4(0xb9970000, REG_W0, src_reg);
737 EMIT4(0xb9160000, dst_reg, rc_reg);
738 if (insn_is_zext(&insn[1]))
742 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
743 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
745 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
748 EMIT4_IMM(0xa7090000, REG_W0, 0);
750 EMIT4(0xb9040000, REG_W1, dst_reg);
752 EMIT4(0xb9870000, REG_W0, src_reg);
754 EMIT4(0xb9040000, dst_reg, rc_reg);
757 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
758 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
760 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
763 if (BPF_OP(insn->code) == BPF_MOD)
765 EMIT4_IMM(0xa7090000, dst_reg, 0);
769 EMIT4_IMM(0xa7080000, REG_W0, 0);
771 EMIT2(0x1800, REG_W1, dst_reg);
772 if (!is_first_pass(jit) && can_use_ldisp_for_lit32(jit)) {
773 /* dl %w0,<d(imm)>(%l) */
774 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
775 EMIT_CONST_U32(imm));
778 EMIT6_PCREL_RILB(0xc40c0000, dst_reg,
779 _EMIT_CONST_U32(imm));
780 jit->seen |= SEEN_LITERAL;
782 EMIT4(0xb9970000, REG_W0, dst_reg);
785 EMIT4(0xb9160000, dst_reg, rc_reg);
786 if (insn_is_zext(&insn[1]))
790 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
791 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
793 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
796 if (BPF_OP(insn->code) == BPF_MOD)
798 EMIT4_IMM(0xa7090000, dst_reg, 0);
802 EMIT4_IMM(0xa7090000, REG_W0, 0);
804 EMIT4(0xb9040000, REG_W1, dst_reg);
805 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
806 /* dlg %w0,<d(imm)>(%l) */
807 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
808 EMIT_CONST_U64(imm));
811 EMIT6_PCREL_RILB(0xc4080000, dst_reg,
812 _EMIT_CONST_U64(imm));
813 jit->seen |= SEEN_LITERAL;
815 EMIT4(0xb9870000, REG_W0, dst_reg);
818 EMIT4(0xb9040000, dst_reg, rc_reg);
824 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
826 EMIT2(0x1400, dst_reg, src_reg);
829 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
831 EMIT4(0xb9800000, dst_reg, src_reg);
833 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
835 EMIT6_IMM(0xc00b0000, dst_reg, imm);
838 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
839 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
840 /* ng %dst,<d(imm)>(%l) */
841 EMIT6_DISP_LH(0xe3000000, 0x0080,
842 dst_reg, REG_0, REG_L,
843 EMIT_CONST_U64(imm));
846 EMIT6_PCREL_RILB(0xc4080000, REG_W0,
847 _EMIT_CONST_U64(imm));
848 jit->seen |= SEEN_LITERAL;
850 EMIT4(0xb9800000, dst_reg, REG_W0);
856 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
858 EMIT2(0x1600, dst_reg, src_reg);
861 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
863 EMIT4(0xb9810000, dst_reg, src_reg);
865 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
867 EMIT6_IMM(0xc00d0000, dst_reg, imm);
870 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
871 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
872 /* og %dst,<d(imm)>(%l) */
873 EMIT6_DISP_LH(0xe3000000, 0x0081,
874 dst_reg, REG_0, REG_L,
875 EMIT_CONST_U64(imm));
878 EMIT6_PCREL_RILB(0xc4080000, REG_W0,
879 _EMIT_CONST_U64(imm));
880 jit->seen |= SEEN_LITERAL;
882 EMIT4(0xb9810000, dst_reg, REG_W0);
888 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
890 EMIT2(0x1700, dst_reg, src_reg);
893 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
895 EMIT4(0xb9820000, dst_reg, src_reg);
897 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
901 EMIT6_IMM(0xc0070000, dst_reg, imm);
904 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
905 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
906 /* xg %dst,<d(imm)>(%l) */
907 EMIT6_DISP_LH(0xe3000000, 0x0082,
908 dst_reg, REG_0, REG_L,
909 EMIT_CONST_U64(imm));
912 EMIT6_PCREL_RILB(0xc4080000, REG_W0,
913 _EMIT_CONST_U64(imm));
914 jit->seen |= SEEN_LITERAL;
916 EMIT4(0xb9820000, dst_reg, REG_W0);
922 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
923 /* sll %dst,0(%src) */
924 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
927 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
928 /* sllg %dst,%dst,0(%src) */
929 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
931 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
934 /* sll %dst,imm(%r0) */
935 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
938 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
941 /* sllg %dst,%dst,imm(%r0) */
942 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
947 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
948 /* srl %dst,0(%src) */
949 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
952 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
953 /* srlg %dst,%dst,0(%src) */
954 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
956 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
959 /* srl %dst,imm(%r0) */
960 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
963 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
966 /* srlg %dst,%dst,imm(%r0) */
967 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
972 case BPF_ALU | BPF_ARSH | BPF_X: /* ((s32) dst) >>= src */
973 /* sra %dst,%dst,0(%src) */
974 EMIT4_DISP(0x8a000000, dst_reg, src_reg, 0);
977 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
978 /* srag %dst,%dst,0(%src) */
979 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
981 case BPF_ALU | BPF_ARSH | BPF_K: /* ((s32) dst >> imm */
984 /* sra %dst,imm(%r0) */
985 EMIT4_DISP(0x8a000000, dst_reg, REG_0, imm);
988 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
991 /* srag %dst,%dst,imm(%r0) */
992 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
997 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
999 EMIT2(0x1300, dst_reg, dst_reg);
1002 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
1003 /* lcgr %dst,%dst */
1004 EMIT4(0xb9030000, dst_reg, dst_reg);
1009 case BPF_ALU | BPF_END | BPF_FROM_BE:
1010 /* s390 is big endian, therefore only clear high order bytes */
1012 case 16: /* dst = (u16) cpu_to_be16(dst) */
1013 /* llghr %dst,%dst */
1014 EMIT4(0xb9850000, dst_reg, dst_reg);
1015 if (insn_is_zext(&insn[1]))
1018 case 32: /* dst = (u32) cpu_to_be32(dst) */
1019 if (!fp->aux->verifier_zext)
1020 /* llgfr %dst,%dst */
1021 EMIT4(0xb9160000, dst_reg, dst_reg);
1023 case 64: /* dst = (u64) cpu_to_be64(dst) */
1027 case BPF_ALU | BPF_END | BPF_FROM_LE:
1029 case 16: /* dst = (u16) cpu_to_le16(dst) */
1030 /* lrvr %dst,%dst */
1031 EMIT4(0xb91f0000, dst_reg, dst_reg);
1032 /* srl %dst,16(%r0) */
1033 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
1034 /* llghr %dst,%dst */
1035 EMIT4(0xb9850000, dst_reg, dst_reg);
1036 if (insn_is_zext(&insn[1]))
1039 case 32: /* dst = (u32) cpu_to_le32(dst) */
1040 /* lrvr %dst,%dst */
1041 EMIT4(0xb91f0000, dst_reg, dst_reg);
1042 if (!fp->aux->verifier_zext)
1043 /* llgfr %dst,%dst */
1044 EMIT4(0xb9160000, dst_reg, dst_reg);
1046 case 64: /* dst = (u64) cpu_to_le64(dst) */
1047 /* lrvgr %dst,%dst */
1048 EMIT4(0xb90f0000, dst_reg, dst_reg);
1055 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
1056 /* stcy %src,off(%dst) */
1057 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
1058 jit->seen |= SEEN_MEM;
1060 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
1061 /* sthy %src,off(%dst) */
1062 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
1063 jit->seen |= SEEN_MEM;
1065 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
1066 /* sty %src,off(%dst) */
1067 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
1068 jit->seen |= SEEN_MEM;
1070 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
1071 /* stg %src,off(%dst) */
1072 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
1073 jit->seen |= SEEN_MEM;
1075 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
1077 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
1078 /* stcy %w0,off(dst) */
1079 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
1080 jit->seen |= SEEN_MEM;
1082 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
1084 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
1085 /* sthy %w0,off(dst) */
1086 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
1087 jit->seen |= SEEN_MEM;
1089 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
1091 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
1092 /* sty %w0,off(%dst) */
1093 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
1094 jit->seen |= SEEN_MEM;
1096 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
1098 EMIT6_IMM(0xc0010000, REG_W0, imm);
1099 /* stg %w0,off(%dst) */
1100 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
1101 jit->seen |= SEEN_MEM;
1104 * BPF_STX XADD (atomic_add)
1106 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */
1107 /* laal %w0,%src,off(%dst) */
1108 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,
1110 jit->seen |= SEEN_MEM;
1112 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */
1113 /* laalg %w0,%src,off(%dst) */
1114 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,
1116 jit->seen |= SEEN_MEM;
1121 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
1122 /* llgc %dst,0(off,%src) */
1123 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
1124 jit->seen |= SEEN_MEM;
1125 if (insn_is_zext(&insn[1]))
1128 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
1129 /* llgh %dst,0(off,%src) */
1130 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
1131 jit->seen |= SEEN_MEM;
1132 if (insn_is_zext(&insn[1]))
1135 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
1136 /* llgf %dst,off(%src) */
1137 jit->seen |= SEEN_MEM;
1138 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
1139 if (insn_is_zext(&insn[1]))
1142 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
1143 /* lg %dst,0(off,%src) */
1144 jit->seen |= SEEN_MEM;
1145 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
1150 case BPF_JMP | BPF_CALL:
1153 bool func_addr_fixed;
1156 ret = bpf_jit_get_func_addr(fp, insn, extra_pass,
1157 &func, &func_addr_fixed);
1161 REG_SET_SEEN(BPF_REG_5);
1162 jit->seen |= SEEN_FUNC;
1164 EMIT6_PCREL_RILB(0xc4080000, REG_W1, _EMIT_CONST_U64(func));
1165 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) {
1166 /* brasl %r14,__s390_indirect_jump_r1 */
1167 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip);
1170 EMIT2(0x0d00, REG_14, REG_W1);
1172 /* lgr %b0,%r2: load return value into %b0 */
1173 EMIT4(0xb9040000, BPF_REG_0, REG_2);
1176 case BPF_JMP | BPF_TAIL_CALL:
1179 * B1: pointer to ctx
1180 * B2: pointer to bpf_array
1181 * B3: index in bpf_array
1183 jit->seen |= SEEN_TAIL_CALL;
1186 * if (index >= array->map.max_entries)
1190 /* llgf %w1,map.max_entries(%b2) */
1191 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,
1192 offsetof(struct bpf_array, map.max_entries));
1193 /* if ((u32)%b3 >= (u32)%w1) goto out; */
1194 if (!is_first_pass(jit) && can_use_rel(jit, jit->labels[0])) {
1195 /* clrj %b3,%w1,0xa,label0 */
1196 EMIT6_PCREL_LABEL(0xec000000, 0x0077, BPF_REG_3,
1200 EMIT2(0x1500, BPF_REG_3, REG_W1);
1201 /* brcl 0xa,label0 */
1202 EMIT6_PCREL_RILC(0xc0040000, 0xa, jit->labels[0]);
1206 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT)
1210 if (jit->seen & SEEN_STACK)
1211 off = STK_OFF_TCCNT + STK_OFF + stack_depth;
1213 off = STK_OFF_TCCNT;
1215 EMIT4_IMM(0xa7080000, REG_W0, 1);
1216 /* laal %w1,%w0,off(%r15) */
1217 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);
1218 if (!is_first_pass(jit) && can_use_rel(jit, jit->labels[0])) {
1219 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */
1220 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1,
1221 MAX_TAIL_CALL_CNT, 0, 0x2);
1223 /* clfi %w1,MAX_TAIL_CALL_CNT */
1224 EMIT6_IMM(0xc20f0000, REG_W1, MAX_TAIL_CALL_CNT);
1225 /* brcl 0x2,label0 */
1226 EMIT6_PCREL_RILC(0xc0040000, 0x2, jit->labels[0]);
1230 * prog = array->ptrs[index];
1235 /* llgfr %r1,%b3: %r1 = (u32) index */
1236 EMIT4(0xb9160000, REG_1, BPF_REG_3);
1237 /* sllg %r1,%r1,3: %r1 *= 8 */
1238 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, REG_1, REG_0, 3);
1239 /* ltg %r1,prog(%b2,%r1) */
1240 EMIT6_DISP_LH(0xe3000000, 0x0002, REG_1, BPF_REG_2,
1241 REG_1, offsetof(struct bpf_array, ptrs));
1242 if (!is_first_pass(jit) && can_use_rel(jit, jit->labels[0])) {
1243 /* brc 0x8,label0 */
1244 EMIT4_PCREL_RIC(0xa7040000, 0x8, jit->labels[0]);
1246 /* brcl 0x8,label0 */
1247 EMIT6_PCREL_RILC(0xc0040000, 0x8, jit->labels[0]);
1251 * Restore registers before calling function
1253 save_restore_regs(jit, REGS_RESTORE, stack_depth);
1256 * goto *(prog->bpf_func + tail_call_start);
1259 /* lg %r1,bpf_func(%r1) */
1260 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0,
1261 offsetof(struct bpf_prog, bpf_func));
1262 /* bc 0xf,tail_call_start(%r1) */
1263 _EMIT4(0x47f01000 + jit->tail_call_start);
1265 jit->labels[0] = jit->prg;
1267 case BPF_JMP | BPF_EXIT: /* return b0 */
1268 last = (i == fp->len - 1) ? 1 : 0;
1272 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg);
1275 * Branch relative (number of skipped instructions) to offset on
1278 * Condition code to mask mapping:
1280 * CC | Description | Mask
1281 * ------------------------------
1282 * 0 | Operands equal | 8
1283 * 1 | First operand low | 4
1284 * 2 | First operand high | 2
1287 * For s390x relative branches: ip = ip + off_bytes
1288 * For BPF relative branches: insn = insn + off_insns + 1
1290 * For example for s390x with offset 0 we jump to the branch
1291 * instruction itself (loop) and for BPF with offset 0 we
1292 * branch to the instruction behind the branch.
1294 case BPF_JMP | BPF_JA: /* if (true) */
1295 mask = 0xf000; /* j */
1297 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
1298 case BPF_JMP32 | BPF_JSGT | BPF_K: /* ((s32) dst > (s32) imm) */
1299 mask = 0x2000; /* jh */
1301 case BPF_JMP | BPF_JSLT | BPF_K: /* ((s64) dst < (s64) imm) */
1302 case BPF_JMP32 | BPF_JSLT | BPF_K: /* ((s32) dst < (s32) imm) */
1303 mask = 0x4000; /* jl */
1305 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
1306 case BPF_JMP32 | BPF_JSGE | BPF_K: /* ((s32) dst >= (s32) imm) */
1307 mask = 0xa000; /* jhe */
1309 case BPF_JMP | BPF_JSLE | BPF_K: /* ((s64) dst <= (s64) imm) */
1310 case BPF_JMP32 | BPF_JSLE | BPF_K: /* ((s32) dst <= (s32) imm) */
1311 mask = 0xc000; /* jle */
1313 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
1314 case BPF_JMP32 | BPF_JGT | BPF_K: /* ((u32) dst_reg > (u32) imm) */
1315 mask = 0x2000; /* jh */
1317 case BPF_JMP | BPF_JLT | BPF_K: /* (dst_reg < imm) */
1318 case BPF_JMP32 | BPF_JLT | BPF_K: /* ((u32) dst_reg < (u32) imm) */
1319 mask = 0x4000; /* jl */
1321 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
1322 case BPF_JMP32 | BPF_JGE | BPF_K: /* ((u32) dst_reg >= (u32) imm) */
1323 mask = 0xa000; /* jhe */
1325 case BPF_JMP | BPF_JLE | BPF_K: /* (dst_reg <= imm) */
1326 case BPF_JMP32 | BPF_JLE | BPF_K: /* ((u32) dst_reg <= (u32) imm) */
1327 mask = 0xc000; /* jle */
1329 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
1330 case BPF_JMP32 | BPF_JNE | BPF_K: /* ((u32) dst_reg != (u32) imm) */
1331 mask = 0x7000; /* jne */
1333 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
1334 case BPF_JMP32 | BPF_JEQ | BPF_K: /* ((u32) dst_reg == (u32) imm) */
1335 mask = 0x8000; /* je */
1337 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
1338 case BPF_JMP32 | BPF_JSET | BPF_K: /* ((u32) dst_reg & (u32) imm) */
1339 mask = 0x7000; /* jnz */
1340 if (BPF_CLASS(insn->code) == BPF_JMP32) {
1341 /* llilf %w1,imm (load zero extend imm) */
1342 EMIT6_IMM(0xc00f0000, REG_W1, imm);
1344 EMIT2(0x1400, REG_W1, dst_reg);
1346 /* lgfi %w1,imm (load sign extend imm) */
1347 EMIT6_IMM(0xc0010000, REG_W1, imm);
1349 EMIT4(0xb9800000, REG_W1, dst_reg);
1353 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1354 case BPF_JMP32 | BPF_JSGT | BPF_X: /* ((s32) dst > (s32) src) */
1355 mask = 0x2000; /* jh */
1357 case BPF_JMP | BPF_JSLT | BPF_X: /* ((s64) dst < (s64) src) */
1358 case BPF_JMP32 | BPF_JSLT | BPF_X: /* ((s32) dst < (s32) src) */
1359 mask = 0x4000; /* jl */
1361 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1362 case BPF_JMP32 | BPF_JSGE | BPF_X: /* ((s32) dst >= (s32) src) */
1363 mask = 0xa000; /* jhe */
1365 case BPF_JMP | BPF_JSLE | BPF_X: /* ((s64) dst <= (s64) src) */
1366 case BPF_JMP32 | BPF_JSLE | BPF_X: /* ((s32) dst <= (s32) src) */
1367 mask = 0xc000; /* jle */
1369 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1370 case BPF_JMP32 | BPF_JGT | BPF_X: /* ((u32) dst > (u32) src) */
1371 mask = 0x2000; /* jh */
1373 case BPF_JMP | BPF_JLT | BPF_X: /* (dst < src) */
1374 case BPF_JMP32 | BPF_JLT | BPF_X: /* ((u32) dst < (u32) src) */
1375 mask = 0x4000; /* jl */
1377 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1378 case BPF_JMP32 | BPF_JGE | BPF_X: /* ((u32) dst >= (u32) src) */
1379 mask = 0xa000; /* jhe */
1381 case BPF_JMP | BPF_JLE | BPF_X: /* (dst <= src) */
1382 case BPF_JMP32 | BPF_JLE | BPF_X: /* ((u32) dst <= (u32) src) */
1383 mask = 0xc000; /* jle */
1385 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1386 case BPF_JMP32 | BPF_JNE | BPF_X: /* ((u32) dst != (u32) src) */
1387 mask = 0x7000; /* jne */
1389 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1390 case BPF_JMP32 | BPF_JEQ | BPF_X: /* ((u32) dst == (u32) src) */
1391 mask = 0x8000; /* je */
1393 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1394 case BPF_JMP32 | BPF_JSET | BPF_X: /* ((u32) dst & (u32) src) */
1396 bool is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1398 mask = 0x7000; /* jnz */
1399 /* nrk or ngrk %w1,%dst,%src */
1400 EMIT4_RRF((is_jmp32 ? 0xb9f40000 : 0xb9e40000),
1401 REG_W1, dst_reg, src_reg);
1404 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1405 /* cfi or cgfi %dst,imm */
1406 EMIT6_IMM(is_jmp32 ? 0xc20d0000 : 0xc20c0000,
1408 if (!is_first_pass(jit) &&
1409 can_use_rel(jit, addrs[i + off + 1])) {
1411 EMIT4_PCREL_RIC(0xa7040000,
1412 mask >> 12, addrs[i + off + 1]);
1415 EMIT6_PCREL_RILC(0xc0040000,
1416 mask >> 12, addrs[i + off + 1]);
1420 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1421 /* clfi or clgfi %dst,imm */
1422 EMIT6_IMM(is_jmp32 ? 0xc20f0000 : 0xc20e0000,
1424 if (!is_first_pass(jit) &&
1425 can_use_rel(jit, addrs[i + off + 1])) {
1427 EMIT4_PCREL_RIC(0xa7040000,
1428 mask >> 12, addrs[i + off + 1]);
1431 EMIT6_PCREL_RILC(0xc0040000,
1432 mask >> 12, addrs[i + off + 1]);
1436 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1437 if (!is_first_pass(jit) &&
1438 can_use_rel(jit, addrs[i + off + 1])) {
1439 /* crj or cgrj %dst,%src,mask,off */
1440 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0076 : 0x0064),
1441 dst_reg, src_reg, i, off, mask);
1443 /* cr or cgr %dst,%src */
1445 EMIT2(0x1900, dst_reg, src_reg);
1447 EMIT4(0xb9200000, dst_reg, src_reg);
1449 EMIT6_PCREL_RILC(0xc0040000,
1450 mask >> 12, addrs[i + off + 1]);
1454 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1455 if (!is_first_pass(jit) &&
1456 can_use_rel(jit, addrs[i + off + 1])) {
1457 /* clrj or clgrj %dst,%src,mask,off */
1458 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0077 : 0x0065),
1459 dst_reg, src_reg, i, off, mask);
1461 /* clr or clgr %dst,%src */
1463 EMIT2(0x1500, dst_reg, src_reg);
1465 EMIT4(0xb9210000, dst_reg, src_reg);
1467 EMIT6_PCREL_RILC(0xc0040000,
1468 mask >> 12, addrs[i + off + 1]);
1472 if (!is_first_pass(jit) &&
1473 can_use_rel(jit, addrs[i + off + 1])) {
1475 EMIT4_PCREL_RIC(0xa7040000,
1476 mask >> 12, addrs[i + off + 1]);
1479 EMIT6_PCREL_RILC(0xc0040000,
1480 mask >> 12, addrs[i + off + 1]);
1484 default: /* too complex, give up */
1485 pr_err("Unknown opcode %02x\n", insn->code);
1492 * Return whether new i-th instruction address does not violate any invariant
1494 static bool bpf_is_new_addr_sane(struct bpf_jit *jit, int i)
1496 /* On the first pass anything goes */
1497 if (is_first_pass(jit))
1500 /* The codegen pass must not change anything */
1501 if (is_codegen_pass(jit))
1502 return jit->addrs[i] == jit->prg;
1504 /* Passes in between must not increase code size */
1505 return jit->addrs[i] >= jit->prg;
1509 * Update the address of i-th instruction
1511 static int bpf_set_addr(struct bpf_jit *jit, int i)
1513 if (!bpf_is_new_addr_sane(jit, i))
1515 jit->addrs[i] = jit->prg;
1520 * Compile eBPF program into s390x code
1522 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp,
1523 bool extra_pass, u32 stack_depth)
1525 int i, insn_count, lit32_size, lit64_size;
1527 jit->lit32 = jit->lit32_start;
1528 jit->lit64 = jit->lit64_start;
1531 bpf_jit_prologue(jit, stack_depth);
1532 if (bpf_set_addr(jit, 0) < 0)
1534 for (i = 0; i < fp->len; i += insn_count) {
1535 insn_count = bpf_jit_insn(jit, fp, i, extra_pass, stack_depth);
1538 /* Next instruction address */
1539 if (bpf_set_addr(jit, i + insn_count) < 0)
1542 bpf_jit_epilogue(jit, stack_depth);
1544 lit32_size = jit->lit32 - jit->lit32_start;
1545 lit64_size = jit->lit64 - jit->lit64_start;
1546 jit->lit32_start = jit->prg;
1548 jit->lit32_start = ALIGN(jit->lit32_start, 4);
1549 jit->lit64_start = jit->lit32_start + lit32_size;
1551 jit->lit64_start = ALIGN(jit->lit64_start, 8);
1552 jit->size = jit->lit64_start + lit64_size;
1553 jit->size_prg = jit->prg;
1557 bool bpf_jit_needs_zext(void)
1562 struct s390_jit_data {
1563 struct bpf_binary_header *header;
1569 * Compile eBPF program "fp"
1571 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
1573 u32 stack_depth = round_up(fp->aux->stack_depth, 8);
1574 struct bpf_prog *tmp, *orig_fp = fp;
1575 struct bpf_binary_header *header;
1576 struct s390_jit_data *jit_data;
1577 bool tmp_blinded = false;
1578 bool extra_pass = false;
1582 if (!fp->jit_requested)
1585 tmp = bpf_jit_blind_constants(fp);
1587 * If blinding was requested and we failed during blinding,
1588 * we must fall back to the interpreter.
1597 jit_data = fp->aux->jit_data;
1599 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
1604 fp->aux->jit_data = jit_data;
1606 if (jit_data->ctx.addrs) {
1607 jit = jit_data->ctx;
1608 header = jit_data->header;
1610 pass = jit_data->pass + 1;
1614 memset(&jit, 0, sizeof(jit));
1615 jit.addrs = kvcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1616 if (jit.addrs == NULL) {
1621 * Three initial passes:
1622 * - 1/2: Determine clobbered registers
1623 * - 3: Calculate program size and addrs arrray
1625 for (pass = 1; pass <= 3; pass++) {
1626 if (bpf_jit_prog(&jit, fp, extra_pass, stack_depth)) {
1632 * Final pass: Allocate and generate program
1634 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 8, jit_fill_hole);
1640 if (bpf_jit_prog(&jit, fp, extra_pass, stack_depth)) {
1641 bpf_jit_binary_free(header);
1645 if (bpf_jit_enable > 1) {
1646 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1647 print_fn_code(jit.prg_buf, jit.size_prg);
1649 if (!fp->is_func || extra_pass) {
1650 bpf_jit_binary_lock_ro(header);
1652 jit_data->header = header;
1653 jit_data->ctx = jit;
1654 jit_data->pass = pass;
1656 fp->bpf_func = (void *) jit.prg_buf;
1658 fp->jited_len = jit.size;
1660 if (!fp->is_func || extra_pass) {
1661 bpf_prog_fill_jited_linfo(fp, jit.addrs + 1);
1665 fp->aux->jit_data = NULL;
1669 bpf_jit_prog_release_other(fp, fp == orig_fp ?