drivers/scsi/lpfc/lpfc_hw4.h

   1 /*******************************************************************
   2  * This file is part of the Emulex Linux Device Driver for         *
   3  * Fibre Channel Host Bus Adapters.                                *
   4  * Copyright (C) 2017-2024 Broadcom. All Rights Reserved. The term *
   5  * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.  *
   6  * Copyright (C) 2009-2016 Emulex.  All rights reserved.           *
   7  * EMULEX and SLI are trademarks of Emulex.                        *
   8  * www.broadcom.com                                                *
   9  *                                                                 *
  10  * This program is free software; you can redistribute it and/or   *
  11  * modify it under the terms of version 2 of the GNU General       *
  12  * Public License as published by the Free Software Foundation.    *
  13  * This program is distributed in the hope that it will be useful. *
  14  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  15  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  16  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  17  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  18  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  19  * more details, a copy of which can be found in the file COPYING  *
  20  * included with this package.                                     *
  21  *******************************************************************/
  22
  23 #include <uapi/scsi/fc/fc_fs.h>
  24 #include <uapi/scsi/fc/fc_els.h>
  25
  26 /* Macros to deal with bit fields. Each bit field must have 3 #defines
  27  * associated with it (_SHIFT, _MASK, and _WORD).
  28  * EG. For a bit field that is in the 7th bit of the "field4" field of a
  29  * structure and is 2 bits in size the following #defines must exist:
  30  *      struct temp {
  31  *              uint32_t        field1;
  32  *              uint32_t        field2;
  33  *              uint32_t        field3;
  34  *              uint32_t        field4;
  35  *      #define example_bit_field_SHIFT         7
  36  *      #define example_bit_field_MASK          0x03
  37  *      #define example_bit_field_WORD          field4
  38  *              uint32_t        field5;
  39  *      };
  40  * Then the macros below may be used to get or set the value of that field.
  41  * EG. To get the value of the bit field from the above example:
  42  *      struct temp t1;
  43  *      value = bf_get(example_bit_field, &t1);
  44  * And then to set that bit field:
  45  *      bf_set(example_bit_field, &t1, 2);
  46  * Or clear that bit field:
  47  *      bf_set(example_bit_field, &t1, 0);
  48  */
  49 #define bf_get_be32(name, ptr) \
  50         ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
  51 #define bf_get_le32(name, ptr) \
  52         ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
  53 #define bf_get(name, ptr) \
  54         (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
  55 #define bf_set_le32(name, ptr, value) \
  56         ((ptr)->name##_WORD = cpu_to_le32(((((value) & \
  57         name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \
  58         ~(name##_MASK << name##_SHIFT)))))
  59 #define bf_set(name, ptr, value) \
  60         ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
  61                  ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
  62
  63 #define get_wqe_reqtag(x)       (((x)->wqe.words[9] >>  0) & 0xFFFF)
  64 #define get_wqe_tmo(x)          (((x)->wqe.words[7] >> 24) & 0x00FF)
  65
  66 #define get_job_ulpword(x, y)   ((x)->iocb.un.ulpWord[y])
  67
  68 #define set_job_ulpstatus(x, y) bf_set(lpfc_wcqe_c_status, &(x)->wcqe_cmpl, y)
  69 #define set_job_ulpword4(x, y)  ((&(x)->wcqe_cmpl)->parameter = y)
  70
  71 struct dma_address {
  72         uint32_t addr_lo;
  73         uint32_t addr_hi;
  74 };
  75
  76 struct lpfc_sli_intf {
  77         uint32_t word0;
  78 #define lpfc_sli_intf_valid_SHIFT               29
  79 #define lpfc_sli_intf_valid_MASK                0x00000007
  80 #define lpfc_sli_intf_valid_WORD                word0
  81 #define LPFC_SLI_INTF_VALID             6
  82 #define lpfc_sli_intf_sli_hint2_SHIFT           24
  83 #define lpfc_sli_intf_sli_hint2_MASK            0x0000001F
  84 #define lpfc_sli_intf_sli_hint2_WORD            word0
  85 #define LPFC_SLI_INTF_SLI_HINT2_NONE    0
  86 #define lpfc_sli_intf_sli_hint1_SHIFT           16
  87 #define lpfc_sli_intf_sli_hint1_MASK            0x000000FF
  88 #define lpfc_sli_intf_sli_hint1_WORD            word0
  89 #define LPFC_SLI_INTF_SLI_HINT1_NONE    0
  90 #define LPFC_SLI_INTF_SLI_HINT1_1       1
  91 #define LPFC_SLI_INTF_SLI_HINT1_2       2
  92 #define lpfc_sli_intf_if_type_SHIFT             12
  93 #define lpfc_sli_intf_if_type_MASK              0x0000000F
  94 #define lpfc_sli_intf_if_type_WORD              word0
  95 #define LPFC_SLI_INTF_IF_TYPE_0         0
  96 #define LPFC_SLI_INTF_IF_TYPE_1         1
  97 #define LPFC_SLI_INTF_IF_TYPE_2         2
  98 #define LPFC_SLI_INTF_IF_TYPE_6         6
  99 #define lpfc_sli_intf_sli_family_SHIFT          8
 100 #define lpfc_sli_intf_sli_family_MASK           0x0000000F
 101 #define lpfc_sli_intf_sli_family_WORD           word0
 102 #define LPFC_SLI_INTF_FAMILY_BE2        0x0
 103 #define LPFC_SLI_INTF_FAMILY_BE3        0x1
 104 #define LPFC_SLI_INTF_FAMILY_LNCR_A0    0xa
 105 #define LPFC_SLI_INTF_FAMILY_LNCR_B0    0xb
 106 #define LPFC_SLI_INTF_FAMILY_G6         0xc
 107 #define LPFC_SLI_INTF_FAMILY_G7         0xd
 108 #define LPFC_SLI_INTF_FAMILY_G7P        0xe
 109 #define lpfc_sli_intf_slirev_SHIFT              4
 110 #define lpfc_sli_intf_slirev_MASK               0x0000000F
 111 #define lpfc_sli_intf_slirev_WORD               word0
 112 #define LPFC_SLI_INTF_REV_SLI3          3
 113 #define LPFC_SLI_INTF_REV_SLI4          4
 114 #define lpfc_sli_intf_func_type_SHIFT           0
 115 #define lpfc_sli_intf_func_type_MASK            0x00000001
 116 #define lpfc_sli_intf_func_type_WORD            word0
 117 #define LPFC_SLI_INTF_IF_TYPE_PHYS      0
 118 #define LPFC_SLI_INTF_IF_TYPE_VIRT      1
 119 };
 120
 121 #define LPFC_SLI4_MBX_EMBED     true
 122 #define LPFC_SLI4_MBX_NEMBED    false
 123
 124 #define LPFC_SLI4_MB_WORD_COUNT         64
 125 #define LPFC_MAX_MQ_PAGE                8
 126 #define LPFC_MAX_WQ_PAGE_V0             4
 127 #define LPFC_MAX_WQ_PAGE                8
 128 #define LPFC_MAX_RQ_PAGE                8
 129 #define LPFC_MAX_CQ_PAGE                4
 130 #define LPFC_MAX_EQ_PAGE                8
 131
 132 #define LPFC_VIR_FUNC_MAX       32 /* Maximum number of virtual functions */
 133 #define LPFC_PCI_FUNC_MAX        5 /* Maximum number of PCI functions */
 134 #define LPFC_VFR_PAGE_SIZE      0x1000 /* 4KB BAR2 per-VF register page size */
 135
 136 /* Define SLI4 Alignment requirements. */
 137 #define LPFC_ALIGN_16_BYTE      16
 138 #define LPFC_ALIGN_64_BYTE      64
 139 #define SLI4_PAGE_SIZE          4096
 140
 141 /* Define SLI4 specific definitions. */
 142 #define LPFC_MQ_CQE_BYTE_OFFSET 256
 143 #define LPFC_MBX_CMD_HDR_LENGTH 16
 144 #define LPFC_MBX_ERROR_RANGE    0x4000
 145 #define LPFC_BMBX_BIT1_ADDR_HI  0x2
 146 #define LPFC_BMBX_BIT1_ADDR_LO  0
 147 #define LPFC_RPI_HDR_COUNT      64
 148 #define LPFC_HDR_TEMPLATE_SIZE  4096
 149 #define LPFC_RPI_ALLOC_ERROR    0xFFFF
 150 #define LPFC_FCF_RECORD_WD_CNT  132
 151 #define LPFC_ENTIRE_FCF_DATABASE 0
 152 #define LPFC_DFLT_FCF_INDEX      0
 153
 154 /* Virtual function numbers */
 155 #define LPFC_VF0                0
 156 #define LPFC_VF1                1
 157 #define LPFC_VF2                2
 158 #define LPFC_VF3                3
 159 #define LPFC_VF4                4
 160 #define LPFC_VF5                5
 161 #define LPFC_VF6                6
 162 #define LPFC_VF7                7
 163 #define LPFC_VF8                8
 164 #define LPFC_VF9                9
 165 #define LPFC_VF10               10
 166 #define LPFC_VF11               11
 167 #define LPFC_VF12               12
 168 #define LPFC_VF13               13
 169 #define LPFC_VF14               14
 170 #define LPFC_VF15               15
 171 #define LPFC_VF16               16
 172 #define LPFC_VF17               17
 173 #define LPFC_VF18               18
 174 #define LPFC_VF19               19
 175 #define LPFC_VF20               20
 176 #define LPFC_VF21               21
 177 #define LPFC_VF22               22
 178 #define LPFC_VF23               23
 179 #define LPFC_VF24               24
 180 #define LPFC_VF25               25
 181 #define LPFC_VF26               26
 182 #define LPFC_VF27               27
 183 #define LPFC_VF28               28
 184 #define LPFC_VF29               29
 185 #define LPFC_VF30               30
 186 #define LPFC_VF31               31
 187
 188 /* PCI function numbers */
 189 #define LPFC_PCI_FUNC0          0
 190 #define LPFC_PCI_FUNC1          1
 191 #define LPFC_PCI_FUNC2          2
 192 #define LPFC_PCI_FUNC3          3
 193 #define LPFC_PCI_FUNC4          4
 194
 195 /* SLI4 interface type-2 PDEV_CTL register */
 196 #define LPFC_CTL_PDEV_CTL_OFFSET        0x414
 197 #define LPFC_CTL_PDEV_CTL_DRST          0x00000001
 198 #define LPFC_CTL_PDEV_CTL_FRST          0x00000002
 199 #define LPFC_CTL_PDEV_CTL_DD            0x00000004
 200 #define LPFC_CTL_PDEV_CTL_LC            0x00000008
 201 #define LPFC_CTL_PDEV_CTL_FRL_ALL       0x00
 202 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE   0x10
 203 #define LPFC_CTL_PDEV_CTL_FRL_NIC       0x20
 204 #define LPFC_CTL_PDEV_CTL_DDL_RAS       0x1000000
 205
 206 #define LPFC_FW_DUMP_REQUEST    (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST)
 207
 208 /* Active interrupt test count */
 209 #define LPFC_ACT_INTR_CNT       4
 210
 211 /* Algrithmns for scheduling FCP commands to WQs */
 212 #define LPFC_FCP_SCHED_BY_HDWQ          0
 213 #define LPFC_FCP_SCHED_BY_CPU           1
 214
 215 /* Algrithmns for NameServer Query after RSCN */
 216 #define LPFC_NS_QUERY_GID_FT    0
 217 #define LPFC_NS_QUERY_GID_PT    1
 218
 219 /* Delay Multiplier constant */
 220 #define LPFC_DMULT_CONST       651042
 221 #define LPFC_DMULT_MAX         1023
 222
 223 /* Configuration of Interrupts / sec for entire HBA port */
 224 #define LPFC_MIN_IMAX          5000
 225 #define LPFC_MAX_IMAX          5000000
 226 #define LPFC_DEF_IMAX          0
 227
 228 #define LPFC_MAX_AUTO_EQ_DELAY 120
 229 #define LPFC_EQ_DELAY_STEP     15
 230 #define LPFC_EQD_ISR_TRIGGER   20000
 231 /* 1s intervals */
 232 #define LPFC_EQ_DELAY_MSECS    1000
 233
 234 #define LPFC_MIN_CPU_MAP       0
 235 #define LPFC_MAX_CPU_MAP       1
 236 #define LPFC_HBA_CPU_MAP       1
 237
 238 /* PORT_CAPABILITIES constants. */
 239 #define LPFC_MAX_SUPPORTED_PAGES        8
 240
 241 enum ulp_bde64_word3 {
 242         ULP_BDE64_SIZE_MASK             = 0xffffff,
 243
 244         ULP_BDE64_TYPE_SHIFT            = 24,
 245         ULP_BDE64_TYPE_MASK             = (0xff << ULP_BDE64_TYPE_SHIFT),
 246
 247         /* BDE (Host_resident) */
 248         ULP_BDE64_TYPE_BDE_64           = (0x00 << ULP_BDE64_TYPE_SHIFT),
 249         /* Immediate Data BDE */
 250         ULP_BDE64_TYPE_BDE_IMMED        = (0x01 << ULP_BDE64_TYPE_SHIFT),
 251         /* BDE (Port-resident) */
 252         ULP_BDE64_TYPE_BDE_64P          = (0x02 << ULP_BDE64_TYPE_SHIFT),
 253         /* Input BDE (Host-resident) */
 254         ULP_BDE64_TYPE_BDE_64I          = (0x08 << ULP_BDE64_TYPE_SHIFT),
 255         /* Input BDE (Port-resident) */
 256         ULP_BDE64_TYPE_BDE_64IP         = (0x0A << ULP_BDE64_TYPE_SHIFT),
 257         /* BLP (Host-resident) */
 258         ULP_BDE64_TYPE_BLP_64           = (0x40 << ULP_BDE64_TYPE_SHIFT),
 259         /* BLP (Port-resident) */
 260         ULP_BDE64_TYPE_BLP_64P          = (0x42 << ULP_BDE64_TYPE_SHIFT),
 261 };
 262
 263 struct ulp_bde64_le {
 264         __le32 type_size; /* type 31:24, size 23:0 */
 265         __le32 addr_low;
 266         __le32 addr_high;
 267 };
 268
 269 struct ulp_bde64 {
 270         union ULP_BDE_TUS {
 271                 uint32_t w;
 272                 struct {
 273 #ifdef __BIG_ENDIAN_BITFIELD
 274                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 275                                                    VALUE !! */
 276                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 277 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 278                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 279                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 280                                                    VALUE !! */
 281 #endif
 282 #define BUFF_TYPE_BDE_64    0x00        /* BDE (Host_resident) */
 283 #define BUFF_TYPE_BDE_IMMED 0x01        /* Immediate Data BDE */
 284 #define BUFF_TYPE_BDE_64P   0x02        /* BDE (Port-resident) */
 285 #define BUFF_TYPE_BDE_64I   0x08        /* Input BDE (Host-resident) */
 286 #define BUFF_TYPE_BDE_64IP  0x0A        /* Input BDE (Port-resident) */
 287 #define BUFF_TYPE_BLP_64    0x40        /* BLP (Host-resident) */
 288 #define BUFF_TYPE_BLP_64P   0x42        /* BLP (Port-resident) */
 289                 } f;
 290         } tus;
 291         uint32_t addrLow;
 292         uint32_t addrHigh;
 293 };
 294
 295 /* Maximun size of immediate data that can fit into a 128 byte WQE */
 296 #define LPFC_MAX_BDE_IMM_SIZE   64
 297
 298 struct lpfc_sli4_flags {
 299         uint32_t word0;
 300 #define lpfc_idx_rsrc_rdy_SHIFT         0
 301 #define lpfc_idx_rsrc_rdy_MASK          0x00000001
 302 #define lpfc_idx_rsrc_rdy_WORD          word0
 303 #define LPFC_IDX_RSRC_RDY               1
 304 #define lpfc_rpi_rsrc_rdy_SHIFT         1
 305 #define lpfc_rpi_rsrc_rdy_MASK          0x00000001
 306 #define lpfc_rpi_rsrc_rdy_WORD          word0
 307 #define LPFC_RPI_RSRC_RDY               1
 308 #define lpfc_vpi_rsrc_rdy_SHIFT         2
 309 #define lpfc_vpi_rsrc_rdy_MASK          0x00000001
 310 #define lpfc_vpi_rsrc_rdy_WORD          word0
 311 #define LPFC_VPI_RSRC_RDY               1
 312 #define lpfc_vfi_rsrc_rdy_SHIFT         3
 313 #define lpfc_vfi_rsrc_rdy_MASK          0x00000001
 314 #define lpfc_vfi_rsrc_rdy_WORD          word0
 315 #define LPFC_VFI_RSRC_RDY               1
 316 #define lpfc_ftr_ashdr_SHIFT            4
 317 #define lpfc_ftr_ashdr_MASK             0x00000001
 318 #define lpfc_ftr_ashdr_WORD             word0
 319 };
 320
 321 struct sli4_bls_rsp {
 322         uint32_t word0_rsvd;      /* Word0 must be reserved */
 323         uint32_t word1;
 324 #define lpfc_abts_orig_SHIFT      0
 325 #define lpfc_abts_orig_MASK       0x00000001
 326 #define lpfc_abts_orig_WORD       word1
 327 #define LPFC_ABTS_UNSOL_RSP       1
 328 #define LPFC_ABTS_UNSOL_INT       0
 329         uint32_t word2;
 330 #define lpfc_abts_rxid_SHIFT      0
 331 #define lpfc_abts_rxid_MASK       0x0000FFFF
 332 #define lpfc_abts_rxid_WORD       word2
 333 #define lpfc_abts_oxid_SHIFT      16
 334 #define lpfc_abts_oxid_MASK       0x0000FFFF
 335 #define lpfc_abts_oxid_WORD       word2
 336         uint32_t word3;
 337 #define lpfc_vndr_code_SHIFT    0
 338 #define lpfc_vndr_code_MASK     0x000000FF
 339 #define lpfc_vndr_code_WORD     word3
 340 #define lpfc_rsn_expln_SHIFT    8
 341 #define lpfc_rsn_expln_MASK     0x000000FF
 342 #define lpfc_rsn_expln_WORD     word3
 343 #define lpfc_rsn_code_SHIFT     16
 344 #define lpfc_rsn_code_MASK      0x000000FF
 345 #define lpfc_rsn_code_WORD      word3
 346
 347         uint32_t word4;
 348         uint32_t word5_rsvd;    /* Word5 must be reserved */
 349 };
 350
 351 /* event queue entry structure */
 352 struct lpfc_eqe {
 353         uint32_t word0;
 354 #define lpfc_eqe_resource_id_SHIFT      16
 355 #define lpfc_eqe_resource_id_MASK       0x0000FFFF
 356 #define lpfc_eqe_resource_id_WORD       word0
 357 #define lpfc_eqe_minor_code_SHIFT       4
 358 #define lpfc_eqe_minor_code_MASK        0x00000FFF
 359 #define lpfc_eqe_minor_code_WORD        word0
 360 #define lpfc_eqe_major_code_SHIFT       1
 361 #define lpfc_eqe_major_code_MASK        0x00000007
 362 #define lpfc_eqe_major_code_WORD        word0
 363 #define lpfc_eqe_valid_SHIFT            0
 364 #define lpfc_eqe_valid_MASK             0x00000001
 365 #define lpfc_eqe_valid_WORD             word0
 366 };
 367
 368 /* completion queue entry structure (common fields for all cqe types) */
 369 struct lpfc_cqe {
 370         uint32_t reserved0;
 371         uint32_t reserved1;
 372         uint32_t reserved2;
 373         uint32_t word3;
 374 #define lpfc_cqe_valid_SHIFT            31
 375 #define lpfc_cqe_valid_MASK             0x00000001
 376 #define lpfc_cqe_valid_WORD             word3
 377 #define lpfc_cqe_code_SHIFT             16
 378 #define lpfc_cqe_code_MASK              0x000000FF
 379 #define lpfc_cqe_code_WORD              word3
 380 };
 381
 382 /* Completion Queue Entry Status Codes */
 383 #define CQE_STATUS_SUCCESS              0x0
 384 #define CQE_STATUS_FCP_RSP_FAILURE      0x1
 385 #define CQE_STATUS_REMOTE_STOP          0x2
 386 #define CQE_STATUS_LOCAL_REJECT         0x3
 387 #define CQE_STATUS_NPORT_RJT            0x4
 388 #define CQE_STATUS_FABRIC_RJT           0x5
 389 #define CQE_STATUS_NPORT_BSY            0x6
 390 #define CQE_STATUS_FABRIC_BSY           0x7
 391 #define CQE_STATUS_INTERMED_RSP         0x8
 392 #define CQE_STATUS_LS_RJT               0x9
 393 #define CQE_STATUS_CMD_REJECT           0xb
 394 #define CQE_STATUS_FCP_TGT_LENCHECK     0xc
 395 #define CQE_STATUS_NEED_BUFF_ENTRY      0xf
 396 #define CQE_STATUS_DI_ERROR             0x16
 397
 398 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
 399 #define CQE_HW_STATUS_NO_ERR            0x0
 400 #define CQE_HW_STATUS_UNDERRUN          0x1
 401 #define CQE_HW_STATUS_OVERRUN           0x2
 402
 403 /* Completion Queue Entry Codes */
 404 #define CQE_CODE_COMPL_WQE              0x1
 405 #define CQE_CODE_RELEASE_WQE            0x2
 406 #define CQE_CODE_RECEIVE                0x4
 407 #define CQE_CODE_XRI_ABORTED            0x5
 408 #define CQE_CODE_RECEIVE_V1             0x9
 409 #define CQE_CODE_NVME_ERSP              0xd
 410
 411 /*
 412  * Define mask value for xri_aborted and wcqe completed CQE extended status.
 413  * Currently, extended status is limited to 9 bits (0x0 -> 0x103) .
 414  */
 415 #define WCQE_PARAM_MASK         0x1FF
 416
 417 /* completion queue entry for wqe completions */
 418 struct lpfc_wcqe_complete {
 419         uint32_t word0;
 420 #define lpfc_wcqe_c_request_tag_SHIFT   16
 421 #define lpfc_wcqe_c_request_tag_MASK    0x0000FFFF
 422 #define lpfc_wcqe_c_request_tag_WORD    word0
 423 #define lpfc_wcqe_c_status_SHIFT        8
 424 #define lpfc_wcqe_c_status_MASK         0x000000FF
 425 #define lpfc_wcqe_c_status_WORD         word0
 426 #define lpfc_wcqe_c_hw_status_SHIFT     0
 427 #define lpfc_wcqe_c_hw_status_MASK      0x000000FF
 428 #define lpfc_wcqe_c_hw_status_WORD      word0
 429 #define lpfc_wcqe_c_ersp0_SHIFT         0
 430 #define lpfc_wcqe_c_ersp0_MASK          0x0000FFFF
 431 #define lpfc_wcqe_c_ersp0_WORD          word0
 432         uint32_t total_data_placed;
 433 #define lpfc_wcqe_c_cmf_cg_SHIFT        31
 434 #define lpfc_wcqe_c_cmf_cg_MASK         0x00000001
 435 #define lpfc_wcqe_c_cmf_cg_WORD         total_data_placed
 436 #define lpfc_wcqe_c_cmf_bw_SHIFT        0
 437 #define lpfc_wcqe_c_cmf_bw_MASK         0x0FFFFFFF
 438 #define lpfc_wcqe_c_cmf_bw_WORD         total_data_placed
 439         uint32_t parameter;
 440 #define lpfc_wcqe_c_bg_edir_SHIFT       5
 441 #define lpfc_wcqe_c_bg_edir_MASK        0x00000001
 442 #define lpfc_wcqe_c_bg_edir_WORD        parameter
 443 #define lpfc_wcqe_c_bg_tdpv_SHIFT       3
 444 #define lpfc_wcqe_c_bg_tdpv_MASK        0x00000001
 445 #define lpfc_wcqe_c_bg_tdpv_WORD        parameter
 446 #define lpfc_wcqe_c_bg_re_SHIFT         2
 447 #define lpfc_wcqe_c_bg_re_MASK          0x00000001
 448 #define lpfc_wcqe_c_bg_re_WORD          parameter
 449 #define lpfc_wcqe_c_bg_ae_SHIFT         1
 450 #define lpfc_wcqe_c_bg_ae_MASK          0x00000001
 451 #define lpfc_wcqe_c_bg_ae_WORD          parameter
 452 #define lpfc_wcqe_c_bg_ge_SHIFT         0
 453 #define lpfc_wcqe_c_bg_ge_MASK          0x00000001
 454 #define lpfc_wcqe_c_bg_ge_WORD          parameter
 455         uint32_t word3;
 456 #define lpfc_wcqe_c_valid_SHIFT         lpfc_cqe_valid_SHIFT
 457 #define lpfc_wcqe_c_valid_MASK          lpfc_cqe_valid_MASK
 458 #define lpfc_wcqe_c_valid_WORD          lpfc_cqe_valid_WORD
 459 #define lpfc_wcqe_c_xb_SHIFT            28
 460 #define lpfc_wcqe_c_xb_MASK             0x00000001
 461 #define lpfc_wcqe_c_xb_WORD             word3
 462 #define lpfc_wcqe_c_pv_SHIFT            27
 463 #define lpfc_wcqe_c_pv_MASK             0x00000001
 464 #define lpfc_wcqe_c_pv_WORD             word3
 465 #define lpfc_wcqe_c_priority_SHIFT      24
 466 #define lpfc_wcqe_c_priority_MASK       0x00000007
 467 #define lpfc_wcqe_c_priority_WORD       word3
 468 #define lpfc_wcqe_c_code_SHIFT          lpfc_cqe_code_SHIFT
 469 #define lpfc_wcqe_c_code_MASK           lpfc_cqe_code_MASK
 470 #define lpfc_wcqe_c_code_WORD           lpfc_cqe_code_WORD
 471 #define lpfc_wcqe_c_sqhead_SHIFT        0
 472 #define lpfc_wcqe_c_sqhead_MASK         0x0000FFFF
 473 #define lpfc_wcqe_c_sqhead_WORD         word3
 474 };
 475
 476 /* completion queue entry for wqe release */
 477 struct lpfc_wcqe_release {
 478         uint32_t reserved0;
 479         uint32_t reserved1;
 480         uint32_t word2;
 481 #define lpfc_wcqe_r_wq_id_SHIFT         16
 482 #define lpfc_wcqe_r_wq_id_MASK          0x0000FFFF
 483 #define lpfc_wcqe_r_wq_id_WORD          word2
 484 #define lpfc_wcqe_r_wqe_index_SHIFT     0
 485 #define lpfc_wcqe_r_wqe_index_MASK      0x0000FFFF
 486 #define lpfc_wcqe_r_wqe_index_WORD      word2
 487         uint32_t word3;
 488 #define lpfc_wcqe_r_valid_SHIFT         lpfc_cqe_valid_SHIFT
 489 #define lpfc_wcqe_r_valid_MASK          lpfc_cqe_valid_MASK
 490 #define lpfc_wcqe_r_valid_WORD          lpfc_cqe_valid_WORD
 491 #define lpfc_wcqe_r_code_SHIFT          lpfc_cqe_code_SHIFT
 492 #define lpfc_wcqe_r_code_MASK           lpfc_cqe_code_MASK
 493 #define lpfc_wcqe_r_code_WORD           lpfc_cqe_code_WORD
 494 };
 495
 496 struct sli4_wcqe_xri_aborted {
 497         uint32_t word0;
 498 #define lpfc_wcqe_xa_status_SHIFT               8
 499 #define lpfc_wcqe_xa_status_MASK                0x000000FF
 500 #define lpfc_wcqe_xa_status_WORD                word0
 501         uint32_t parameter;
 502         uint32_t word2;
 503 #define lpfc_wcqe_xa_remote_xid_SHIFT   16
 504 #define lpfc_wcqe_xa_remote_xid_MASK    0x0000FFFF
 505 #define lpfc_wcqe_xa_remote_xid_WORD    word2
 506 #define lpfc_wcqe_xa_xri_SHIFT          0
 507 #define lpfc_wcqe_xa_xri_MASK           0x0000FFFF
 508 #define lpfc_wcqe_xa_xri_WORD           word2
 509         uint32_t word3;
 510 #define lpfc_wcqe_xa_valid_SHIFT        lpfc_cqe_valid_SHIFT
 511 #define lpfc_wcqe_xa_valid_MASK         lpfc_cqe_valid_MASK
 512 #define lpfc_wcqe_xa_valid_WORD         lpfc_cqe_valid_WORD
 513 #define lpfc_wcqe_xa_ia_SHIFT           30
 514 #define lpfc_wcqe_xa_ia_MASK            0x00000001
 515 #define lpfc_wcqe_xa_ia_WORD            word3
 516 #define CQE_XRI_ABORTED_IA_REMOTE       0
 517 #define CQE_XRI_ABORTED_IA_LOCAL        1
 518 #define lpfc_wcqe_xa_br_SHIFT           29
 519 #define lpfc_wcqe_xa_br_MASK            0x00000001
 520 #define lpfc_wcqe_xa_br_WORD            word3
 521 #define CQE_XRI_ABORTED_BR_BA_ACC       0
 522 #define CQE_XRI_ABORTED_BR_BA_RJT       1
 523 #define lpfc_wcqe_xa_eo_SHIFT           28
 524 #define lpfc_wcqe_xa_eo_MASK            0x00000001
 525 #define lpfc_wcqe_xa_eo_WORD            word3
 526 #define CQE_XRI_ABORTED_EO_REMOTE       0
 527 #define CQE_XRI_ABORTED_EO_LOCAL        1
 528 #define lpfc_wcqe_xa_code_SHIFT         lpfc_cqe_code_SHIFT
 529 #define lpfc_wcqe_xa_code_MASK          lpfc_cqe_code_MASK
 530 #define lpfc_wcqe_xa_code_WORD          lpfc_cqe_code_WORD
 531 };
 532
 533 /* completion queue entry structure for rqe completion */
 534 struct lpfc_rcqe {
 535         uint32_t word0;
 536 #define lpfc_rcqe_iv_SHIFT              31
 537 #define lpfc_rcqe_iv_MASK               0x00000001
 538 #define lpfc_rcqe_iv_WORD               word0
 539 #define lpfc_rcqe_status_SHIFT          8
 540 #define lpfc_rcqe_status_MASK           0x000000FF
 541 #define lpfc_rcqe_status_WORD           word0
 542 #define FC_STATUS_RQ_SUCCESS            0x10 /* Async receive successful */
 543 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED   0x11 /* payload truncated */
 544 #define FC_STATUS_INSUFF_BUF_NEED_BUF   0x12 /* Insufficient buffers */
 545 #define FC_STATUS_INSUFF_BUF_FRM_DISC   0x13 /* Frame Discard */
 546 #define FC_STATUS_RQ_DMA_FAILURE        0x14 /* DMA failure */
 547         uint32_t word1;
 548 #define lpfc_rcqe_fcf_id_v1_SHIFT       0
 549 #define lpfc_rcqe_fcf_id_v1_MASK        0x0000003F
 550 #define lpfc_rcqe_fcf_id_v1_WORD        word1
 551         uint32_t word2;
 552 #define lpfc_rcqe_length_SHIFT          16
 553 #define lpfc_rcqe_length_MASK           0x0000FFFF
 554 #define lpfc_rcqe_length_WORD           word2
 555 #define lpfc_rcqe_rq_id_SHIFT           6
 556 #define lpfc_rcqe_rq_id_MASK            0x000003FF
 557 #define lpfc_rcqe_rq_id_WORD            word2
 558 #define lpfc_rcqe_fcf_id_SHIFT          0
 559 #define lpfc_rcqe_fcf_id_MASK           0x0000003F
 560 #define lpfc_rcqe_fcf_id_WORD           word2
 561 #define lpfc_rcqe_rq_id_v1_SHIFT        0
 562 #define lpfc_rcqe_rq_id_v1_MASK         0x0000FFFF
 563 #define lpfc_rcqe_rq_id_v1_WORD         word2
 564         uint32_t word3;
 565 #define lpfc_rcqe_valid_SHIFT           lpfc_cqe_valid_SHIFT
 566 #define lpfc_rcqe_valid_MASK            lpfc_cqe_valid_MASK
 567 #define lpfc_rcqe_valid_WORD            lpfc_cqe_valid_WORD
 568 #define lpfc_rcqe_port_SHIFT            30
 569 #define lpfc_rcqe_port_MASK             0x00000001
 570 #define lpfc_rcqe_port_WORD             word3
 571 #define lpfc_rcqe_hdr_length_SHIFT      24
 572 #define lpfc_rcqe_hdr_length_MASK       0x0000001F
 573 #define lpfc_rcqe_hdr_length_WORD       word3
 574 #define lpfc_rcqe_code_SHIFT            lpfc_cqe_code_SHIFT
 575 #define lpfc_rcqe_code_MASK             lpfc_cqe_code_MASK
 576 #define lpfc_rcqe_code_WORD             lpfc_cqe_code_WORD
 577 #define lpfc_rcqe_eof_SHIFT             8
 578 #define lpfc_rcqe_eof_MASK              0x000000FF
 579 #define lpfc_rcqe_eof_WORD              word3
 580 #define FCOE_EOFn       0x41
 581 #define FCOE_EOFt       0x42
 582 #define FCOE_EOFni      0x49
 583 #define FCOE_EOFa       0x50
 584 #define lpfc_rcqe_sof_SHIFT             0
 585 #define lpfc_rcqe_sof_MASK              0x000000FF
 586 #define lpfc_rcqe_sof_WORD              word3
 587 #define FCOE_SOFi2      0x2d
 588 #define FCOE_SOFi3      0x2e
 589 #define FCOE_SOFn2      0x35
 590 #define FCOE_SOFn3      0x36
 591 };
 592
 593 struct lpfc_rqe {
 594         uint32_t address_hi;
 595         uint32_t address_lo;
 596 };
 597
 598 /* buffer descriptors */
 599 struct lpfc_bde4 {
 600         uint32_t addr_hi;
 601         uint32_t addr_lo;
 602         uint32_t word2;
 603 #define lpfc_bde4_last_SHIFT            31
 604 #define lpfc_bde4_last_MASK             0x00000001
 605 #define lpfc_bde4_last_WORD             word2
 606 #define lpfc_bde4_sge_offset_SHIFT      0
 607 #define lpfc_bde4_sge_offset_MASK       0x000003FF
 608 #define lpfc_bde4_sge_offset_WORD       word2
 609         uint32_t word3;
 610 #define lpfc_bde4_length_SHIFT          0
 611 #define lpfc_bde4_length_MASK           0x000000FF
 612 #define lpfc_bde4_length_WORD           word3
 613 };
 614
 615 struct lpfc_register {
 616         uint32_t word0;
 617 };
 618
 619 #define LPFC_PORT_SEM_UE_RECOVERABLE    0xE000
 620 #define LPFC_PORT_SEM_MASK              0xF000
 621 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
 622 #define LPFC_UERR_STATUS_HI             0x00A4
 623 #define LPFC_UERR_STATUS_LO             0x00A0
 624 #define LPFC_UE_MASK_HI                 0x00AC
 625 #define LPFC_UE_MASK_LO                 0x00A8
 626
 627 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
 628 #define LPFC_SLI_INTF                   0x0058
 629 #define LPFC_SLI_ASIC_VER               0x009C
 630
 631 #define LPFC_CTL_PORT_SEM_OFFSET        0x400
 632 #define lpfc_port_smphr_perr_SHIFT      31
 633 #define lpfc_port_smphr_perr_MASK       0x1
 634 #define lpfc_port_smphr_perr_WORD       word0
 635 #define lpfc_port_smphr_sfi_SHIFT       30
 636 #define lpfc_port_smphr_sfi_MASK        0x1
 637 #define lpfc_port_smphr_sfi_WORD        word0
 638 #define lpfc_port_smphr_nip_SHIFT       29
 639 #define lpfc_port_smphr_nip_MASK        0x1
 640 #define lpfc_port_smphr_nip_WORD        word0
 641 #define lpfc_port_smphr_ipc_SHIFT       28
 642 #define lpfc_port_smphr_ipc_MASK        0x1
 643 #define lpfc_port_smphr_ipc_WORD        word0
 644 #define lpfc_port_smphr_scr1_SHIFT      27
 645 #define lpfc_port_smphr_scr1_MASK       0x1
 646 #define lpfc_port_smphr_scr1_WORD       word0
 647 #define lpfc_port_smphr_scr2_SHIFT      26
 648 #define lpfc_port_smphr_scr2_MASK       0x1
 649 #define lpfc_port_smphr_scr2_WORD       word0
 650 #define lpfc_port_smphr_host_scratch_SHIFT      16
 651 #define lpfc_port_smphr_host_scratch_MASK       0xFF
 652 #define lpfc_port_smphr_host_scratch_WORD       word0
 653 #define lpfc_port_smphr_port_status_SHIFT       0
 654 #define lpfc_port_smphr_port_status_MASK        0xFFFF
 655 #define lpfc_port_smphr_port_status_WORD        word0
 656
 657 #define LPFC_POST_STAGE_POWER_ON_RESET                  0x0000
 658 #define LPFC_POST_STAGE_AWAITING_HOST_RDY               0x0001
 659 #define LPFC_POST_STAGE_HOST_RDY                        0x0002
 660 #define LPFC_POST_STAGE_BE_RESET                        0x0003
 661 #define LPFC_POST_STAGE_SEEPROM_CS_START                0x0100
 662 #define LPFC_POST_STAGE_SEEPROM_CS_DONE                 0x0101
 663 #define LPFC_POST_STAGE_DDR_CONFIG_START                0x0200
 664 #define LPFC_POST_STAGE_DDR_CONFIG_DONE                 0x0201
 665 #define LPFC_POST_STAGE_DDR_CALIBRATE_START             0x0300
 666 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE              0x0301
 667 #define LPFC_POST_STAGE_DDR_TEST_START                  0x0400
 668 #define LPFC_POST_STAGE_DDR_TEST_DONE                   0x0401
 669 #define LPFC_POST_STAGE_REDBOOT_INIT_START              0x0600
 670 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE               0x0601
 671 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START             0x0700
 672 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE              0x0701
 673 #define LPFC_POST_STAGE_ARMFW_START                     0x0800
 674 #define LPFC_POST_STAGE_DHCP_QUERY_START                0x0900
 675 #define LPFC_POST_STAGE_DHCP_QUERY_DONE                 0x0901
 676 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START     0x0A00
 677 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE      0x0A01
 678 #define LPFC_POST_STAGE_RC_OPTION_SET                   0x0B00
 679 #define LPFC_POST_STAGE_SWITCH_LINK                     0x0B01
 680 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE               0x0B02
 681 #define LPFC_POST_STAGE_PERFROM_TFTP                    0x0B03
 682 #define LPFC_POST_STAGE_PARSE_XML                       0x0B04
 683 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE                  0x0B05
 684 #define LPFC_POST_STAGE_FLASH_IMAGE                     0x0B06
 685 #define LPFC_POST_STAGE_RC_DONE                         0x0B07
 686 #define LPFC_POST_STAGE_REBOOT_SYSTEM                   0x0B08
 687 #define LPFC_POST_STAGE_MAC_ADDRESS                     0x0C00
 688 #define LPFC_POST_STAGE_PORT_READY                      0xC000
 689 #define LPFC_POST_STAGE_PORT_UE                         0xF000
 690
 691 #define LPFC_CTL_PORT_STA_OFFSET        0x404
 692 #define lpfc_sliport_status_err_SHIFT   31
 693 #define lpfc_sliport_status_err_MASK    0x1
 694 #define lpfc_sliport_status_err_WORD    word0
 695 #define lpfc_sliport_status_end_SHIFT   30
 696 #define lpfc_sliport_status_end_MASK    0x1
 697 #define lpfc_sliport_status_end_WORD    word0
 698 #define lpfc_sliport_status_oti_SHIFT   29
 699 #define lpfc_sliport_status_oti_MASK    0x1
 700 #define lpfc_sliport_status_oti_WORD    word0
 701 #define lpfc_sliport_status_dip_SHIFT   25
 702 #define lpfc_sliport_status_dip_MASK    0x1
 703 #define lpfc_sliport_status_dip_WORD    word0
 704 #define lpfc_sliport_status_rn_SHIFT    24
 705 #define lpfc_sliport_status_rn_MASK     0x1
 706 #define lpfc_sliport_status_rn_WORD     word0
 707 #define lpfc_sliport_status_rdy_SHIFT   23
 708 #define lpfc_sliport_status_rdy_MASK    0x1
 709 #define lpfc_sliport_status_rdy_WORD    word0
 710 #define lpfc_sliport_status_pldv_SHIFT  0
 711 #define lpfc_sliport_status_pldv_MASK   0x1
 712 #define lpfc_sliport_status_pldv_WORD   word0
 713 #define CFG_PLD                         0x3C
 714 #define MAX_IF_TYPE_2_RESETS            6
 715
 716 #define LPFC_CTL_PORT_CTL_OFFSET        0x408
 717 #define lpfc_sliport_ctrl_end_SHIFT     30
 718 #define lpfc_sliport_ctrl_end_MASK      0x1
 719 #define lpfc_sliport_ctrl_end_WORD      word0
 720 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
 721 #define LPFC_SLIPORT_BIG_ENDIAN    1
 722 #define lpfc_sliport_ctrl_ip_SHIFT      27
 723 #define lpfc_sliport_ctrl_ip_MASK       0x1
 724 #define lpfc_sliport_ctrl_ip_WORD       word0
 725 #define LPFC_SLIPORT_INIT_PORT  1
 726
 727 #define LPFC_CTL_PORT_ER1_OFFSET        0x40C
 728 #define LPFC_CTL_PORT_ER2_OFFSET        0x410
 729
 730 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET   0x418
 731 #define lpfc_sliport_eqdelay_delay_SHIFT 16
 732 #define lpfc_sliport_eqdelay_delay_MASK 0xffff
 733 #define lpfc_sliport_eqdelay_delay_WORD word0
 734 #define lpfc_sliport_eqdelay_id_SHIFT   0
 735 #define lpfc_sliport_eqdelay_id_MASK    0xfff
 736 #define lpfc_sliport_eqdelay_id_WORD    word0
 737 #define LPFC_SEC_TO_USEC                1000000
 738 #define LPFC_SEC_TO_MSEC                1000
 739 #define LPFC_MSECS_TO_SECS(msecs) ((msecs) / 1000)
 740
 741 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
 742  * reside in BAR 2.
 743  */
 744 #define LPFC_SLIPORT_IF0_SMPHR  0x00AC
 745
 746 #define LPFC_IMR_MASK_ALL       0xFFFFFFFF
 747 #define LPFC_ISCR_CLEAR_ALL     0xFFFFFFFF
 748
 749 #define LPFC_HST_ISR0           0x0C18
 750 #define LPFC_HST_ISR1           0x0C1C
 751 #define LPFC_HST_ISR2           0x0C20
 752 #define LPFC_HST_ISR3           0x0C24
 753 #define LPFC_HST_ISR4           0x0C28
 754
 755 #define LPFC_HST_IMR0           0x0C48
 756 #define LPFC_HST_IMR1           0x0C4C
 757 #define LPFC_HST_IMR2           0x0C50
 758 #define LPFC_HST_IMR3           0x0C54
 759 #define LPFC_HST_IMR4           0x0C58
 760
 761 #define LPFC_HST_ISCR0          0x0C78
 762 #define LPFC_HST_ISCR1          0x0C7C
 763 #define LPFC_HST_ISCR2          0x0C80
 764 #define LPFC_HST_ISCR3          0x0C84
 765 #define LPFC_HST_ISCR4          0x0C88
 766
 767 #define LPFC_SLI4_INTR0                 BIT0
 768 #define LPFC_SLI4_INTR1                 BIT1
 769 #define LPFC_SLI4_INTR2                 BIT2
 770 #define LPFC_SLI4_INTR3                 BIT3
 771 #define LPFC_SLI4_INTR4                 BIT4
 772 #define LPFC_SLI4_INTR5                 BIT5
 773 #define LPFC_SLI4_INTR6                 BIT6
 774 #define LPFC_SLI4_INTR7                 BIT7
 775 #define LPFC_SLI4_INTR8                 BIT8
 776 #define LPFC_SLI4_INTR9                 BIT9
 777 #define LPFC_SLI4_INTR10                BIT10
 778 #define LPFC_SLI4_INTR11                BIT11
 779 #define LPFC_SLI4_INTR12                BIT12
 780 #define LPFC_SLI4_INTR13                BIT13
 781 #define LPFC_SLI4_INTR14                BIT14
 782 #define LPFC_SLI4_INTR15                BIT15
 783 #define LPFC_SLI4_INTR16                BIT16
 784 #define LPFC_SLI4_INTR17                BIT17
 785 #define LPFC_SLI4_INTR18                BIT18
 786 #define LPFC_SLI4_INTR19                BIT19
 787 #define LPFC_SLI4_INTR20                BIT20
 788 #define LPFC_SLI4_INTR21                BIT21
 789 #define LPFC_SLI4_INTR22                BIT22
 790 #define LPFC_SLI4_INTR23                BIT23
 791 #define LPFC_SLI4_INTR24                BIT24
 792 #define LPFC_SLI4_INTR25                BIT25
 793 #define LPFC_SLI4_INTR26                BIT26
 794 #define LPFC_SLI4_INTR27                BIT27
 795 #define LPFC_SLI4_INTR28                BIT28
 796 #define LPFC_SLI4_INTR29                BIT29
 797 #define LPFC_SLI4_INTR30                BIT30
 798 #define LPFC_SLI4_INTR31                BIT31
 799
 800 /*
 801  * The Doorbell registers defined here exist in different BAR
 802  * register sets depending on the UCNA Port's reported if_type
 803  * value.  For UCNA ports running SLI4 and if_type 0, they reside in
 804  * BAR4.  For UCNA ports running SLI4 and if_type 2, they reside in
 805  * BAR0.  For FC ports running SLI4 and if_type 6, they reside in
 806  * BAR2. The offsets and base address are different,  so the driver
 807  * has to compute the register addresses accordingly
 808  */
 809 #define LPFC_ULP0_RQ_DOORBELL           0x00A0
 810 #define LPFC_ULP1_RQ_DOORBELL           0x00C0
 811 #define LPFC_IF6_RQ_DOORBELL            0x0080
 812 #define lpfc_rq_db_list_fm_num_posted_SHIFT     24
 813 #define lpfc_rq_db_list_fm_num_posted_MASK      0x00FF
 814 #define lpfc_rq_db_list_fm_num_posted_WORD      word0
 815 #define lpfc_rq_db_list_fm_index_SHIFT          16
 816 #define lpfc_rq_db_list_fm_index_MASK           0x00FF
 817 #define lpfc_rq_db_list_fm_index_WORD           word0
 818 #define lpfc_rq_db_list_fm_id_SHIFT             0
 819 #define lpfc_rq_db_list_fm_id_MASK              0xFFFF
 820 #define lpfc_rq_db_list_fm_id_WORD              word0
 821 #define lpfc_rq_db_ring_fm_num_posted_SHIFT     16
 822 #define lpfc_rq_db_ring_fm_num_posted_MASK      0x3FFF
 823 #define lpfc_rq_db_ring_fm_num_posted_WORD      word0
 824 #define lpfc_rq_db_ring_fm_id_SHIFT             0
 825 #define lpfc_rq_db_ring_fm_id_MASK              0xFFFF
 826 #define lpfc_rq_db_ring_fm_id_WORD              word0
 827
 828 #define LPFC_ULP0_WQ_DOORBELL           0x0040
 829 #define LPFC_ULP1_WQ_DOORBELL           0x0060
 830 #define lpfc_wq_db_list_fm_num_posted_SHIFT     24
 831 #define lpfc_wq_db_list_fm_num_posted_MASK      0x00FF
 832 #define lpfc_wq_db_list_fm_num_posted_WORD      word0
 833 #define lpfc_wq_db_list_fm_index_SHIFT          16
 834 #define lpfc_wq_db_list_fm_index_MASK           0x00FF
 835 #define lpfc_wq_db_list_fm_index_WORD           word0
 836 #define lpfc_wq_db_list_fm_id_SHIFT             0
 837 #define lpfc_wq_db_list_fm_id_MASK              0xFFFF
 838 #define lpfc_wq_db_list_fm_id_WORD              word0
 839 #define lpfc_wq_db_ring_fm_num_posted_SHIFT     16
 840 #define lpfc_wq_db_ring_fm_num_posted_MASK      0x3FFF
 841 #define lpfc_wq_db_ring_fm_num_posted_WORD      word0
 842 #define lpfc_wq_db_ring_fm_id_SHIFT             0
 843 #define lpfc_wq_db_ring_fm_id_MASK              0xFFFF
 844 #define lpfc_wq_db_ring_fm_id_WORD              word0
 845
 846 #define LPFC_IF6_WQ_DOORBELL            0x0040
 847 #define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24
 848 #define lpfc_if6_wq_db_list_fm_num_posted_MASK  0x00FF
 849 #define lpfc_if6_wq_db_list_fm_num_posted_WORD  word0
 850 #define lpfc_if6_wq_db_list_fm_dpp_SHIFT        23
 851 #define lpfc_if6_wq_db_list_fm_dpp_MASK         0x0001
 852 #define lpfc_if6_wq_db_list_fm_dpp_WORD         word0
 853 #define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT     16
 854 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK      0x001F
 855 #define lpfc_if6_wq_db_list_fm_dpp_id_WORD      word0
 856 #define lpfc_if6_wq_db_list_fm_id_SHIFT         0
 857 #define lpfc_if6_wq_db_list_fm_id_MASK          0xFFFF
 858 #define lpfc_if6_wq_db_list_fm_id_WORD          word0
 859
 860 #define LPFC_EQCQ_DOORBELL              0x0120
 861 #define lpfc_eqcq_doorbell_se_SHIFT             31
 862 #define lpfc_eqcq_doorbell_se_MASK              0x0001
 863 #define lpfc_eqcq_doorbell_se_WORD              word0
 864 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF    0
 865 #define LPFC_EQCQ_SOLICIT_ENABLE_ON     1
 866 #define lpfc_eqcq_doorbell_arm_SHIFT            29
 867 #define lpfc_eqcq_doorbell_arm_MASK             0x0001
 868 #define lpfc_eqcq_doorbell_arm_WORD             word0
 869 #define lpfc_eqcq_doorbell_num_released_SHIFT   16
 870 #define lpfc_eqcq_doorbell_num_released_MASK    0x1FFF
 871 #define lpfc_eqcq_doorbell_num_released_WORD    word0
 872 #define lpfc_eqcq_doorbell_qt_SHIFT             10
 873 #define lpfc_eqcq_doorbell_qt_MASK              0x0001
 874 #define lpfc_eqcq_doorbell_qt_WORD              word0
 875 #define LPFC_QUEUE_TYPE_COMPLETION      0
 876 #define LPFC_QUEUE_TYPE_EVENT           1
 877 #define lpfc_eqcq_doorbell_eqci_SHIFT           9
 878 #define lpfc_eqcq_doorbell_eqci_MASK            0x0001
 879 #define lpfc_eqcq_doorbell_eqci_WORD            word0
 880 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT        0
 881 #define lpfc_eqcq_doorbell_cqid_lo_MASK         0x03FF
 882 #define lpfc_eqcq_doorbell_cqid_lo_WORD         word0
 883 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT        11
 884 #define lpfc_eqcq_doorbell_cqid_hi_MASK         0x001F
 885 #define lpfc_eqcq_doorbell_cqid_hi_WORD         word0
 886 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT        0
 887 #define lpfc_eqcq_doorbell_eqid_lo_MASK         0x01FF
 888 #define lpfc_eqcq_doorbell_eqid_lo_WORD         word0
 889 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT        11
 890 #define lpfc_eqcq_doorbell_eqid_hi_MASK         0x001F
 891 #define lpfc_eqcq_doorbell_eqid_hi_WORD         word0
 892 #define LPFC_CQID_HI_FIELD_SHIFT                10
 893 #define LPFC_EQID_HI_FIELD_SHIFT                9
 894
 895 #define LPFC_IF6_CQ_DOORBELL                    0x00C0
 896 #define lpfc_if6_cq_doorbell_se_SHIFT           31
 897 #define lpfc_if6_cq_doorbell_se_MASK            0x0001
 898 #define lpfc_if6_cq_doorbell_se_WORD            word0
 899 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF          0
 900 #define LPFC_IF6_CQ_SOLICIT_ENABLE_ON           1
 901 #define lpfc_if6_cq_doorbell_arm_SHIFT          29
 902 #define lpfc_if6_cq_doorbell_arm_MASK           0x0001
 903 #define lpfc_if6_cq_doorbell_arm_WORD           word0
 904 #define lpfc_if6_cq_doorbell_num_released_SHIFT 16
 905 #define lpfc_if6_cq_doorbell_num_released_MASK  0x1FFF
 906 #define lpfc_if6_cq_doorbell_num_released_WORD  word0
 907 #define lpfc_if6_cq_doorbell_cqid_SHIFT         0
 908 #define lpfc_if6_cq_doorbell_cqid_MASK          0xFFFF
 909 #define lpfc_if6_cq_doorbell_cqid_WORD          word0
 910
 911 #define LPFC_IF6_EQ_DOORBELL                    0x0120
 912 #define lpfc_if6_eq_doorbell_io_SHIFT           31
 913 #define lpfc_if6_eq_doorbell_io_MASK            0x0001
 914 #define lpfc_if6_eq_doorbell_io_WORD            word0
 915 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF           0
 916 #define LPFC_IF6_EQ_INTR_OVERRIDE_ON            1
 917 #define lpfc_if6_eq_doorbell_arm_SHIFT          29
 918 #define lpfc_if6_eq_doorbell_arm_MASK           0x0001
 919 #define lpfc_if6_eq_doorbell_arm_WORD           word0
 920 #define lpfc_if6_eq_doorbell_num_released_SHIFT 16
 921 #define lpfc_if6_eq_doorbell_num_released_MASK  0x1FFF
 922 #define lpfc_if6_eq_doorbell_num_released_WORD  word0
 923 #define lpfc_if6_eq_doorbell_eqid_SHIFT         0
 924 #define lpfc_if6_eq_doorbell_eqid_MASK          0x0FFF
 925 #define lpfc_if6_eq_doorbell_eqid_WORD          word0
 926
 927 #define LPFC_BMBX                       0x0160
 928 #define lpfc_bmbx_addr_SHIFT            2
 929 #define lpfc_bmbx_addr_MASK             0x3FFFFFFF
 930 #define lpfc_bmbx_addr_WORD             word0
 931 #define lpfc_bmbx_hi_SHIFT              1
 932 #define lpfc_bmbx_hi_MASK               0x0001
 933 #define lpfc_bmbx_hi_WORD               word0
 934 #define lpfc_bmbx_rdy_SHIFT             0
 935 #define lpfc_bmbx_rdy_MASK              0x0001
 936 #define lpfc_bmbx_rdy_WORD              word0
 937
 938 #define LPFC_MQ_DOORBELL                        0x0140
 939 #define LPFC_IF6_MQ_DOORBELL                    0x0160
 940 #define lpfc_mq_doorbell_num_posted_SHIFT       16
 941 #define lpfc_mq_doorbell_num_posted_MASK        0x3FFF
 942 #define lpfc_mq_doorbell_num_posted_WORD        word0
 943 #define lpfc_mq_doorbell_id_SHIFT               0
 944 #define lpfc_mq_doorbell_id_MASK                0xFFFF
 945 #define lpfc_mq_doorbell_id_WORD                word0
 946
 947 struct lpfc_sli4_cfg_mhdr {
 948         uint32_t word1;
 949 #define lpfc_mbox_hdr_emb_SHIFT         0
 950 #define lpfc_mbox_hdr_emb_MASK          0x00000001
 951 #define lpfc_mbox_hdr_emb_WORD          word1
 952 #define lpfc_mbox_hdr_sge_cnt_SHIFT     3
 953 #define lpfc_mbox_hdr_sge_cnt_MASK      0x0000001F
 954 #define lpfc_mbox_hdr_sge_cnt_WORD      word1
 955         uint32_t payload_length;
 956         uint32_t tag_lo;
 957         uint32_t tag_hi;
 958         uint32_t reserved5;
 959 };
 960
 961 union lpfc_sli4_cfg_shdr {
 962         struct {
 963                 uint32_t word6;
 964 #define lpfc_mbox_hdr_opcode_SHIFT      0
 965 #define lpfc_mbox_hdr_opcode_MASK       0x000000FF
 966 #define lpfc_mbox_hdr_opcode_WORD       word6
 967 #define lpfc_mbox_hdr_subsystem_SHIFT   8
 968 #define lpfc_mbox_hdr_subsystem_MASK    0x000000FF
 969 #define lpfc_mbox_hdr_subsystem_WORD    word6
 970 #define lpfc_mbox_hdr_port_number_SHIFT 16
 971 #define lpfc_mbox_hdr_port_number_MASK  0x000000FF
 972 #define lpfc_mbox_hdr_port_number_WORD  word6
 973 #define lpfc_mbox_hdr_domain_SHIFT      24
 974 #define lpfc_mbox_hdr_domain_MASK       0x000000FF
 975 #define lpfc_mbox_hdr_domain_WORD       word6
 976                 uint32_t timeout;
 977                 uint32_t request_length;
 978                 uint32_t word9;
 979 #define lpfc_mbox_hdr_version_SHIFT     0
 980 #define lpfc_mbox_hdr_version_MASK      0x000000FF
 981 #define lpfc_mbox_hdr_version_WORD      word9
 982 #define lpfc_mbox_hdr_pf_num_SHIFT      16
 983 #define lpfc_mbox_hdr_pf_num_MASK       0x000000FF
 984 #define lpfc_mbox_hdr_pf_num_WORD       word9
 985 #define lpfc_mbox_hdr_vh_num_SHIFT      24
 986 #define lpfc_mbox_hdr_vh_num_MASK       0x000000FF
 987 #define lpfc_mbox_hdr_vh_num_WORD       word9
 988 #define LPFC_Q_CREATE_VERSION_2 2
 989 #define LPFC_Q_CREATE_VERSION_1 1
 990 #define LPFC_Q_CREATE_VERSION_0 0
 991 #define LPFC_OPCODE_VERSION_0   0
 992 #define LPFC_OPCODE_VERSION_1   1
 993         } request;
 994         struct {
 995                 uint32_t word6;
 996 #define lpfc_mbox_hdr_opcode_SHIFT              0
 997 #define lpfc_mbox_hdr_opcode_MASK               0x000000FF
 998 #define lpfc_mbox_hdr_opcode_WORD               word6
 999 #define lpfc_mbox_hdr_subsystem_SHIFT           8
1000 #define lpfc_mbox_hdr_subsystem_MASK            0x000000FF
1001 #define lpfc_mbox_hdr_subsystem_WORD            word6
1002 #define lpfc_mbox_hdr_domain_SHIFT              24
1003 #define lpfc_mbox_hdr_domain_MASK               0x000000FF
1004 #define lpfc_mbox_hdr_domain_WORD               word6
1005                 uint32_t word7;
1006 #define lpfc_mbox_hdr_status_SHIFT              0
1007 #define lpfc_mbox_hdr_status_MASK               0x000000FF
1008 #define lpfc_mbox_hdr_status_WORD               word7
1009 #define lpfc_mbox_hdr_add_status_SHIFT          8
1010 #define lpfc_mbox_hdr_add_status_MASK           0x000000FF
1011 #define lpfc_mbox_hdr_add_status_WORD           word7
1012 #define LPFC_ADD_STATUS_INCOMPAT_OBJ            0xA2
1013 #define lpfc_mbox_hdr_add_status_2_SHIFT        16
1014 #define lpfc_mbox_hdr_add_status_2_MASK         0x000000FF
1015 #define lpfc_mbox_hdr_add_status_2_WORD         word7
1016 #define LPFC_ADD_STATUS_2_INCOMPAT_FLASH        0x01
1017 #define LPFC_ADD_STATUS_2_INCORRECT_ASIC        0x02
1018                 uint32_t response_length;
1019                 uint32_t actual_response_length;
1020         } response;
1021 };
1022
1023 /* Mailbox Header structures.
1024  * struct mbox_header is defined for first generation SLI4_CFG mailbox
1025  * calls deployed for BE-based ports.
1026  *
1027  * struct sli4_mbox_header is defined for second generation SLI4
1028  * ports that don't deploy the SLI4_CFG mechanism.
1029  */
1030 struct mbox_header {
1031         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
1032         union  lpfc_sli4_cfg_shdr cfg_shdr;
1033 };
1034
1035 #define LPFC_EXTENT_LOCAL               0
1036 #define LPFC_TIMEOUT_DEFAULT            0
1037 #define LPFC_EXTENT_VERSION_DEFAULT     0
1038
1039 /* Subsystem Definitions */
1040 #define LPFC_MBOX_SUBSYSTEM_NA          0x0
1041 #define LPFC_MBOX_SUBSYSTEM_COMMON      0x1
1042 #define LPFC_MBOX_SUBSYSTEM_LOWLEVEL    0xB
1043 #define LPFC_MBOX_SUBSYSTEM_FCOE        0xC
1044
1045 /* Device Specific Definitions */
1046
1047 /* The HOST ENDIAN defines are in Big Endian format. */
1048 #define HOST_ENDIAN_LOW_WORD0   0xFF3412FF
1049 #define HOST_ENDIAN_HIGH_WORD1  0xFF7856FF
1050
1051 /* Common Opcodes */
1052 #define LPFC_MBOX_OPCODE_NA                             0x00
1053 #define LPFC_MBOX_OPCODE_CQ_CREATE                      0x0C
1054 #define LPFC_MBOX_OPCODE_EQ_CREATE                      0x0D
1055 #define LPFC_MBOX_OPCODE_MQ_CREATE                      0x15
1056 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES            0x20
1057 #define LPFC_MBOX_OPCODE_NOP                            0x21
1058 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY                0x29
1059 #define LPFC_MBOX_OPCODE_MQ_DESTROY                     0x35
1060 #define LPFC_MBOX_OPCODE_CQ_DESTROY                     0x36
1061 #define LPFC_MBOX_OPCODE_EQ_DESTROY                     0x37
1062 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG                   0x3A
1063 #define LPFC_MBOX_OPCODE_FUNCTION_RESET                 0x3D
1064 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG       0x3E
1065 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG                0x43
1066 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG              0x45
1067 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG              0x46
1068 #define LPFC_MBOX_OPCODE_GET_PORT_NAME                  0x4D
1069 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT                  0x5A
1070 #define LPFC_MBOX_OPCODE_GET_VPD_DATA                   0x5B
1071 #define LPFC_MBOX_OPCODE_SET_HOST_DATA                  0x5D
1072 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION                0x73
1073 #define LPFC_MBOX_OPCODE_RESET_LICENSES                 0x74
1074 #define LPFC_MBOX_OPCODE_REG_CONGESTION_BUF             0x8E
1075 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO           0x9A
1076 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT          0x9B
1077 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT              0x9C
1078 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT            0x9D
1079 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG            0xA0
1080 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES         0xA1
1081 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG             0xA4
1082 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG             0xA5
1083 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST               0xA6
1084 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE                0xA8
1085 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG     0xA9
1086 #define LPFC_MBOX_OPCODE_READ_OBJECT                    0xAB
1087 #define LPFC_MBOX_OPCODE_WRITE_OBJECT                   0xAC
1088 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST               0xAD
1089 #define LPFC_MBOX_OPCODE_DELETE_OBJECT                  0xAE
1090 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS            0xB5
1091 #define LPFC_MBOX_OPCODE_SET_FEATURES                   0xBF
1092
1093 /* FCoE Opcodes */
1094 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE                 0x01
1095 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY                0x02
1096 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES            0x03
1097 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES          0x04
1098 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE                 0x05
1099 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY                0x06
1100 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE            0x08
1101 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF                   0x09
1102 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF                0x0A
1103 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE         0x0B
1104 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF            0x10
1105 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET             0x1D
1106 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS       0x21
1107 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE           0x22
1108 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK        0x23
1109 #define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE         0x42
1110
1111 /* Low level Opcodes */
1112 #define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION            0x37
1113
1114 /* Mailbox command structures */
1115 struct eq_context {
1116         uint32_t word0;
1117 #define lpfc_eq_context_size_SHIFT      31
1118 #define lpfc_eq_context_size_MASK       0x00000001
1119 #define lpfc_eq_context_size_WORD       word0
1120 #define LPFC_EQE_SIZE_4                 0x0
1121 #define LPFC_EQE_SIZE_16                0x1
1122 #define lpfc_eq_context_valid_SHIFT     29
1123 #define lpfc_eq_context_valid_MASK      0x00000001
1124 #define lpfc_eq_context_valid_WORD      word0
1125 #define lpfc_eq_context_autovalid_SHIFT 28
1126 #define lpfc_eq_context_autovalid_MASK  0x00000001
1127 #define lpfc_eq_context_autovalid_WORD  word0
1128         uint32_t word1;
1129 #define lpfc_eq_context_count_SHIFT     26
1130 #define lpfc_eq_context_count_MASK      0x00000003
1131 #define lpfc_eq_context_count_WORD      word1
1132 #define LPFC_EQ_CNT_256         0x0
1133 #define LPFC_EQ_CNT_512         0x1
1134 #define LPFC_EQ_CNT_1024        0x2
1135 #define LPFC_EQ_CNT_2048        0x3
1136 #define LPFC_EQ_CNT_4096        0x4
1137         uint32_t word2;
1138 #define lpfc_eq_context_delay_multi_SHIFT       13
1139 #define lpfc_eq_context_delay_multi_MASK        0x000003FF
1140 #define lpfc_eq_context_delay_multi_WORD        word2
1141         uint32_t reserved3;
1142 };
1143
1144 struct eq_delay_info {
1145         uint32_t eq_id;
1146         uint32_t phase;
1147         uint32_t delay_multi;
1148 };
1149 #define LPFC_MAX_EQ_DELAY_EQID_CNT      8
1150
1151 struct sgl_page_pairs {
1152         uint32_t sgl_pg0_addr_lo;
1153         uint32_t sgl_pg0_addr_hi;
1154         uint32_t sgl_pg1_addr_lo;
1155         uint32_t sgl_pg1_addr_hi;
1156 };
1157
1158 struct lpfc_mbx_post_sgl_pages {
1159         struct mbox_header header;
1160         uint32_t word0;
1161 #define lpfc_post_sgl_pages_xri_SHIFT   0
1162 #define lpfc_post_sgl_pages_xri_MASK    0x0000FFFF
1163 #define lpfc_post_sgl_pages_xri_WORD    word0
1164 #define lpfc_post_sgl_pages_xricnt_SHIFT        16
1165 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
1166 #define lpfc_post_sgl_pages_xricnt_WORD word0
1167         struct sgl_page_pairs  sgl_pg_pairs[1];
1168 };
1169
1170 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
1171 struct lpfc_mbx_post_uembed_sgl_page1 {
1172         union  lpfc_sli4_cfg_shdr cfg_shdr;
1173         uint32_t word0;
1174         struct sgl_page_pairs sgl_pg_pairs;
1175 };
1176
1177 struct lpfc_mbx_sge {
1178         uint32_t pa_lo;
1179         uint32_t pa_hi;
1180         uint32_t length;
1181 };
1182
1183 struct lpfc_mbx_host_buf {
1184         uint32_t length;
1185         uint32_t pa_lo;
1186         uint32_t pa_hi;
1187 };
1188
1189 struct lpfc_mbx_nembed_cmd {
1190         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
1191 #define LPFC_SLI4_MBX_SGE_MAX_PAGES     19
1192         struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1193 };
1194
1195 struct lpfc_mbx_nembed_sge_virt {
1196         void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1197 };
1198
1199 #define LPFC_MBX_OBJECT_NAME_LEN_DW     26
1200 struct lpfc_mbx_read_object {  /* Version 0 */
1201         struct mbox_header header;
1202         union {
1203                 struct {
1204                         uint32_t word0;
1205 #define lpfc_mbx_rd_object_rlen_SHIFT   0
1206 #define lpfc_mbx_rd_object_rlen_MASK    0x00FFFFFF
1207 #define lpfc_mbx_rd_object_rlen_WORD    word0
1208                         uint32_t rd_object_offset;
1209                         __le32 rd_object_name[LPFC_MBX_OBJECT_NAME_LEN_DW];
1210 #define LPFC_OBJ_NAME_SZ 104   /* 26 x sizeof(uint32_t) is 104. */
1211                         uint32_t rd_object_cnt;
1212                         struct lpfc_mbx_host_buf rd_object_hbuf[4];
1213                 } request;
1214                 struct {
1215                         uint32_t rd_object_actual_rlen;
1216                         uint32_t word1;
1217 #define lpfc_mbx_rd_object_eof_SHIFT    31
1218 #define lpfc_mbx_rd_object_eof_MASK     0x1
1219 #define lpfc_mbx_rd_object_eof_WORD     word1
1220                 } response;
1221         } u;
1222 };
1223
1224 struct lpfc_mbx_eq_create {
1225         struct mbox_header header;
1226         union {
1227                 struct {
1228                         uint32_t word0;
1229 #define lpfc_mbx_eq_create_num_pages_SHIFT      0
1230 #define lpfc_mbx_eq_create_num_pages_MASK       0x0000FFFF
1231 #define lpfc_mbx_eq_create_num_pages_WORD       word0
1232                         struct eq_context context;
1233                         struct dma_address page[LPFC_MAX_EQ_PAGE];
1234                 } request;
1235                 struct {
1236                         uint32_t word0;
1237 #define lpfc_mbx_eq_create_q_id_SHIFT   0
1238 #define lpfc_mbx_eq_create_q_id_MASK    0x0000FFFF
1239 #define lpfc_mbx_eq_create_q_id_WORD    word0
1240                 } response;
1241         } u;
1242 };
1243
1244 struct lpfc_mbx_modify_eq_delay {
1245         struct mbox_header header;
1246         union {
1247                 struct {
1248                         uint32_t num_eq;
1249                         struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT];
1250                 } request;
1251                 struct {
1252                         uint32_t word0;
1253                 } response;
1254         } u;
1255 };
1256
1257 struct lpfc_mbx_eq_destroy {
1258         struct mbox_header header;
1259         union {
1260                 struct {
1261                         uint32_t word0;
1262 #define lpfc_mbx_eq_destroy_q_id_SHIFT  0
1263 #define lpfc_mbx_eq_destroy_q_id_MASK   0x0000FFFF
1264 #define lpfc_mbx_eq_destroy_q_id_WORD   word0
1265                 } request;
1266                 struct {
1267                         uint32_t word0;
1268                 } response;
1269         } u;
1270 };
1271
1272 struct lpfc_mbx_nop {
1273         struct mbox_header header;
1274         uint32_t context[2];
1275 };
1276
1277
1278
1279 struct lpfc_mbx_set_ras_fwlog {
1280         struct mbox_header header;
1281         union {
1282                 struct {
1283                         uint32_t word4;
1284 #define lpfc_fwlog_enable_SHIFT         0
1285 #define lpfc_fwlog_enable_MASK          0x00000001
1286 #define lpfc_fwlog_enable_WORD          word4
1287 #define lpfc_fwlog_loglvl_SHIFT         8
1288 #define lpfc_fwlog_loglvl_MASK          0x0000000F
1289 #define lpfc_fwlog_loglvl_WORD          word4
1290 #define lpfc_fwlog_ra_SHIFT             15
1291 #define lpfc_fwlog_ra_WORD              0x00000008
1292 #define lpfc_fwlog_buffcnt_SHIFT        16
1293 #define lpfc_fwlog_buffcnt_MASK         0x000000FF
1294 #define lpfc_fwlog_buffcnt_WORD         word4
1295 #define lpfc_fwlog_buffsz_SHIFT         24
1296 #define lpfc_fwlog_buffsz_MASK          0x000000FF
1297 #define lpfc_fwlog_buffsz_WORD          word4
1298                         uint32_t word5;
1299 #define lpfc_fwlog_acqe_SHIFT           0
1300 #define lpfc_fwlog_acqe_MASK            0x0000FFFF
1301 #define lpfc_fwlog_acqe_WORD            word5
1302 #define lpfc_fwlog_cqid_SHIFT           16
1303 #define lpfc_fwlog_cqid_MASK            0x0000FFFF
1304 #define lpfc_fwlog_cqid_WORD            word5
1305 #define LPFC_MAX_FWLOG_PAGE     16
1306                         struct dma_address lwpd;
1307                         struct dma_address buff_fwlog[LPFC_MAX_FWLOG_PAGE];
1308                 } request;
1309                 struct {
1310                         uint32_t word0;
1311                 } response;
1312         } u;
1313 };
1314
1315
1316 struct cq_context {
1317         uint32_t word0;
1318 #define lpfc_cq_context_event_SHIFT     31
1319 #define lpfc_cq_context_event_MASK      0x00000001
1320 #define lpfc_cq_context_event_WORD      word0
1321 #define lpfc_cq_context_valid_SHIFT     29
1322 #define lpfc_cq_context_valid_MASK      0x00000001
1323 #define lpfc_cq_context_valid_WORD      word0
1324 #define lpfc_cq_context_count_SHIFT     27
1325 #define lpfc_cq_context_count_MASK      0x00000003
1326 #define lpfc_cq_context_count_WORD      word0
1327 #define LPFC_CQ_CNT_256         0x0
1328 #define LPFC_CQ_CNT_512         0x1
1329 #define LPFC_CQ_CNT_1024        0x2
1330 #define LPFC_CQ_CNT_WORD7       0x3
1331 #define lpfc_cq_context_autovalid_SHIFT 15
1332 #define lpfc_cq_context_autovalid_MASK  0x00000001
1333 #define lpfc_cq_context_autovalid_WORD  word0
1334         uint32_t word1;
1335 #define lpfc_cq_eq_id_SHIFT             22      /* Version 0 Only */
1336 #define lpfc_cq_eq_id_MASK              0x000000FF
1337 #define lpfc_cq_eq_id_WORD              word1
1338 #define lpfc_cq_eq_id_2_SHIFT           0       /* Version 2 Only */
1339 #define lpfc_cq_eq_id_2_MASK            0x0000FFFF
1340 #define lpfc_cq_eq_id_2_WORD            word1
1341         uint32_t lpfc_cq_context_count;         /* Version 2 Only */
1342         uint32_t reserved1;
1343 };
1344
1345 struct lpfc_mbx_cq_create {
1346         struct mbox_header header;
1347         union {
1348                 struct {
1349                         uint32_t word0;
1350 #define lpfc_mbx_cq_create_page_size_SHIFT      16      /* Version 2 Only */
1351 #define lpfc_mbx_cq_create_page_size_MASK       0x000000FF
1352 #define lpfc_mbx_cq_create_page_size_WORD       word0
1353 #define lpfc_mbx_cq_create_num_pages_SHIFT      0
1354 #define lpfc_mbx_cq_create_num_pages_MASK       0x0000FFFF
1355 #define lpfc_mbx_cq_create_num_pages_WORD       word0
1356                         struct cq_context context;
1357                         struct dma_address page[LPFC_MAX_CQ_PAGE];
1358                 } request;
1359                 struct {
1360                         uint32_t word0;
1361 #define lpfc_mbx_cq_create_q_id_SHIFT   0
1362 #define lpfc_mbx_cq_create_q_id_MASK    0x0000FFFF
1363 #define lpfc_mbx_cq_create_q_id_WORD    word0
1364                 } response;
1365         } u;
1366 };
1367
1368 struct lpfc_mbx_cq_create_set {
1369         union  lpfc_sli4_cfg_shdr cfg_shdr;
1370         union {
1371                 struct {
1372                         uint32_t word0;
1373 #define lpfc_mbx_cq_create_set_page_size_SHIFT  16      /* Version 2 Only */
1374 #define lpfc_mbx_cq_create_set_page_size_MASK   0x000000FF
1375 #define lpfc_mbx_cq_create_set_page_size_WORD   word0
1376 #define lpfc_mbx_cq_create_set_num_pages_SHIFT  0
1377 #define lpfc_mbx_cq_create_set_num_pages_MASK   0x0000FFFF
1378 #define lpfc_mbx_cq_create_set_num_pages_WORD   word0
1379                         uint32_t word1;
1380 #define lpfc_mbx_cq_create_set_evt_SHIFT        31
1381 #define lpfc_mbx_cq_create_set_evt_MASK         0x00000001
1382 #define lpfc_mbx_cq_create_set_evt_WORD         word1
1383 #define lpfc_mbx_cq_create_set_valid_SHIFT      29
1384 #define lpfc_mbx_cq_create_set_valid_MASK       0x00000001
1385 #define lpfc_mbx_cq_create_set_valid_WORD       word1
1386 #define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT    27
1387 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK     0x00000003
1388 #define lpfc_mbx_cq_create_set_cqe_cnt_WORD     word1
1389 #define lpfc_mbx_cq_create_set_cqe_size_SHIFT   25
1390 #define lpfc_mbx_cq_create_set_cqe_size_MASK    0x00000003
1391 #define lpfc_mbx_cq_create_set_cqe_size_WORD    word1
1392 #define lpfc_mbx_cq_create_set_autovalid_SHIFT  15
1393 #define lpfc_mbx_cq_create_set_autovalid_MASK   0x0000001
1394 #define lpfc_mbx_cq_create_set_autovalid_WORD   word1
1395 #define lpfc_mbx_cq_create_set_nodelay_SHIFT    14
1396 #define lpfc_mbx_cq_create_set_nodelay_MASK     0x00000001
1397 #define lpfc_mbx_cq_create_set_nodelay_WORD     word1
1398 #define lpfc_mbx_cq_create_set_clswm_SHIFT      12
1399 #define lpfc_mbx_cq_create_set_clswm_MASK       0x00000003
1400 #define lpfc_mbx_cq_create_set_clswm_WORD       word1
1401                         uint32_t word2;
1402 #define lpfc_mbx_cq_create_set_arm_SHIFT        31
1403 #define lpfc_mbx_cq_create_set_arm_MASK         0x00000001
1404 #define lpfc_mbx_cq_create_set_arm_WORD         word2
1405 #define lpfc_mbx_cq_create_set_cq_cnt_SHIFT     16
1406 #define lpfc_mbx_cq_create_set_cq_cnt_MASK      0x00007FFF
1407 #define lpfc_mbx_cq_create_set_cq_cnt_WORD      word2
1408 #define lpfc_mbx_cq_create_set_num_cq_SHIFT     0
1409 #define lpfc_mbx_cq_create_set_num_cq_MASK      0x0000FFFF
1410 #define lpfc_mbx_cq_create_set_num_cq_WORD      word2
1411                         uint32_t word3;
1412 #define lpfc_mbx_cq_create_set_eq_id1_SHIFT     16
1413 #define lpfc_mbx_cq_create_set_eq_id1_MASK      0x0000FFFF
1414 #define lpfc_mbx_cq_create_set_eq_id1_WORD      word3
1415 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT     0
1416 #define lpfc_mbx_cq_create_set_eq_id0_MASK      0x0000FFFF
1417 #define lpfc_mbx_cq_create_set_eq_id0_WORD      word3
1418                         uint32_t word4;
1419 #define lpfc_mbx_cq_create_set_eq_id3_SHIFT     16
1420 #define lpfc_mbx_cq_create_set_eq_id3_MASK      0x0000FFFF
1421 #define lpfc_mbx_cq_create_set_eq_id3_WORD      word4
1422 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT     0
1423 #define lpfc_mbx_cq_create_set_eq_id2_MASK      0x0000FFFF
1424 #define lpfc_mbx_cq_create_set_eq_id2_WORD      word4
1425                         uint32_t word5;
1426 #define lpfc_mbx_cq_create_set_eq_id5_SHIFT     16
1427 #define lpfc_mbx_cq_create_set_eq_id5_MASK      0x0000FFFF
1428 #define lpfc_mbx_cq_create_set_eq_id5_WORD      word5
1429 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT     0
1430 #define lpfc_mbx_cq_create_set_eq_id4_MASK      0x0000FFFF
1431 #define lpfc_mbx_cq_create_set_eq_id4_WORD      word5
1432                         uint32_t word6;
1433 #define lpfc_mbx_cq_create_set_eq_id7_SHIFT     16
1434 #define lpfc_mbx_cq_create_set_eq_id7_MASK      0x0000FFFF
1435 #define lpfc_mbx_cq_create_set_eq_id7_WORD      word6
1436 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT     0
1437 #define lpfc_mbx_cq_create_set_eq_id6_MASK      0x0000FFFF
1438 #define lpfc_mbx_cq_create_set_eq_id6_WORD      word6
1439                         uint32_t word7;
1440 #define lpfc_mbx_cq_create_set_eq_id9_SHIFT     16
1441 #define lpfc_mbx_cq_create_set_eq_id9_MASK      0x0000FFFF
1442 #define lpfc_mbx_cq_create_set_eq_id9_WORD      word7
1443 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT     0
1444 #define lpfc_mbx_cq_create_set_eq_id8_MASK      0x0000FFFF
1445 #define lpfc_mbx_cq_create_set_eq_id8_WORD      word7
1446                         uint32_t word8;
1447 #define lpfc_mbx_cq_create_set_eq_id11_SHIFT    16
1448 #define lpfc_mbx_cq_create_set_eq_id11_MASK     0x0000FFFF
1449 #define lpfc_mbx_cq_create_set_eq_id11_WORD     word8
1450 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT    0
1451 #define lpfc_mbx_cq_create_set_eq_id10_MASK     0x0000FFFF
1452 #define lpfc_mbx_cq_create_set_eq_id10_WORD     word8
1453                         uint32_t word9;
1454 #define lpfc_mbx_cq_create_set_eq_id13_SHIFT    16
1455 #define lpfc_mbx_cq_create_set_eq_id13_MASK     0x0000FFFF
1456 #define lpfc_mbx_cq_create_set_eq_id13_WORD     word9
1457 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT    0
1458 #define lpfc_mbx_cq_create_set_eq_id12_MASK     0x0000FFFF
1459 #define lpfc_mbx_cq_create_set_eq_id12_WORD     word9
1460                         uint32_t word10;
1461 #define lpfc_mbx_cq_create_set_eq_id15_SHIFT    16
1462 #define lpfc_mbx_cq_create_set_eq_id15_MASK     0x0000FFFF
1463 #define lpfc_mbx_cq_create_set_eq_id15_WORD     word10
1464 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT    0
1465 #define lpfc_mbx_cq_create_set_eq_id14_MASK     0x0000FFFF
1466 #define lpfc_mbx_cq_create_set_eq_id14_WORD     word10
1467                         struct dma_address page[1];
1468                 } request;
1469                 struct {
1470                         uint32_t word0;
1471 #define lpfc_mbx_cq_create_set_num_alloc_SHIFT  16
1472 #define lpfc_mbx_cq_create_set_num_alloc_MASK   0x0000FFFF
1473 #define lpfc_mbx_cq_create_set_num_alloc_WORD   word0
1474 #define lpfc_mbx_cq_create_set_base_id_SHIFT    0
1475 #define lpfc_mbx_cq_create_set_base_id_MASK     0x0000FFFF
1476 #define lpfc_mbx_cq_create_set_base_id_WORD     word0
1477                 } response;
1478         } u;
1479 };
1480
1481 struct lpfc_mbx_cq_destroy {
1482         struct mbox_header header;
1483         union {
1484                 struct {
1485                         uint32_t word0;
1486 #define lpfc_mbx_cq_destroy_q_id_SHIFT  0
1487 #define lpfc_mbx_cq_destroy_q_id_MASK   0x0000FFFF
1488 #define lpfc_mbx_cq_destroy_q_id_WORD   word0
1489                 } request;
1490                 struct {
1491                         uint32_t word0;
1492                 } response;
1493         } u;
1494 };
1495
1496 struct wq_context {
1497         uint32_t reserved0;
1498         uint32_t reserved1;
1499         uint32_t reserved2;
1500         uint32_t reserved3;
1501 };
1502
1503 struct lpfc_mbx_wq_create {
1504         struct mbox_header header;
1505         union {
1506                 struct {        /* Version 0 Request */
1507                         uint32_t word0;
1508 #define lpfc_mbx_wq_create_num_pages_SHIFT      0
1509 #define lpfc_mbx_wq_create_num_pages_MASK       0x000000FF
1510 #define lpfc_mbx_wq_create_num_pages_WORD       word0
1511 #define lpfc_mbx_wq_create_dua_SHIFT            8
1512 #define lpfc_mbx_wq_create_dua_MASK             0x00000001
1513 #define lpfc_mbx_wq_create_dua_WORD             word0
1514 #define lpfc_mbx_wq_create_cq_id_SHIFT          16
1515 #define lpfc_mbx_wq_create_cq_id_MASK           0x0000FFFF
1516 #define lpfc_mbx_wq_create_cq_id_WORD           word0
1517                         struct dma_address page[LPFC_MAX_WQ_PAGE_V0];
1518                         uint32_t word9;
1519 #define lpfc_mbx_wq_create_bua_SHIFT            0
1520 #define lpfc_mbx_wq_create_bua_MASK             0x00000001
1521 #define lpfc_mbx_wq_create_bua_WORD             word9
1522 #define lpfc_mbx_wq_create_ulp_num_SHIFT        8
1523 #define lpfc_mbx_wq_create_ulp_num_MASK         0x000000FF
1524 #define lpfc_mbx_wq_create_ulp_num_WORD         word9
1525                 } request;
1526                 struct {        /* Version 1 Request */
1527                         uint32_t word0; /* Word 0 is the same as in v0 */
1528                         uint32_t word1;
1529 #define lpfc_mbx_wq_create_page_size_SHIFT      0
1530 #define lpfc_mbx_wq_create_page_size_MASK       0x000000FF
1531 #define lpfc_mbx_wq_create_page_size_WORD       word1
1532 #define LPFC_WQ_PAGE_SIZE_4096  0x1
1533 #define lpfc_mbx_wq_create_dpp_req_SHIFT        15
1534 #define lpfc_mbx_wq_create_dpp_req_MASK         0x00000001
1535 #define lpfc_mbx_wq_create_dpp_req_WORD         word1
1536 #define lpfc_mbx_wq_create_doe_SHIFT            14
1537 #define lpfc_mbx_wq_create_doe_MASK             0x00000001
1538 #define lpfc_mbx_wq_create_doe_WORD             word1
1539 #define lpfc_mbx_wq_create_toe_SHIFT            13
1540 #define lpfc_mbx_wq_create_toe_MASK             0x00000001
1541 #define lpfc_mbx_wq_create_toe_WORD             word1
1542 #define lpfc_mbx_wq_create_wqe_size_SHIFT       8
1543 #define lpfc_mbx_wq_create_wqe_size_MASK        0x0000000F
1544 #define lpfc_mbx_wq_create_wqe_size_WORD        word1
1545 #define LPFC_WQ_WQE_SIZE_64     0x5
1546 #define LPFC_WQ_WQE_SIZE_128    0x6
1547 #define lpfc_mbx_wq_create_wqe_count_SHIFT      16
1548 #define lpfc_mbx_wq_create_wqe_count_MASK       0x0000FFFF
1549 #define lpfc_mbx_wq_create_wqe_count_WORD       word1
1550                         uint32_t word2;
1551                         struct dma_address page[LPFC_MAX_WQ_PAGE-1];
1552                 } request_1;
1553                 struct {
1554                         uint32_t word0;
1555 #define lpfc_mbx_wq_create_q_id_SHIFT   0
1556 #define lpfc_mbx_wq_create_q_id_MASK    0x0000FFFF
1557 #define lpfc_mbx_wq_create_q_id_WORD    word0
1558                         uint32_t doorbell_offset;
1559                         uint32_t word2;
1560 #define lpfc_mbx_wq_create_bar_set_SHIFT        0
1561 #define lpfc_mbx_wq_create_bar_set_MASK         0x0000FFFF
1562 #define lpfc_mbx_wq_create_bar_set_WORD         word2
1563 #define WQ_PCI_BAR_0_AND_1      0x00
1564 #define WQ_PCI_BAR_2_AND_3      0x01
1565 #define WQ_PCI_BAR_4_AND_5      0x02
1566 #define lpfc_mbx_wq_create_db_format_SHIFT      16
1567 #define lpfc_mbx_wq_create_db_format_MASK       0x0000FFFF
1568 #define lpfc_mbx_wq_create_db_format_WORD       word2
1569                 } response;
1570                 struct {
1571                         uint32_t word0;
1572 #define lpfc_mbx_wq_create_dpp_rsp_SHIFT        31
1573 #define lpfc_mbx_wq_create_dpp_rsp_MASK         0x00000001
1574 #define lpfc_mbx_wq_create_dpp_rsp_WORD         word0
1575 #define lpfc_mbx_wq_create_v1_q_id_SHIFT        0
1576 #define lpfc_mbx_wq_create_v1_q_id_MASK         0x0000FFFF
1577 #define lpfc_mbx_wq_create_v1_q_id_WORD         word0
1578                         uint32_t word1;
1579 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT     0
1580 #define lpfc_mbx_wq_create_v1_bar_set_MASK      0x0000000F
1581 #define lpfc_mbx_wq_create_v1_bar_set_WORD      word1
1582                         uint32_t doorbell_offset;
1583                         uint32_t word3;
1584 #define lpfc_mbx_wq_create_dpp_id_SHIFT         16
1585 #define lpfc_mbx_wq_create_dpp_id_MASK          0x0000001F
1586 #define lpfc_mbx_wq_create_dpp_id_WORD          word3
1587 #define lpfc_mbx_wq_create_dpp_bar_SHIFT        0
1588 #define lpfc_mbx_wq_create_dpp_bar_MASK         0x0000000F
1589 #define lpfc_mbx_wq_create_dpp_bar_WORD         word3
1590                         uint32_t dpp_offset;
1591                 } response_1;
1592         } u;
1593 };
1594
1595 struct lpfc_mbx_wq_destroy {
1596         struct mbox_header header;
1597         union {
1598                 struct {
1599                         uint32_t word0;
1600 #define lpfc_mbx_wq_destroy_q_id_SHIFT  0
1601 #define lpfc_mbx_wq_destroy_q_id_MASK   0x0000FFFF
1602 #define lpfc_mbx_wq_destroy_q_id_WORD   word0
1603                 } request;
1604                 struct {
1605                         uint32_t word0;
1606                 } response;
1607         } u;
1608 };
1609
1610 #define LPFC_HDR_BUF_SIZE 128
1611 #define LPFC_DATA_BUF_SIZE 2048
1612 #define LPFC_NVMET_DATA_BUF_SIZE 128
1613 struct rq_context {
1614         uint32_t word0;
1615 #define lpfc_rq_context_rqe_count_SHIFT 16      /* Version 0 Only */
1616 #define lpfc_rq_context_rqe_count_MASK  0x0000000F
1617 #define lpfc_rq_context_rqe_count_WORD  word0
1618 #define LPFC_RQ_RING_SIZE_512           9       /* 512 entries */
1619 #define LPFC_RQ_RING_SIZE_1024          10      /* 1024 entries */
1620 #define LPFC_RQ_RING_SIZE_2048          11      /* 2048 entries */
1621 #define LPFC_RQ_RING_SIZE_4096          12      /* 4096 entries */
1622 #define lpfc_rq_context_rqe_count_1_SHIFT       16      /* Version 1-2 Only */
1623 #define lpfc_rq_context_rqe_count_1_MASK        0x0000FFFF
1624 #define lpfc_rq_context_rqe_count_1_WORD        word0
1625 #define lpfc_rq_context_rqe_size_SHIFT  8               /* Version 1-2 Only */
1626 #define lpfc_rq_context_rqe_size_MASK   0x0000000F
1627 #define lpfc_rq_context_rqe_size_WORD   word0
1628 #define LPFC_RQE_SIZE_8         2
1629 #define LPFC_RQE_SIZE_16        3
1630 #define LPFC_RQE_SIZE_32        4
1631 #define LPFC_RQE_SIZE_64        5
1632 #define LPFC_RQE_SIZE_128       6
1633 #define lpfc_rq_context_page_size_SHIFT 0               /* Version 1 Only */
1634 #define lpfc_rq_context_page_size_MASK  0x000000FF
1635 #define lpfc_rq_context_page_size_WORD  word0
1636 #define LPFC_RQ_PAGE_SIZE_4096  0x1
1637         uint32_t word1;
1638 #define lpfc_rq_context_data_size_SHIFT 16              /* Version 2 Only */
1639 #define lpfc_rq_context_data_size_MASK  0x0000FFFF
1640 #define lpfc_rq_context_data_size_WORD  word1
1641 #define lpfc_rq_context_hdr_size_SHIFT  0               /* Version 2 Only */
1642 #define lpfc_rq_context_hdr_size_MASK   0x0000FFFF
1643 #define lpfc_rq_context_hdr_size_WORD   word1
1644         uint32_t word2;
1645 #define lpfc_rq_context_cq_id_SHIFT     16
1646 #define lpfc_rq_context_cq_id_MASK      0x0000FFFF
1647 #define lpfc_rq_context_cq_id_WORD      word2
1648 #define lpfc_rq_context_buf_size_SHIFT  0
1649 #define lpfc_rq_context_buf_size_MASK   0x0000FFFF
1650 #define lpfc_rq_context_buf_size_WORD   word2
1651 #define lpfc_rq_context_base_cq_SHIFT   0               /* Version 2 Only */
1652 #define lpfc_rq_context_base_cq_MASK    0x0000FFFF
1653 #define lpfc_rq_context_base_cq_WORD    word2
1654         uint32_t buffer_size;                           /* Version 1 Only */
1655 };
1656
1657 struct lpfc_mbx_rq_create {
1658         struct mbox_header header;
1659         union {
1660                 struct {
1661                         uint32_t word0;
1662 #define lpfc_mbx_rq_create_num_pages_SHIFT      0
1663 #define lpfc_mbx_rq_create_num_pages_MASK       0x0000FFFF
1664 #define lpfc_mbx_rq_create_num_pages_WORD       word0
1665 #define lpfc_mbx_rq_create_dua_SHIFT            16
1666 #define lpfc_mbx_rq_create_dua_MASK             0x00000001
1667 #define lpfc_mbx_rq_create_dua_WORD             word0
1668 #define lpfc_mbx_rq_create_bqu_SHIFT            17
1669 #define lpfc_mbx_rq_create_bqu_MASK             0x00000001
1670 #define lpfc_mbx_rq_create_bqu_WORD             word0
1671 #define lpfc_mbx_rq_create_ulp_num_SHIFT        24
1672 #define lpfc_mbx_rq_create_ulp_num_MASK         0x000000FF
1673 #define lpfc_mbx_rq_create_ulp_num_WORD         word0
1674                         struct rq_context context;
1675                         struct dma_address page[LPFC_MAX_RQ_PAGE];
1676                 } request;
1677                 struct {
1678                         uint32_t word0;
1679 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT       16
1680 #define lpfc_mbx_rq_create_q_cnt_v2_MASK        0x0000FFFF
1681 #define lpfc_mbx_rq_create_q_cnt_v2_WORD        word0
1682 #define lpfc_mbx_rq_create_q_id_SHIFT           0
1683 #define lpfc_mbx_rq_create_q_id_MASK            0x0000FFFF
1684 #define lpfc_mbx_rq_create_q_id_WORD            word0
1685                         uint32_t doorbell_offset;
1686                         uint32_t word2;
1687 #define lpfc_mbx_rq_create_bar_set_SHIFT        0
1688 #define lpfc_mbx_rq_create_bar_set_MASK         0x0000FFFF
1689 #define lpfc_mbx_rq_create_bar_set_WORD         word2
1690 #define lpfc_mbx_rq_create_db_format_SHIFT      16
1691 #define lpfc_mbx_rq_create_db_format_MASK       0x0000FFFF
1692 #define lpfc_mbx_rq_create_db_format_WORD       word2
1693                 } response;
1694         } u;
1695 };
1696
1697 struct lpfc_mbx_rq_create_v2 {
1698         union  lpfc_sli4_cfg_shdr cfg_shdr;
1699         union {
1700                 struct {
1701                         uint32_t word0;
1702 #define lpfc_mbx_rq_create_num_pages_SHIFT      0
1703 #define lpfc_mbx_rq_create_num_pages_MASK       0x0000FFFF
1704 #define lpfc_mbx_rq_create_num_pages_WORD       word0
1705 #define lpfc_mbx_rq_create_rq_cnt_SHIFT         16
1706 #define lpfc_mbx_rq_create_rq_cnt_MASK          0x000000FF
1707 #define lpfc_mbx_rq_create_rq_cnt_WORD          word0
1708 #define lpfc_mbx_rq_create_dua_SHIFT            16
1709 #define lpfc_mbx_rq_create_dua_MASK             0x00000001
1710 #define lpfc_mbx_rq_create_dua_WORD             word0
1711 #define lpfc_mbx_rq_create_bqu_SHIFT            17
1712 #define lpfc_mbx_rq_create_bqu_MASK             0x00000001
1713 #define lpfc_mbx_rq_create_bqu_WORD             word0
1714 #define lpfc_mbx_rq_create_ulp_num_SHIFT        24
1715 #define lpfc_mbx_rq_create_ulp_num_MASK         0x000000FF
1716 #define lpfc_mbx_rq_create_ulp_num_WORD         word0
1717 #define lpfc_mbx_rq_create_dim_SHIFT            29
1718 #define lpfc_mbx_rq_create_dim_MASK             0x00000001
1719 #define lpfc_mbx_rq_create_dim_WORD             word0
1720 #define lpfc_mbx_rq_create_dfd_SHIFT            30
1721 #define lpfc_mbx_rq_create_dfd_MASK             0x00000001
1722 #define lpfc_mbx_rq_create_dfd_WORD             word0
1723 #define lpfc_mbx_rq_create_dnb_SHIFT            31
1724 #define lpfc_mbx_rq_create_dnb_MASK             0x00000001
1725 #define lpfc_mbx_rq_create_dnb_WORD             word0
1726                         struct rq_context context;
1727                         struct dma_address page[1];
1728                 } request;
1729                 struct {
1730                         uint32_t word0;
1731 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT       16
1732 #define lpfc_mbx_rq_create_q_cnt_v2_MASK        0x0000FFFF
1733 #define lpfc_mbx_rq_create_q_cnt_v2_WORD        word0
1734 #define lpfc_mbx_rq_create_q_id_SHIFT           0
1735 #define lpfc_mbx_rq_create_q_id_MASK            0x0000FFFF
1736 #define lpfc_mbx_rq_create_q_id_WORD            word0
1737                         uint32_t doorbell_offset;
1738                         uint32_t word2;
1739 #define lpfc_mbx_rq_create_bar_set_SHIFT        0
1740 #define lpfc_mbx_rq_create_bar_set_MASK         0x0000FFFF
1741 #define lpfc_mbx_rq_create_bar_set_WORD         word2
1742 #define lpfc_mbx_rq_create_db_format_SHIFT      16
1743 #define lpfc_mbx_rq_create_db_format_MASK       0x0000FFFF
1744 #define lpfc_mbx_rq_create_db_format_WORD       word2
1745                 } response;
1746         } u;
1747 };
1748
1749 struct lpfc_mbx_rq_destroy {
1750         struct mbox_header header;
1751         union {
1752                 struct {
1753                         uint32_t word0;
1754 #define lpfc_mbx_rq_destroy_q_id_SHIFT  0
1755 #define lpfc_mbx_rq_destroy_q_id_MASK   0x0000FFFF
1756 #define lpfc_mbx_rq_destroy_q_id_WORD   word0
1757                 } request;
1758                 struct {
1759                         uint32_t word0;
1760                 } response;
1761         } u;
1762 };
1763
1764 struct mq_context {
1765         uint32_t word0;
1766 #define lpfc_mq_context_cq_id_SHIFT     22      /* Version 0 Only */
1767 #define lpfc_mq_context_cq_id_MASK      0x000003FF
1768 #define lpfc_mq_context_cq_id_WORD      word0
1769 #define lpfc_mq_context_ring_size_SHIFT 16
1770 #define lpfc_mq_context_ring_size_MASK  0x0000000F
1771 #define lpfc_mq_context_ring_size_WORD  word0
1772 #define LPFC_MQ_RING_SIZE_16            0x5
1773 #define LPFC_MQ_RING_SIZE_32            0x6
1774 #define LPFC_MQ_RING_SIZE_64            0x7
1775 #define LPFC_MQ_RING_SIZE_128           0x8
1776         uint32_t word1;
1777 #define lpfc_mq_context_valid_SHIFT     31
1778 #define lpfc_mq_context_valid_MASK      0x00000001
1779 #define lpfc_mq_context_valid_WORD      word1
1780         uint32_t reserved2;
1781         uint32_t reserved3;
1782 };
1783
1784 struct lpfc_mbx_mq_create {
1785         struct mbox_header header;
1786         union {
1787                 struct {
1788                         uint32_t word0;
1789 #define lpfc_mbx_mq_create_num_pages_SHIFT      0
1790 #define lpfc_mbx_mq_create_num_pages_MASK       0x0000FFFF
1791 #define lpfc_mbx_mq_create_num_pages_WORD       word0
1792                         struct mq_context context;
1793                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1794                 } request;
1795                 struct {
1796                         uint32_t word0;
1797 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1798 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1799 #define lpfc_mbx_mq_create_q_id_WORD    word0
1800                 } response;
1801         } u;
1802 };
1803
1804 struct lpfc_mbx_mq_create_ext {
1805         struct mbox_header header;
1806         union {
1807                 struct {
1808                         uint32_t word0;
1809 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT  0
1810 #define lpfc_mbx_mq_create_ext_num_pages_MASK   0x0000FFFF
1811 #define lpfc_mbx_mq_create_ext_num_pages_WORD   word0
1812 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT      16      /* Version 1 Only */
1813 #define lpfc_mbx_mq_create_ext_cq_id_MASK       0x0000FFFF
1814 #define lpfc_mbx_mq_create_ext_cq_id_WORD       word0
1815                         uint32_t async_evt_bmap;
1816 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT     LPFC_TRAILER_CODE_LINK
1817 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK      0x00000001
1818 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD      async_evt_bmap
1819 #define LPFC_EVT_CODE_LINK_NO_LINK      0x0
1820 #define LPFC_EVT_CODE_LINK_10_MBIT      0x1
1821 #define LPFC_EVT_CODE_LINK_100_MBIT     0x2
1822 #define LPFC_EVT_CODE_LINK_1_GBIT       0x3
1823 #define LPFC_EVT_CODE_LINK_10_GBIT      0x4
1824 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT      LPFC_TRAILER_CODE_FCOE
1825 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK       0x00000001
1826 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD       async_evt_bmap
1827 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT   LPFC_TRAILER_CODE_GRP5
1828 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK    0x00000001
1829 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD    async_evt_bmap
1830 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT       LPFC_TRAILER_CODE_FC
1831 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK        0x00000001
1832 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD        async_evt_bmap
1833 #define LPFC_EVT_CODE_FC_NO_LINK        0x0
1834 #define LPFC_EVT_CODE_FC_1_GBAUD        0x1
1835 #define LPFC_EVT_CODE_FC_2_GBAUD        0x2
1836 #define LPFC_EVT_CODE_FC_4_GBAUD        0x4
1837 #define LPFC_EVT_CODE_FC_8_GBAUD        0x8
1838 #define LPFC_EVT_CODE_FC_10_GBAUD       0xA
1839 #define LPFC_EVT_CODE_FC_16_GBAUD       0x10
1840 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT      LPFC_TRAILER_CODE_SLI
1841 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK       0x00000001
1842 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD       async_evt_bmap
1843                         struct mq_context context;
1844                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1845                 } request;
1846                 struct {
1847                         uint32_t word0;
1848 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1849 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1850 #define lpfc_mbx_mq_create_q_id_WORD    word0
1851                 } response;
1852         } u;
1853 #define LPFC_ASYNC_EVENT_LINK_STATE     0x2
1854 #define LPFC_ASYNC_EVENT_FCF_STATE      0x4
1855 #define LPFC_ASYNC_EVENT_GROUP5         0x20
1856 };
1857
1858 struct lpfc_mbx_mq_destroy {
1859         struct mbox_header header;
1860         union {
1861                 struct {
1862                         uint32_t word0;
1863 #define lpfc_mbx_mq_destroy_q_id_SHIFT  0
1864 #define lpfc_mbx_mq_destroy_q_id_MASK   0x0000FFFF
1865 #define lpfc_mbx_mq_destroy_q_id_WORD   word0
1866                 } request;
1867                 struct {
1868                         uint32_t word0;
1869                 } response;
1870         } u;
1871 };
1872
1873 /* Start Gen 2 SLI4 Mailbox definitions: */
1874
1875 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */
1876 #define LPFC_RSC_TYPE_FCOE_VFI  0x20
1877 #define LPFC_RSC_TYPE_FCOE_VPI  0x21
1878 #define LPFC_RSC_TYPE_FCOE_RPI  0x22
1879 #define LPFC_RSC_TYPE_FCOE_XRI  0x23
1880
1881 struct lpfc_mbx_get_rsrc_extent_info {
1882         struct mbox_header header;
1883         union {
1884                 struct {
1885                         uint32_t word4;
1886 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT        0
1887 #define lpfc_mbx_get_rsrc_extent_info_type_MASK         0x0000FFFF
1888 #define lpfc_mbx_get_rsrc_extent_info_type_WORD         word4
1889                 } req;
1890                 struct {
1891                         uint32_t word4;
1892 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT         0
1893 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK          0x0000FFFF
1894 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD          word4
1895 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT        16
1896 #define lpfc_mbx_get_rsrc_extent_info_size_MASK         0x0000FFFF
1897 #define lpfc_mbx_get_rsrc_extent_info_size_WORD         word4
1898                 } rsp;
1899         } u;
1900 };
1901
1902 struct lpfc_mbx_query_fw_config {
1903         struct mbox_header header;
1904         struct {
1905                 uint32_t config_number;
1906 #define LPFC_FC_FCOE            0x00000007
1907                 uint32_t asic_revision;
1908                 uint32_t physical_port;
1909                 uint32_t function_mode;
1910 #define LPFC_FCOE_INI_MODE      0x00000040
1911 #define LPFC_FCOE_TGT_MODE      0x00000080
1912 #define LPFC_DUA_MODE           0x00000800
1913                 uint32_t ulp0_mode;
1914 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040
1915 #define LPFC_ULP_FCOE_TGT_MODE  0x00000080
1916                 uint32_t ulp0_nap_words[12];
1917                 uint32_t ulp1_mode;
1918                 uint32_t ulp1_nap_words[12];
1919                 uint32_t function_capabilities;
1920                 uint32_t cqid_base;
1921                 uint32_t cqid_tot;
1922                 uint32_t eqid_base;
1923                 uint32_t eqid_tot;
1924                 uint32_t ulp0_nap2_words[2];
1925                 uint32_t ulp1_nap2_words[2];
1926         } rsp;
1927 };
1928
1929 struct lpfc_mbx_set_beacon_config {
1930         struct mbox_header header;
1931         uint32_t word4;
1932 #define lpfc_mbx_set_beacon_port_num_SHIFT              0
1933 #define lpfc_mbx_set_beacon_port_num_MASK               0x0000003F
1934 #define lpfc_mbx_set_beacon_port_num_WORD               word4
1935 #define lpfc_mbx_set_beacon_port_type_SHIFT             6
1936 #define lpfc_mbx_set_beacon_port_type_MASK              0x00000003
1937 #define lpfc_mbx_set_beacon_port_type_WORD              word4
1938 #define lpfc_mbx_set_beacon_state_SHIFT                 8
1939 #define lpfc_mbx_set_beacon_state_MASK                  0x000000FF
1940 #define lpfc_mbx_set_beacon_state_WORD                  word4
1941 #define lpfc_mbx_set_beacon_duration_SHIFT              16
1942 #define lpfc_mbx_set_beacon_duration_MASK               0x000000FF
1943 #define lpfc_mbx_set_beacon_duration_WORD               word4
1944
1945 /* COMMON_SET_BEACON_CONFIG_V1 */
1946 #define lpfc_mbx_set_beacon_duration_v1_SHIFT           16
1947 #define lpfc_mbx_set_beacon_duration_v1_MASK            0x0000FFFF
1948 #define lpfc_mbx_set_beacon_duration_v1_WORD            word4
1949         uint32_t word5;  /* RESERVED  */
1950 };
1951
1952 struct lpfc_id_range {
1953         uint32_t word5;
1954 #define lpfc_mbx_rsrc_id_word4_0_SHIFT  0
1955 #define lpfc_mbx_rsrc_id_word4_0_MASK   0x0000FFFF
1956 #define lpfc_mbx_rsrc_id_word4_0_WORD   word5
1957 #define lpfc_mbx_rsrc_id_word4_1_SHIFT  16
1958 #define lpfc_mbx_rsrc_id_word4_1_MASK   0x0000FFFF
1959 #define lpfc_mbx_rsrc_id_word4_1_WORD   word5
1960 };
1961
1962 struct lpfc_mbx_set_link_diag_state {
1963         struct mbox_header header;
1964         union {
1965                 struct {
1966                         uint32_t word0;
1967 #define lpfc_mbx_set_diag_state_diag_SHIFT      0
1968 #define lpfc_mbx_set_diag_state_diag_MASK       0x00000001
1969 #define lpfc_mbx_set_diag_state_diag_WORD       word0
1970 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT    2
1971 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK     0x00000001
1972 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD     word0
1973 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE        0
1974 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE           1
1975 #define lpfc_mbx_set_diag_state_link_num_SHIFT  16
1976 #define lpfc_mbx_set_diag_state_link_num_MASK   0x0000003F
1977 #define lpfc_mbx_set_diag_state_link_num_WORD   word0
1978 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22
1979 #define lpfc_mbx_set_diag_state_link_type_MASK  0x00000003
1980 #define lpfc_mbx_set_diag_state_link_type_WORD  word0
1981                 } req;
1982                 struct {
1983                         uint32_t word0;
1984                 } rsp;
1985         } u;
1986 };
1987
1988 struct lpfc_mbx_set_link_diag_loopback {
1989         struct mbox_header header;
1990         union {
1991                 struct {
1992                         uint32_t word0;
1993 #define lpfc_mbx_set_diag_lpbk_type_SHIFT               0
1994 #define lpfc_mbx_set_diag_lpbk_type_MASK                0x00000003
1995 #define lpfc_mbx_set_diag_lpbk_type_WORD                word0
1996 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE                 0x0
1997 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL                0x1
1998 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES                  0x2
1999 #define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED        0x3
2000 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT           16
2001 #define lpfc_mbx_set_diag_lpbk_link_num_MASK            0x0000003F
2002 #define lpfc_mbx_set_diag_lpbk_link_num_WORD            word0
2003 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT          22
2004 #define lpfc_mbx_set_diag_lpbk_link_type_MASK           0x00000003
2005 #define lpfc_mbx_set_diag_lpbk_link_type_WORD           word0
2006                 } req;
2007                 struct {
2008                         uint32_t word0;
2009                 } rsp;
2010         } u;
2011 };
2012
2013 struct lpfc_mbx_run_link_diag_test {
2014         struct mbox_header header;
2015         union {
2016                 struct {
2017                         uint32_t word0;
2018 #define lpfc_mbx_run_diag_test_link_num_SHIFT   16
2019 #define lpfc_mbx_run_diag_test_link_num_MASK    0x0000003F
2020 #define lpfc_mbx_run_diag_test_link_num_WORD    word0
2021 #define lpfc_mbx_run_diag_test_link_type_SHIFT  22
2022 #define lpfc_mbx_run_diag_test_link_type_MASK   0x00000003
2023 #define lpfc_mbx_run_diag_test_link_type_WORD   word0
2024                         uint32_t word1;
2025 #define lpfc_mbx_run_diag_test_test_id_SHIFT    0
2026 #define lpfc_mbx_run_diag_test_test_id_MASK     0x0000FFFF
2027 #define lpfc_mbx_run_diag_test_test_id_WORD     word1
2028 #define lpfc_mbx_run_diag_test_loops_SHIFT      16
2029 #define lpfc_mbx_run_diag_test_loops_MASK       0x0000FFFF
2030 #define lpfc_mbx_run_diag_test_loops_WORD       word1
2031                         uint32_t word2;
2032 #define lpfc_mbx_run_diag_test_test_ver_SHIFT   0
2033 #define lpfc_mbx_run_diag_test_test_ver_MASK    0x0000FFFF
2034 #define lpfc_mbx_run_diag_test_test_ver_WORD    word2
2035 #define lpfc_mbx_run_diag_test_err_act_SHIFT    16
2036 #define lpfc_mbx_run_diag_test_err_act_MASK     0x000000FF
2037 #define lpfc_mbx_run_diag_test_err_act_WORD     word2
2038                 } req;
2039                 struct {
2040                         uint32_t word0;
2041                 } rsp;
2042         } u;
2043 };
2044
2045 /*
2046  * struct lpfc_mbx_alloc_rsrc_extents:
2047  * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires
2048  * 6 words of header + 4 words of shared subcommand header +
2049  * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total.
2050  *
2051  * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes
2052  * for extents payload.
2053  *
2054  * 212/2 (bytes per extent) = 106 extents.
2055  * 106/2 (extents per word) = 53 words.
2056  * lpfc_id_range id is statically size to 53.
2057  *
2058  * This mailbox definition is used for ALLOC or GET_ALLOCATED
2059  * extent ranges.  For ALLOC, the type and cnt are required.
2060  * For GET_ALLOCATED, only the type is required.
2061  */
2062 struct lpfc_mbx_alloc_rsrc_extents {
2063         struct mbox_header header;
2064         union {
2065                 struct {
2066                         uint32_t word4;
2067 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT  0
2068 #define lpfc_mbx_alloc_rsrc_extents_type_MASK   0x0000FFFF
2069 #define lpfc_mbx_alloc_rsrc_extents_type_WORD   word4
2070 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT   16
2071 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK    0x0000FFFF
2072 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD    word4
2073                 } req;
2074                 struct {
2075                         uint32_t word4;
2076 #define lpfc_mbx_rsrc_cnt_SHIFT 0
2077 #define lpfc_mbx_rsrc_cnt_MASK  0x0000FFFF
2078 #define lpfc_mbx_rsrc_cnt_WORD  word4
2079                         struct lpfc_id_range id[53];
2080                 } rsp;
2081         } u;
2082 };
2083
2084 /*
2085  * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this
2086  * structure shares the same SHIFT/MASK/WORD defines provided in the
2087  * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in
2088  * the structures defined above.  This non-embedded structure provides for the
2089  * maximum number of extents supported by the port.
2090  */
2091 struct lpfc_mbx_nembed_rsrc_extent {
2092         union  lpfc_sli4_cfg_shdr cfg_shdr;
2093         uint32_t word4;
2094         struct lpfc_id_range id;
2095 };
2096
2097 struct lpfc_mbx_dealloc_rsrc_extents {
2098         struct mbox_header header;
2099         struct {
2100                 uint32_t word4;
2101 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT        0
2102 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK         0x0000FFFF
2103 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD         word4
2104         } req;
2105
2106 };
2107
2108 /* Start SLI4 FCoE specific mbox structures. */
2109
2110 struct lpfc_mbx_post_hdr_tmpl {
2111         struct mbox_header header;
2112         uint32_t word10;
2113 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT  0
2114 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK   0x0000FFFF
2115 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD   word10
2116 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT   16
2117 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK    0x0000FFFF
2118 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD    word10
2119         uint32_t rpi_paddr_lo;
2120         uint32_t rpi_paddr_hi;
2121 };
2122
2123 struct sli4_sge {       /* SLI-4 */
2124         uint32_t addr_hi;
2125         uint32_t addr_lo;
2126
2127         uint32_t word2;
2128 #define lpfc_sli4_sge_offset_SHIFT      0
2129 #define lpfc_sli4_sge_offset_MASK       0x07FFFFFF
2130 #define lpfc_sli4_sge_offset_WORD       word2
2131 #define lpfc_sli4_sge_type_SHIFT        27
2132 #define lpfc_sli4_sge_type_MASK         0x0000000F
2133 #define lpfc_sli4_sge_type_WORD         word2
2134 #define LPFC_SGE_TYPE_DATA              0x0
2135 #define LPFC_SGE_TYPE_DIF               0x4
2136 #define LPFC_SGE_TYPE_LSP               0x5
2137 #define LPFC_SGE_TYPE_PEDIF             0x6
2138 #define LPFC_SGE_TYPE_PESEED            0x7
2139 #define LPFC_SGE_TYPE_DISEED            0x8
2140 #define LPFC_SGE_TYPE_ENC               0x9
2141 #define LPFC_SGE_TYPE_ATM               0xA
2142 #define LPFC_SGE_TYPE_SKIP              0xC
2143 #define lpfc_sli4_sge_last_SHIFT        31 /* Last SEG in the SGL sets it */
2144 #define lpfc_sli4_sge_last_MASK         0x00000001
2145 #define lpfc_sli4_sge_last_WORD         word2
2146         uint32_t sge_len;
2147 };
2148
2149 struct sli4_sge_le {
2150         __le32 addr_hi;
2151         __le32 addr_lo;
2152
2153         __le32 word2;
2154         __le32 sge_len;
2155 };
2156
2157 struct sli4_hybrid_sgl {
2158         struct list_head list_node;
2159         struct sli4_sge *dma_sgl;
2160         dma_addr_t dma_phys_sgl;
2161 };
2162
2163 struct fcp_cmd_rsp_buf {
2164         struct list_head list_node;
2165
2166         /* for storing cmd/rsp dma alloc'ed virt_addr */
2167         struct fcp_cmnd *fcp_cmnd;
2168         struct fcp_rsp *fcp_rsp;
2169
2170         /* for storing this cmd/rsp's dma mapped phys addr from per CPU pool */
2171         dma_addr_t fcp_cmd_rsp_dma_handle;
2172 };
2173
2174 struct sli4_sge_diseed {        /* SLI-4 */
2175         uint32_t ref_tag;
2176         uint32_t ref_tag_tran;
2177
2178         uint32_t word2;
2179 #define lpfc_sli4_sge_dif_apptran_SHIFT 0
2180 #define lpfc_sli4_sge_dif_apptran_MASK  0x0000FFFF
2181 #define lpfc_sli4_sge_dif_apptran_WORD  word2
2182 #define lpfc_sli4_sge_dif_af_SHIFT      24
2183 #define lpfc_sli4_sge_dif_af_MASK       0x00000001
2184 #define lpfc_sli4_sge_dif_af_WORD       word2
2185 #define lpfc_sli4_sge_dif_na_SHIFT      25
2186 #define lpfc_sli4_sge_dif_na_MASK       0x00000001
2187 #define lpfc_sli4_sge_dif_na_WORD       word2
2188 #define lpfc_sli4_sge_dif_hi_SHIFT      26
2189 #define lpfc_sli4_sge_dif_hi_MASK       0x00000001
2190 #define lpfc_sli4_sge_dif_hi_WORD       word2
2191 #define lpfc_sli4_sge_dif_type_SHIFT    27
2192 #define lpfc_sli4_sge_dif_type_MASK     0x0000000F
2193 #define lpfc_sli4_sge_dif_type_WORD     word2
2194 #define lpfc_sli4_sge_dif_last_SHIFT    31 /* Last SEG in the SGL sets it */
2195 #define lpfc_sli4_sge_dif_last_MASK     0x00000001
2196 #define lpfc_sli4_sge_dif_last_WORD     word2
2197         uint32_t word3;
2198 #define lpfc_sli4_sge_dif_apptag_SHIFT  0
2199 #define lpfc_sli4_sge_dif_apptag_MASK   0x0000FFFF
2200 #define lpfc_sli4_sge_dif_apptag_WORD   word3
2201 #define lpfc_sli4_sge_dif_bs_SHIFT      16
2202 #define lpfc_sli4_sge_dif_bs_MASK       0x00000007
2203 #define lpfc_sli4_sge_dif_bs_WORD       word3
2204 #define lpfc_sli4_sge_dif_ai_SHIFT      19
2205 #define lpfc_sli4_sge_dif_ai_MASK       0x00000001
2206 #define lpfc_sli4_sge_dif_ai_WORD       word3
2207 #define lpfc_sli4_sge_dif_me_SHIFT      20
2208 #define lpfc_sli4_sge_dif_me_MASK       0x00000001
2209 #define lpfc_sli4_sge_dif_me_WORD       word3
2210 #define lpfc_sli4_sge_dif_re_SHIFT      21
2211 #define lpfc_sli4_sge_dif_re_MASK       0x00000001
2212 #define lpfc_sli4_sge_dif_re_WORD       word3
2213 #define lpfc_sli4_sge_dif_ce_SHIFT      22
2214 #define lpfc_sli4_sge_dif_ce_MASK       0x00000001
2215 #define lpfc_sli4_sge_dif_ce_WORD       word3
2216 #define lpfc_sli4_sge_dif_nr_SHIFT      23
2217 #define lpfc_sli4_sge_dif_nr_MASK       0x00000001
2218 #define lpfc_sli4_sge_dif_nr_WORD       word3
2219 #define lpfc_sli4_sge_dif_oprx_SHIFT    24
2220 #define lpfc_sli4_sge_dif_oprx_MASK     0x0000000F
2221 #define lpfc_sli4_sge_dif_oprx_WORD     word3
2222 #define lpfc_sli4_sge_dif_optx_SHIFT    28
2223 #define lpfc_sli4_sge_dif_optx_MASK     0x0000000F
2224 #define lpfc_sli4_sge_dif_optx_WORD     word3
2225 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */
2226 };
2227
2228 struct fcf_record {
2229         uint32_t max_rcv_size;
2230         uint32_t fka_adv_period;
2231         uint32_t fip_priority;
2232         uint32_t word3;
2233 #define lpfc_fcf_record_mac_0_SHIFT             0
2234 #define lpfc_fcf_record_mac_0_MASK              0x000000FF
2235 #define lpfc_fcf_record_mac_0_WORD              word3
2236 #define lpfc_fcf_record_mac_1_SHIFT             8
2237 #define lpfc_fcf_record_mac_1_MASK              0x000000FF
2238 #define lpfc_fcf_record_mac_1_WORD              word3
2239 #define lpfc_fcf_record_mac_2_SHIFT             16
2240 #define lpfc_fcf_record_mac_2_MASK              0x000000FF
2241 #define lpfc_fcf_record_mac_2_WORD              word3
2242 #define lpfc_fcf_record_mac_3_SHIFT             24
2243 #define lpfc_fcf_record_mac_3_MASK              0x000000FF
2244 #define lpfc_fcf_record_mac_3_WORD              word3
2245         uint32_t word4;
2246 #define lpfc_fcf_record_mac_4_SHIFT             0
2247 #define lpfc_fcf_record_mac_4_MASK              0x000000FF
2248 #define lpfc_fcf_record_mac_4_WORD              word4
2249 #define lpfc_fcf_record_mac_5_SHIFT             8
2250 #define lpfc_fcf_record_mac_5_MASK              0x000000FF
2251 #define lpfc_fcf_record_mac_5_WORD              word4
2252 #define lpfc_fcf_record_fcf_avail_SHIFT         16
2253 #define lpfc_fcf_record_fcf_avail_MASK          0x000000FF
2254 #define lpfc_fcf_record_fcf_avail_WORD          word4
2255 #define lpfc_fcf_record_mac_addr_prov_SHIFT     24
2256 #define lpfc_fcf_record_mac_addr_prov_MASK      0x000000FF
2257 #define lpfc_fcf_record_mac_addr_prov_WORD      word4
2258 #define LPFC_FCF_FPMA           1       /* Fabric Provided MAC Address */
2259 #define LPFC_FCF_SPMA           2       /* Server Provided MAC Address */
2260         uint32_t word5;
2261 #define lpfc_fcf_record_fab_name_0_SHIFT        0
2262 #define lpfc_fcf_record_fab_name_0_MASK         0x000000FF
2263 #define lpfc_fcf_record_fab_name_0_WORD         word5
2264 #define lpfc_fcf_record_fab_name_1_SHIFT        8
2265 #define lpfc_fcf_record_fab_name_1_MASK         0x000000FF
2266 #define lpfc_fcf_record_fab_name_1_WORD         word5
2267 #define lpfc_fcf_record_fab_name_2_SHIFT        16
2268 #define lpfc_fcf_record_fab_name_2_MASK         0x000000FF
2269 #define lpfc_fcf_record_fab_name_2_WORD         word5
2270 #define lpfc_fcf_record_fab_name_3_SHIFT        24
2271 #define lpfc_fcf_record_fab_name_3_MASK         0x000000FF
2272 #define lpfc_fcf_record_fab_name_3_WORD         word5
2273         uint32_t word6;
2274 #define lpfc_fcf_record_fab_name_4_SHIFT        0
2275 #define lpfc_fcf_record_fab_name_4_MASK         0x000000FF
2276 #define lpfc_fcf_record_fab_name_4_WORD         word6
2277 #define lpfc_fcf_record_fab_name_5_SHIFT        8
2278 #define lpfc_fcf_record_fab_name_5_MASK         0x000000FF
2279 #define lpfc_fcf_record_fab_name_5_WORD         word6
2280 #define lpfc_fcf_record_fab_name_6_SHIFT        16
2281 #define lpfc_fcf_record_fab_name_6_MASK         0x000000FF
2282 #define lpfc_fcf_record_fab_name_6_WORD         word6
2283 #define lpfc_fcf_record_fab_name_7_SHIFT        24
2284 #define lpfc_fcf_record_fab_name_7_MASK         0x000000FF
2285 #define lpfc_fcf_record_fab_name_7_WORD         word6
2286         uint32_t word7;
2287 #define lpfc_fcf_record_fc_map_0_SHIFT          0
2288 #define lpfc_fcf_record_fc_map_0_MASK           0x000000FF
2289 #define lpfc_fcf_record_fc_map_0_WORD           word7
2290 #define lpfc_fcf_record_fc_map_1_SHIFT          8
2291 #define lpfc_fcf_record_fc_map_1_MASK           0x000000FF
2292 #define lpfc_fcf_record_fc_map_1_WORD           word7
2293 #define lpfc_fcf_record_fc_map_2_SHIFT          16
2294 #define lpfc_fcf_record_fc_map_2_MASK           0x000000FF
2295 #define lpfc_fcf_record_fc_map_2_WORD           word7
2296 #define lpfc_fcf_record_fcf_valid_SHIFT         24
2297 #define lpfc_fcf_record_fcf_valid_MASK          0x00000001
2298 #define lpfc_fcf_record_fcf_valid_WORD          word7
2299 #define lpfc_fcf_record_fcf_fc_SHIFT            25
2300 #define lpfc_fcf_record_fcf_fc_MASK             0x00000001
2301 #define lpfc_fcf_record_fcf_fc_WORD             word7
2302 #define lpfc_fcf_record_fcf_sol_SHIFT           31
2303 #define lpfc_fcf_record_fcf_sol_MASK            0x00000001
2304 #define lpfc_fcf_record_fcf_sol_WORD            word7
2305         uint32_t word8;
2306 #define lpfc_fcf_record_fcf_index_SHIFT         0
2307 #define lpfc_fcf_record_fcf_index_MASK          0x0000FFFF
2308 #define lpfc_fcf_record_fcf_index_WORD          word8
2309 #define lpfc_fcf_record_fcf_state_SHIFT         16
2310 #define lpfc_fcf_record_fcf_state_MASK          0x0000FFFF
2311 #define lpfc_fcf_record_fcf_state_WORD          word8
2312         uint8_t vlan_bitmap[512];
2313         uint32_t word137;
2314 #define lpfc_fcf_record_switch_name_0_SHIFT     0
2315 #define lpfc_fcf_record_switch_name_0_MASK      0x000000FF
2316 #define lpfc_fcf_record_switch_name_0_WORD      word137
2317 #define lpfc_fcf_record_switch_name_1_SHIFT     8
2318 #define lpfc_fcf_record_switch_name_1_MASK      0x000000FF
2319 #define lpfc_fcf_record_switch_name_1_WORD      word137
2320 #define lpfc_fcf_record_switch_name_2_SHIFT     16
2321 #define lpfc_fcf_record_switch_name_2_MASK      0x000000FF
2322 #define lpfc_fcf_record_switch_name_2_WORD      word137
2323 #define lpfc_fcf_record_switch_name_3_SHIFT     24
2324 #define lpfc_fcf_record_switch_name_3_MASK      0x000000FF
2325 #define lpfc_fcf_record_switch_name_3_WORD      word137
2326         uint32_t word138;
2327 #define lpfc_fcf_record_switch_name_4_SHIFT     0
2328 #define lpfc_fcf_record_switch_name_4_MASK      0x000000FF
2329 #define lpfc_fcf_record_switch_name_4_WORD      word138
2330 #define lpfc_fcf_record_switch_name_5_SHIFT     8
2331 #define lpfc_fcf_record_switch_name_5_MASK      0x000000FF
2332 #define lpfc_fcf_record_switch_name_5_WORD      word138
2333 #define lpfc_fcf_record_switch_name_6_SHIFT     16
2334 #define lpfc_fcf_record_switch_name_6_MASK      0x000000FF
2335 #define lpfc_fcf_record_switch_name_6_WORD      word138
2336 #define lpfc_fcf_record_switch_name_7_SHIFT     24
2337 #define lpfc_fcf_record_switch_name_7_MASK      0x000000FF
2338 #define lpfc_fcf_record_switch_name_7_WORD      word138
2339 };
2340
2341 struct lpfc_mbx_read_fcf_tbl {
2342         union lpfc_sli4_cfg_shdr cfg_shdr;
2343         union {
2344                 struct {
2345                         uint32_t word10;
2346 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT        0
2347 #define lpfc_mbx_read_fcf_tbl_indx_MASK         0x0000FFFF
2348 #define lpfc_mbx_read_fcf_tbl_indx_WORD         word10
2349                 } request;
2350                 struct {
2351                         uint32_t eventag;
2352                 } response;
2353         } u;
2354         uint32_t word11;
2355 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT   0
2356 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK    0x0000FFFF
2357 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD    word11
2358 };
2359
2360 struct lpfc_mbx_add_fcf_tbl_entry {
2361         union lpfc_sli4_cfg_shdr cfg_shdr;
2362         uint32_t word10;
2363 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT        0
2364 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK         0x0000FFFF
2365 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD         word10
2366         struct lpfc_mbx_sge fcf_sge;
2367 };
2368
2369 struct lpfc_mbx_del_fcf_tbl_entry {
2370         struct mbox_header header;
2371         uint32_t word10;
2372 #define lpfc_mbx_del_fcf_tbl_count_SHIFT        0
2373 #define lpfc_mbx_del_fcf_tbl_count_MASK         0x0000FFFF
2374 #define lpfc_mbx_del_fcf_tbl_count_WORD         word10
2375 #define lpfc_mbx_del_fcf_tbl_index_SHIFT        16
2376 #define lpfc_mbx_del_fcf_tbl_index_MASK         0x0000FFFF
2377 #define lpfc_mbx_del_fcf_tbl_index_WORD         word10
2378 };
2379
2380 struct lpfc_mbx_redisc_fcf_tbl {
2381         struct mbox_header header;
2382         uint32_t word10;
2383 #define lpfc_mbx_redisc_fcf_count_SHIFT         0
2384 #define lpfc_mbx_redisc_fcf_count_MASK          0x0000FFFF
2385 #define lpfc_mbx_redisc_fcf_count_WORD          word10
2386         uint32_t resvd;
2387         uint32_t word12;
2388 #define lpfc_mbx_redisc_fcf_index_SHIFT         0
2389 #define lpfc_mbx_redisc_fcf_index_MASK          0x0000FFFF
2390 #define lpfc_mbx_redisc_fcf_index_WORD          word12
2391 };
2392
2393 /* Status field for embedded SLI_CONFIG mailbox command */
2394 #define STATUS_SUCCESS                                  0x0
2395 #define STATUS_FAILED                                   0x1
2396 #define STATUS_ILLEGAL_REQUEST                          0x2
2397 #define STATUS_ILLEGAL_FIELD                            0x3
2398 #define STATUS_INSUFFICIENT_BUFFER                      0x4
2399 #define STATUS_UNAUTHORIZED_REQUEST                     0x5
2400 #define STATUS_FLASHROM_SAVE_FAILED                     0x17
2401 #define STATUS_FLASHROM_RESTORE_FAILED                  0x18
2402 #define STATUS_ICCBINDEX_ALLOC_FAILED                   0x1a
2403 #define STATUS_IOCTLHANDLE_ALLOC_FAILED                 0x1b
2404 #define STATUS_INVALID_PHY_ADDR_FROM_OSM                0x1c
2405 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM            0x1d
2406 #define STATUS_ASSERT_FAILED                            0x1e
2407 #define STATUS_INVALID_SESSION                          0x1f
2408 #define STATUS_INVALID_CONNECTION                       0x20
2409 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT               0x21
2410 #define STATUS_BTL_NO_FREE_SLOT_PATH                    0x24
2411 #define STATUS_BTL_NO_FREE_SLOT_TGTID                   0x25
2412 #define STATUS_OSM_DEVSLOT_NOT_FOUND                    0x26
2413 #define STATUS_FLASHROM_READ_FAILED                     0x27
2414 #define STATUS_POLL_IOCTL_TIMEOUT                       0x28
2415 #define STATUS_ERROR_ACITMAIN                           0x2a
2416 #define STATUS_REBOOT_REQUIRED                          0x2c
2417 #define STATUS_FCF_IN_USE                               0x3a
2418 #define STATUS_FCF_TABLE_EMPTY                          0x43
2419
2420 /*
2421  * Additional status field for embedded SLI_CONFIG mailbox
2422  * command.
2423  */
2424 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE             0x67
2425 #define ADD_STATUS_FW_NOT_SUPPORTED                     0xEB
2426 #define ADD_STATUS_INVALID_REQUEST                      0x4B
2427 #define ADD_STATUS_INVALID_OBJECT_NAME                  0xA0
2428 #define ADD_STATUS_FW_DOWNLOAD_HW_DISABLED              0x58
2429
2430 struct lpfc_mbx_sli4_config {
2431         struct mbox_header header;
2432 };
2433
2434 struct lpfc_mbx_init_vfi {
2435         uint32_t word1;
2436 #define lpfc_init_vfi_vr_SHIFT          31
2437 #define lpfc_init_vfi_vr_MASK           0x00000001
2438 #define lpfc_init_vfi_vr_WORD           word1
2439 #define lpfc_init_vfi_vt_SHIFT          30
2440 #define lpfc_init_vfi_vt_MASK           0x00000001
2441 #define lpfc_init_vfi_vt_WORD           word1
2442 #define lpfc_init_vfi_vf_SHIFT          29
2443 #define lpfc_init_vfi_vf_MASK           0x00000001
2444 #define lpfc_init_vfi_vf_WORD           word1
2445 #define lpfc_init_vfi_vp_SHIFT          28
2446 #define lpfc_init_vfi_vp_MASK           0x00000001
2447 #define lpfc_init_vfi_vp_WORD           word1
2448 #define lpfc_init_vfi_vfi_SHIFT         0
2449 #define lpfc_init_vfi_vfi_MASK          0x0000FFFF
2450 #define lpfc_init_vfi_vfi_WORD          word1
2451         uint32_t word2;
2452 #define lpfc_init_vfi_vpi_SHIFT         16
2453 #define lpfc_init_vfi_vpi_MASK          0x0000FFFF
2454 #define lpfc_init_vfi_vpi_WORD          word2
2455 #define lpfc_init_vfi_fcfi_SHIFT        0
2456 #define lpfc_init_vfi_fcfi_MASK         0x0000FFFF
2457 #define lpfc_init_vfi_fcfi_WORD         word2
2458         uint32_t word3;
2459 #define lpfc_init_vfi_pri_SHIFT         13
2460 #define lpfc_init_vfi_pri_MASK          0x00000007
2461 #define lpfc_init_vfi_pri_WORD          word3
2462 #define lpfc_init_vfi_vf_id_SHIFT       1
2463 #define lpfc_init_vfi_vf_id_MASK        0x00000FFF
2464 #define lpfc_init_vfi_vf_id_WORD        word3
2465         uint32_t word4;
2466 #define lpfc_init_vfi_hop_count_SHIFT   24
2467 #define lpfc_init_vfi_hop_count_MASK    0x000000FF
2468 #define lpfc_init_vfi_hop_count_WORD    word4
2469 };
2470 #define MBX_VFI_IN_USE                  0x9F02
2471
2472
2473 struct lpfc_mbx_reg_vfi {
2474         uint32_t word1;
2475 #define lpfc_reg_vfi_upd_SHIFT          29
2476 #define lpfc_reg_vfi_upd_MASK           0x00000001
2477 #define lpfc_reg_vfi_upd_WORD           word1
2478 #define lpfc_reg_vfi_vp_SHIFT           28
2479 #define lpfc_reg_vfi_vp_MASK            0x00000001
2480 #define lpfc_reg_vfi_vp_WORD            word1
2481 #define lpfc_reg_vfi_vfi_SHIFT          0
2482 #define lpfc_reg_vfi_vfi_MASK           0x0000FFFF
2483 #define lpfc_reg_vfi_vfi_WORD           word1
2484         uint32_t word2;
2485 #define lpfc_reg_vfi_vpi_SHIFT          16
2486 #define lpfc_reg_vfi_vpi_MASK           0x0000FFFF
2487 #define lpfc_reg_vfi_vpi_WORD           word2
2488 #define lpfc_reg_vfi_fcfi_SHIFT         0
2489 #define lpfc_reg_vfi_fcfi_MASK          0x0000FFFF
2490 #define lpfc_reg_vfi_fcfi_WORD          word2
2491         uint32_t wwn[2];
2492         struct ulp_bde64 bde;
2493         uint32_t e_d_tov;
2494         uint32_t r_a_tov;
2495         uint32_t word10;
2496 #define lpfc_reg_vfi_nport_id_SHIFT     0
2497 #define lpfc_reg_vfi_nport_id_MASK      0x00FFFFFF
2498 #define lpfc_reg_vfi_nport_id_WORD      word10
2499 #define lpfc_reg_vfi_bbcr_SHIFT         27
2500 #define lpfc_reg_vfi_bbcr_MASK          0x00000001
2501 #define lpfc_reg_vfi_bbcr_WORD          word10
2502 #define lpfc_reg_vfi_bbscn_SHIFT        28
2503 #define lpfc_reg_vfi_bbscn_MASK         0x0000000F
2504 #define lpfc_reg_vfi_bbscn_WORD         word10
2505 };
2506
2507 struct lpfc_mbx_init_vpi {
2508         uint32_t word1;
2509 #define lpfc_init_vpi_vfi_SHIFT         16
2510 #define lpfc_init_vpi_vfi_MASK          0x0000FFFF
2511 #define lpfc_init_vpi_vfi_WORD          word1
2512 #define lpfc_init_vpi_vpi_SHIFT         0
2513 #define lpfc_init_vpi_vpi_MASK          0x0000FFFF
2514 #define lpfc_init_vpi_vpi_WORD          word1
2515 };
2516
2517 struct lpfc_mbx_read_vpi {
2518         uint32_t word1_rsvd;
2519         uint32_t word2;
2520 #define lpfc_mbx_read_vpi_vnportid_SHIFT        0
2521 #define lpfc_mbx_read_vpi_vnportid_MASK         0x00FFFFFF
2522 #define lpfc_mbx_read_vpi_vnportid_WORD         word2
2523         uint32_t word3_rsvd;
2524         uint32_t word4;
2525 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT        0
2526 #define lpfc_mbx_read_vpi_acq_alpa_MASK         0x000000FF
2527 #define lpfc_mbx_read_vpi_acq_alpa_WORD         word4
2528 #define lpfc_mbx_read_vpi_pb_SHIFT              15
2529 #define lpfc_mbx_read_vpi_pb_MASK               0x00000001
2530 #define lpfc_mbx_read_vpi_pb_WORD               word4
2531 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT       16
2532 #define lpfc_mbx_read_vpi_spec_alpa_MASK        0x000000FF
2533 #define lpfc_mbx_read_vpi_spec_alpa_WORD        word4
2534 #define lpfc_mbx_read_vpi_ns_SHIFT              30
2535 #define lpfc_mbx_read_vpi_ns_MASK               0x00000001
2536 #define lpfc_mbx_read_vpi_ns_WORD               word4
2537 #define lpfc_mbx_read_vpi_hl_SHIFT              31
2538 #define lpfc_mbx_read_vpi_hl_MASK               0x00000001
2539 #define lpfc_mbx_read_vpi_hl_WORD               word4
2540         uint32_t word5_rsvd;
2541         uint32_t word6;
2542 #define lpfc_mbx_read_vpi_vpi_SHIFT             0
2543 #define lpfc_mbx_read_vpi_vpi_MASK              0x0000FFFF
2544 #define lpfc_mbx_read_vpi_vpi_WORD              word6
2545         uint32_t word7;
2546 #define lpfc_mbx_read_vpi_mac_0_SHIFT           0
2547 #define lpfc_mbx_read_vpi_mac_0_MASK            0x000000FF
2548 #define lpfc_mbx_read_vpi_mac_0_WORD            word7
2549 #define lpfc_mbx_read_vpi_mac_1_SHIFT           8
2550 #define lpfc_mbx_read_vpi_mac_1_MASK            0x000000FF
2551 #define lpfc_mbx_read_vpi_mac_1_WORD            word7
2552 #define lpfc_mbx_read_vpi_mac_2_SHIFT           16
2553 #define lpfc_mbx_read_vpi_mac_2_MASK            0x000000FF
2554 #define lpfc_mbx_read_vpi_mac_2_WORD            word7
2555 #define lpfc_mbx_read_vpi_mac_3_SHIFT           24
2556 #define lpfc_mbx_read_vpi_mac_3_MASK            0x000000FF
2557 #define lpfc_mbx_read_vpi_mac_3_WORD            word7
2558         uint32_t word8;
2559 #define lpfc_mbx_read_vpi_mac_4_SHIFT           0
2560 #define lpfc_mbx_read_vpi_mac_4_MASK            0x000000FF
2561 #define lpfc_mbx_read_vpi_mac_4_WORD            word8
2562 #define lpfc_mbx_read_vpi_mac_5_SHIFT           8
2563 #define lpfc_mbx_read_vpi_mac_5_MASK            0x000000FF
2564 #define lpfc_mbx_read_vpi_mac_5_WORD            word8
2565 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT        16
2566 #define lpfc_mbx_read_vpi_vlan_tag_MASK         0x00000FFF
2567 #define lpfc_mbx_read_vpi_vlan_tag_WORD         word8
2568 #define lpfc_mbx_read_vpi_vv_SHIFT              28
2569 #define lpfc_mbx_read_vpi_vv_MASK               0x0000001
2570 #define lpfc_mbx_read_vpi_vv_WORD               word8
2571 };
2572
2573 struct lpfc_mbx_unreg_vfi {
2574         uint32_t word1_rsvd;
2575         uint32_t word2;
2576 #define lpfc_unreg_vfi_vfi_SHIFT        0
2577 #define lpfc_unreg_vfi_vfi_MASK         0x0000FFFF
2578 #define lpfc_unreg_vfi_vfi_WORD         word2
2579 };
2580
2581 struct lpfc_mbx_resume_rpi {
2582         uint32_t word1;
2583 #define lpfc_resume_rpi_index_SHIFT     0
2584 #define lpfc_resume_rpi_index_MASK      0x0000FFFF
2585 #define lpfc_resume_rpi_index_WORD      word1
2586 #define lpfc_resume_rpi_ii_SHIFT        30
2587 #define lpfc_resume_rpi_ii_MASK         0x00000003
2588 #define lpfc_resume_rpi_ii_WORD         word1
2589 #define RESUME_INDEX_RPI                0
2590 #define RESUME_INDEX_VPI                1
2591 #define RESUME_INDEX_VFI                2
2592 #define RESUME_INDEX_FCFI               3
2593         uint32_t event_tag;
2594 };
2595
2596 #define REG_FCF_INVALID_QID     0xFFFF
2597 struct lpfc_mbx_reg_fcfi {
2598         uint32_t word1;
2599 #define lpfc_reg_fcfi_info_index_SHIFT  0
2600 #define lpfc_reg_fcfi_info_index_MASK   0x0000FFFF
2601 #define lpfc_reg_fcfi_info_index_WORD   word1
2602 #define lpfc_reg_fcfi_fcfi_SHIFT        16
2603 #define lpfc_reg_fcfi_fcfi_MASK         0x0000FFFF
2604 #define lpfc_reg_fcfi_fcfi_WORD         word1
2605         uint32_t word2;
2606 #define lpfc_reg_fcfi_rq_id1_SHIFT      0
2607 #define lpfc_reg_fcfi_rq_id1_MASK       0x0000FFFF
2608 #define lpfc_reg_fcfi_rq_id1_WORD       word2
2609 #define lpfc_reg_fcfi_rq_id0_SHIFT      16
2610 #define lpfc_reg_fcfi_rq_id0_MASK       0x0000FFFF
2611 #define lpfc_reg_fcfi_rq_id0_WORD       word2
2612         uint32_t word3;
2613 #define lpfc_reg_fcfi_rq_id3_SHIFT      0
2614 #define lpfc_reg_fcfi_rq_id3_MASK       0x0000FFFF
2615 #define lpfc_reg_fcfi_rq_id3_WORD       word3
2616 #define lpfc_reg_fcfi_rq_id2_SHIFT      16
2617 #define lpfc_reg_fcfi_rq_id2_MASK       0x0000FFFF
2618 #define lpfc_reg_fcfi_rq_id2_WORD       word3
2619         uint32_t word4;
2620 #define lpfc_reg_fcfi_type_match0_SHIFT 24
2621 #define lpfc_reg_fcfi_type_match0_MASK  0x000000FF
2622 #define lpfc_reg_fcfi_type_match0_WORD  word4
2623 #define lpfc_reg_fcfi_type_mask0_SHIFT  16
2624 #define lpfc_reg_fcfi_type_mask0_MASK   0x000000FF
2625 #define lpfc_reg_fcfi_type_mask0_WORD   word4
2626 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8
2627 #define lpfc_reg_fcfi_rctl_match0_MASK  0x000000FF
2628 #define lpfc_reg_fcfi_rctl_match0_WORD  word4
2629 #define lpfc_reg_fcfi_rctl_mask0_SHIFT  0
2630 #define lpfc_reg_fcfi_rctl_mask0_MASK   0x000000FF
2631 #define lpfc_reg_fcfi_rctl_mask0_WORD   word4
2632         uint32_t word5;
2633 #define lpfc_reg_fcfi_type_match1_SHIFT 24
2634 #define lpfc_reg_fcfi_type_match1_MASK  0x000000FF
2635 #define lpfc_reg_fcfi_type_match1_WORD  word5
2636 #define lpfc_reg_fcfi_type_mask1_SHIFT  16
2637 #define lpfc_reg_fcfi_type_mask1_MASK   0x000000FF
2638 #define lpfc_reg_fcfi_type_mask1_WORD   word5
2639 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8
2640 #define lpfc_reg_fcfi_rctl_match1_MASK  0x000000FF
2641 #define lpfc_reg_fcfi_rctl_match1_WORD  word5
2642 #define lpfc_reg_fcfi_rctl_mask1_SHIFT  0
2643 #define lpfc_reg_fcfi_rctl_mask1_MASK   0x000000FF
2644 #define lpfc_reg_fcfi_rctl_mask1_WORD   word5
2645         uint32_t word6;
2646 #define lpfc_reg_fcfi_type_match2_SHIFT 24
2647 #define lpfc_reg_fcfi_type_match2_MASK  0x000000FF
2648 #define lpfc_reg_fcfi_type_match2_WORD  word6
2649 #define lpfc_reg_fcfi_type_mask2_SHIFT  16
2650 #define lpfc_reg_fcfi_type_mask2_MASK   0x000000FF
2651 #define lpfc_reg_fcfi_type_mask2_WORD   word6
2652 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8
2653 #define lpfc_reg_fcfi_rctl_match2_MASK  0x000000FF
2654 #define lpfc_reg_fcfi_rctl_match2_WORD  word6
2655 #define lpfc_reg_fcfi_rctl_mask2_SHIFT  0
2656 #define lpfc_reg_fcfi_rctl_mask2_MASK   0x000000FF
2657 #define lpfc_reg_fcfi_rctl_mask2_WORD   word6
2658         uint32_t word7;
2659 #define lpfc_reg_fcfi_type_match3_SHIFT 24
2660 #define lpfc_reg_fcfi_type_match3_MASK  0x000000FF
2661 #define lpfc_reg_fcfi_type_match3_WORD  word7
2662 #define lpfc_reg_fcfi_type_mask3_SHIFT  16
2663 #define lpfc_reg_fcfi_type_mask3_MASK   0x000000FF
2664 #define lpfc_reg_fcfi_type_mask3_WORD   word7
2665 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8
2666 #define lpfc_reg_fcfi_rctl_match3_MASK  0x000000FF
2667 #define lpfc_reg_fcfi_rctl_match3_WORD  word7
2668 #define lpfc_reg_fcfi_rctl_mask3_SHIFT  0
2669 #define lpfc_reg_fcfi_rctl_mask3_MASK   0x000000FF
2670 #define lpfc_reg_fcfi_rctl_mask3_WORD   word7
2671         uint32_t word8;
2672 #define lpfc_reg_fcfi_mam_SHIFT         13
2673 #define lpfc_reg_fcfi_mam_MASK          0x00000003
2674 #define lpfc_reg_fcfi_mam_WORD          word8
2675 #define LPFC_MAM_BOTH           0       /* Both SPMA and FPMA */
2676 #define LPFC_MAM_SPMA           1       /* Server Provided MAC Address */
2677 #define LPFC_MAM_FPMA           2       /* Fabric Provided MAC Address */
2678 #define lpfc_reg_fcfi_vv_SHIFT          12
2679 #define lpfc_reg_fcfi_vv_MASK           0x00000001
2680 #define lpfc_reg_fcfi_vv_WORD           word8
2681 #define lpfc_reg_fcfi_vlan_tag_SHIFT    0
2682 #define lpfc_reg_fcfi_vlan_tag_MASK     0x00000FFF
2683 #define lpfc_reg_fcfi_vlan_tag_WORD     word8
2684 };
2685
2686 struct lpfc_mbx_reg_fcfi_mrq {
2687         uint32_t word1;
2688 #define lpfc_reg_fcfi_mrq_info_index_SHIFT      0
2689 #define lpfc_reg_fcfi_mrq_info_index_MASK       0x0000FFFF
2690 #define lpfc_reg_fcfi_mrq_info_index_WORD       word1
2691 #define lpfc_reg_fcfi_mrq_fcfi_SHIFT            16
2692 #define lpfc_reg_fcfi_mrq_fcfi_MASK             0x0000FFFF
2693 #define lpfc_reg_fcfi_mrq_fcfi_WORD             word1
2694         uint32_t word2;
2695 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT          0
2696 #define lpfc_reg_fcfi_mrq_rq_id1_MASK           0x0000FFFF
2697 #define lpfc_reg_fcfi_mrq_rq_id1_WORD           word2
2698 #define lpfc_reg_fcfi_mrq_rq_id0_SHIFT          16
2699 #define lpfc_reg_fcfi_mrq_rq_id0_MASK           0x0000FFFF
2700 #define lpfc_reg_fcfi_mrq_rq_id0_WORD           word2
2701         uint32_t word3;
2702 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT          0
2703 #define lpfc_reg_fcfi_mrq_rq_id3_MASK           0x0000FFFF
2704 #define lpfc_reg_fcfi_mrq_rq_id3_WORD           word3
2705 #define lpfc_reg_fcfi_mrq_rq_id2_SHIFT          16
2706 #define lpfc_reg_fcfi_mrq_rq_id2_MASK           0x0000FFFF
2707 #define lpfc_reg_fcfi_mrq_rq_id2_WORD           word3
2708         uint32_t word4;
2709 #define lpfc_reg_fcfi_mrq_type_match0_SHIFT     24
2710 #define lpfc_reg_fcfi_mrq_type_match0_MASK      0x000000FF
2711 #define lpfc_reg_fcfi_mrq_type_match0_WORD      word4
2712 #define lpfc_reg_fcfi_mrq_type_mask0_SHIFT      16
2713 #define lpfc_reg_fcfi_mrq_type_mask0_MASK       0x000000FF
2714 #define lpfc_reg_fcfi_mrq_type_mask0_WORD       word4
2715 #define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT     8
2716 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK      0x000000FF
2717 #define lpfc_reg_fcfi_mrq_rctl_match0_WORD      word4
2718 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT      0
2719 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK       0x000000FF
2720 #define lpfc_reg_fcfi_mrq_rctl_mask0_WORD       word4
2721         uint32_t word5;
2722 #define lpfc_reg_fcfi_mrq_type_match1_SHIFT     24
2723 #define lpfc_reg_fcfi_mrq_type_match1_MASK      0x000000FF
2724 #define lpfc_reg_fcfi_mrq_type_match1_WORD      word5
2725 #define lpfc_reg_fcfi_mrq_type_mask1_SHIFT      16
2726 #define lpfc_reg_fcfi_mrq_type_mask1_MASK       0x000000FF
2727 #define lpfc_reg_fcfi_mrq_type_mask1_WORD       word5
2728 #define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT     8
2729 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK      0x000000FF
2730 #define lpfc_reg_fcfi_mrq_rctl_match1_WORD      word5
2731 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT      0
2732 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK       0x000000FF
2733 #define lpfc_reg_fcfi_mrq_rctl_mask1_WORD       word5
2734         uint32_t word6;
2735 #define lpfc_reg_fcfi_mrq_type_match2_SHIFT     24
2736 #define lpfc_reg_fcfi_mrq_type_match2_MASK      0x000000FF
2737 #define lpfc_reg_fcfi_mrq_type_match2_WORD      word6
2738 #define lpfc_reg_fcfi_mrq_type_mask2_SHIFT      16
2739 #define lpfc_reg_fcfi_mrq_type_mask2_MASK       0x000000FF
2740 #define lpfc_reg_fcfi_mrq_type_mask2_WORD       word6
2741 #define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT     8
2742 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK      0x000000FF
2743 #define lpfc_reg_fcfi_mrq_rctl_match2_WORD      word6
2744 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT      0
2745 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK       0x000000FF
2746 #define lpfc_reg_fcfi_mrq_rctl_mask2_WORD       word6
2747         uint32_t word7;
2748 #define lpfc_reg_fcfi_mrq_type_match3_SHIFT     24
2749 #define lpfc_reg_fcfi_mrq_type_match3_MASK      0x000000FF
2750 #define lpfc_reg_fcfi_mrq_type_match3_WORD      word7
2751 #define lpfc_reg_fcfi_mrq_type_mask3_SHIFT      16
2752 #define lpfc_reg_fcfi_mrq_type_mask3_MASK       0x000000FF
2753 #define lpfc_reg_fcfi_mrq_type_mask3_WORD       word7
2754 #define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT     8
2755 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK      0x000000FF
2756 #define lpfc_reg_fcfi_mrq_rctl_match3_WORD      word7
2757 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT      0
2758 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK       0x000000FF
2759 #define lpfc_reg_fcfi_mrq_rctl_mask3_WORD       word7
2760         uint32_t word8;
2761 #define lpfc_reg_fcfi_mrq_ptc7_SHIFT            31
2762 #define lpfc_reg_fcfi_mrq_ptc7_MASK             0x00000001
2763 #define lpfc_reg_fcfi_mrq_ptc7_WORD             word8
2764 #define lpfc_reg_fcfi_mrq_ptc6_SHIFT            30
2765 #define lpfc_reg_fcfi_mrq_ptc6_MASK             0x00000001
2766 #define lpfc_reg_fcfi_mrq_ptc6_WORD             word8
2767 #define lpfc_reg_fcfi_mrq_ptc5_SHIFT            29
2768 #define lpfc_reg_fcfi_mrq_ptc5_MASK             0x00000001
2769 #define lpfc_reg_fcfi_mrq_ptc5_WORD             word8
2770 #define lpfc_reg_fcfi_mrq_ptc4_SHIFT            28
2771 #define lpfc_reg_fcfi_mrq_ptc4_MASK             0x00000001
2772 #define lpfc_reg_fcfi_mrq_ptc4_WORD             word8
2773 #define lpfc_reg_fcfi_mrq_ptc3_SHIFT            27
2774 #define lpfc_reg_fcfi_mrq_ptc3_MASK             0x00000001
2775 #define lpfc_reg_fcfi_mrq_ptc3_WORD             word8
2776 #define lpfc_reg_fcfi_mrq_ptc2_SHIFT            26
2777 #define lpfc_reg_fcfi_mrq_ptc2_MASK             0x00000001
2778 #define lpfc_reg_fcfi_mrq_ptc2_WORD             word8
2779 #define lpfc_reg_fcfi_mrq_ptc1_SHIFT            25
2780 #define lpfc_reg_fcfi_mrq_ptc1_MASK             0x00000001
2781 #define lpfc_reg_fcfi_mrq_ptc1_WORD             word8
2782 #define lpfc_reg_fcfi_mrq_ptc0_SHIFT            24
2783 #define lpfc_reg_fcfi_mrq_ptc0_MASK             0x00000001
2784 #define lpfc_reg_fcfi_mrq_ptc0_WORD             word8
2785 #define lpfc_reg_fcfi_mrq_pt7_SHIFT             23
2786 #define lpfc_reg_fcfi_mrq_pt7_MASK              0x00000001
2787 #define lpfc_reg_fcfi_mrq_pt7_WORD              word8
2788 #define lpfc_reg_fcfi_mrq_pt6_SHIFT             22
2789 #define lpfc_reg_fcfi_mrq_pt6_MASK              0x00000001
2790 #define lpfc_reg_fcfi_mrq_pt6_WORD              word8
2791 #define lpfc_reg_fcfi_mrq_pt5_SHIFT             21
2792 #define lpfc_reg_fcfi_mrq_pt5_MASK              0x00000001
2793 #define lpfc_reg_fcfi_mrq_pt5_WORD              word8
2794 #define lpfc_reg_fcfi_mrq_pt4_SHIFT             20
2795 #define lpfc_reg_fcfi_mrq_pt4_MASK              0x00000001
2796 #define lpfc_reg_fcfi_mrq_pt4_WORD              word8
2797 #define lpfc_reg_fcfi_mrq_pt3_SHIFT             19
2798 #define lpfc_reg_fcfi_mrq_pt3_MASK              0x00000001
2799 #define lpfc_reg_fcfi_mrq_pt3_WORD              word8
2800 #define lpfc_reg_fcfi_mrq_pt2_SHIFT             18
2801 #define lpfc_reg_fcfi_mrq_pt2_MASK              0x00000001
2802 #define lpfc_reg_fcfi_mrq_pt2_WORD              word8
2803 #define lpfc_reg_fcfi_mrq_pt1_SHIFT             17
2804 #define lpfc_reg_fcfi_mrq_pt1_MASK              0x00000001
2805 #define lpfc_reg_fcfi_mrq_pt1_WORD              word8
2806 #define lpfc_reg_fcfi_mrq_pt0_SHIFT             16
2807 #define lpfc_reg_fcfi_mrq_pt0_MASK              0x00000001
2808 #define lpfc_reg_fcfi_mrq_pt0_WORD              word8
2809 #define lpfc_reg_fcfi_mrq_xmv_SHIFT             15
2810 #define lpfc_reg_fcfi_mrq_xmv_MASK              0x00000001
2811 #define lpfc_reg_fcfi_mrq_xmv_WORD              word8
2812 #define lpfc_reg_fcfi_mrq_mode_SHIFT            13
2813 #define lpfc_reg_fcfi_mrq_mode_MASK             0x00000001
2814 #define lpfc_reg_fcfi_mrq_mode_WORD             word8
2815 #define lpfc_reg_fcfi_mrq_vv_SHIFT              12
2816 #define lpfc_reg_fcfi_mrq_vv_MASK               0x00000001
2817 #define lpfc_reg_fcfi_mrq_vv_WORD               word8
2818 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT        0
2819 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK         0x00000FFF
2820 #define lpfc_reg_fcfi_mrq_vlan_tag_WORD         word8
2821         uint32_t word9;
2822 #define lpfc_reg_fcfi_mrq_policy_SHIFT          12
2823 #define lpfc_reg_fcfi_mrq_policy_MASK           0x0000000F
2824 #define lpfc_reg_fcfi_mrq_policy_WORD           word9
2825 #define lpfc_reg_fcfi_mrq_filter_SHIFT          8
2826 #define lpfc_reg_fcfi_mrq_filter_MASK           0x0000000F
2827 #define lpfc_reg_fcfi_mrq_filter_WORD           word9
2828 #define lpfc_reg_fcfi_mrq_npairs_SHIFT          0
2829 #define lpfc_reg_fcfi_mrq_npairs_MASK           0x000000FF
2830 #define lpfc_reg_fcfi_mrq_npairs_WORD           word9
2831         uint32_t word10;
2832         uint32_t word11;
2833         uint32_t word12;
2834         uint32_t word13;
2835         uint32_t word14;
2836         uint32_t word15;
2837         uint32_t word16;
2838 };
2839
2840 struct lpfc_mbx_unreg_fcfi {
2841         uint32_t word1_rsv;
2842         uint32_t word2;
2843 #define lpfc_unreg_fcfi_SHIFT           0
2844 #define lpfc_unreg_fcfi_MASK            0x0000FFFF
2845 #define lpfc_unreg_fcfi_WORD            word2
2846 };
2847
2848 struct lpfc_mbx_read_rev {
2849         uint32_t word1;
2850 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT           16
2851 #define lpfc_mbx_rd_rev_sli_lvl_MASK            0x0000000F
2852 #define lpfc_mbx_rd_rev_sli_lvl_WORD            word1
2853 #define lpfc_mbx_rd_rev_fcoe_SHIFT              20
2854 #define lpfc_mbx_rd_rev_fcoe_MASK               0x00000001
2855 #define lpfc_mbx_rd_rev_fcoe_WORD               word1
2856 #define lpfc_mbx_rd_rev_cee_ver_SHIFT           21
2857 #define lpfc_mbx_rd_rev_cee_ver_MASK            0x00000003
2858 #define lpfc_mbx_rd_rev_cee_ver_WORD            word1
2859 #define LPFC_PREDCBX_CEE_MODE   0
2860 #define LPFC_DCBX_CEE_MODE      1
2861 #define lpfc_mbx_rd_rev_vpd_SHIFT               29
2862 #define lpfc_mbx_rd_rev_vpd_MASK                0x00000001
2863 #define lpfc_mbx_rd_rev_vpd_WORD                word1
2864         uint32_t first_hw_rev;
2865 #define LPFC_G7_ASIC_1                          0xd
2866         uint32_t second_hw_rev;
2867         uint32_t word4_rsvd;
2868         uint32_t third_hw_rev;
2869         uint32_t word6;
2870 #define lpfc_mbx_rd_rev_fcph_low_SHIFT          0
2871 #define lpfc_mbx_rd_rev_fcph_low_MASK           0x000000FF
2872 #define lpfc_mbx_rd_rev_fcph_low_WORD           word6
2873 #define lpfc_mbx_rd_rev_fcph_high_SHIFT         8
2874 #define lpfc_mbx_rd_rev_fcph_high_MASK          0x000000FF
2875 #define lpfc_mbx_rd_rev_fcph_high_WORD          word6
2876 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT       16
2877 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK        0x000000FF
2878 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD        word6
2879 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT      24
2880 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK       0x000000FF
2881 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD       word6
2882         uint32_t word7_rsvd;
2883         uint32_t fw_id_rev;
2884         uint8_t  fw_name[16];
2885         uint32_t ulp_fw_id_rev;
2886         uint8_t  ulp_fw_name[16];
2887         uint32_t word18_47_rsvd[30];
2888         uint32_t word48;
2889 #define lpfc_mbx_rd_rev_avail_len_SHIFT         0
2890 #define lpfc_mbx_rd_rev_avail_len_MASK          0x00FFFFFF
2891 #define lpfc_mbx_rd_rev_avail_len_WORD          word48
2892         uint32_t vpd_paddr_low;
2893         uint32_t vpd_paddr_high;
2894         uint32_t avail_vpd_len;
2895         uint32_t rsvd_52_63[12];
2896 };
2897
2898 struct lpfc_mbx_read_config {
2899         uint32_t word1;
2900 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT     31
2901 #define lpfc_mbx_rd_conf_extnts_inuse_MASK      0x00000001
2902 #define lpfc_mbx_rd_conf_extnts_inuse_WORD      word1
2903 #define lpfc_mbx_rd_conf_fawwpn_SHIFT           30
2904 #define lpfc_mbx_rd_conf_fawwpn_MASK            0x00000001
2905 #define lpfc_mbx_rd_conf_fawwpn_WORD            word1
2906 #define lpfc_mbx_rd_conf_wcs_SHIFT              28      /* warning signaling */
2907 #define lpfc_mbx_rd_conf_wcs_MASK               0x00000001
2908 #define lpfc_mbx_rd_conf_wcs_WORD               word1
2909 #define lpfc_mbx_rd_conf_acs_SHIFT              27      /* alarm signaling */
2910 #define lpfc_mbx_rd_conf_acs_MASK               0x00000001
2911 #define lpfc_mbx_rd_conf_acs_WORD               word1
2912         uint32_t word2;
2913 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT         0
2914 #define lpfc_mbx_rd_conf_lnk_numb_MASK          0x0000003F
2915 #define lpfc_mbx_rd_conf_lnk_numb_WORD          word2
2916 #define lpfc_mbx_rd_conf_lnk_type_SHIFT         6
2917 #define lpfc_mbx_rd_conf_lnk_type_MASK          0x00000003
2918 #define lpfc_mbx_rd_conf_lnk_type_WORD          word2
2919 #define LPFC_LNK_TYPE_GE        0
2920 #define LPFC_LNK_TYPE_FC        1
2921 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT          8
2922 #define lpfc_mbx_rd_conf_lnk_ldv_MASK           0x00000001
2923 #define lpfc_mbx_rd_conf_lnk_ldv_WORD           word2
2924 #define lpfc_mbx_rd_conf_trunk_SHIFT            12
2925 #define lpfc_mbx_rd_conf_trunk_MASK             0x0000000F
2926 #define lpfc_mbx_rd_conf_trunk_WORD             word2
2927 #define lpfc_mbx_rd_conf_pt_SHIFT               20
2928 #define lpfc_mbx_rd_conf_pt_MASK                0x00000003
2929 #define lpfc_mbx_rd_conf_pt_WORD                word2
2930 #define lpfc_mbx_rd_conf_tf_SHIFT               22
2931 #define lpfc_mbx_rd_conf_tf_MASK                0x00000001
2932 #define lpfc_mbx_rd_conf_tf_WORD                word2
2933 #define lpfc_mbx_rd_conf_ptv_SHIFT              23
2934 #define lpfc_mbx_rd_conf_ptv_MASK               0x00000001
2935 #define lpfc_mbx_rd_conf_ptv_WORD               word2
2936 #define lpfc_mbx_rd_conf_topology_SHIFT         24
2937 #define lpfc_mbx_rd_conf_topology_MASK          0x000000FF
2938 #define lpfc_mbx_rd_conf_topology_WORD          word2
2939         uint32_t rsvd_3;
2940         uint32_t word4;
2941 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT          0
2942 #define lpfc_mbx_rd_conf_e_d_tov_MASK           0x0000FFFF
2943 #define lpfc_mbx_rd_conf_e_d_tov_WORD           word4
2944         uint32_t rsvd_5;
2945         uint32_t word6;
2946 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT          0
2947 #define lpfc_mbx_rd_conf_r_a_tov_MASK           0x0000FFFF
2948 #define lpfc_mbx_rd_conf_r_a_tov_WORD           word6
2949 #define lpfc_mbx_rd_conf_link_speed_SHIFT       16
2950 #define lpfc_mbx_rd_conf_link_speed_MASK        0x0000FFFF
2951 #define lpfc_mbx_rd_conf_link_speed_WORD        word6
2952         uint32_t rsvd_7;
2953         uint32_t word8;
2954 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT        0
2955 #define lpfc_mbx_rd_conf_bbscn_min_MASK         0x0000000F
2956 #define lpfc_mbx_rd_conf_bbscn_min_WORD         word8
2957 #define lpfc_mbx_rd_conf_bbscn_max_SHIFT        4
2958 #define lpfc_mbx_rd_conf_bbscn_max_MASK         0x0000000F
2959 #define lpfc_mbx_rd_conf_bbscn_max_WORD         word8
2960 #define lpfc_mbx_rd_conf_bbscn_def_SHIFT        8
2961 #define lpfc_mbx_rd_conf_bbscn_def_MASK         0x0000000F
2962 #define lpfc_mbx_rd_conf_bbscn_def_WORD         word8
2963         uint32_t word9;
2964 #define lpfc_mbx_rd_conf_lmt_SHIFT              0
2965 #define lpfc_mbx_rd_conf_lmt_MASK               0x0000FFFF
2966 #define lpfc_mbx_rd_conf_lmt_WORD               word9
2967         uint32_t rsvd_10;
2968         uint32_t rsvd_11;
2969         uint32_t word12;
2970 #define lpfc_mbx_rd_conf_xri_base_SHIFT         0
2971 #define lpfc_mbx_rd_conf_xri_base_MASK          0x0000FFFF
2972 #define lpfc_mbx_rd_conf_xri_base_WORD          word12
2973 #define lpfc_mbx_rd_conf_xri_count_SHIFT        16
2974 #define lpfc_mbx_rd_conf_xri_count_MASK         0x0000FFFF
2975 #define lpfc_mbx_rd_conf_xri_count_WORD         word12
2976         uint32_t word13;
2977 #define lpfc_mbx_rd_conf_rpi_base_SHIFT         0
2978 #define lpfc_mbx_rd_conf_rpi_base_MASK          0x0000FFFF
2979 #define lpfc_mbx_rd_conf_rpi_base_WORD          word13
2980 #define lpfc_mbx_rd_conf_rpi_count_SHIFT        16
2981 #define lpfc_mbx_rd_conf_rpi_count_MASK         0x0000FFFF
2982 #define lpfc_mbx_rd_conf_rpi_count_WORD         word13
2983         uint32_t word14;
2984 #define lpfc_mbx_rd_conf_vpi_base_SHIFT         0
2985 #define lpfc_mbx_rd_conf_vpi_base_MASK          0x0000FFFF
2986 #define lpfc_mbx_rd_conf_vpi_base_WORD          word14
2987 #define lpfc_mbx_rd_conf_vpi_count_SHIFT        16
2988 #define lpfc_mbx_rd_conf_vpi_count_MASK         0x0000FFFF
2989 #define lpfc_mbx_rd_conf_vpi_count_WORD         word14
2990         uint32_t word15;
2991 #define lpfc_mbx_rd_conf_vfi_base_SHIFT         0
2992 #define lpfc_mbx_rd_conf_vfi_base_MASK          0x0000FFFF
2993 #define lpfc_mbx_rd_conf_vfi_base_WORD          word15
2994 #define lpfc_mbx_rd_conf_vfi_count_SHIFT        16
2995 #define lpfc_mbx_rd_conf_vfi_count_MASK         0x0000FFFF
2996 #define lpfc_mbx_rd_conf_vfi_count_WORD         word15
2997         uint32_t word16;
2998 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT       16
2999 #define lpfc_mbx_rd_conf_fcfi_count_MASK        0x0000FFFF
3000 #define lpfc_mbx_rd_conf_fcfi_count_WORD        word16
3001         uint32_t word17;
3002 #define lpfc_mbx_rd_conf_rq_count_SHIFT         0
3003 #define lpfc_mbx_rd_conf_rq_count_MASK          0x0000FFFF
3004 #define lpfc_mbx_rd_conf_rq_count_WORD          word17
3005 #define lpfc_mbx_rd_conf_eq_count_SHIFT         16
3006 #define lpfc_mbx_rd_conf_eq_count_MASK          0x0000FFFF
3007 #define lpfc_mbx_rd_conf_eq_count_WORD          word17
3008         uint32_t word18;
3009 #define lpfc_mbx_rd_conf_wq_count_SHIFT         0
3010 #define lpfc_mbx_rd_conf_wq_count_MASK          0x0000FFFF
3011 #define lpfc_mbx_rd_conf_wq_count_WORD          word18
3012 #define lpfc_mbx_rd_conf_cq_count_SHIFT         16
3013 #define lpfc_mbx_rd_conf_cq_count_MASK          0x0000FFFF
3014 #define lpfc_mbx_rd_conf_cq_count_WORD          word18
3015 };
3016
3017 struct lpfc_mbx_request_features {
3018         uint32_t word1;
3019 #define lpfc_mbx_rq_ftr_qry_SHIFT               0
3020 #define lpfc_mbx_rq_ftr_qry_MASK                0x00000001
3021 #define lpfc_mbx_rq_ftr_qry_WORD                word1
3022         uint32_t word2;
3023 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT           0
3024 #define lpfc_mbx_rq_ftr_rq_iaab_MASK            0x00000001
3025 #define lpfc_mbx_rq_ftr_rq_iaab_WORD            word2
3026 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT           1
3027 #define lpfc_mbx_rq_ftr_rq_npiv_MASK            0x00000001
3028 #define lpfc_mbx_rq_ftr_rq_npiv_WORD            word2
3029 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT            2
3030 #define lpfc_mbx_rq_ftr_rq_dif_MASK             0x00000001
3031 #define lpfc_mbx_rq_ftr_rq_dif_WORD             word2
3032 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT             3
3033 #define lpfc_mbx_rq_ftr_rq_vf_MASK              0x00000001
3034 #define lpfc_mbx_rq_ftr_rq_vf_WORD              word2
3035 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT           4
3036 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK            0x00000001
3037 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD            word2
3038 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT           5
3039 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK            0x00000001
3040 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD            word2
3041 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT           6
3042 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK            0x00000001
3043 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD            word2
3044 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT           7
3045 #define lpfc_mbx_rq_ftr_rq_ifip_MASK            0x00000001
3046 #define lpfc_mbx_rq_ftr_rq_ifip_WORD            word2
3047 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT           9
3048 #define lpfc_mbx_rq_ftr_rq_iaar_MASK            0x00000001
3049 #define lpfc_mbx_rq_ftr_rq_iaar_WORD            word2
3050 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT          11
3051 #define lpfc_mbx_rq_ftr_rq_perfh_MASK           0x00000001
3052 #define lpfc_mbx_rq_ftr_rq_perfh_WORD           word2
3053 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT           16
3054 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK            0x00000001
3055 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD            word2
3056 #define lpfc_mbx_rq_ftr_rq_ashdr_SHIFT          17
3057 #define lpfc_mbx_rq_ftr_rq_ashdr_MASK           0x00000001
3058 #define lpfc_mbx_rq_ftr_rq_ashdr_WORD           word2
3059         uint32_t word3;
3060 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT          0
3061 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK           0x00000001
3062 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD           word3
3063 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT          1
3064 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK           0x00000001
3065 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD           word3
3066 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT           2
3067 #define lpfc_mbx_rq_ftr_rsp_dif_MASK            0x00000001
3068 #define lpfc_mbx_rq_ftr_rsp_dif_WORD            word3
3069 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT            3
3070 #define lpfc_mbx_rq_ftr_rsp_vf__MASK            0x00000001
3071 #define lpfc_mbx_rq_ftr_rsp_vf_WORD             word3
3072 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT          4
3073 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK           0x00000001
3074 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD           word3
3075 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT          5
3076 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK           0x00000001
3077 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD           word3
3078 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT          6
3079 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK           0x00000001
3080 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD           word3
3081 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT          7
3082 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK           0x00000001
3083 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD           word3
3084 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT         11
3085 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK          0x00000001
3086 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD          word3
3087 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT          16
3088 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK           0x00000001
3089 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD           word3
3090 #define lpfc_mbx_rq_ftr_rsp_ashdr_SHIFT         17
3091 #define lpfc_mbx_rq_ftr_rsp_ashdr_MASK          0x00000001
3092 #define lpfc_mbx_rq_ftr_rsp_ashdr_WORD          word3
3093 };
3094
3095 struct lpfc_mbx_memory_dump_type3 {
3096         uint32_t word1;
3097 #define lpfc_mbx_memory_dump_type3_type_SHIFT    0
3098 #define lpfc_mbx_memory_dump_type3_type_MASK     0x0000000f
3099 #define lpfc_mbx_memory_dump_type3_type_WORD     word1
3100 #define lpfc_mbx_memory_dump_type3_link_SHIFT    24
3101 #define lpfc_mbx_memory_dump_type3_link_MASK     0x000000ff
3102 #define lpfc_mbx_memory_dump_type3_link_WORD     word1
3103         uint32_t word2;
3104 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT  0
3105 #define lpfc_mbx_memory_dump_type3_page_no_MASK   0x0000ffff
3106 #define lpfc_mbx_memory_dump_type3_page_no_WORD   word2
3107 #define lpfc_mbx_memory_dump_type3_offset_SHIFT   16
3108 #define lpfc_mbx_memory_dump_type3_offset_MASK    0x0000ffff
3109 #define lpfc_mbx_memory_dump_type3_offset_WORD    word2
3110         uint32_t word3;
3111 #define lpfc_mbx_memory_dump_type3_length_SHIFT  0
3112 #define lpfc_mbx_memory_dump_type3_length_MASK   0x00ffffff
3113 #define lpfc_mbx_memory_dump_type3_length_WORD   word3
3114         uint32_t addr_lo;
3115         uint32_t addr_hi;
3116         uint32_t return_len;
3117 };
3118
3119 #define DMP_PAGE_A0             0xa0
3120 #define DMP_PAGE_A2             0xa2
3121 #define DMP_SFF_PAGE_A0_SIZE    256
3122 #define DMP_SFF_PAGE_A2_SIZE    256
3123
3124 #define SFP_WAVELENGTH_LC1310   1310
3125 #define SFP_WAVELENGTH_LL1550   1550
3126
3127
3128 /*
3129  *  * SFF-8472 TABLE 3.4
3130  *   */
3131 #define  SFF_PG0_CONNECTOR_UNKNOWN    0x00   /* Unknown  */
3132 #define  SFF_PG0_CONNECTOR_SC         0x01   /* SC       */
3133 #define  SFF_PG0_CONNECTOR_FC_COPPER1 0x02   /* FC style 1 copper connector */
3134 #define  SFF_PG0_CONNECTOR_FC_COPPER2 0x03   /* FC style 2 copper connector */
3135 #define  SFF_PG0_CONNECTOR_BNC        0x04   /* BNC / TNC */
3136 #define  SFF_PG0_CONNECTOR__FC_COAX   0x05   /* FC coaxial headers */
3137 #define  SFF_PG0_CONNECTOR_FIBERJACK  0x06   /* FiberJack */
3138 #define  SFF_PG0_CONNECTOR_LC         0x07   /* LC        */
3139 #define  SFF_PG0_CONNECTOR_MT         0x08   /* MT - RJ   */
3140 #define  SFF_PG0_CONNECTOR_MU         0x09   /* MU        */
3141 #define  SFF_PG0_CONNECTOR_SF         0x0A   /* SG        */
3142 #define  SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */
3143 #define  SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */
3144 #define  SFF_PG0_CONNECTOR_HSSDC_II   0x20   /* HSSDC II */
3145 #define  SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */
3146 #define  SFF_PG0_CONNECTOR_RJ45       0x22  /* RJ45 */
3147
3148 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */
3149
3150 #define SSF_IDENTIFIER                  0
3151 #define SSF_EXT_IDENTIFIER              1
3152 #define SSF_CONNECTOR                   2
3153 #define SSF_TRANSCEIVER_CODE_B0         3
3154 #define SSF_TRANSCEIVER_CODE_B1         4
3155 #define SSF_TRANSCEIVER_CODE_B2         5
3156 #define SSF_TRANSCEIVER_CODE_B3         6
3157 #define SSF_TRANSCEIVER_CODE_B4         7
3158 #define SSF_TRANSCEIVER_CODE_B5         8
3159 #define SSF_TRANSCEIVER_CODE_B6         9
3160 #define SSF_TRANSCEIVER_CODE_B7         10
3161 #define SSF_ENCODING                    11
3162 #define SSF_BR_NOMINAL                  12
3163 #define SSF_RATE_IDENTIFIER             13
3164 #define SSF_LENGTH_9UM_KM               14
3165 #define SSF_LENGTH_9UM                  15
3166 #define SSF_LENGTH_50UM_OM2             16
3167 #define SSF_LENGTH_62UM_OM1             17
3168 #define SFF_LENGTH_COPPER               18
3169 #define SSF_LENGTH_50UM_OM3             19
3170 #define SSF_VENDOR_NAME                 20
3171 #define SSF_TRANSCEIVER2                36
3172 #define SSF_VENDOR_OUI                  37
3173 #define SSF_VENDOR_PN                   40
3174 #define SSF_VENDOR_REV                  56
3175 #define SSF_WAVELENGTH_B1               60
3176 #define SSF_WAVELENGTH_B0               61
3177 #define SSF_CC_BASE                     63
3178 #define SSF_OPTIONS_B1                  64
3179 #define SSF_OPTIONS_B0                  65
3180 #define SSF_BR_MAX                      66
3181 #define SSF_BR_MIN                      67
3182 #define SSF_VENDOR_SN                   68
3183 #define SSF_DATE_CODE                   84
3184 #define SSF_MONITORING_TYPEDIAGNOSTIC   92
3185 #define SSF_ENHANCED_OPTIONS            93
3186 #define SFF_8472_COMPLIANCE             94
3187 #define SSF_CC_EXT                      95
3188 #define SSF_A0_VENDOR_SPECIFIC          96
3189
3190 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */
3191
3192 #define SSF_TEMP_HIGH_ALARM             0
3193 #define SSF_TEMP_LOW_ALARM              2
3194 #define SSF_TEMP_HIGH_WARNING           4
3195 #define SSF_TEMP_LOW_WARNING            6
3196 #define SSF_VOLTAGE_HIGH_ALARM          8
3197 #define SSF_VOLTAGE_LOW_ALARM           10
3198 #define SSF_VOLTAGE_HIGH_WARNING        12
3199 #define SSF_VOLTAGE_LOW_WARNING         14
3200 #define SSF_BIAS_HIGH_ALARM             16
3201 #define SSF_BIAS_LOW_ALARM              18
3202 #define SSF_BIAS_HIGH_WARNING           20
3203 #define SSF_BIAS_LOW_WARNING            22
3204 #define SSF_TXPOWER_HIGH_ALARM          24
3205 #define SSF_TXPOWER_LOW_ALARM           26
3206 #define SSF_TXPOWER_HIGH_WARNING        28
3207 #define SSF_TXPOWER_LOW_WARNING         30
3208 #define SSF_RXPOWER_HIGH_ALARM          32
3209 #define SSF_RXPOWER_LOW_ALARM           34
3210 #define SSF_RXPOWER_HIGH_WARNING        36
3211 #define SSF_RXPOWER_LOW_WARNING         38
3212 #define SSF_EXT_CAL_CONSTANTS           56
3213 #define SSF_CC_DMI                      95
3214 #define SFF_TEMPERATURE_B1              96
3215 #define SFF_TEMPERATURE_B0              97
3216 #define SFF_VCC_B1                      98
3217 #define SFF_VCC_B0                      99
3218 #define SFF_TX_BIAS_CURRENT_B1          100
3219 #define SFF_TX_BIAS_CURRENT_B0          101
3220 #define SFF_TXPOWER_B1                  102
3221 #define SFF_TXPOWER_B0                  103
3222 #define SFF_RXPOWER_B1                  104
3223 #define SFF_RXPOWER_B0                  105
3224 #define SSF_STATUS_CONTROL              110
3225 #define SSF_ALARM_FLAGS                 112
3226 #define SSF_WARNING_FLAGS               116
3227 #define SSF_EXT_TATUS_CONTROL_B1        118
3228 #define SSF_EXT_TATUS_CONTROL_B0        119
3229 #define SSF_A2_VENDOR_SPECIFIC          120
3230 #define SSF_USER_EEPROM                 128
3231 #define SSF_VENDOR_CONTROL              148
3232
3233
3234 /*
3235  * Tranceiver codes Fibre Channel SFF-8472
3236  * Table 3.5.
3237  */
3238
3239 struct sff_trasnceiver_codes_byte0 {
3240         uint8_t inifiband:4;
3241         uint8_t teng_ethernet:4;
3242 };
3243
3244 struct sff_trasnceiver_codes_byte1 {
3245         uint8_t  sonet:6;
3246         uint8_t  escon:2;
3247 };
3248
3249 struct sff_trasnceiver_codes_byte2 {
3250         uint8_t  soNet:8;
3251 };
3252
3253 struct sff_trasnceiver_codes_byte3 {
3254         uint8_t ethernet:8;
3255 };
3256
3257 struct sff_trasnceiver_codes_byte4 {
3258         uint8_t fc_el_lo:1;
3259         uint8_t fc_lw_laser:1;
3260         uint8_t fc_sw_laser:1;
3261         uint8_t fc_md_distance:1;
3262         uint8_t fc_lg_distance:1;
3263         uint8_t fc_int_distance:1;
3264         uint8_t fc_short_distance:1;
3265         uint8_t fc_vld_distance:1;
3266 };
3267
3268 struct sff_trasnceiver_codes_byte5 {
3269         uint8_t reserved1:1;
3270         uint8_t reserved2:1;
3271         uint8_t fc_sfp_active:1;  /* Active cable   */
3272         uint8_t fc_sfp_passive:1; /* Passive cable  */
3273         uint8_t fc_lw_laser:1;     /* Longwave laser */
3274         uint8_t fc_sw_laser_sl:1;
3275         uint8_t fc_sw_laser_sn:1;
3276         uint8_t fc_el_hi:1;        /* Electrical enclosure high bit */
3277 };
3278
3279 struct sff_trasnceiver_codes_byte6 {
3280         uint8_t fc_tm_sm:1;      /* Single Mode */
3281         uint8_t reserved:1;
3282         uint8_t fc_tm_m6:1;       /* Multimode, 62.5um (M6) */
3283         uint8_t fc_tm_tv:1;      /* Video Coax (TV) */
3284         uint8_t fc_tm_mi:1;      /* Miniature Coax (MI) */
3285         uint8_t fc_tm_tp:1;      /* Twisted Pair (TP) */
3286         uint8_t fc_tm_tw:1;      /* Twin Axial Pair  */
3287 };
3288
3289 struct sff_trasnceiver_codes_byte7 {
3290         uint8_t fc_sp_100MB:1;   /*  100 MB/sec */
3291         uint8_t speed_chk_ecc:1;
3292         uint8_t fc_sp_200mb:1;   /*  200 MB/sec */
3293         uint8_t fc_sp_3200MB:1;  /* 3200 MB/sec */
3294         uint8_t fc_sp_400MB:1;   /*  400 MB/sec */
3295         uint8_t fc_sp_1600MB:1;  /* 1600 MB/sec */
3296         uint8_t fc_sp_800MB:1;   /*  800 MB/sec */
3297         uint8_t fc_sp_1200MB:1;  /* 1200 MB/sec */
3298 };
3299
3300 /* User writable non-volatile memory, SFF-8472 Table 3.20 */
3301 struct user_eeprom {
3302         uint8_t vendor_name[16];
3303         uint8_t vendor_oui[3];
3304         uint8_t vendor_pn[816];
3305         uint8_t vendor_rev[4];
3306         uint8_t vendor_sn[16];
3307         uint8_t datecode[6];
3308         uint8_t lot_code[2];
3309         uint8_t reserved191[57];
3310 };
3311
3312 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \
3313                                &(~((SLI4_PAGE_SIZE)-1)))
3314
3315 struct lpfc_sli4_parameters {
3316         uint32_t word0;
3317 #define cfg_prot_type_SHIFT                     0
3318 #define cfg_prot_type_MASK                      0x000000FF
3319 #define cfg_prot_type_WORD                      word0
3320         uint32_t word1;
3321 #define cfg_ft_SHIFT                            0
3322 #define cfg_ft_MASK                             0x00000001
3323 #define cfg_ft_WORD                             word1
3324 #define cfg_sli_rev_SHIFT                       4
3325 #define cfg_sli_rev_MASK                        0x0000000f
3326 #define cfg_sli_rev_WORD                        word1
3327 #define cfg_sli_family_SHIFT                    8
3328 #define cfg_sli_family_MASK                     0x0000000f
3329 #define cfg_sli_family_WORD                     word1
3330 #define cfg_if_type_SHIFT                       12
3331 #define cfg_if_type_MASK                        0x0000000f
3332 #define cfg_if_type_WORD                        word1
3333 #define cfg_sli_hint_1_SHIFT                    16
3334 #define cfg_sli_hint_1_MASK                     0x000000ff
3335 #define cfg_sli_hint_1_WORD                     word1
3336 #define cfg_sli_hint_2_SHIFT                    24
3337 #define cfg_sli_hint_2_MASK                     0x0000001f
3338 #define cfg_sli_hint_2_WORD                     word1
3339         uint32_t word2;
3340 #define cfg_eqav_SHIFT                          31
3341 #define cfg_eqav_MASK                           0x00000001
3342 #define cfg_eqav_WORD                           word2
3343         uint32_t word3;
3344         uint32_t word4;
3345 #define cfg_cqv_SHIFT                           14
3346 #define cfg_cqv_MASK                            0x00000003
3347 #define cfg_cqv_WORD                            word4
3348 #define cfg_cqpsize_SHIFT                       16
3349 #define cfg_cqpsize_MASK                        0x000000ff
3350 #define cfg_cqpsize_WORD                        word4
3351 #define cfg_cqav_SHIFT                          31
3352 #define cfg_cqav_MASK                           0x00000001
3353 #define cfg_cqav_WORD                           word4
3354         uint32_t word5;
3355         uint32_t word6;
3356 #define cfg_mqv_SHIFT                           14
3357 #define cfg_mqv_MASK                            0x00000003
3358 #define cfg_mqv_WORD                            word6
3359         uint32_t word7;
3360         uint32_t word8;
3361 #define cfg_wqpcnt_SHIFT                        0
3362 #define cfg_wqpcnt_MASK                         0x0000000f
3363 #define cfg_wqpcnt_WORD                         word8
3364 #define cfg_wqsize_SHIFT                        8
3365 #define cfg_wqsize_MASK                         0x0000000f
3366 #define cfg_wqsize_WORD                         word8
3367 #define cfg_wqv_SHIFT                           14
3368 #define cfg_wqv_MASK                            0x00000003
3369 #define cfg_wqv_WORD                            word8
3370 #define cfg_wqpsize_SHIFT                       16
3371 #define cfg_wqpsize_MASK                        0x000000ff
3372 #define cfg_wqpsize_WORD                        word8
3373         uint32_t word9;
3374         uint32_t word10;
3375 #define cfg_rqv_SHIFT                           14
3376 #define cfg_rqv_MASK                            0x00000003
3377 #define cfg_rqv_WORD                            word10
3378         uint32_t word11;
3379 #define cfg_rq_db_window_SHIFT                  28
3380 #define cfg_rq_db_window_MASK                   0x0000000f
3381 #define cfg_rq_db_window_WORD                   word11
3382         uint32_t word12;
3383 #define cfg_fcoe_SHIFT                          0
3384 #define cfg_fcoe_MASK                           0x00000001
3385 #define cfg_fcoe_WORD                           word12
3386 #define cfg_ext_SHIFT                           1
3387 #define cfg_ext_MASK                            0x00000001
3388 #define cfg_ext_WORD                            word12
3389 #define cfg_hdrr_SHIFT                          2
3390 #define cfg_hdrr_MASK                           0x00000001
3391 #define cfg_hdrr_WORD                           word12
3392 #define cfg_phwq_SHIFT                          15
3393 #define cfg_phwq_MASK                           0x00000001
3394 #define cfg_phwq_WORD                           word12
3395 #define cfg_oas_SHIFT                           25
3396 #define cfg_oas_MASK                            0x00000001
3397 #define cfg_oas_WORD                            word12
3398 #define cfg_loopbk_scope_SHIFT                  28
3399 #define cfg_loopbk_scope_MASK                   0x0000000f
3400 #define cfg_loopbk_scope_WORD                   word12
3401         uint32_t sge_supp_len;
3402         uint32_t word14;
3403 #define cfg_sgl_page_cnt_SHIFT                  0
3404 #define cfg_sgl_page_cnt_MASK                   0x0000000f
3405 #define cfg_sgl_page_cnt_WORD                   word14
3406 #define cfg_sgl_page_size_SHIFT                 8
3407 #define cfg_sgl_page_size_MASK                  0x000000ff
3408 #define cfg_sgl_page_size_WORD                  word14
3409 #define cfg_sgl_pp_align_SHIFT                  16
3410 #define cfg_sgl_pp_align_MASK                   0x000000ff
3411 #define cfg_sgl_pp_align_WORD                   word14
3412         uint32_t word15;
3413         uint32_t word16;
3414         uint32_t word17;
3415         uint32_t word18;
3416         uint32_t word19;
3417 #define cfg_ext_embed_cb_SHIFT                  0
3418 #define cfg_ext_embed_cb_MASK                   0x00000001
3419 #define cfg_ext_embed_cb_WORD                   word19
3420 #define cfg_mds_diags_SHIFT                     1
3421 #define cfg_mds_diags_MASK                      0x00000001
3422 #define cfg_mds_diags_WORD                      word19
3423 #define cfg_nvme_SHIFT                          3
3424 #define cfg_nvme_MASK                           0x00000001
3425 #define cfg_nvme_WORD                           word19
3426 #define cfg_xib_SHIFT                           4
3427 #define cfg_xib_MASK                            0x00000001
3428 #define cfg_xib_WORD                            word19
3429 #define cfg_xpsgl_SHIFT                         6
3430 #define cfg_xpsgl_MASK                          0x00000001
3431 #define cfg_xpsgl_WORD                          word19
3432 #define cfg_eqdr_SHIFT                          8
3433 #define cfg_eqdr_MASK                           0x00000001
3434 #define cfg_eqdr_WORD                           word19
3435 #define cfg_nosr_SHIFT                          9
3436 #define cfg_nosr_MASK                           0x00000001
3437 #define cfg_nosr_WORD                           word19
3438 #define cfg_bv1s_SHIFT                          10
3439 #define cfg_bv1s_MASK                           0x00000001
3440 #define cfg_bv1s_WORD                           word19
3441
3442 #define cfg_nsler_SHIFT                         12
3443 #define cfg_nsler_MASK                          0x00000001
3444 #define cfg_nsler_WORD                          word19
3445 #define cfg_pvl_SHIFT                           13
3446 #define cfg_pvl_MASK                            0x00000001
3447 #define cfg_pvl_WORD                            word19
3448
3449 #define cfg_pbde_SHIFT                          20
3450 #define cfg_pbde_MASK                           0x00000001
3451 #define cfg_pbde_WORD                           word19
3452
3453         uint32_t word20;
3454 #define cfg_max_tow_xri_SHIFT                   0
3455 #define cfg_max_tow_xri_MASK                    0x0000ffff
3456 #define cfg_max_tow_xri_WORD                    word20
3457
3458         uint32_t word21;
3459 #define cfg_mi_ver_SHIFT                        0
3460 #define cfg_mi_ver_MASK                         0x0000ffff
3461 #define cfg_mi_ver_WORD                         word21
3462 #define cfg_cmf_SHIFT                           24
3463 #define cfg_cmf_MASK                            0x000000ff
3464 #define cfg_cmf_WORD                            word21
3465
3466         uint32_t mib_size;
3467         uint32_t word23;                        /* RESERVED */
3468
3469         uint32_t word24;
3470 #define cfg_frag_field_offset_SHIFT             0
3471 #define cfg_frag_field_offset_MASK              0x0000ffff
3472 #define cfg_frag_field_offset_WORD              word24
3473
3474 #define cfg_frag_field_size_SHIFT               16
3475 #define cfg_frag_field_size_MASK                0x0000ffff
3476 #define cfg_frag_field_size_WORD                word24
3477
3478         uint32_t word25;
3479 #define cfg_sgl_field_offset_SHIFT              0
3480 #define cfg_sgl_field_offset_MASK               0x0000ffff
3481 #define cfg_sgl_field_offset_WORD               word25
3482
3483 #define cfg_sgl_field_size_SHIFT                16
3484 #define cfg_sgl_field_size_MASK                 0x0000ffff
3485 #define cfg_sgl_field_size_WORD                 word25
3486
3487         uint32_t word26;        /* Chain SGE initial value LOW  */
3488         uint32_t word27;        /* Chain SGE initial value HIGH */
3489 #define LPFC_NODELAY_MAX_IO                     32
3490 };
3491
3492 #define LPFC_SET_UE_RECOVERY            0x10
3493 #define LPFC_SET_MDS_DIAGS              0x12
3494 #define LPFC_SET_DUAL_DUMP              0x1e
3495 #define LPFC_SET_CGN_SIGNAL             0x1f
3496 #define LPFC_SET_ENABLE_MI              0x21
3497 #define LPFC_SET_LD_SIGNAL              0x23
3498 #define LPFC_SET_ENABLE_CMF             0x24
3499 struct lpfc_mbx_set_feature {
3500         struct mbox_header header;
3501         uint32_t feature;
3502         uint32_t param_len;
3503         uint32_t word6;
3504 #define lpfc_mbx_set_feature_UER_SHIFT  0
3505 #define lpfc_mbx_set_feature_UER_MASK   0x00000001
3506 #define lpfc_mbx_set_feature_UER_WORD   word6
3507 #define lpfc_mbx_set_feature_mds_SHIFT  2
3508 #define lpfc_mbx_set_feature_mds_MASK   0x00000001
3509 #define lpfc_mbx_set_feature_mds_WORD   word6
3510 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT  1
3511 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK   0x00000001
3512 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD   word6
3513 #define lpfc_mbx_set_feature_CGN_warn_freq_SHIFT 0
3514 #define lpfc_mbx_set_feature_CGN_warn_freq_MASK  0x0000ffff
3515 #define lpfc_mbx_set_feature_CGN_warn_freq_WORD  word6
3516 #define lpfc_mbx_set_feature_dd_SHIFT           0
3517 #define lpfc_mbx_set_feature_dd_MASK            0x00000001
3518 #define lpfc_mbx_set_feature_dd_WORD            word6
3519 #define lpfc_mbx_set_feature_ddquery_SHIFT      1
3520 #define lpfc_mbx_set_feature_ddquery_MASK       0x00000001
3521 #define lpfc_mbx_set_feature_ddquery_WORD       word6
3522 #define LPFC_DISABLE_DUAL_DUMP          0
3523 #define LPFC_ENABLE_DUAL_DUMP           1
3524 #define LPFC_QUERY_OP_DUAL_DUMP         2
3525 #define lpfc_mbx_set_feature_cmf_SHIFT          0
3526 #define lpfc_mbx_set_feature_cmf_MASK           0x00000001
3527 #define lpfc_mbx_set_feature_cmf_WORD           word6
3528 #define lpfc_mbx_set_feature_lds_qry_SHIFT      0
3529 #define lpfc_mbx_set_feature_lds_qry_MASK       0x00000001
3530 #define lpfc_mbx_set_feature_lds_qry_WORD       word6
3531 #define LPFC_QUERY_LDS_OP               1
3532 #define lpfc_mbx_set_feature_mi_SHIFT           0
3533 #define lpfc_mbx_set_feature_mi_MASK            0x0000ffff
3534 #define lpfc_mbx_set_feature_mi_WORD            word6
3535 #define lpfc_mbx_set_feature_milunq_SHIFT       16
3536 #define lpfc_mbx_set_feature_milunq_MASK        0x0000ffff
3537 #define lpfc_mbx_set_feature_milunq_WORD        word6
3538         u32 word7;
3539 #define lpfc_mbx_set_feature_UERP_SHIFT 0
3540 #define lpfc_mbx_set_feature_UERP_MASK  0x0000ffff
3541 #define lpfc_mbx_set_feature_UERP_WORD  word7
3542 #define lpfc_mbx_set_feature_UESR_SHIFT 16
3543 #define lpfc_mbx_set_feature_UESR_MASK  0x0000ffff
3544 #define lpfc_mbx_set_feature_UESR_WORD  word7
3545 #define lpfc_mbx_set_feature_CGN_alarm_freq_SHIFT 0
3546 #define lpfc_mbx_set_feature_CGN_alarm_freq_MASK  0x0000ffff
3547 #define lpfc_mbx_set_feature_CGN_alarm_freq_WORD  word7
3548         u32 word8;
3549 #define lpfc_mbx_set_feature_CGN_acqe_freq_SHIFT 0
3550 #define lpfc_mbx_set_feature_CGN_acqe_freq_MASK  0x000000ff
3551 #define lpfc_mbx_set_feature_CGN_acqe_freq_WORD  word8
3552         u32 word9;
3553         u32 word10;
3554 };
3555
3556
3557 #define LPFC_SET_HOST_OS_DRIVER_VERSION    0x2
3558 #define LPFC_SET_HOST_DATE_TIME            0x4
3559
3560 struct lpfc_mbx_set_host_date_time {
3561         uint32_t word6;
3562 #define lpfc_mbx_set_host_month_WORD    word6
3563 #define lpfc_mbx_set_host_month_SHIFT   16
3564 #define lpfc_mbx_set_host_month_MASK    0xFF
3565 #define lpfc_mbx_set_host_day_WORD      word6
3566 #define lpfc_mbx_set_host_day_SHIFT     8
3567 #define lpfc_mbx_set_host_day_MASK      0xFF
3568 #define lpfc_mbx_set_host_year_WORD     word6
3569 #define lpfc_mbx_set_host_year_SHIFT    0
3570 #define lpfc_mbx_set_host_year_MASK     0xFF
3571         uint32_t word7;
3572 #define lpfc_mbx_set_host_hour_WORD     word7
3573 #define lpfc_mbx_set_host_hour_SHIFT    16
3574 #define lpfc_mbx_set_host_hour_MASK     0xFF
3575 #define lpfc_mbx_set_host_min_WORD      word7
3576 #define lpfc_mbx_set_host_min_SHIFT     8
3577 #define lpfc_mbx_set_host_min_MASK      0xFF
3578 #define lpfc_mbx_set_host_sec_WORD      word7
3579 #define lpfc_mbx_set_host_sec_SHIFT     0
3580 #define lpfc_mbx_set_host_sec_MASK      0xFF
3581 };
3582
3583 struct lpfc_mbx_set_host_data {
3584 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE   48
3585         struct mbox_header header;
3586         uint32_t param_id;
3587         uint32_t param_len;
3588         union {
3589                 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE];
3590                 struct  lpfc_mbx_set_host_date_time tm;
3591         } un;
3592 };
3593
3594 struct lpfc_mbx_set_trunk_mode {
3595         struct mbox_header header;
3596         uint32_t word0;
3597 #define lpfc_mbx_set_trunk_mode_WORD      word0
3598 #define lpfc_mbx_set_trunk_mode_SHIFT     0
3599 #define lpfc_mbx_set_trunk_mode_MASK      0xFF
3600         uint32_t word1;
3601         uint32_t word2;
3602 };
3603
3604 struct lpfc_mbx_get_sli4_parameters {
3605         struct mbox_header header;
3606         struct lpfc_sli4_parameters sli4_parameters;
3607 };
3608
3609 struct lpfc_mbx_reg_congestion_buf {
3610         struct mbox_header header;
3611         uint32_t word0;
3612 #define lpfc_mbx_reg_cgn_buf_type_WORD          word0
3613 #define lpfc_mbx_reg_cgn_buf_type_SHIFT         0
3614 #define lpfc_mbx_reg_cgn_buf_type_MASK          0xFF
3615 #define lpfc_mbx_reg_cgn_buf_cnt_WORD           word0
3616 #define lpfc_mbx_reg_cgn_buf_cnt_SHIFT          16
3617 #define lpfc_mbx_reg_cgn_buf_cnt_MASK           0xFF
3618         uint32_t word1;
3619         uint32_t length;
3620         uint32_t addr_lo;
3621         uint32_t addr_hi;
3622 };
3623
3624 struct lpfc_rscr_desc_generic {
3625 #define LPFC_RSRC_DESC_WSIZE                    22
3626         uint32_t desc[LPFC_RSRC_DESC_WSIZE];
3627 };
3628
3629 struct lpfc_rsrc_desc_pcie {
3630         uint32_t word0;
3631 #define lpfc_rsrc_desc_pcie_type_SHIFT          0
3632 #define lpfc_rsrc_desc_pcie_type_MASK           0x000000ff
3633 #define lpfc_rsrc_desc_pcie_type_WORD           word0
3634 #define LPFC_RSRC_DESC_TYPE_PCIE                0x40
3635 #define lpfc_rsrc_desc_pcie_length_SHIFT        8
3636 #define lpfc_rsrc_desc_pcie_length_MASK         0x000000ff
3637 #define lpfc_rsrc_desc_pcie_length_WORD         word0
3638         uint32_t word1;
3639 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT         0
3640 #define lpfc_rsrc_desc_pcie_pfnum_MASK          0x000000ff
3641 #define lpfc_rsrc_desc_pcie_pfnum_WORD          word1
3642         uint32_t reserved;
3643         uint32_t word3;
3644 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT     0
3645 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK      0x000000ff
3646 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD      word3
3647 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT        8
3648 #define lpfc_rsrc_desc_pcie_pf_sta_MASK         0x000000ff
3649 #define lpfc_rsrc_desc_pcie_pf_sta_WORD         word3
3650 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT       16
3651 #define lpfc_rsrc_desc_pcie_pf_type_MASK        0x000000ff
3652 #define lpfc_rsrc_desc_pcie_pf_type_WORD        word3
3653         uint32_t word4;
3654 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT     0
3655 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK      0x0000ffff
3656 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD      word4
3657 };
3658
3659 struct lpfc_rsrc_desc_fcfcoe {
3660         uint32_t word0;
3661 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT        0
3662 #define lpfc_rsrc_desc_fcfcoe_type_MASK         0x000000ff
3663 #define lpfc_rsrc_desc_fcfcoe_type_WORD         word0
3664 #define LPFC_RSRC_DESC_TYPE_FCFCOE              0x43
3665 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT      8
3666 #define lpfc_rsrc_desc_fcfcoe_length_MASK       0x000000ff
3667 #define lpfc_rsrc_desc_fcfcoe_length_WORD       word0
3668 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD      0
3669 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH    72
3670 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH    88
3671         uint32_t word1;
3672 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT       0
3673 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK        0x000000ff
3674 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD        word1
3675 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT       16
3676 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK        0x000007ff
3677 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD        word1
3678         uint32_t word2;
3679 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT     0
3680 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK      0x0000ffff
3681 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD      word2
3682 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT     16
3683 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK      0x0000ffff
3684 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD      word2
3685         uint32_t word3;
3686 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT      0
3687 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK       0x0000ffff
3688 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD       word3
3689 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT      16
3690 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK       0x0000ffff
3691 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD       word3
3692         uint32_t word4;
3693 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT      0
3694 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK       0x0000ffff
3695 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD       word4
3696 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT     16
3697 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK      0x0000ffff
3698 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD      word4
3699         uint32_t word5;
3700 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT    0
3701 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK     0x0000ffff
3702 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD     word5
3703 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT     16
3704 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK      0x0000ffff
3705 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD      word5
3706         uint32_t word6;
3707         uint32_t word7;
3708         uint32_t word8;
3709         uint32_t word9;
3710         uint32_t word10;
3711         uint32_t word11;
3712         uint32_t word12;
3713         uint32_t word13;
3714 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT      0
3715 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK       0x0000003f
3716 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD       word13
3717 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT      6
3718 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK       0x00000003
3719 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD       word13
3720 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT         8
3721 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK          0x00000001
3722 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD          word13
3723 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT         9
3724 #define lpfc_rsrc_desc_fcfcoe_lld_MASK          0x00000001
3725 #define lpfc_rsrc_desc_fcfcoe_lld_WORD          word13
3726 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT      16
3727 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK       0x0000ffff
3728 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD       word13
3729 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */
3730         uint32_t bw_min;
3731         uint32_t bw_max;
3732         uint32_t iops_min;
3733         uint32_t iops_max;
3734         uint32_t reserved[4];
3735 };
3736
3737 struct lpfc_func_cfg {
3738 #define LPFC_RSRC_DESC_MAX_NUM                  2
3739         uint32_t rsrc_desc_count;
3740         struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3741 };
3742
3743 struct lpfc_mbx_get_func_cfg {
3744         struct mbox_header header;
3745 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE       0x0
3746 #define LPFC_CFG_TYPE_FACTURY_DEFAULT           0x1
3747 #define LPFC_CFG_TYPE_CURRENT_ACTIVE            0x2
3748         struct lpfc_func_cfg func_cfg;
3749 };
3750
3751 struct lpfc_prof_cfg {
3752 #define LPFC_RSRC_DESC_MAX_NUM                  2
3753         uint32_t rsrc_desc_count;
3754         struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3755 };
3756
3757 struct lpfc_mbx_get_prof_cfg {
3758         struct mbox_header header;
3759 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE       0x0
3760 #define LPFC_CFG_TYPE_FACTURY_DEFAULT           0x1
3761 #define LPFC_CFG_TYPE_CURRENT_ACTIVE            0x2
3762         union {
3763                 struct {
3764                         uint32_t word10;
3765 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT     0
3766 #define lpfc_mbx_get_prof_cfg_prof_id_MASK      0x000000ff
3767 #define lpfc_mbx_get_prof_cfg_prof_id_WORD      word10
3768 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT     8
3769 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK      0x00000003
3770 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD      word10
3771                 } request;
3772                 struct {
3773                         struct lpfc_prof_cfg prof_cfg;
3774                 } response;
3775         } u;
3776 };
3777
3778 struct lpfc_controller_attribute {
3779         uint32_t version_string[8];
3780         uint32_t manufacturer_name[8];
3781         uint32_t supported_modes;
3782         uint32_t word17;
3783 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT       0
3784 #define lpfc_cntl_attr_eprom_ver_lo_MASK        0x000000ff
3785 #define lpfc_cntl_attr_eprom_ver_lo_WORD        word17
3786 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT       8
3787 #define lpfc_cntl_attr_eprom_ver_hi_MASK        0x000000ff
3788 #define lpfc_cntl_attr_eprom_ver_hi_WORD        word17
3789 #define lpfc_cntl_attr_flash_id_SHIFT           16
3790 #define lpfc_cntl_attr_flash_id_MASK            0x000000ff
3791 #define lpfc_cntl_attr_flash_id_WORD            word17
3792         uint32_t mbx_da_struct_ver;
3793         uint32_t ep_fw_da_struct_ver;
3794         uint32_t ncsi_ver_str[3];
3795         uint32_t dflt_ext_timeout;
3796         uint32_t model_number[8];
3797         uint32_t description[16];
3798         uint32_t serial_number[8];
3799         uint32_t ip_ver_str[8];
3800         uint32_t fw_ver_str[8];
3801         uint32_t bios_ver_str[8];
3802         uint32_t redboot_ver_str[8];
3803         uint32_t driver_ver_str[8];
3804         uint32_t flash_fw_ver_str[8];
3805         uint32_t functionality;
3806         uint32_t word105;
3807 #define lpfc_cntl_attr_max_cbd_len_SHIFT        0
3808 #define lpfc_cntl_attr_max_cbd_len_MASK         0x0000ffff
3809 #define lpfc_cntl_attr_max_cbd_len_WORD         word105
3810 #define lpfc_cntl_attr_asic_rev_SHIFT           16
3811 #define lpfc_cntl_attr_asic_rev_MASK            0x000000ff
3812 #define lpfc_cntl_attr_asic_rev_WORD            word105
3813 #define lpfc_cntl_attr_gen_guid0_SHIFT          24
3814 #define lpfc_cntl_attr_gen_guid0_MASK           0x000000ff
3815 #define lpfc_cntl_attr_gen_guid0_WORD           word105
3816         uint32_t gen_guid1_12[3];
3817         uint32_t word109;
3818 #define lpfc_cntl_attr_gen_guid13_14_SHIFT      0
3819 #define lpfc_cntl_attr_gen_guid13_14_MASK       0x0000ffff
3820 #define lpfc_cntl_attr_gen_guid13_14_WORD       word109
3821 #define lpfc_cntl_attr_gen_guid15_SHIFT         16
3822 #define lpfc_cntl_attr_gen_guid15_MASK          0x000000ff
3823 #define lpfc_cntl_attr_gen_guid15_WORD          word109
3824 #define lpfc_cntl_attr_hba_port_cnt_SHIFT       24
3825 #define lpfc_cntl_attr_hba_port_cnt_MASK        0x000000ff
3826 #define lpfc_cntl_attr_hba_port_cnt_WORD        word109
3827         uint32_t word110;
3828 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT       0
3829 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK        0x0000ffff
3830 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD        word110
3831 #define lpfc_cntl_attr_multi_func_dev_SHIFT     24
3832 #define lpfc_cntl_attr_multi_func_dev_MASK      0x000000ff
3833 #define lpfc_cntl_attr_multi_func_dev_WORD      word110
3834         uint32_t word111;
3835 #define lpfc_cntl_attr_cache_valid_SHIFT        0
3836 #define lpfc_cntl_attr_cache_valid_MASK         0x000000ff
3837 #define lpfc_cntl_attr_cache_valid_WORD         word111
3838 #define lpfc_cntl_attr_hba_status_SHIFT         8
3839 #define lpfc_cntl_attr_hba_status_MASK          0x000000ff
3840 #define lpfc_cntl_attr_hba_status_WORD          word111
3841 #define lpfc_cntl_attr_max_domain_SHIFT         16
3842 #define lpfc_cntl_attr_max_domain_MASK          0x000000ff
3843 #define lpfc_cntl_attr_max_domain_WORD          word111
3844 #define lpfc_cntl_attr_lnk_numb_SHIFT           24
3845 #define lpfc_cntl_attr_lnk_numb_MASK            0x0000003f
3846 #define lpfc_cntl_attr_lnk_numb_WORD            word111
3847 #define lpfc_cntl_attr_lnk_type_SHIFT           30
3848 #define lpfc_cntl_attr_lnk_type_MASK            0x00000003
3849 #define lpfc_cntl_attr_lnk_type_WORD            word111
3850         uint32_t fw_post_status;
3851         uint32_t hba_mtu[8];
3852         uint32_t word121;
3853         uint32_t reserved1[3];
3854         uint32_t word125;
3855 #define lpfc_cntl_attr_pci_vendor_id_SHIFT      0
3856 #define lpfc_cntl_attr_pci_vendor_id_MASK       0x0000ffff
3857 #define lpfc_cntl_attr_pci_vendor_id_WORD       word125
3858 #define lpfc_cntl_attr_pci_device_id_SHIFT      16
3859 #define lpfc_cntl_attr_pci_device_id_MASK       0x0000ffff
3860 #define lpfc_cntl_attr_pci_device_id_WORD       word125
3861         uint32_t word126;
3862 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT      0
3863 #define lpfc_cntl_attr_pci_subvdr_id_MASK       0x0000ffff
3864 #define lpfc_cntl_attr_pci_subvdr_id_WORD       word126
3865 #define lpfc_cntl_attr_pci_subsys_id_SHIFT      16
3866 #define lpfc_cntl_attr_pci_subsys_id_MASK       0x0000ffff
3867 #define lpfc_cntl_attr_pci_subsys_id_WORD       word126
3868         uint32_t word127;
3869 #define lpfc_cntl_attr_pci_bus_num_SHIFT        0
3870 #define lpfc_cntl_attr_pci_bus_num_MASK         0x000000ff
3871 #define lpfc_cntl_attr_pci_bus_num_WORD         word127
3872 #define lpfc_cntl_attr_pci_dev_num_SHIFT        8
3873 #define lpfc_cntl_attr_pci_dev_num_MASK         0x000000ff
3874 #define lpfc_cntl_attr_pci_dev_num_WORD         word127
3875 #define lpfc_cntl_attr_pci_fnc_num_SHIFT        16
3876 #define lpfc_cntl_attr_pci_fnc_num_MASK         0x000000ff
3877 #define lpfc_cntl_attr_pci_fnc_num_WORD         word127
3878 #define lpfc_cntl_attr_inf_type_SHIFT           24
3879 #define lpfc_cntl_attr_inf_type_MASK            0x000000ff
3880 #define lpfc_cntl_attr_inf_type_WORD            word127
3881         uint32_t unique_id[2];
3882         uint32_t word130;
3883 #define lpfc_cntl_attr_num_netfil_SHIFT         0
3884 #define lpfc_cntl_attr_num_netfil_MASK          0x000000ff
3885 #define lpfc_cntl_attr_num_netfil_WORD          word130
3886         uint32_t reserved2[4];
3887 };
3888
3889 struct lpfc_mbx_get_cntl_attributes {
3890         union  lpfc_sli4_cfg_shdr cfg_shdr;
3891         struct lpfc_controller_attribute cntl_attr;
3892 };
3893
3894 struct lpfc_mbx_get_port_name {
3895         struct mbox_header header;
3896         union {
3897                 struct {
3898                         uint32_t word4;
3899 #define lpfc_mbx_get_port_name_lnk_type_SHIFT   0
3900 #define lpfc_mbx_get_port_name_lnk_type_MASK    0x00000003
3901 #define lpfc_mbx_get_port_name_lnk_type_WORD    word4
3902                 } request;
3903                 struct {
3904                         uint32_t word4;
3905 #define lpfc_mbx_get_port_name_name0_SHIFT      0
3906 #define lpfc_mbx_get_port_name_name0_MASK       0x000000FF
3907 #define lpfc_mbx_get_port_name_name0_WORD       word4
3908 #define lpfc_mbx_get_port_name_name1_SHIFT      8
3909 #define lpfc_mbx_get_port_name_name1_MASK       0x000000FF
3910 #define lpfc_mbx_get_port_name_name1_WORD       word4
3911 #define lpfc_mbx_get_port_name_name2_SHIFT      16
3912 #define lpfc_mbx_get_port_name_name2_MASK       0x000000FF
3913 #define lpfc_mbx_get_port_name_name2_WORD       word4
3914 #define lpfc_mbx_get_port_name_name3_SHIFT      24
3915 #define lpfc_mbx_get_port_name_name3_MASK       0x000000FF
3916 #define lpfc_mbx_get_port_name_name3_WORD       word4
3917 #define LPFC_LINK_NUMBER_0                      0
3918 #define LPFC_LINK_NUMBER_1                      1
3919 #define LPFC_LINK_NUMBER_2                      2
3920 #define LPFC_LINK_NUMBER_3                      3
3921                 } response;
3922         } u;
3923 };
3924
3925 /* Mailbox Completion Queue Error Messages */
3926 #define MB_CQE_STATUS_SUCCESS                   0x0
3927 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES   0x1
3928 #define MB_CQE_STATUS_INVALID_PARAMETER         0x2
3929 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES    0x3
3930 #define MB_CEQ_STATUS_QUEUE_FLUSHING            0x4
3931 #define MB_CQE_STATUS_DMA_FAILED                0x5
3932
3933
3934 #define LPFC_MBX_WR_CONFIG_MAX_BDE              1
3935 struct lpfc_mbx_wr_object {
3936         struct mbox_header header;
3937         union {
3938                 struct {
3939                         uint32_t word4;
3940 #define lpfc_wr_object_eof_SHIFT                31
3941 #define lpfc_wr_object_eof_MASK                 0x00000001
3942 #define lpfc_wr_object_eof_WORD                 word4
3943 #define lpfc_wr_object_eas_SHIFT                29
3944 #define lpfc_wr_object_eas_MASK                 0x00000001
3945 #define lpfc_wr_object_eas_WORD                 word4
3946 #define lpfc_wr_object_write_length_SHIFT       0
3947 #define lpfc_wr_object_write_length_MASK        0x00FFFFFF
3948 #define lpfc_wr_object_write_length_WORD        word4
3949                         uint32_t write_offset;
3950                         uint32_t object_name[LPFC_MBX_OBJECT_NAME_LEN_DW];
3951                         uint32_t bde_count;
3952                         struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE];
3953                 } request;
3954                 struct {
3955                         uint32_t actual_write_length;
3956                         uint32_t word5;
3957 #define lpfc_wr_object_change_status_SHIFT      0
3958 #define lpfc_wr_object_change_status_MASK       0x000000FF
3959 #define lpfc_wr_object_change_status_WORD       word5
3960 #define LPFC_CHANGE_STATUS_NO_RESET_NEEDED      0x00
3961 #define LPFC_CHANGE_STATUS_PHYS_DEV_RESET       0x01
3962 #define LPFC_CHANGE_STATUS_FW_RESET             0x02
3963 #define LPFC_CHANGE_STATUS_PORT_MIGRATION       0x04
3964 #define LPFC_CHANGE_STATUS_PCI_RESET            0x05
3965 #define lpfc_wr_object_csf_SHIFT                8
3966 #define lpfc_wr_object_csf_MASK                 0x00000001
3967 #define lpfc_wr_object_csf_WORD                 word5
3968                 } response;
3969         } u;
3970 };
3971
3972 /* mailbox queue entry structure */
3973 struct lpfc_mqe {
3974         uint32_t word0;
3975 #define lpfc_mqe_status_SHIFT           16
3976 #define lpfc_mqe_status_MASK            0x0000FFFF
3977 #define lpfc_mqe_status_WORD            word0
3978 #define lpfc_mqe_command_SHIFT          8
3979 #define lpfc_mqe_command_MASK           0x000000FF
3980 #define lpfc_mqe_command_WORD           word0
3981         union {
3982                 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
3983                 /* sli4 mailbox commands */
3984                 struct lpfc_mbx_sli4_config sli4_config;
3985                 struct lpfc_mbx_init_vfi init_vfi;
3986                 struct lpfc_mbx_reg_vfi reg_vfi;
3987                 struct lpfc_mbx_reg_vfi unreg_vfi;
3988                 struct lpfc_mbx_init_vpi init_vpi;
3989                 struct lpfc_mbx_resume_rpi resume_rpi;
3990                 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
3991                 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
3992                 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
3993                 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl;
3994                 struct lpfc_mbx_reg_fcfi reg_fcfi;
3995                 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq;
3996                 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
3997                 struct lpfc_mbx_mq_create mq_create;
3998                 struct lpfc_mbx_mq_create_ext mq_create_ext;
3999                 struct lpfc_mbx_read_object read_object;
4000                 struct lpfc_mbx_eq_create eq_create;
4001                 struct lpfc_mbx_modify_eq_delay eq_delay;
4002                 struct lpfc_mbx_cq_create cq_create;
4003                 struct lpfc_mbx_cq_create_set cq_create_set;
4004                 struct lpfc_mbx_wq_create wq_create;
4005                 struct lpfc_mbx_rq_create rq_create;
4006                 struct lpfc_mbx_rq_create_v2 rq_create_v2;
4007                 struct lpfc_mbx_mq_destroy mq_destroy;
4008                 struct lpfc_mbx_eq_destroy eq_destroy;
4009                 struct lpfc_mbx_cq_destroy cq_destroy;
4010                 struct lpfc_mbx_wq_destroy wq_destroy;
4011                 struct lpfc_mbx_rq_destroy rq_destroy;
4012                 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info;
4013                 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents;
4014                 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents;
4015                 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
4016                 struct lpfc_mbx_nembed_cmd nembed_cmd;
4017                 struct lpfc_mbx_read_rev read_rev;
4018                 struct lpfc_mbx_read_vpi read_vpi;
4019                 struct lpfc_mbx_read_config rd_config;
4020                 struct lpfc_mbx_request_features req_ftrs;
4021                 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
4022                 struct lpfc_mbx_query_fw_config query_fw_cfg;
4023                 struct lpfc_mbx_set_beacon_config beacon_config;
4024                 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters;
4025                 struct lpfc_mbx_reg_congestion_buf reg_congestion_buf;
4026                 struct lpfc_mbx_set_link_diag_state link_diag_state;
4027                 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback;
4028                 struct lpfc_mbx_run_link_diag_test link_diag_test;
4029                 struct lpfc_mbx_get_func_cfg get_func_cfg;
4030                 struct lpfc_mbx_get_prof_cfg get_prof_cfg;
4031                 struct lpfc_mbx_wr_object wr_object;
4032                 struct lpfc_mbx_get_port_name get_port_name;
4033                 struct lpfc_mbx_set_feature  set_feature;
4034                 struct lpfc_mbx_memory_dump_type3 mem_dump_type3;
4035                 struct lpfc_mbx_set_host_data set_host_data;
4036                 struct lpfc_mbx_set_trunk_mode set_trunk_mode;
4037                 struct lpfc_mbx_nop nop;
4038                 struct lpfc_mbx_set_ras_fwlog ras_fwlog;
4039         } un;
4040 };
4041
4042 struct lpfc_mcqe {
4043         uint32_t word0;
4044 #define lpfc_mcqe_status_SHIFT          0
4045 #define lpfc_mcqe_status_MASK           0x0000FFFF
4046 #define lpfc_mcqe_status_WORD           word0
4047 #define lpfc_mcqe_ext_status_SHIFT      16
4048 #define lpfc_mcqe_ext_status_MASK       0x0000FFFF
4049 #define lpfc_mcqe_ext_status_WORD       word0
4050         uint32_t mcqe_tag0;
4051         uint32_t mcqe_tag1;
4052         uint32_t trailer;
4053 #define lpfc_trailer_valid_SHIFT        31
4054 #define lpfc_trailer_valid_MASK         0x00000001
4055 #define lpfc_trailer_valid_WORD         trailer
4056 #define lpfc_trailer_async_SHIFT        30
4057 #define lpfc_trailer_async_MASK         0x00000001
4058 #define lpfc_trailer_async_WORD         trailer
4059 #define lpfc_trailer_hpi_SHIFT          29
4060 #define lpfc_trailer_hpi_MASK           0x00000001
4061 #define lpfc_trailer_hpi_WORD           trailer
4062 #define lpfc_trailer_completed_SHIFT    28
4063 #define lpfc_trailer_completed_MASK     0x00000001
4064 #define lpfc_trailer_completed_WORD     trailer
4065 #define lpfc_trailer_consumed_SHIFT     27
4066 #define lpfc_trailer_consumed_MASK      0x00000001
4067 #define lpfc_trailer_consumed_WORD      trailer
4068 #define lpfc_trailer_type_SHIFT         16
4069 #define lpfc_trailer_type_MASK          0x000000FF
4070 #define lpfc_trailer_type_WORD          trailer
4071 #define lpfc_trailer_code_SHIFT         8
4072 #define lpfc_trailer_code_MASK          0x000000FF
4073 #define lpfc_trailer_code_WORD          trailer
4074 #define LPFC_TRAILER_CODE_LINK  0x1
4075 #define LPFC_TRAILER_CODE_FCOE  0x2
4076 #define LPFC_TRAILER_CODE_DCBX  0x3
4077 #define LPFC_TRAILER_CODE_GRP5  0x5
4078 #define LPFC_TRAILER_CODE_FC    0x10
4079 #define LPFC_TRAILER_CODE_SLI   0x11
4080 };
4081
4082 struct lpfc_acqe_link {
4083         uint32_t word0;
4084 #define lpfc_acqe_link_speed_SHIFT              24
4085 #define lpfc_acqe_link_speed_MASK               0x000000FF
4086 #define lpfc_acqe_link_speed_WORD               word0
4087 #define LPFC_ASYNC_LINK_SPEED_ZERO              0x0
4088 #define LPFC_ASYNC_LINK_SPEED_10MBPS            0x1
4089 #define LPFC_ASYNC_LINK_SPEED_100MBPS           0x2
4090 #define LPFC_ASYNC_LINK_SPEED_1GBPS             0x3
4091 #define LPFC_ASYNC_LINK_SPEED_10GBPS            0x4
4092 #define LPFC_ASYNC_LINK_SPEED_20GBPS            0x5
4093 #define LPFC_ASYNC_LINK_SPEED_25GBPS            0x6
4094 #define LPFC_ASYNC_LINK_SPEED_40GBPS            0x7
4095 #define LPFC_ASYNC_LINK_SPEED_100GBPS           0x8
4096 #define lpfc_acqe_link_duplex_SHIFT             16
4097 #define lpfc_acqe_link_duplex_MASK              0x000000FF
4098 #define lpfc_acqe_link_duplex_WORD              word0
4099 #define LPFC_ASYNC_LINK_DUPLEX_NONE             0x0
4100 #define LPFC_ASYNC_LINK_DUPLEX_HALF             0x1
4101 #define LPFC_ASYNC_LINK_DUPLEX_FULL             0x2
4102 #define lpfc_acqe_link_status_SHIFT             8
4103 #define lpfc_acqe_link_status_MASK              0x000000FF
4104 #define lpfc_acqe_link_status_WORD              word0
4105 #define LPFC_ASYNC_LINK_STATUS_DOWN             0x0
4106 #define LPFC_ASYNC_LINK_STATUS_UP               0x1
4107 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN     0x2
4108 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP       0x3
4109 #define lpfc_acqe_link_type_SHIFT               6
4110 #define lpfc_acqe_link_type_MASK                0x00000003
4111 #define lpfc_acqe_link_type_WORD                word0
4112 #define lpfc_acqe_link_number_SHIFT             0
4113 #define lpfc_acqe_link_number_MASK              0x0000003F
4114 #define lpfc_acqe_link_number_WORD              word0
4115         uint32_t word1;
4116 #define lpfc_acqe_link_fault_SHIFT      0
4117 #define lpfc_acqe_link_fault_MASK       0x000000FF
4118 #define lpfc_acqe_link_fault_WORD       word1
4119 #define LPFC_ASYNC_LINK_FAULT_NONE      0x0
4120 #define LPFC_ASYNC_LINK_FAULT_LOCAL     0x1
4121 #define LPFC_ASYNC_LINK_FAULT_REMOTE    0x2
4122 #define LPFC_ASYNC_LINK_FAULT_LR_LRR    0x3
4123 #define lpfc_acqe_logical_link_speed_SHIFT      16
4124 #define lpfc_acqe_logical_link_speed_MASK       0x0000FFFF
4125 #define lpfc_acqe_logical_link_speed_WORD       word1
4126         uint32_t event_tag;
4127         uint32_t trailer;
4128 #define LPFC_LINK_EVENT_TYPE_PHYSICAL   0x0
4129 #define LPFC_LINK_EVENT_TYPE_VIRTUAL    0x1
4130 };
4131
4132 struct lpfc_acqe_fip {
4133         uint32_t index;
4134         uint32_t word1;
4135 #define lpfc_acqe_fip_fcf_count_SHIFT           0
4136 #define lpfc_acqe_fip_fcf_count_MASK            0x0000FFFF
4137 #define lpfc_acqe_fip_fcf_count_WORD            word1
4138 #define lpfc_acqe_fip_event_type_SHIFT          16
4139 #define lpfc_acqe_fip_event_type_MASK           0x0000FFFF
4140 #define lpfc_acqe_fip_event_type_WORD           word1
4141         uint32_t event_tag;
4142         uint32_t trailer;
4143 #define LPFC_FIP_EVENT_TYPE_NEW_FCF             0x1
4144 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL      0x2
4145 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD            0x3
4146 #define LPFC_FIP_EVENT_TYPE_CVL                 0x4
4147 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD       0x5
4148 };
4149
4150 struct lpfc_acqe_dcbx {
4151         uint32_t tlv_ttl;
4152         uint32_t reserved;
4153         uint32_t event_tag;
4154         uint32_t trailer;
4155 };
4156
4157 struct lpfc_acqe_grp5 {
4158         uint32_t word0;
4159 #define lpfc_acqe_grp5_type_SHIFT               6
4160 #define lpfc_acqe_grp5_type_MASK                0x00000003
4161 #define lpfc_acqe_grp5_type_WORD                word0
4162 #define lpfc_acqe_grp5_number_SHIFT             0
4163 #define lpfc_acqe_grp5_number_MASK              0x0000003F
4164 #define lpfc_acqe_grp5_number_WORD              word0
4165         uint32_t word1;
4166 #define lpfc_acqe_grp5_llink_spd_SHIFT  16
4167 #define lpfc_acqe_grp5_llink_spd_MASK   0x0000FFFF
4168 #define lpfc_acqe_grp5_llink_spd_WORD   word1
4169         uint32_t event_tag;
4170         uint32_t trailer;
4171 };
4172
4173 extern const char *const trunk_errmsg[];
4174
4175 struct lpfc_acqe_fc_la {
4176         uint32_t word0;
4177 #define lpfc_acqe_fc_la_speed_SHIFT             24
4178 #define lpfc_acqe_fc_la_speed_MASK              0x000000FF
4179 #define lpfc_acqe_fc_la_speed_WORD              word0
4180 #define LPFC_FC_LA_SPEED_UNKNOWN                0x0
4181 #define LPFC_FC_LA_SPEED_1G             0x1
4182 #define LPFC_FC_LA_SPEED_2G             0x2
4183 #define LPFC_FC_LA_SPEED_4G             0x4
4184 #define LPFC_FC_LA_SPEED_8G             0x8
4185 #define LPFC_FC_LA_SPEED_10G            0xA
4186 #define LPFC_FC_LA_SPEED_16G            0x10
4187 #define LPFC_FC_LA_SPEED_32G            0x20
4188 #define LPFC_FC_LA_SPEED_64G            0x21
4189 #define LPFC_FC_LA_SPEED_128G           0x22
4190 #define LPFC_FC_LA_SPEED_256G           0x23
4191 #define lpfc_acqe_fc_la_topology_SHIFT          16
4192 #define lpfc_acqe_fc_la_topology_MASK           0x000000FF
4193 #define lpfc_acqe_fc_la_topology_WORD           word0
4194 #define LPFC_FC_LA_TOP_UNKOWN           0x0
4195 #define LPFC_FC_LA_TOP_P2P              0x1
4196 #define LPFC_FC_LA_TOP_FCAL             0x2
4197 #define LPFC_FC_LA_TOP_INTERNAL_LOOP    0x3
4198 #define LPFC_FC_LA_TOP_SERDES_LOOP      0x4
4199 #define lpfc_acqe_fc_la_att_type_SHIFT          8
4200 #define lpfc_acqe_fc_la_att_type_MASK           0x000000FF
4201 #define lpfc_acqe_fc_la_att_type_WORD           word0
4202 #define LPFC_FC_LA_TYPE_LINK_UP         0x1
4203 #define LPFC_FC_LA_TYPE_LINK_DOWN       0x2
4204 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA    0x3
4205 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN   0x4
4206 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK    0x5
4207 #define LPFC_FC_LA_TYPE_UNEXP_WWPN      0x6
4208 #define LPFC_FC_LA_TYPE_TRUNKING_EVENT  0x7
4209 #define LPFC_FC_LA_TYPE_ACTIVATE_FAIL           0x8
4210 #define LPFC_FC_LA_TYPE_LINK_RESET_PRTCL_EVT    0x9
4211 #define lpfc_acqe_fc_la_port_type_SHIFT         6
4212 #define lpfc_acqe_fc_la_port_type_MASK          0x00000003
4213 #define lpfc_acqe_fc_la_port_type_WORD          word0
4214 #define LPFC_LINK_TYPE_ETHERNET         0x0
4215 #define LPFC_LINK_TYPE_FC               0x1
4216 #define lpfc_acqe_fc_la_port_number_SHIFT       0
4217 #define lpfc_acqe_fc_la_port_number_MASK        0x0000003F
4218 #define lpfc_acqe_fc_la_port_number_WORD        word0
4219
4220 /* Attention Type is 0x07 (Trunking Event) word0 */
4221 #define lpfc_acqe_fc_la_trunk_link_status_port0_SHIFT   16
4222 #define lpfc_acqe_fc_la_trunk_link_status_port0_MASK    0x0000001
4223 #define lpfc_acqe_fc_la_trunk_link_status_port0_WORD    word0
4224 #define lpfc_acqe_fc_la_trunk_link_status_port1_SHIFT   17
4225 #define lpfc_acqe_fc_la_trunk_link_status_port1_MASK    0x0000001
4226 #define lpfc_acqe_fc_la_trunk_link_status_port1_WORD    word0
4227 #define lpfc_acqe_fc_la_trunk_link_status_port2_SHIFT   18
4228 #define lpfc_acqe_fc_la_trunk_link_status_port2_MASK    0x0000001
4229 #define lpfc_acqe_fc_la_trunk_link_status_port2_WORD    word0
4230 #define lpfc_acqe_fc_la_trunk_link_status_port3_SHIFT   19
4231 #define lpfc_acqe_fc_la_trunk_link_status_port3_MASK    0x0000001
4232 #define lpfc_acqe_fc_la_trunk_link_status_port3_WORD    word0
4233 #define lpfc_acqe_fc_la_trunk_config_port0_SHIFT        20
4234 #define lpfc_acqe_fc_la_trunk_config_port0_MASK         0x0000001
4235 #define lpfc_acqe_fc_la_trunk_config_port0_WORD         word0
4236 #define lpfc_acqe_fc_la_trunk_config_port1_SHIFT        21
4237 #define lpfc_acqe_fc_la_trunk_config_port1_MASK         0x0000001
4238 #define lpfc_acqe_fc_la_trunk_config_port1_WORD         word0
4239 #define lpfc_acqe_fc_la_trunk_config_port2_SHIFT        22
4240 #define lpfc_acqe_fc_la_trunk_config_port2_MASK         0x0000001
4241 #define lpfc_acqe_fc_la_trunk_config_port2_WORD         word0
4242 #define lpfc_acqe_fc_la_trunk_config_port3_SHIFT        23
4243 #define lpfc_acqe_fc_la_trunk_config_port3_MASK         0x0000001
4244 #define lpfc_acqe_fc_la_trunk_config_port3_WORD         word0
4245         uint32_t word1;
4246 #define lpfc_acqe_fc_la_llink_spd_SHIFT         16
4247 #define lpfc_acqe_fc_la_llink_spd_MASK          0x0000FFFF
4248 #define lpfc_acqe_fc_la_llink_spd_WORD          word1
4249 #define lpfc_acqe_fc_la_fault_SHIFT             0
4250 #define lpfc_acqe_fc_la_fault_MASK              0x000000FF
4251 #define lpfc_acqe_fc_la_fault_WORD              word1
4252 #define lpfc_acqe_fc_la_link_status_SHIFT       8
4253 #define lpfc_acqe_fc_la_link_status_MASK        0x0000007F
4254 #define lpfc_acqe_fc_la_link_status_WORD        word1
4255 #define lpfc_acqe_fc_la_trunk_fault_SHIFT               0
4256 #define lpfc_acqe_fc_la_trunk_fault_MASK                0x0000000F
4257 #define lpfc_acqe_fc_la_trunk_fault_WORD                word1
4258 #define lpfc_acqe_fc_la_trunk_linkmask_SHIFT            4
4259 #define lpfc_acqe_fc_la_trunk_linkmask_MASK             0x000000F
4260 #define lpfc_acqe_fc_la_trunk_linkmask_WORD             word1
4261 #define LPFC_FC_LA_FAULT_NONE           0x0
4262 #define LPFC_FC_LA_FAULT_LOCAL          0x1
4263 #define LPFC_FC_LA_FAULT_REMOTE         0x2
4264         uint32_t event_tag;
4265         uint32_t trailer;
4266 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK           0x1
4267 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK       0x2
4268 };
4269
4270 struct lpfc_acqe_misconfigured_event {
4271         struct {
4272         uint32_t word0;
4273 #define lpfc_sli_misconfigured_port0_state_SHIFT        0
4274 #define lpfc_sli_misconfigured_port0_state_MASK         0x000000FF
4275 #define lpfc_sli_misconfigured_port0_state_WORD         word0
4276 #define lpfc_sli_misconfigured_port1_state_SHIFT        8
4277 #define lpfc_sli_misconfigured_port1_state_MASK         0x000000FF
4278 #define lpfc_sli_misconfigured_port1_state_WORD         word0
4279 #define lpfc_sli_misconfigured_port2_state_SHIFT        16
4280 #define lpfc_sli_misconfigured_port2_state_MASK         0x000000FF
4281 #define lpfc_sli_misconfigured_port2_state_WORD         word0
4282 #define lpfc_sli_misconfigured_port3_state_SHIFT        24
4283 #define lpfc_sli_misconfigured_port3_state_MASK         0x000000FF
4284 #define lpfc_sli_misconfigured_port3_state_WORD         word0
4285         uint32_t word1;
4286 #define lpfc_sli_misconfigured_port0_op_SHIFT           0
4287 #define lpfc_sli_misconfigured_port0_op_MASK            0x00000001
4288 #define lpfc_sli_misconfigured_port0_op_WORD            word1
4289 #define lpfc_sli_misconfigured_port0_severity_SHIFT     1
4290 #define lpfc_sli_misconfigured_port0_severity_MASK      0x00000003
4291 #define lpfc_sli_misconfigured_port0_severity_WORD      word1
4292 #define lpfc_sli_misconfigured_port1_op_SHIFT           8
4293 #define lpfc_sli_misconfigured_port1_op_MASK            0x00000001
4294 #define lpfc_sli_misconfigured_port1_op_WORD            word1
4295 #define lpfc_sli_misconfigured_port1_severity_SHIFT     9
4296 #define lpfc_sli_misconfigured_port1_severity_MASK      0x00000003
4297 #define lpfc_sli_misconfigured_port1_severity_WORD      word1
4298 #define lpfc_sli_misconfigured_port2_op_SHIFT           16
4299 #define lpfc_sli_misconfigured_port2_op_MASK            0x00000001
4300 #define lpfc_sli_misconfigured_port2_op_WORD            word1
4301 #define lpfc_sli_misconfigured_port2_severity_SHIFT     17
4302 #define lpfc_sli_misconfigured_port2_severity_MASK      0x00000003
4303 #define lpfc_sli_misconfigured_port2_severity_WORD      word1
4304 #define lpfc_sli_misconfigured_port3_op_SHIFT           24
4305 #define lpfc_sli_misconfigured_port3_op_MASK            0x00000001
4306 #define lpfc_sli_misconfigured_port3_op_WORD            word1
4307 #define lpfc_sli_misconfigured_port3_severity_SHIFT     25
4308 #define lpfc_sli_misconfigured_port3_severity_MASK      0x00000003
4309 #define lpfc_sli_misconfigured_port3_severity_WORD      word1
4310         } theEvent;
4311 #define LPFC_SLI_EVENT_STATUS_VALID                     0x00
4312 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT       0x01
4313 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE        0x02
4314 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED       0x03
4315 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED       0x04
4316 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED       0x05
4317 };
4318
4319 struct lpfc_acqe_cgn_signal {
4320         u32 word0;
4321 #define lpfc_warn_acqe_SHIFT            0
4322 #define lpfc_warn_acqe_MASK             0x7FFFFFFF
4323 #define lpfc_warn_acqe_WORD             word0
4324 #define lpfc_imm_acqe_SHIFT             31
4325 #define lpfc_imm_acqe_MASK              0x1
4326 #define lpfc_imm_acqe_WORD              word0
4327         u32 alarm_cnt;
4328         u32 word2;
4329         u32 trailer;
4330 };
4331
4332 struct lpfc_acqe_sli {
4333         uint32_t event_data1;
4334         uint32_t event_data2;
4335         uint32_t event_data3;
4336         uint32_t trailer;
4337 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR          0x1
4338 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP           0x2
4339 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP           0x3
4340 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST          0x4
4341 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP           0x5
4342 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED       0x9
4343 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT        0xA
4344 #define LPFC_SLI_EVENT_TYPE_PORT_PARAMS_CHG     0xE
4345 #define LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN       0xF
4346 #define LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE      0x10
4347 #define LPFC_SLI_EVENT_TYPE_CGN_SIGNAL          0x11
4348 #define LPFC_SLI_EVENT_TYPE_RD_SIGNAL           0x12
4349 #define LPFC_SLI_EVENT_TYPE_RESET_CM_STATS      0x13
4350 };
4351
4352 /*
4353  * Define the bootstrap mailbox (bmbx) region used to communicate
4354  * mailbox command between the host and port. The mailbox consists
4355  * of a payload area of 256 bytes and a completion queue of length
4356  * 16 bytes.
4357  */
4358 struct lpfc_bmbx_create {
4359         struct lpfc_mqe mqe;
4360         struct lpfc_mcqe mcqe;
4361 };
4362
4363 #define SGL_ALIGN_SZ 64
4364 #define SGL_PAGE_SIZE 4096
4365 /* align SGL addr on a size boundary - adjust address up */
4366 #define NO_XRI  0xffff
4367
4368 struct wqe_common {
4369         uint32_t word6;
4370 #define wqe_xri_tag_SHIFT     0
4371 #define wqe_xri_tag_MASK      0x0000FFFF
4372 #define wqe_xri_tag_WORD      word6
4373 #define wqe_ctxt_tag_SHIFT    16
4374 #define wqe_ctxt_tag_MASK     0x0000FFFF
4375 #define wqe_ctxt_tag_WORD     word6
4376         uint32_t word7;
4377 #define wqe_dif_SHIFT         0
4378 #define wqe_dif_MASK          0x00000003
4379 #define wqe_dif_WORD          word7
4380 #define LPFC_WQE_DIF_PASSTHRU   1
4381 #define LPFC_WQE_DIF_STRIP      2
4382 #define LPFC_WQE_DIF_INSERT     3
4383 #define wqe_ct_SHIFT          2
4384 #define wqe_ct_MASK           0x00000003
4385 #define wqe_ct_WORD           word7
4386 #define wqe_status_SHIFT      4
4387 #define wqe_status_MASK       0x0000000f
4388 #define wqe_status_WORD       word7
4389 #define wqe_cmnd_SHIFT        8
4390 #define wqe_cmnd_MASK         0x000000ff
4391 #define wqe_cmnd_WORD         word7
4392 #define wqe_class_SHIFT       16
4393 #define wqe_class_MASK        0x00000007
4394 #define wqe_class_WORD        word7
4395 #define wqe_ar_SHIFT          19
4396 #define wqe_ar_MASK           0x00000001
4397 #define wqe_ar_WORD           word7
4398 #define wqe_ag_SHIFT          wqe_ar_SHIFT
4399 #define wqe_ag_MASK           wqe_ar_MASK
4400 #define wqe_ag_WORD           wqe_ar_WORD
4401 #define wqe_pu_SHIFT          20
4402 #define wqe_pu_MASK           0x00000003
4403 #define wqe_pu_WORD           word7
4404 #define wqe_erp_SHIFT         22
4405 #define wqe_erp_MASK          0x00000001
4406 #define wqe_erp_WORD          word7
4407 #define wqe_conf_SHIFT        wqe_erp_SHIFT
4408 #define wqe_conf_MASK         wqe_erp_MASK
4409 #define wqe_conf_WORD         wqe_erp_WORD
4410 #define wqe_lnk_SHIFT         23
4411 #define wqe_lnk_MASK          0x00000001
4412 #define wqe_lnk_WORD          word7
4413 #define wqe_tmo_SHIFT         24
4414 #define wqe_tmo_MASK          0x000000ff
4415 #define wqe_tmo_WORD          word7
4416         uint32_t abort_tag; /* word 8 in WQE */
4417         uint32_t word9;
4418 #define wqe_reqtag_SHIFT      0
4419 #define wqe_reqtag_MASK       0x0000FFFF
4420 #define wqe_reqtag_WORD       word9
4421 #define wqe_temp_rpi_SHIFT    16
4422 #define wqe_temp_rpi_MASK     0x0000FFFF
4423 #define wqe_temp_rpi_WORD     word9
4424 #define wqe_rcvoxid_SHIFT     16
4425 #define wqe_rcvoxid_MASK      0x0000FFFF
4426 #define wqe_rcvoxid_WORD      word9
4427 #define wqe_sof_SHIFT         24
4428 #define wqe_sof_MASK          0x000000FF
4429 #define wqe_sof_WORD          word9
4430 #define wqe_eof_SHIFT         16
4431 #define wqe_eof_MASK          0x000000FF
4432 #define wqe_eof_WORD          word9
4433         uint32_t word10;
4434 #define wqe_ebde_cnt_SHIFT    0
4435 #define wqe_ebde_cnt_MASK     0x0000000f
4436 #define wqe_ebde_cnt_WORD     word10
4437 #define wqe_xchg_SHIFT        4
4438 #define wqe_xchg_MASK         0x00000001
4439 #define wqe_xchg_WORD         word10
4440 #define LPFC_SCSI_XCHG        0x0
4441 #define LPFC_NVME_XCHG        0x1
4442 #define wqe_appid_SHIFT       5
4443 #define wqe_appid_MASK        0x00000001
4444 #define wqe_appid_WORD        word10
4445 #define wqe_oas_SHIFT         6
4446 #define wqe_oas_MASK          0x00000001
4447 #define wqe_oas_WORD          word10
4448 #define wqe_lenloc_SHIFT      7
4449 #define wqe_lenloc_MASK       0x00000003
4450 #define wqe_lenloc_WORD       word10
4451 #define LPFC_WQE_LENLOC_NONE            0
4452 #define LPFC_WQE_LENLOC_WORD3   1
4453 #define LPFC_WQE_LENLOC_WORD12  2
4454 #define LPFC_WQE_LENLOC_WORD4   3
4455 #define wqe_qosd_SHIFT        9
4456 #define wqe_qosd_MASK         0x00000001
4457 #define wqe_qosd_WORD         word10
4458 #define wqe_xbl_SHIFT         11
4459 #define wqe_xbl_MASK          0x00000001
4460 #define wqe_xbl_WORD          word10
4461 #define wqe_iod_SHIFT         13
4462 #define wqe_iod_MASK          0x00000001
4463 #define wqe_iod_WORD          word10
4464 #define LPFC_WQE_IOD_NONE       0
4465 #define LPFC_WQE_IOD_WRITE      0
4466 #define LPFC_WQE_IOD_READ       1
4467 #define wqe_dbde_SHIFT        14
4468 #define wqe_dbde_MASK         0x00000001
4469 #define wqe_dbde_WORD         word10
4470 #define wqe_wqes_SHIFT        15
4471 #define wqe_wqes_MASK         0x00000001
4472 #define wqe_wqes_WORD         word10
4473 /* Note that this field overlaps above fields */
4474 #define wqe_wqid_SHIFT        1
4475 #define wqe_wqid_MASK         0x00007fff
4476 #define wqe_wqid_WORD         word10
4477 #define wqe_pri_SHIFT         16
4478 #define wqe_pri_MASK          0x00000007
4479 #define wqe_pri_WORD          word10
4480 #define wqe_pv_SHIFT          19
4481 #define wqe_pv_MASK           0x00000001
4482 #define wqe_pv_WORD           word10
4483 #define wqe_xc_SHIFT          21
4484 #define wqe_xc_MASK           0x00000001
4485 #define wqe_xc_WORD           word10
4486 #define wqe_sr_SHIFT          22
4487 #define wqe_sr_MASK           0x00000001
4488 #define wqe_sr_WORD           word10
4489 #define wqe_ccpe_SHIFT        23
4490 #define wqe_ccpe_MASK         0x00000001
4491 #define wqe_ccpe_WORD         word10
4492 #define wqe_ccp_SHIFT         24
4493 #define wqe_ccp_MASK          0x000000ff
4494 #define wqe_ccp_WORD          word10
4495         uint32_t word11;
4496 #define wqe_cmd_type_SHIFT    0
4497 #define wqe_cmd_type_MASK     0x0000000f
4498 #define wqe_cmd_type_WORD     word11
4499 #define wqe_els_id_SHIFT      4
4500 #define wqe_els_id_MASK       0x00000007
4501 #define wqe_els_id_WORD       word11
4502 #define wqe_irsp_SHIFT        4
4503 #define wqe_irsp_MASK         0x00000001
4504 #define wqe_irsp_WORD         word11
4505 #define wqe_pbde_SHIFT        5
4506 #define wqe_pbde_MASK         0x00000001
4507 #define wqe_pbde_WORD         word11
4508 #define wqe_sup_SHIFT         6
4509 #define wqe_sup_MASK          0x00000001
4510 #define wqe_sup_WORD          word11
4511 #define wqe_ffrq_SHIFT         6
4512 #define wqe_ffrq_MASK          0x00000001
4513 #define wqe_ffrq_WORD          word11
4514 #define wqe_wqec_SHIFT        7
4515 #define wqe_wqec_MASK         0x00000001
4516 #define wqe_wqec_WORD         word11
4517 #define wqe_irsplen_SHIFT     8
4518 #define wqe_irsplen_MASK      0x0000000f
4519 #define wqe_irsplen_WORD      word11
4520 #define wqe_cqid_SHIFT        16
4521 #define wqe_cqid_MASK         0x0000ffff
4522 #define wqe_cqid_WORD         word11
4523 #define LPFC_WQE_CQ_ID_DEFAULT  0xffff
4524 };
4525
4526 struct wqe_did {
4527         uint32_t word5;
4528 #define wqe_els_did_SHIFT         0
4529 #define wqe_els_did_MASK          0x00FFFFFF
4530 #define wqe_els_did_WORD          word5
4531 #define wqe_xmit_bls_pt_SHIFT         28
4532 #define wqe_xmit_bls_pt_MASK          0x00000003
4533 #define wqe_xmit_bls_pt_WORD          word5
4534 #define wqe_xmit_bls_ar_SHIFT         30
4535 #define wqe_xmit_bls_ar_MASK          0x00000001
4536 #define wqe_xmit_bls_ar_WORD          word5
4537 #define wqe_xmit_bls_xo_SHIFT         31
4538 #define wqe_xmit_bls_xo_MASK          0x00000001
4539 #define wqe_xmit_bls_xo_WORD          word5
4540 };
4541
4542 struct lpfc_wqe_generic{
4543         struct ulp_bde64 bde;
4544         uint32_t word3;
4545         uint32_t word4;
4546         uint32_t word5;
4547         struct wqe_common wqe_com;
4548         uint32_t payload[4];
4549 };
4550
4551 enum els_request64_wqe_word11 {
4552         LPFC_ELS_ID_DEFAULT,
4553         LPFC_ELS_ID_LOGO,
4554         LPFC_ELS_ID_FDISC,
4555         LPFC_ELS_ID_FLOGI,
4556         LPFC_ELS_ID_PLOGI,
4557 };
4558
4559 struct els_request64_wqe {
4560         struct ulp_bde64 bde;
4561         uint32_t payload_len;
4562         uint32_t word4;
4563 #define els_req64_sid_SHIFT         0
4564 #define els_req64_sid_MASK          0x00FFFFFF
4565 #define els_req64_sid_WORD          word4
4566 #define els_req64_sp_SHIFT          24
4567 #define els_req64_sp_MASK           0x00000001
4568 #define els_req64_sp_WORD           word4
4569 #define els_req64_vf_SHIFT          25
4570 #define els_req64_vf_MASK           0x00000001
4571 #define els_req64_vf_WORD           word4
4572         struct wqe_did  wqe_dest;
4573         struct wqe_common wqe_com; /* words 6-11 */
4574         uint32_t word12;
4575 #define els_req64_vfid_SHIFT        1
4576 #define els_req64_vfid_MASK         0x00000FFF
4577 #define els_req64_vfid_WORD         word12
4578 #define els_req64_pri_SHIFT         13
4579 #define els_req64_pri_MASK          0x00000007
4580 #define els_req64_pri_WORD          word12
4581         uint32_t word13;
4582 #define els_req64_hopcnt_SHIFT      24
4583 #define els_req64_hopcnt_MASK       0x000000ff
4584 #define els_req64_hopcnt_WORD       word13
4585         uint32_t word14;
4586         uint32_t max_response_payload_len;
4587 };
4588
4589 struct xmit_els_rsp64_wqe {
4590         struct ulp_bde64 bde;
4591         uint32_t response_payload_len;
4592         uint32_t word4;
4593 #define els_rsp64_sid_SHIFT         0
4594 #define els_rsp64_sid_MASK          0x00FFFFFF
4595 #define els_rsp64_sid_WORD          word4
4596 #define els_rsp64_sp_SHIFT          24
4597 #define els_rsp64_sp_MASK           0x00000001
4598 #define els_rsp64_sp_WORD           word4
4599         struct wqe_did wqe_dest;
4600         struct wqe_common wqe_com; /* words 6-11 */
4601         uint32_t word12;
4602 #define wqe_rsp_temp_rpi_SHIFT    0
4603 #define wqe_rsp_temp_rpi_MASK     0x0000FFFF
4604 #define wqe_rsp_temp_rpi_WORD     word12
4605         uint32_t rsvd_13_15[3];
4606 };
4607
4608 struct xmit_bls_rsp64_wqe {
4609         uint32_t payload0;
4610 /* Payload0 for BA_ACC */
4611 #define xmit_bls_rsp64_acc_seq_id_SHIFT        16
4612 #define xmit_bls_rsp64_acc_seq_id_MASK         0x000000ff
4613 #define xmit_bls_rsp64_acc_seq_id_WORD         payload0
4614 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT   24
4615 #define xmit_bls_rsp64_acc_seq_id_vald_MASK    0x000000ff
4616 #define xmit_bls_rsp64_acc_seq_id_vald_WORD    payload0
4617 /* Payload0 for BA_RJT */
4618 #define xmit_bls_rsp64_rjt_vspec_SHIFT   0
4619 #define xmit_bls_rsp64_rjt_vspec_MASK    0x000000ff
4620 #define xmit_bls_rsp64_rjt_vspec_WORD    payload0
4621 #define xmit_bls_rsp64_rjt_expc_SHIFT    8
4622 #define xmit_bls_rsp64_rjt_expc_MASK     0x000000ff
4623 #define xmit_bls_rsp64_rjt_expc_WORD     payload0
4624 #define xmit_bls_rsp64_rjt_rsnc_SHIFT    16
4625 #define xmit_bls_rsp64_rjt_rsnc_MASK     0x000000ff
4626 #define xmit_bls_rsp64_rjt_rsnc_WORD     payload0
4627         uint32_t word1;
4628 #define xmit_bls_rsp64_rxid_SHIFT  0
4629 #define xmit_bls_rsp64_rxid_MASK   0x0000ffff
4630 #define xmit_bls_rsp64_rxid_WORD   word1
4631 #define xmit_bls_rsp64_oxid_SHIFT  16
4632 #define xmit_bls_rsp64_oxid_MASK   0x0000ffff
4633 #define xmit_bls_rsp64_oxid_WORD   word1
4634         uint32_t word2;
4635 #define xmit_bls_rsp64_seqcnthi_SHIFT  0
4636 #define xmit_bls_rsp64_seqcnthi_MASK   0x0000ffff
4637 #define xmit_bls_rsp64_seqcnthi_WORD   word2
4638 #define xmit_bls_rsp64_seqcntlo_SHIFT  16
4639 #define xmit_bls_rsp64_seqcntlo_MASK   0x0000ffff
4640 #define xmit_bls_rsp64_seqcntlo_WORD   word2
4641         uint32_t rsrvd3;
4642         uint32_t rsrvd4;
4643         struct wqe_did  wqe_dest;
4644         struct wqe_common wqe_com; /* words 6-11 */
4645         uint32_t word12;
4646 #define xmit_bls_rsp64_temprpi_SHIFT  0
4647 #define xmit_bls_rsp64_temprpi_MASK   0x0000ffff
4648 #define xmit_bls_rsp64_temprpi_WORD   word12
4649         uint32_t rsvd_13_15[3];
4650 };
4651
4652 struct wqe_rctl_dfctl {
4653         uint32_t word5;
4654 #define wqe_si_SHIFT 2
4655 #define wqe_si_MASK  0x000000001
4656 #define wqe_si_WORD  word5
4657 #define wqe_la_SHIFT 3
4658 #define wqe_la_MASK  0x000000001
4659 #define wqe_la_WORD  word5
4660 #define wqe_xo_SHIFT    6
4661 #define wqe_xo_MASK     0x000000001
4662 #define wqe_xo_WORD     word5
4663 #define wqe_ls_SHIFT 7
4664 #define wqe_ls_MASK  0x000000001
4665 #define wqe_ls_WORD  word5
4666 #define wqe_dfctl_SHIFT 8
4667 #define wqe_dfctl_MASK  0x0000000ff
4668 #define wqe_dfctl_WORD  word5
4669 #define wqe_type_SHIFT 16
4670 #define wqe_type_MASK  0x0000000ff
4671 #define wqe_type_WORD  word5
4672 #define wqe_rctl_SHIFT 24
4673 #define wqe_rctl_MASK  0x0000000ff
4674 #define wqe_rctl_WORD  word5
4675 };
4676
4677 struct xmit_seq64_wqe {
4678         struct ulp_bde64 bde;
4679         uint32_t rsvd3;
4680         uint32_t relative_offset;
4681         struct wqe_rctl_dfctl wge_ctl;
4682         struct wqe_common wqe_com; /* words 6-11 */
4683         uint32_t xmit_len;
4684         uint32_t rsvd_12_15[3];
4685 };
4686 struct xmit_bcast64_wqe {
4687         struct ulp_bde64 bde;
4688         uint32_t seq_payload_len;
4689         uint32_t rsvd4;
4690         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
4691         struct wqe_common wqe_com;     /* words 6-11 */
4692         uint32_t rsvd_12_15[4];
4693 };
4694
4695 struct gen_req64_wqe {
4696         struct ulp_bde64 bde;
4697         uint32_t request_payload_len;
4698         uint32_t relative_offset;
4699         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
4700         struct wqe_common wqe_com;     /* words 6-11 */
4701         uint32_t rsvd_12_14[3];
4702         uint32_t max_response_payload_len;
4703 };
4704
4705 /* Define NVME PRLI request to fabric. NVME is a
4706  * fabric-only protocol.
4707  * Updated to red-lined v1.08 on Sept 16, 2016
4708  */
4709 struct lpfc_nvme_prli {
4710         uint32_t word1;
4711         /* The Response Code is defined in the FCP PRLI lpfc_hw.h */
4712 #define prli_acc_rsp_code_SHIFT         8
4713 #define prli_acc_rsp_code_MASK          0x0000000f
4714 #define prli_acc_rsp_code_WORD          word1
4715 #define prli_estabImagePair_SHIFT       13
4716 #define prli_estabImagePair_MASK        0x00000001
4717 #define prli_estabImagePair_WORD        word1
4718 #define prli_type_code_ext_SHIFT        16
4719 #define prli_type_code_ext_MASK         0x000000ff
4720 #define prli_type_code_ext_WORD         word1
4721 #define prli_type_code_SHIFT            24
4722 #define prli_type_code_MASK             0x000000ff
4723 #define prli_type_code_WORD             word1
4724         uint32_t word_rsvd2;
4725         uint32_t word_rsvd3;
4726
4727         uint32_t word4;
4728 #define prli_fba_SHIFT                  0
4729 #define prli_fba_MASK                   0x00000001
4730 #define prli_fba_WORD                   word4
4731 #define prli_disc_SHIFT                 3
4732 #define prli_disc_MASK                  0x00000001
4733 #define prli_disc_WORD                  word4
4734 #define prli_tgt_SHIFT                  4
4735 #define prli_tgt_MASK                   0x00000001
4736 #define prli_tgt_WORD                   word4
4737 #define prli_init_SHIFT                 5
4738 #define prli_init_MASK                  0x00000001
4739 #define prli_init_WORD                  word4
4740 #define prli_conf_SHIFT                 7
4741 #define prli_conf_MASK                  0x00000001
4742 #define prli_conf_WORD                  word4
4743 #define prli_nsler_SHIFT                8
4744 #define prli_nsler_MASK                 0x00000001
4745 #define prli_nsler_WORD                 word4
4746         uint32_t word5;
4747 #define prli_fb_sz_SHIFT                0
4748 #define prli_fb_sz_MASK                 0x0000ffff
4749 #define prli_fb_sz_WORD                 word5
4750 #define LPFC_NVMET_FB_SZ_MAX  65536   /* Driver target mode only. */
4751 };
4752
4753 struct create_xri_wqe {
4754         uint32_t rsrvd[5];           /* words 0-4 */
4755         struct wqe_did  wqe_dest;  /* word 5 */
4756         struct wqe_common wqe_com; /* words 6-11 */
4757         uint32_t rsvd_12_15[4];         /* word 12-15 */
4758 };
4759
4760 #define T_REQUEST_TAG 3
4761 #define T_XRI_TAG 1
4762
4763 struct cmf_sync_wqe {
4764         uint32_t rsrvd[3];
4765         uint32_t word3;
4766 #define cmf_sync_interval_SHIFT 0
4767 #define cmf_sync_interval_MASK  0x00000ffff
4768 #define cmf_sync_interval_WORD  word3
4769 #define cmf_sync_afpin_SHIFT    16
4770 #define cmf_sync_afpin_MASK     0x000000001
4771 #define cmf_sync_afpin_WORD     word3
4772 #define cmf_sync_asig_SHIFT     17
4773 #define cmf_sync_asig_MASK      0x000000001
4774 #define cmf_sync_asig_WORD      word3
4775 #define cmf_sync_op_SHIFT       20
4776 #define cmf_sync_op_MASK        0x00000000f
4777 #define cmf_sync_op_WORD        word3
4778 #define cmf_sync_ver_SHIFT      24
4779 #define cmf_sync_ver_MASK       0x0000000ff
4780 #define cmf_sync_ver_WORD       word3
4781 #define LPFC_CMF_SYNC_VER       1
4782         uint32_t event_tag;
4783         uint32_t word5;
4784 #define cmf_sync_wsigmax_SHIFT  0
4785 #define cmf_sync_wsigmax_MASK   0x00000ffff
4786 #define cmf_sync_wsigmax_WORD   word5
4787 #define cmf_sync_wsigcnt_SHIFT  16
4788 #define cmf_sync_wsigcnt_MASK   0x00000ffff
4789 #define cmf_sync_wsigcnt_WORD   word5
4790         uint32_t word6;
4791         uint32_t word7;
4792 #define cmf_sync_cmnd_SHIFT     8
4793 #define cmf_sync_cmnd_MASK      0x0000000ff
4794 #define cmf_sync_cmnd_WORD      word7
4795         uint32_t word8;
4796         uint32_t word9;
4797 #define cmf_sync_reqtag_SHIFT   0
4798 #define cmf_sync_reqtag_MASK    0x00000ffff
4799 #define cmf_sync_reqtag_WORD    word9
4800 #define cmf_sync_wfpinmax_SHIFT 16
4801 #define cmf_sync_wfpinmax_MASK  0x0000000ff
4802 #define cmf_sync_wfpinmax_WORD  word9
4803 #define cmf_sync_wfpincnt_SHIFT 24
4804 #define cmf_sync_wfpincnt_MASK  0x0000000ff
4805 #define cmf_sync_wfpincnt_WORD  word9
4806         uint32_t word10;
4807 #define cmf_sync_qosd_SHIFT     9
4808 #define cmf_sync_qosd_MASK      0x00000001
4809 #define cmf_sync_qosd_WORD      word10
4810         uint32_t word11;
4811 #define cmf_sync_cmd_type_SHIFT 0
4812 #define cmf_sync_cmd_type_MASK  0x0000000f
4813 #define cmf_sync_cmd_type_WORD  word11
4814 #define cmf_sync_wqec_SHIFT     7
4815 #define cmf_sync_wqec_MASK      0x00000001
4816 #define cmf_sync_wqec_WORD      word11
4817 #define cmf_sync_cqid_SHIFT     16
4818 #define cmf_sync_cqid_MASK      0x0000ffff
4819 #define cmf_sync_cqid_WORD      word11
4820         uint32_t read_bytes;
4821         uint32_t word13;
4822 #define cmf_sync_period_SHIFT   24
4823 #define cmf_sync_period_MASK    0x000000ff
4824 #define cmf_sync_period_WORD    word13
4825         uint32_t word14;
4826         uint32_t word15;
4827 };
4828
4829 struct abort_cmd_wqe {
4830         uint32_t rsrvd[3];
4831         uint32_t word3;
4832 #define abort_cmd_ia_SHIFT  0
4833 #define abort_cmd_ia_MASK  0x000000001
4834 #define abort_cmd_ia_WORD  word3
4835 #define abort_cmd_criteria_SHIFT  8
4836 #define abort_cmd_criteria_MASK  0x0000000ff
4837 #define abort_cmd_criteria_WORD  word3
4838         uint32_t rsrvd4;
4839         uint32_t rsrvd5;
4840         struct wqe_common wqe_com;     /* words 6-11 */
4841         uint32_t rsvd_12_15[4];         /* word 12-15 */
4842 };
4843
4844 struct fcp_iwrite64_wqe {
4845         struct ulp_bde64 bde;
4846         uint32_t word3;
4847 #define cmd_buff_len_SHIFT  16
4848 #define cmd_buff_len_MASK  0x00000ffff
4849 #define cmd_buff_len_WORD  word3
4850 #define payload_offset_len_SHIFT 0
4851 #define payload_offset_len_MASK 0x0000ffff
4852 #define payload_offset_len_WORD word3
4853         uint32_t total_xfer_len;
4854         uint32_t initial_xfer_len;
4855         struct wqe_common wqe_com;     /* words 6-11 */
4856         uint32_t rsrvd12;
4857         struct ulp_bde64 ph_bde;       /* words 13-15 */
4858 };
4859
4860 struct fcp_iread64_wqe {
4861         struct ulp_bde64 bde;
4862         uint32_t word3;
4863 #define cmd_buff_len_SHIFT  16
4864 #define cmd_buff_len_MASK  0x00000ffff
4865 #define cmd_buff_len_WORD  word3
4866 #define payload_offset_len_SHIFT 0
4867 #define payload_offset_len_MASK 0x0000ffff
4868 #define payload_offset_len_WORD word3
4869         uint32_t total_xfer_len;       /* word 4 */
4870         uint32_t rsrvd5;               /* word 5 */
4871         struct wqe_common wqe_com;     /* words 6-11 */
4872         uint32_t rsrvd12;
4873         struct ulp_bde64 ph_bde;       /* words 13-15 */
4874 };
4875
4876 struct fcp_icmnd64_wqe {
4877         struct ulp_bde64 bde;          /* words 0-2 */
4878         uint32_t word3;
4879 #define cmd_buff_len_SHIFT  16
4880 #define cmd_buff_len_MASK  0x00000ffff
4881 #define cmd_buff_len_WORD  word3
4882 #define payload_offset_len_SHIFT 0
4883 #define payload_offset_len_MASK 0x0000ffff
4884 #define payload_offset_len_WORD word3
4885         uint32_t rsrvd4;               /* word 4 */
4886         uint32_t rsrvd5;               /* word 5 */
4887         struct wqe_common wqe_com;     /* words 6-11 */
4888         uint32_t rsvd_12_15[4];        /* word 12-15 */
4889 };
4890
4891 struct fcp_trsp64_wqe {
4892         struct ulp_bde64 bde;
4893         uint32_t response_len;
4894         uint32_t rsvd_4_5[2];
4895         struct wqe_common wqe_com;      /* words 6-11 */
4896         uint32_t rsvd_12_15[4];         /* word 12-15 */
4897 };
4898
4899 struct fcp_tsend64_wqe {
4900         struct ulp_bde64 bde;
4901         uint32_t payload_offset_len;
4902         uint32_t relative_offset;
4903         uint32_t reserved;
4904         struct wqe_common wqe_com;     /* words 6-11 */
4905         uint32_t fcp_data_len;         /* word 12 */
4906         uint32_t rsvd_13_15[3];        /* word 13-15 */
4907 };
4908
4909 struct fcp_treceive64_wqe {
4910         struct ulp_bde64 bde;
4911         uint32_t payload_offset_len;
4912         uint32_t relative_offset;
4913         uint32_t reserved;
4914         struct wqe_common wqe_com;     /* words 6-11 */
4915         uint32_t fcp_data_len;         /* word 12 */
4916         uint32_t rsvd_13_15[3];        /* word 13-15 */
4917 };
4918 #define TXRDY_PAYLOAD_LEN      12
4919
4920 #define CMD_SEND_FRAME  0xE1
4921
4922 struct send_frame_wqe {
4923         struct ulp_bde64 bde;          /* words 0-2 */
4924         uint32_t frame_len;            /* word 3 */
4925         uint32_t fc_hdr_wd0;           /* word 4 */
4926         uint32_t fc_hdr_wd1;           /* word 5 */
4927         struct wqe_common wqe_com;     /* words 6-11 */
4928         uint32_t fc_hdr_wd2;           /* word 12 */
4929         uint32_t fc_hdr_wd3;           /* word 13 */
4930         uint32_t fc_hdr_wd4;           /* word 14 */
4931         uint32_t fc_hdr_wd5;           /* word 15 */
4932 };
4933
4934 #define ELS_RDF_REG_TAG_CNT             4
4935 struct lpfc_els_rdf_reg_desc {
4936         struct fc_df_desc_fpin_reg      reg_desc;       /* descriptor header */
4937         __be32                          desc_tags[ELS_RDF_REG_TAG_CNT];
4938                                                         /* tags in reg_desc */
4939 };
4940
4941 struct lpfc_els_rdf_req {
4942         struct fc_els_rdf               rdf;       /* hdr up to descriptors */
4943         struct lpfc_els_rdf_reg_desc    reg_d1; /* 1st descriptor */
4944 };
4945
4946 struct lpfc_els_rdf_rsp {
4947         struct fc_els_rdf_resp          rdf_resp;  /* hdr up to descriptors */
4948         struct lpfc_els_rdf_reg_desc    reg_d1; /* 1st descriptor */
4949 };
4950
4951 union lpfc_wqe {
4952         uint32_t words[16];
4953         struct lpfc_wqe_generic generic;
4954         struct fcp_icmnd64_wqe fcp_icmd;
4955         struct fcp_iread64_wqe fcp_iread;
4956         struct fcp_iwrite64_wqe fcp_iwrite;
4957         struct abort_cmd_wqe abort_cmd;
4958         struct cmf_sync_wqe cmf_sync;
4959         struct create_xri_wqe create_xri;
4960         struct xmit_bcast64_wqe xmit_bcast64;
4961         struct xmit_seq64_wqe xmit_sequence;
4962         struct xmit_bls_rsp64_wqe xmit_bls_rsp;
4963         struct xmit_els_rsp64_wqe xmit_els_rsp;
4964         struct els_request64_wqe els_req;
4965         struct gen_req64_wqe gen_req;
4966         struct fcp_trsp64_wqe fcp_trsp;
4967         struct fcp_tsend64_wqe fcp_tsend;
4968         struct fcp_treceive64_wqe fcp_treceive;
4969         struct send_frame_wqe send_frame;
4970 };
4971
4972 union lpfc_wqe128 {
4973         uint32_t words[32];
4974         struct lpfc_wqe_generic generic;
4975         struct fcp_icmnd64_wqe fcp_icmd;
4976         struct fcp_iread64_wqe fcp_iread;
4977         struct fcp_iwrite64_wqe fcp_iwrite;
4978         struct abort_cmd_wqe abort_cmd;
4979         struct cmf_sync_wqe cmf_sync;
4980         struct create_xri_wqe create_xri;
4981         struct xmit_bcast64_wqe xmit_bcast64;
4982         struct xmit_seq64_wqe xmit_sequence;
4983         struct xmit_bls_rsp64_wqe xmit_bls_rsp;
4984         struct xmit_els_rsp64_wqe xmit_els_rsp;
4985         struct els_request64_wqe els_req;
4986         struct gen_req64_wqe gen_req;
4987         struct fcp_trsp64_wqe fcp_trsp;
4988         struct fcp_tsend64_wqe fcp_tsend;
4989         struct fcp_treceive64_wqe fcp_treceive;
4990         struct send_frame_wqe send_frame;
4991 };
4992
4993 #define MAGIC_NUMBER_G6 0xFEAA0003
4994 #define MAGIC_NUMBER_G7 0xFEAA0005
4995 #define MAGIC_NUMBER_G7P 0xFEAA0020
4996
4997 struct lpfc_grp_hdr {
4998         uint32_t size;
4999         uint32_t magic_number;
5000         uint32_t word2;
5001 #define lpfc_grp_hdr_file_type_SHIFT    24
5002 #define lpfc_grp_hdr_file_type_MASK     0x000000FF
5003 #define lpfc_grp_hdr_file_type_WORD     word2
5004 #define lpfc_grp_hdr_id_SHIFT           16
5005 #define lpfc_grp_hdr_id_MASK            0x000000FF
5006 #define lpfc_grp_hdr_id_WORD            word2
5007         uint8_t rev_name[128];
5008         uint8_t date[12];
5009         uint8_t revision[32];
5010 };
5011
5012 /* Defines for WQE command type */
5013 #define FCP_COMMAND             0x0
5014 #define NVME_READ_CMD           0x0
5015 #define FCP_COMMAND_DATA_OUT    0x1
5016 #define NVME_WRITE_CMD          0x1
5017 #define COMMAND_DATA_IN         0x0
5018 #define COMMAND_DATA_OUT        0x1
5019 #define FCP_COMMAND_TRECEIVE    0x2
5020 #define FCP_COMMAND_TRSP        0x3
5021 #define FCP_COMMAND_TSEND       0x7
5022 #define OTHER_COMMAND           0x8
5023 #define CMF_SYNC_COMMAND        0xA
5024 #define ELS_COMMAND_NON_FIP     0xC
5025 #define ELS_COMMAND_FIP         0xD
5026
5027 #define LPFC_NVME_EMBED_CMD     0x0
5028 #define LPFC_NVME_EMBED_WRITE   0x1
5029 #define LPFC_NVME_EMBED_READ    0x2
5030
5031 /* WQE Commands */
5032 #define CMD_ABORT_XRI_WQE       0x0F
5033 #define CMD_XMIT_SEQUENCE64_WQE 0x82
5034 #define CMD_XMIT_BCAST64_WQE    0x84
5035 #define CMD_ELS_REQUEST64_WQE   0x8A
5036 #define CMD_XMIT_ELS_RSP64_WQE  0x95
5037 #define CMD_XMIT_BLS_RSP64_WQE  0x97
5038 #define CMD_FCP_IWRITE64_WQE    0x98
5039 #define CMD_FCP_IREAD64_WQE     0x9A
5040 #define CMD_FCP_ICMND64_WQE     0x9C
5041 #define CMD_FCP_TSEND64_WQE     0x9F
5042 #define CMD_FCP_TRECEIVE64_WQE  0xA1
5043 #define CMD_FCP_TRSP64_WQE      0xA3
5044 #define CMD_GEN_REQUEST64_WQE   0xC2
5045 #define CMD_CMF_SYNC_WQE        0xE8
5046
5047 #define CMD_WQE_MASK            0xff
5048
5049
5050 #define LPFC_FW_DUMP    1
5051 #define LPFC_FW_RESET   2
5052 #define LPFC_DV_RESET   3
5053
5054 /* On some kernels, enum fc_ls_tlv_dtag does not have
5055  * these 2 enums defined, on other kernels it does.
5056  * To get aound this we need to add these 2 defines here.
5057  */
5058 #ifndef ELS_DTAG_LNK_FAULT_CAP
5059 #define ELS_DTAG_LNK_FAULT_CAP        0x0001000D
5060 #endif
5061 #ifndef ELS_DTAG_CG_SIGNAL_CAP
5062 #define ELS_DTAG_CG_SIGNAL_CAP        0x0001000F
5063 #endif
5064
5065 /*
5066  * Initializer useful for decoding FPIN string table.
5067  */
5068 #define FC_FPIN_CONGN_SEVERITY_INIT {                           \
5069         { FPIN_CONGN_SEVERITY_WARNING,          "Warning" },    \
5070         { FPIN_CONGN_SEVERITY_ERROR,            "Alarm" },      \
5071 }
5072
5073 /* Used for logging FPIN messages */
5074 #define LPFC_FPIN_WWPN_LINE_SZ  128
5075 #define LPFC_FPIN_WWPN_LINE_CNT 6
5076 #define LPFC_FPIN_WWPN_NUM_LINE 6