drivers/regulator/axp20x-regulator.c

   1 /*
   2  * AXP20x regulators driver.
   3  *
   4  * Copyright (C) 2013 Carlo Caione <[email protected]>
   5  *
   6  * This file is subject to the terms and conditions of the GNU General
   7  * Public License. See the file "COPYING" in the main directory of this
   8  * archive for more details.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/bitops.h>
  17 #include <linux/delay.h>
  18 #include <linux/err.h>
  19 #include <linux/init.h>
  20 #include <linux/mfd/axp20x.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/regmap.h>
  25 #include <linux/regulator/driver.h>
  26 #include <linux/regulator/machine.h>
  27 #include <linux/regulator/of_regulator.h>
  28
  29 #define AXP20X_GPIO0_FUNC_MASK          GENMASK(3, 0)
  30 #define AXP20X_GPIO1_FUNC_MASK          GENMASK(3, 0)
  31
  32 #define AXP20X_IO_ENABLED               0x03
  33 #define AXP20X_IO_DISABLED              0x07
  34
  35 #define AXP20X_WORKMODE_DCDC2_MASK      BIT_MASK(2)
  36 #define AXP20X_WORKMODE_DCDC3_MASK      BIT_MASK(1)
  37
  38 #define AXP20X_FREQ_DCDC_MASK           GENMASK(3, 0)
  39
  40 #define AXP20X_VBUS_IPSOUT_MGMT_MASK    BIT_MASK(2)
  41
  42 #define AXP20X_DCDC2_V_OUT_MASK         GENMASK(5, 0)
  43 #define AXP20X_DCDC3_V_OUT_MASK         GENMASK(7, 0)
  44 #define AXP20X_LDO2_V_OUT_MASK          GENMASK(7, 4)
  45 #define AXP20X_LDO3_V_OUT_MASK          GENMASK(6, 0)
  46 #define AXP20X_LDO4_V_OUT_MASK          GENMASK(3, 0)
  47 #define AXP20X_LDO5_V_OUT_MASK          GENMASK(7, 4)
  48
  49 #define AXP20X_PWR_OUT_EXTEN_MASK       BIT_MASK(0)
  50 #define AXP20X_PWR_OUT_DCDC3_MASK       BIT_MASK(1)
  51 #define AXP20X_PWR_OUT_LDO2_MASK        BIT_MASK(2)
  52 #define AXP20X_PWR_OUT_LDO4_MASK        BIT_MASK(3)
  53 #define AXP20X_PWR_OUT_DCDC2_MASK       BIT_MASK(4)
  54 #define AXP20X_PWR_OUT_LDO3_MASK        BIT_MASK(6)
  55
  56 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK        BIT_MASK(0)
  57 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(x) \
  58         ((x) << 0)
  59 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK         BIT_MASK(1)
  60 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(x) \
  61         ((x) << 1)
  62 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK          BIT_MASK(2)
  63 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN               BIT(2)
  64 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK           BIT_MASK(3)
  65 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN                BIT(3)
  66
  67 #define AXP20X_LDO4_V_OUT_1250mV_START  0x0
  68 #define AXP20X_LDO4_V_OUT_1250mV_STEPS  0
  69 #define AXP20X_LDO4_V_OUT_1250mV_END    \
  70         (AXP20X_LDO4_V_OUT_1250mV_START + AXP20X_LDO4_V_OUT_1250mV_STEPS)
  71 #define AXP20X_LDO4_V_OUT_1300mV_START  0x1
  72 #define AXP20X_LDO4_V_OUT_1300mV_STEPS  7
  73 #define AXP20X_LDO4_V_OUT_1300mV_END    \
  74         (AXP20X_LDO4_V_OUT_1300mV_START + AXP20X_LDO4_V_OUT_1300mV_STEPS)
  75 #define AXP20X_LDO4_V_OUT_2500mV_START  0x9
  76 #define AXP20X_LDO4_V_OUT_2500mV_STEPS  0
  77 #define AXP20X_LDO4_V_OUT_2500mV_END    \
  78         (AXP20X_LDO4_V_OUT_2500mV_START + AXP20X_LDO4_V_OUT_2500mV_STEPS)
  79 #define AXP20X_LDO4_V_OUT_2700mV_START  0xa
  80 #define AXP20X_LDO4_V_OUT_2700mV_STEPS  1
  81 #define AXP20X_LDO4_V_OUT_2700mV_END    \
  82         (AXP20X_LDO4_V_OUT_2700mV_START + AXP20X_LDO4_V_OUT_2700mV_STEPS)
  83 #define AXP20X_LDO4_V_OUT_3000mV_START  0xc
  84 #define AXP20X_LDO4_V_OUT_3000mV_STEPS  3
  85 #define AXP20X_LDO4_V_OUT_3000mV_END    \
  86         (AXP20X_LDO4_V_OUT_3000mV_START + AXP20X_LDO4_V_OUT_3000mV_STEPS)
  87 #define AXP20X_LDO4_V_OUT_NUM_VOLTAGES  16
  88
  89 #define AXP22X_IO_ENABLED               0x03
  90 #define AXP22X_IO_DISABLED              0x04
  91
  92 #define AXP22X_WORKMODE_DCDCX_MASK(x)   BIT_MASK(x)
  93
  94 #define AXP22X_MISC_N_VBUSEN_FUNC       BIT(4)
  95
  96 #define AXP22X_DCDC1_V_OUT_MASK         GENMASK(4, 0)
  97 #define AXP22X_DCDC2_V_OUT_MASK         GENMASK(5, 0)
  98 #define AXP22X_DCDC3_V_OUT_MASK         GENMASK(5, 0)
  99 #define AXP22X_DCDC4_V_OUT_MASK         GENMASK(5, 0)
 100 #define AXP22X_DCDC5_V_OUT_MASK         GENMASK(4, 0)
 101 #define AXP22X_DC5LDO_V_OUT_MASK        GENMASK(2, 0)
 102 #define AXP22X_ALDO1_V_OUT_MASK         GENMASK(4, 0)
 103 #define AXP22X_ALDO2_V_OUT_MASK         GENMASK(4, 0)
 104 #define AXP22X_ALDO3_V_OUT_MASK         GENMASK(4, 0)
 105 #define AXP22X_DLDO1_V_OUT_MASK         GENMASK(4, 0)
 106 #define AXP22X_DLDO2_V_OUT_MASK         GENMASK(4, 0)
 107 #define AXP22X_DLDO3_V_OUT_MASK         GENMASK(4, 0)
 108 #define AXP22X_DLDO4_V_OUT_MASK         GENMASK(4, 0)
 109 #define AXP22X_ELDO1_V_OUT_MASK         GENMASK(4, 0)
 110 #define AXP22X_ELDO2_V_OUT_MASK         GENMASK(4, 0)
 111 #define AXP22X_ELDO3_V_OUT_MASK         GENMASK(4, 0)
 112 #define AXP22X_LDO_IO0_V_OUT_MASK       GENMASK(4, 0)
 113 #define AXP22X_LDO_IO1_V_OUT_MASK       GENMASK(4, 0)
 114
 115 #define AXP22X_PWR_OUT_DC5LDO_MASK      BIT_MASK(0)
 116 #define AXP22X_PWR_OUT_DCDC1_MASK       BIT_MASK(1)
 117 #define AXP22X_PWR_OUT_DCDC2_MASK       BIT_MASK(2)
 118 #define AXP22X_PWR_OUT_DCDC3_MASK       BIT_MASK(3)
 119 #define AXP22X_PWR_OUT_DCDC4_MASK       BIT_MASK(4)
 120 #define AXP22X_PWR_OUT_DCDC5_MASK       BIT_MASK(5)
 121 #define AXP22X_PWR_OUT_ALDO1_MASK       BIT_MASK(6)
 122 #define AXP22X_PWR_OUT_ALDO2_MASK       BIT_MASK(7)
 123
 124 #define AXP22X_PWR_OUT_SW_MASK          BIT_MASK(6)
 125 #define AXP22X_PWR_OUT_DC1SW_MASK       BIT_MASK(7)
 126
 127 #define AXP22X_PWR_OUT_ELDO1_MASK       BIT_MASK(0)
 128 #define AXP22X_PWR_OUT_ELDO2_MASK       BIT_MASK(1)
 129 #define AXP22X_PWR_OUT_ELDO3_MASK       BIT_MASK(2)
 130 #define AXP22X_PWR_OUT_DLDO1_MASK       BIT_MASK(3)
 131 #define AXP22X_PWR_OUT_DLDO2_MASK       BIT_MASK(4)
 132 #define AXP22X_PWR_OUT_DLDO3_MASK       BIT_MASK(5)
 133 #define AXP22X_PWR_OUT_DLDO4_MASK       BIT_MASK(6)
 134 #define AXP22X_PWR_OUT_ALDO3_MASK       BIT_MASK(7)
 135
 136 #define AXP313A_DCDC1_NUM_VOLTAGES      107
 137 #define AXP313A_DCDC23_NUM_VOLTAGES     88
 138 #define AXP313A_DCDC_V_OUT_MASK         GENMASK(6, 0)
 139 #define AXP313A_LDO_V_OUT_MASK          GENMASK(4, 0)
 140
 141 #define AXP717_DCDC1_NUM_VOLTAGES       88
 142 #define AXP717_DCDC2_NUM_VOLTAGES       107
 143 #define AXP717_DCDC3_NUM_VOLTAGES       103
 144 #define AXP717_DCDC_V_OUT_MASK          GENMASK(6, 0)
 145 #define AXP717_LDO_V_OUT_MASK           GENMASK(4, 0)
 146
 147 #define AXP803_PWR_OUT_DCDC1_MASK       BIT_MASK(0)
 148 #define AXP803_PWR_OUT_DCDC2_MASK       BIT_MASK(1)
 149 #define AXP803_PWR_OUT_DCDC3_MASK       BIT_MASK(2)
 150 #define AXP803_PWR_OUT_DCDC4_MASK       BIT_MASK(3)
 151 #define AXP803_PWR_OUT_DCDC5_MASK       BIT_MASK(4)
 152 #define AXP803_PWR_OUT_DCDC6_MASK       BIT_MASK(5)
 153
 154 #define AXP803_PWR_OUT_FLDO1_MASK       BIT_MASK(2)
 155 #define AXP803_PWR_OUT_FLDO2_MASK       BIT_MASK(3)
 156
 157 #define AXP803_DCDC1_V_OUT_MASK         GENMASK(4, 0)
 158 #define AXP803_DCDC2_V_OUT_MASK         GENMASK(6, 0)
 159 #define AXP803_DCDC3_V_OUT_MASK         GENMASK(6, 0)
 160 #define AXP803_DCDC4_V_OUT_MASK         GENMASK(6, 0)
 161 #define AXP803_DCDC5_V_OUT_MASK         GENMASK(6, 0)
 162 #define AXP803_DCDC6_V_OUT_MASK         GENMASK(6, 0)
 163
 164 #define AXP803_FLDO1_V_OUT_MASK         GENMASK(3, 0)
 165 #define AXP803_FLDO2_V_OUT_MASK         GENMASK(3, 0)
 166
 167 #define AXP803_DCDC23_POLYPHASE_DUAL    BIT(6)
 168 #define AXP803_DCDC56_POLYPHASE_DUAL    BIT(5)
 169
 170 #define AXP803_DCDC234_500mV_START      0x00
 171 #define AXP803_DCDC234_500mV_STEPS      70
 172 #define AXP803_DCDC234_500mV_END        \
 173         (AXP803_DCDC234_500mV_START + AXP803_DCDC234_500mV_STEPS)
 174 #define AXP803_DCDC234_1220mV_START     0x47
 175 #define AXP803_DCDC234_1220mV_STEPS     4
 176 #define AXP803_DCDC234_1220mV_END       \
 177         (AXP803_DCDC234_1220mV_START + AXP803_DCDC234_1220mV_STEPS)
 178 #define AXP803_DCDC234_NUM_VOLTAGES     76
 179
 180 #define AXP803_DCDC5_800mV_START        0x00
 181 #define AXP803_DCDC5_800mV_STEPS        32
 182 #define AXP803_DCDC5_800mV_END          \
 183         (AXP803_DCDC5_800mV_START + AXP803_DCDC5_800mV_STEPS)
 184 #define AXP803_DCDC5_1140mV_START       0x21
 185 #define AXP803_DCDC5_1140mV_STEPS       35
 186 #define AXP803_DCDC5_1140mV_END         \
 187         (AXP803_DCDC5_1140mV_START + AXP803_DCDC5_1140mV_STEPS)
 188 #define AXP803_DCDC5_NUM_VOLTAGES       69
 189
 190 #define AXP803_DCDC6_600mV_START        0x00
 191 #define AXP803_DCDC6_600mV_STEPS        50
 192 #define AXP803_DCDC6_600mV_END          \
 193         (AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS)
 194 #define AXP803_DCDC6_1120mV_START       0x33
 195 #define AXP803_DCDC6_1120mV_STEPS       20
 196 #define AXP803_DCDC6_1120mV_END         \
 197         (AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS)
 198 #define AXP803_DCDC6_NUM_VOLTAGES       72
 199
 200 #define AXP803_DLDO2_700mV_START        0x00
 201 #define AXP803_DLDO2_700mV_STEPS        26
 202 #define AXP803_DLDO2_700mV_END          \
 203         (AXP803_DLDO2_700mV_START + AXP803_DLDO2_700mV_STEPS)
 204 #define AXP803_DLDO2_3400mV_START       0x1b
 205 #define AXP803_DLDO2_3400mV_STEPS       4
 206 #define AXP803_DLDO2_3400mV_END         \
 207         (AXP803_DLDO2_3400mV_START + AXP803_DLDO2_3400mV_STEPS)
 208 #define AXP803_DLDO2_NUM_VOLTAGES       32
 209
 210 #define AXP806_DCDCA_V_CTRL_MASK        GENMASK(6, 0)
 211 #define AXP806_DCDCB_V_CTRL_MASK        GENMASK(4, 0)
 212 #define AXP806_DCDCC_V_CTRL_MASK        GENMASK(6, 0)
 213 #define AXP806_DCDCD_V_CTRL_MASK        GENMASK(5, 0)
 214 #define AXP806_DCDCE_V_CTRL_MASK        GENMASK(4, 0)
 215 #define AXP806_ALDO1_V_CTRL_MASK        GENMASK(4, 0)
 216 #define AXP806_ALDO2_V_CTRL_MASK        GENMASK(4, 0)
 217 #define AXP806_ALDO3_V_CTRL_MASK        GENMASK(4, 0)
 218 #define AXP806_BLDO1_V_CTRL_MASK        GENMASK(3, 0)
 219 #define AXP806_BLDO2_V_CTRL_MASK        GENMASK(3, 0)
 220 #define AXP806_BLDO3_V_CTRL_MASK        GENMASK(3, 0)
 221 #define AXP806_BLDO4_V_CTRL_MASK        GENMASK(3, 0)
 222 #define AXP806_CLDO1_V_CTRL_MASK        GENMASK(4, 0)
 223 #define AXP806_CLDO2_V_CTRL_MASK        GENMASK(4, 0)
 224 #define AXP806_CLDO3_V_CTRL_MASK        GENMASK(4, 0)
 225
 226 #define AXP806_PWR_OUT_DCDCA_MASK       BIT_MASK(0)
 227 #define AXP806_PWR_OUT_DCDCB_MASK       BIT_MASK(1)
 228 #define AXP806_PWR_OUT_DCDCC_MASK       BIT_MASK(2)
 229 #define AXP806_PWR_OUT_DCDCD_MASK       BIT_MASK(3)
 230 #define AXP806_PWR_OUT_DCDCE_MASK       BIT_MASK(4)
 231 #define AXP806_PWR_OUT_ALDO1_MASK       BIT_MASK(5)
 232 #define AXP806_PWR_OUT_ALDO2_MASK       BIT_MASK(6)
 233 #define AXP806_PWR_OUT_ALDO3_MASK       BIT_MASK(7)
 234 #define AXP806_PWR_OUT_BLDO1_MASK       BIT_MASK(0)
 235 #define AXP806_PWR_OUT_BLDO2_MASK       BIT_MASK(1)
 236 #define AXP806_PWR_OUT_BLDO3_MASK       BIT_MASK(2)
 237 #define AXP806_PWR_OUT_BLDO4_MASK       BIT_MASK(3)
 238 #define AXP806_PWR_OUT_CLDO1_MASK       BIT_MASK(4)
 239 #define AXP806_PWR_OUT_CLDO2_MASK       BIT_MASK(5)
 240 #define AXP806_PWR_OUT_CLDO3_MASK       BIT_MASK(6)
 241 #define AXP806_PWR_OUT_SW_MASK          BIT_MASK(7)
 242
 243 #define AXP806_DCDCAB_POLYPHASE_DUAL    0x40
 244 #define AXP806_DCDCABC_POLYPHASE_TRI    0x80
 245 #define AXP806_DCDCABC_POLYPHASE_MASK   GENMASK(7, 6)
 246
 247 #define AXP806_DCDCDE_POLYPHASE_DUAL    BIT(5)
 248
 249 #define AXP806_DCDCA_600mV_START        0x00
 250 #define AXP806_DCDCA_600mV_STEPS        50
 251 #define AXP806_DCDCA_600mV_END          \
 252         (AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS)
 253 #define AXP806_DCDCA_1120mV_START       0x33
 254 #define AXP806_DCDCA_1120mV_STEPS       20
 255 #define AXP806_DCDCA_1120mV_END         \
 256         (AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS)
 257 #define AXP806_DCDCA_NUM_VOLTAGES       72
 258
 259 #define AXP806_DCDCD_600mV_START        0x00
 260 #define AXP806_DCDCD_600mV_STEPS        45
 261 #define AXP806_DCDCD_600mV_END          \
 262         (AXP806_DCDCD_600mV_START + AXP806_DCDCD_600mV_STEPS)
 263 #define AXP806_DCDCD_1600mV_START       0x2e
 264 #define AXP806_DCDCD_1600mV_STEPS       17
 265 #define AXP806_DCDCD_1600mV_END         \
 266         (AXP806_DCDCD_1600mV_START + AXP806_DCDCD_1600mV_STEPS)
 267 #define AXP806_DCDCD_NUM_VOLTAGES       64
 268
 269 #define AXP809_DCDC4_600mV_START        0x00
 270 #define AXP809_DCDC4_600mV_STEPS        47
 271 #define AXP809_DCDC4_600mV_END          \
 272         (AXP809_DCDC4_600mV_START + AXP809_DCDC4_600mV_STEPS)
 273 #define AXP809_DCDC4_1800mV_START       0x30
 274 #define AXP809_DCDC4_1800mV_STEPS       8
 275 #define AXP809_DCDC4_1800mV_END         \
 276         (AXP809_DCDC4_1800mV_START + AXP809_DCDC4_1800mV_STEPS)
 277 #define AXP809_DCDC4_NUM_VOLTAGES       57
 278
 279 #define AXP813_DCDC7_V_OUT_MASK         GENMASK(6, 0)
 280
 281 #define AXP813_PWR_OUT_DCDC7_MASK       BIT_MASK(6)
 282
 283 #define AXP15060_DCDC1_V_CTRL_MASK              GENMASK(4, 0)
 284 #define AXP15060_DCDC2_V_CTRL_MASK              GENMASK(6, 0)
 285 #define AXP15060_DCDC3_V_CTRL_MASK              GENMASK(6, 0)
 286 #define AXP15060_DCDC4_V_CTRL_MASK              GENMASK(6, 0)
 287 #define AXP15060_DCDC5_V_CTRL_MASK              GENMASK(6, 0)
 288 #define AXP15060_DCDC6_V_CTRL_MASK              GENMASK(4, 0)
 289 #define AXP15060_ALDO1_V_CTRL_MASK              GENMASK(4, 0)
 290 #define AXP15060_ALDO2_V_CTRL_MASK              GENMASK(4, 0)
 291 #define AXP15060_ALDO3_V_CTRL_MASK              GENMASK(4, 0)
 292 #define AXP15060_ALDO4_V_CTRL_MASK              GENMASK(4, 0)
 293 #define AXP15060_ALDO5_V_CTRL_MASK              GENMASK(4, 0)
 294 #define AXP15060_BLDO1_V_CTRL_MASK              GENMASK(4, 0)
 295 #define AXP15060_BLDO2_V_CTRL_MASK              GENMASK(4, 0)
 296 #define AXP15060_BLDO3_V_CTRL_MASK              GENMASK(4, 0)
 297 #define AXP15060_BLDO4_V_CTRL_MASK              GENMASK(4, 0)
 298 #define AXP15060_BLDO5_V_CTRL_MASK              GENMASK(4, 0)
 299 #define AXP15060_CLDO1_V_CTRL_MASK              GENMASK(4, 0)
 300 #define AXP15060_CLDO2_V_CTRL_MASK              GENMASK(4, 0)
 301 #define AXP15060_CLDO3_V_CTRL_MASK              GENMASK(4, 0)
 302 #define AXP15060_CLDO4_V_CTRL_MASK              GENMASK(5, 0)
 303 #define AXP15060_CPUSLDO_V_CTRL_MASK            GENMASK(3, 0)
 304
 305 #define AXP15060_PWR_OUT_DCDC1_MASK     BIT_MASK(0)
 306 #define AXP15060_PWR_OUT_DCDC2_MASK     BIT_MASK(1)
 307 #define AXP15060_PWR_OUT_DCDC3_MASK     BIT_MASK(2)
 308 #define AXP15060_PWR_OUT_DCDC4_MASK     BIT_MASK(3)
 309 #define AXP15060_PWR_OUT_DCDC5_MASK     BIT_MASK(4)
 310 #define AXP15060_PWR_OUT_DCDC6_MASK     BIT_MASK(5)
 311 #define AXP15060_PWR_OUT_ALDO1_MASK     BIT_MASK(0)
 312 #define AXP15060_PWR_OUT_ALDO2_MASK     BIT_MASK(1)
 313 #define AXP15060_PWR_OUT_ALDO3_MASK     BIT_MASK(2)
 314 #define AXP15060_PWR_OUT_ALDO4_MASK     BIT_MASK(3)
 315 #define AXP15060_PWR_OUT_ALDO5_MASK     BIT_MASK(4)
 316 #define AXP15060_PWR_OUT_BLDO1_MASK     BIT_MASK(5)
 317 #define AXP15060_PWR_OUT_BLDO2_MASK     BIT_MASK(6)
 318 #define AXP15060_PWR_OUT_BLDO3_MASK     BIT_MASK(7)
 319 #define AXP15060_PWR_OUT_BLDO4_MASK     BIT_MASK(0)
 320 #define AXP15060_PWR_OUT_BLDO5_MASK     BIT_MASK(1)
 321 #define AXP15060_PWR_OUT_CLDO1_MASK     BIT_MASK(2)
 322 #define AXP15060_PWR_OUT_CLDO2_MASK     BIT_MASK(3)
 323 #define AXP15060_PWR_OUT_CLDO3_MASK     BIT_MASK(4)
 324 #define AXP15060_PWR_OUT_CLDO4_MASK     BIT_MASK(5)
 325 #define AXP15060_PWR_OUT_CPUSLDO_MASK   BIT_MASK(6)
 326 #define AXP15060_PWR_OUT_SW_MASK                BIT_MASK(7)
 327
 328 #define AXP15060_DCDC23_POLYPHASE_DUAL_MASK             BIT_MASK(6)
 329 #define AXP15060_DCDC46_POLYPHASE_DUAL_MASK             BIT_MASK(7)
 330
 331 #define AXP15060_DCDC234_500mV_START    0x00
 332 #define AXP15060_DCDC234_500mV_STEPS    70
 333 #define AXP15060_DCDC234_500mV_END              \
 334         (AXP15060_DCDC234_500mV_START + AXP15060_DCDC234_500mV_STEPS)
 335 #define AXP15060_DCDC234_1220mV_START   0x47
 336 #define AXP15060_DCDC234_1220mV_STEPS   16
 337 #define AXP15060_DCDC234_1220mV_END             \
 338         (AXP15060_DCDC234_1220mV_START + AXP15060_DCDC234_1220mV_STEPS)
 339 #define AXP15060_DCDC234_NUM_VOLTAGES   88
 340
 341 #define AXP15060_DCDC5_800mV_START      0x00
 342 #define AXP15060_DCDC5_800mV_STEPS      32
 343 #define AXP15060_DCDC5_800mV_END                \
 344         (AXP15060_DCDC5_800mV_START + AXP15060_DCDC5_800mV_STEPS)
 345 #define AXP15060_DCDC5_1140mV_START     0x21
 346 #define AXP15060_DCDC5_1140mV_STEPS     35
 347 #define AXP15060_DCDC5_1140mV_END               \
 348         (AXP15060_DCDC5_1140mV_START + AXP15060_DCDC5_1140mV_STEPS)
 349 #define AXP15060_DCDC5_NUM_VOLTAGES     69
 350
 351 #define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg,    \
 352                     _vmask, _ereg, _emask, _enable_val, _disable_val)           \
 353         [_family##_##_id] = {                                                   \
 354                 .name           = (_match),                                     \
 355                 .supply_name    = (_supply),                                    \
 356                 .of_match       = of_match_ptr(_match),                         \
 357                 .regulators_node = of_match_ptr("regulators"),                  \
 358                 .type           = REGULATOR_VOLTAGE,                            \
 359                 .id             = _family##_##_id,                              \
 360                 .n_voltages     = (((_max) - (_min)) / (_step) + 1),            \
 361                 .owner          = THIS_MODULE,                                  \
 362                 .min_uV         = (_min) * 1000,                                \
 363                 .uV_step        = (_step) * 1000,                               \
 364                 .vsel_reg       = (_vreg),                                      \
 365                 .vsel_mask      = (_vmask),                                     \
 366                 .enable_reg     = (_ereg),                                      \
 367                 .enable_mask    = (_emask),                                     \
 368                 .enable_val     = (_enable_val),                                \
 369                 .disable_val    = (_disable_val),                               \
 370                 .ops            = &axp20x_ops,                                  \
 371         }
 372
 373 #define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg,       \
 374                  _vmask, _ereg, _emask)                                         \
 375         [_family##_##_id] = {                                                   \
 376                 .name           = (_match),                                     \
 377                 .supply_name    = (_supply),                                    \
 378                 .of_match       = of_match_ptr(_match),                         \
 379                 .regulators_node = of_match_ptr("regulators"),                  \
 380                 .type           = REGULATOR_VOLTAGE,                            \
 381                 .id             = _family##_##_id,                              \
 382                 .n_voltages     = (((_max) - (_min)) / (_step) + 1),            \
 383                 .owner          = THIS_MODULE,                                  \
 384                 .min_uV         = (_min) * 1000,                                \
 385                 .uV_step        = (_step) * 1000,                               \
 386                 .vsel_reg       = (_vreg),                                      \
 387                 .vsel_mask      = (_vmask),                                     \
 388                 .enable_reg     = (_ereg),                                      \
 389                 .enable_mask    = (_emask),                                     \
 390                 .ops            = &axp20x_ops,                                  \
 391         }
 392
 393 #define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask)               \
 394         [_family##_##_id] = {                                                   \
 395                 .name           = (_match),                                     \
 396                 .supply_name    = (_supply),                                    \
 397                 .of_match       = of_match_ptr(_match),                         \
 398                 .regulators_node = of_match_ptr("regulators"),                  \
 399                 .type           = REGULATOR_VOLTAGE,                            \
 400                 .id             = _family##_##_id,                              \
 401                 .owner          = THIS_MODULE,                                  \
 402                 .enable_reg     = (_ereg),                                      \
 403                 .enable_mask    = (_emask),                                     \
 404                 .ops            = &axp20x_ops_sw,                               \
 405         }
 406
 407 #define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt)                    \
 408         [_family##_##_id] = {                                                   \
 409                 .name           = (_match),                                     \
 410                 .supply_name    = (_supply),                                    \
 411                 .of_match       = of_match_ptr(_match),                         \
 412                 .regulators_node = of_match_ptr("regulators"),                  \
 413                 .type           = REGULATOR_VOLTAGE,                            \
 414                 .id             = _family##_##_id,                              \
 415                 .n_voltages     = 1,                                            \
 416                 .owner          = THIS_MODULE,                                  \
 417                 .min_uV         = (_volt) * 1000,                               \
 418                 .ops            = &axp20x_ops_fixed                             \
 419         }
 420
 421 #define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages,    \
 422                         _vreg, _vmask, _ereg, _emask)                           \
 423         [_family##_##_id] = {                                                   \
 424                 .name           = (_match),                                     \
 425                 .supply_name    = (_supply),                                    \
 426                 .of_match       = of_match_ptr(_match),                         \
 427                 .regulators_node = of_match_ptr("regulators"),                  \
 428                 .type           = REGULATOR_VOLTAGE,                            \
 429                 .id             = _family##_##_id,                              \
 430                 .n_voltages     = (_n_voltages),                                \
 431                 .owner          = THIS_MODULE,                                  \
 432                 .vsel_reg       = (_vreg),                                      \
 433                 .vsel_mask      = (_vmask),                                     \
 434                 .enable_reg     = (_ereg),                                      \
 435                 .enable_mask    = (_emask),                                     \
 436                 .linear_ranges  = (_ranges),                                    \
 437                 .n_linear_ranges = ARRAY_SIZE(_ranges),                         \
 438                 .ops            = &axp20x_ops_range,                            \
 439         }
 440
 441 static const int axp209_dcdc2_ldo3_slew_rates[] = {
 442         1600,
 443          800,
 444 };
 445
 446 static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp)
 447 {
 448         struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
 449         int id = rdev_get_id(rdev);
 450         u8 reg, mask, enable, cfg = 0xff;
 451         const int *slew_rates;
 452         int rate_count = 0;
 453
 454         switch (axp20x->variant) {
 455         case AXP209_ID:
 456                 if (id == AXP20X_DCDC2) {
 457                         slew_rates = axp209_dcdc2_ldo3_slew_rates;
 458                         rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
 459                         reg = AXP20X_DCDC2_LDO3_V_RAMP;
 460                         mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK |
 461                                AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK;
 462                         enable = (ramp > 0) ?
 463                                  AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN : 0;
 464                         break;
 465                 }
 466
 467                 if (id == AXP20X_LDO3) {
 468                         slew_rates = axp209_dcdc2_ldo3_slew_rates;
 469                         rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
 470                         reg = AXP20X_DCDC2_LDO3_V_RAMP;
 471                         mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK |
 472                                AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK;
 473                         enable = (ramp > 0) ?
 474                                  AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN : 0;
 475                         break;
 476                 }
 477
 478                 if (rate_count > 0)
 479                         break;
 480
 481                 fallthrough;
 482         default:
 483                 /* Not supported for this regulator */
 484                 return -ENOTSUPP;
 485         }
 486
 487         if (ramp == 0) {
 488                 cfg = enable;
 489         } else {
 490                 int i;
 491
 492                 for (i = 0; i < rate_count; i++) {
 493                         if (ramp > slew_rates[i])
 494                                 break;
 495
 496                         if (id == AXP20X_DCDC2)
 497                                 cfg = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(i);
 498                         else
 499                                 cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i);
 500                 }
 501
 502                 if (cfg == 0xff) {
 503                         dev_err(axp20x->dev, "unsupported ramp value %d", ramp);
 504                         return -EINVAL;
 505                 }
 506
 507                 cfg |= enable;
 508         }
 509
 510         return regmap_update_bits(axp20x->regmap, reg, mask, cfg);
 511 }
 512
 513 static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev)
 514 {
 515         struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
 516         int id = rdev_get_id(rdev);
 517
 518         switch (axp20x->variant) {
 519         case AXP209_ID:
 520                 if ((id == AXP20X_LDO3) &&
 521                     rdev->constraints && rdev->constraints->soft_start) {
 522                         int v_out;
 523                         int ret;
 524
 525                         /*
 526                          * On some boards, the LDO3 can be overloaded when
 527                          * turning on, causing the entire PMIC to shutdown
 528                          * without warning. Turning it on at the minimal voltage
 529                          * and then setting the voltage to the requested value
 530                          * works reliably.
 531                          */
 532                         if (regulator_is_enabled_regmap(rdev))
 533                                 break;
 534
 535                         v_out = regulator_get_voltage_sel_regmap(rdev);
 536                         if (v_out < 0)
 537                                 return v_out;
 538
 539                         if (v_out == 0)
 540                                 break;
 541
 542                         ret = regulator_set_voltage_sel_regmap(rdev, 0x00);
 543                         /*
 544                          * A small pause is needed between
 545                          * setting the voltage and enabling the LDO to give the
 546                          * internal state machine time to process the request.
 547                          */
 548                         usleep_range(1000, 5000);
 549                         ret |= regulator_enable_regmap(rdev);
 550                         ret |= regulator_set_voltage_sel_regmap(rdev, v_out);
 551
 552                         return ret;
 553                 }
 554                 break;
 555         default:
 556                 /* No quirks */
 557                 break;
 558         }
 559
 560         return regulator_enable_regmap(rdev);
 561 };
 562
 563 static const struct regulator_ops axp20x_ops_fixed = {
 564         .list_voltage           = regulator_list_voltage_linear,
 565 };
 566
 567 static const struct regulator_ops axp20x_ops_range = {
 568         .set_voltage_sel        = regulator_set_voltage_sel_regmap,
 569         .get_voltage_sel        = regulator_get_voltage_sel_regmap,
 570         .list_voltage           = regulator_list_voltage_linear_range,
 571         .enable                 = regulator_enable_regmap,
 572         .disable                = regulator_disable_regmap,
 573         .is_enabled             = regulator_is_enabled_regmap,
 574 };
 575
 576 static const struct regulator_ops axp20x_ops = {
 577         .set_voltage_sel        = regulator_set_voltage_sel_regmap,
 578         .get_voltage_sel        = regulator_get_voltage_sel_regmap,
 579         .list_voltage           = regulator_list_voltage_linear,
 580         .enable                 = axp20x_regulator_enable_regmap,
 581         .disable                = regulator_disable_regmap,
 582         .is_enabled             = regulator_is_enabled_regmap,
 583         .set_ramp_delay         = axp20x_set_ramp_delay,
 584 };
 585
 586 static const struct regulator_ops axp20x_ops_sw = {
 587         .enable                 = regulator_enable_regmap,
 588         .disable                = regulator_disable_regmap,
 589         .is_enabled             = regulator_is_enabled_regmap,
 590 };
 591
 592 static const struct linear_range axp20x_ldo4_ranges[] = {
 593         REGULATOR_LINEAR_RANGE(1250000,
 594                                AXP20X_LDO4_V_OUT_1250mV_START,
 595                                AXP20X_LDO4_V_OUT_1250mV_END,
 596                                0),
 597         REGULATOR_LINEAR_RANGE(1300000,
 598                                AXP20X_LDO4_V_OUT_1300mV_START,
 599                                AXP20X_LDO4_V_OUT_1300mV_END,
 600                                100000),
 601         REGULATOR_LINEAR_RANGE(2500000,
 602                                AXP20X_LDO4_V_OUT_2500mV_START,
 603                                AXP20X_LDO4_V_OUT_2500mV_END,
 604                                0),
 605         REGULATOR_LINEAR_RANGE(2700000,
 606                                AXP20X_LDO4_V_OUT_2700mV_START,
 607                                AXP20X_LDO4_V_OUT_2700mV_END,
 608                                100000),
 609         REGULATOR_LINEAR_RANGE(3000000,
 610                                AXP20X_LDO4_V_OUT_3000mV_START,
 611                                AXP20X_LDO4_V_OUT_3000mV_END,
 612                                100000),
 613 };
 614
 615 static const struct regulator_desc axp20x_regulators[] = {
 616         AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25,
 617                  AXP20X_DCDC2_V_OUT, AXP20X_DCDC2_V_OUT_MASK,
 618                  AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC2_MASK),
 619         AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25,
 620                  AXP20X_DCDC3_V_OUT, AXP20X_DCDC3_V_OUT_MASK,
 621                  AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC3_MASK),
 622         AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300),
 623         AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100,
 624                  AXP20X_LDO24_V_OUT, AXP20X_LDO2_V_OUT_MASK,
 625                  AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO2_MASK),
 626         AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25,
 627                  AXP20X_LDO3_V_OUT, AXP20X_LDO3_V_OUT_MASK,
 628                  AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO3_MASK),
 629         AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in",
 630                         axp20x_ldo4_ranges, AXP20X_LDO4_V_OUT_NUM_VOLTAGES,
 631                         AXP20X_LDO24_V_OUT, AXP20X_LDO4_V_OUT_MASK,
 632                         AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO4_MASK),
 633         AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100,
 634                     AXP20X_LDO5_V_OUT, AXP20X_LDO5_V_OUT_MASK,
 635                     AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
 636                     AXP20X_IO_ENABLED, AXP20X_IO_DISABLED),
 637 };
 638
 639 static const struct regulator_desc axp22x_regulators[] = {
 640         AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
 641                  AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
 642                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
 643         AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
 644                  AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
 645                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
 646         AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
 647                  AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
 648                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
 649         AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20,
 650                  AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
 651                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
 652         AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
 653                  AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
 654                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
 655         /* secondary switchable output of DCDC1 */
 656         AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL,
 657                     AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
 658         /* LDO regulator internally chained to DCDC5 */
 659         AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
 660                  AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
 661                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
 662         AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
 663                  AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
 664                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
 665         AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
 666                  AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
 667                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
 668         AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
 669                  AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
 670                  AXP22X_PWR_OUT_CTRL3, AXP22X_PWR_OUT_ALDO3_MASK),
 671         AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
 672                  AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
 673                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
 674         AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
 675                  AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
 676                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
 677         AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
 678                  AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
 679                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
 680         AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
 681                  AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
 682                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
 683         AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
 684                  AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
 685                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
 686         AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
 687                  AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
 688                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
 689         AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
 690                  AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
 691                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
 692         /* Note the datasheet only guarantees reliable operation up to
 693          * 3.3V, this needs to be enforced via dts provided constraints */
 694         AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
 695                     AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
 696                     AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
 697                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 698         /* Note the datasheet only guarantees reliable operation up to
 699          * 3.3V, this needs to be enforced via dts provided constraints */
 700         AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
 701                     AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
 702                     AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
 703                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 704         AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000),
 705 };
 706
 707 static const struct regulator_desc axp22x_drivevbus_regulator = {
 708         .name           = "drivevbus",
 709         .supply_name    = "drivevbus",
 710         .of_match       = of_match_ptr("drivevbus"),
 711         .regulators_node = of_match_ptr("regulators"),
 712         .type           = REGULATOR_VOLTAGE,
 713         .owner          = THIS_MODULE,
 714         .enable_reg     = AXP20X_VBUS_IPSOUT_MGMT,
 715         .enable_mask    = AXP20X_VBUS_IPSOUT_MGMT_MASK,
 716         .ops            = &axp20x_ops_sw,
 717 };
 718
 719 static const struct linear_range axp313a_dcdc1_ranges[] = {
 720         REGULATOR_LINEAR_RANGE(500000,   0,  70,  10000),
 721         REGULATOR_LINEAR_RANGE(1220000, 71,  87,  20000),
 722         REGULATOR_LINEAR_RANGE(1600000, 88, 106, 100000),
 723 };
 724
 725 static const struct linear_range axp313a_dcdc2_ranges[] = {
 726         REGULATOR_LINEAR_RANGE(500000,   0, 70, 10000),
 727         REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000),
 728 };
 729
 730 /*
 731  * This is deviating from the datasheet. The values here are taken from the
 732  * BSP driver and have been confirmed by measurements.
 733  */
 734 static const struct linear_range axp313a_dcdc3_ranges[] = {
 735         REGULATOR_LINEAR_RANGE(500000,   0,  70, 10000),
 736         REGULATOR_LINEAR_RANGE(1220000, 71, 102, 20000),
 737 };
 738
 739 static const struct regulator_desc axp313a_regulators[] = {
 740         AXP_DESC_RANGES(AXP313A, DCDC1, "dcdc1", "vin1",
 741                         axp313a_dcdc1_ranges, AXP313A_DCDC1_NUM_VOLTAGES,
 742                         AXP313A_DCDC1_CONTROL, AXP313A_DCDC_V_OUT_MASK,
 743                         AXP313A_OUTPUT_CONTROL, BIT(0)),
 744         AXP_DESC_RANGES(AXP313A, DCDC2, "dcdc2", "vin2",
 745                         axp313a_dcdc2_ranges, AXP313A_DCDC23_NUM_VOLTAGES,
 746                         AXP313A_DCDC2_CONTROL, AXP313A_DCDC_V_OUT_MASK,
 747                         AXP313A_OUTPUT_CONTROL, BIT(1)),
 748         AXP_DESC_RANGES(AXP313A, DCDC3, "dcdc3", "vin3",
 749                         axp313a_dcdc3_ranges, AXP313A_DCDC23_NUM_VOLTAGES,
 750                         AXP313A_DCDC3_CONTROL, AXP313A_DCDC_V_OUT_MASK,
 751                         AXP313A_OUTPUT_CONTROL, BIT(2)),
 752         AXP_DESC(AXP313A, ALDO1, "aldo1", "vin1", 500, 3500, 100,
 753                  AXP313A_ALDO1_CONTROL, AXP313A_LDO_V_OUT_MASK,
 754                  AXP313A_OUTPUT_CONTROL, BIT(3)),
 755         AXP_DESC(AXP313A, DLDO1, "dldo1", "vin1", 500, 3500, 100,
 756                  AXP313A_DLDO1_CONTROL, AXP313A_LDO_V_OUT_MASK,
 757                  AXP313A_OUTPUT_CONTROL, BIT(4)),
 758         AXP_DESC_FIXED(AXP313A, RTC_LDO, "rtc-ldo", "vin1", 1800),
 759 };
 760
 761 static const struct linear_range axp717_dcdc1_ranges[] = {
 762         REGULATOR_LINEAR_RANGE(500000,   0, 70, 10000),
 763         REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000),
 764 };
 765
 766 /*
 767  * The manual says that the last voltage is 3.4V, encoded as 0b1101011 (107),
 768  * but every other method proves that this is wrong, so it's really 106 that
 769  * programs the final 3.4V.
 770  */
 771 static const struct linear_range axp717_dcdc2_ranges[] = {
 772         REGULATOR_LINEAR_RANGE(500000,   0,  70,  10000),
 773         REGULATOR_LINEAR_RANGE(1220000, 71,  87,  20000),
 774         REGULATOR_LINEAR_RANGE(1600000, 88, 106, 100000),
 775 };
 776
 777 static const struct linear_range axp717_dcdc3_ranges[] = {
 778         REGULATOR_LINEAR_RANGE(500000,   0,  70, 10000),
 779         REGULATOR_LINEAR_RANGE(1220000, 71, 102, 20000),
 780 };
 781
 782 static const struct regulator_desc axp717_regulators[] = {
 783         AXP_DESC_RANGES(AXP717, DCDC1, "dcdc1", "vin1",
 784                         axp717_dcdc1_ranges, AXP717_DCDC1_NUM_VOLTAGES,
 785                         AXP717_DCDC1_CONTROL, AXP717_DCDC_V_OUT_MASK,
 786                         AXP717_DCDC_OUTPUT_CONTROL, BIT(0)),
 787         AXP_DESC_RANGES(AXP717, DCDC2, "dcdc2", "vin2",
 788                         axp717_dcdc2_ranges, AXP717_DCDC2_NUM_VOLTAGES,
 789                         AXP717_DCDC2_CONTROL, AXP717_DCDC_V_OUT_MASK,
 790                         AXP717_DCDC_OUTPUT_CONTROL, BIT(1)),
 791         AXP_DESC_RANGES(AXP717, DCDC3, "dcdc3", "vin3",
 792                         axp717_dcdc3_ranges, AXP717_DCDC3_NUM_VOLTAGES,
 793                         AXP717_DCDC3_CONTROL, AXP717_DCDC_V_OUT_MASK,
 794                         AXP717_DCDC_OUTPUT_CONTROL, BIT(2)),
 795         AXP_DESC(AXP717, DCDC4, "dcdc4", "vin4", 1000, 3700, 100,
 796                  AXP717_DCDC4_CONTROL, AXP717_DCDC_V_OUT_MASK,
 797                  AXP717_DCDC_OUTPUT_CONTROL, BIT(3)),
 798         AXP_DESC(AXP717, ALDO1, "aldo1", "aldoin", 500, 3500, 100,
 799                  AXP717_ALDO1_CONTROL, AXP717_LDO_V_OUT_MASK,
 800                  AXP717_LDO0_OUTPUT_CONTROL, BIT(0)),
 801         AXP_DESC(AXP717, ALDO2, "aldo2", "aldoin", 500, 3500, 100,
 802                  AXP717_ALDO2_CONTROL, AXP717_LDO_V_OUT_MASK,
 803                  AXP717_LDO0_OUTPUT_CONTROL, BIT(1)),
 804         AXP_DESC(AXP717, ALDO3, "aldo3", "aldoin", 500, 3500, 100,
 805                  AXP717_ALDO3_CONTROL, AXP717_LDO_V_OUT_MASK,
 806                  AXP717_LDO0_OUTPUT_CONTROL, BIT(2)),
 807         AXP_DESC(AXP717, ALDO4, "aldo4", "aldoin", 500, 3500, 100,
 808                  AXP717_ALDO4_CONTROL, AXP717_LDO_V_OUT_MASK,
 809                  AXP717_LDO0_OUTPUT_CONTROL, BIT(3)),
 810         AXP_DESC(AXP717, BLDO1, "bldo1", "bldoin", 500, 3500, 100,
 811                  AXP717_BLDO1_CONTROL, AXP717_LDO_V_OUT_MASK,
 812                  AXP717_LDO0_OUTPUT_CONTROL, BIT(4)),
 813         AXP_DESC(AXP717, BLDO2, "bldo2", "bldoin", 500, 3500, 100,
 814                  AXP717_BLDO2_CONTROL, AXP717_LDO_V_OUT_MASK,
 815                  AXP717_LDO0_OUTPUT_CONTROL, BIT(5)),
 816         AXP_DESC(AXP717, BLDO3, "bldo3", "bldoin", 500, 3500, 100,
 817                  AXP717_BLDO3_CONTROL, AXP717_LDO_V_OUT_MASK,
 818                  AXP717_LDO0_OUTPUT_CONTROL, BIT(6)),
 819         AXP_DESC(AXP717, BLDO4, "bldo4", "bldoin", 500, 3500, 100,
 820                  AXP717_BLDO4_CONTROL, AXP717_LDO_V_OUT_MASK,
 821                  AXP717_LDO0_OUTPUT_CONTROL, BIT(7)),
 822         AXP_DESC(AXP717, CLDO1, "cldo1", "cldoin", 500, 3500, 100,
 823                  AXP717_CLDO1_CONTROL, AXP717_LDO_V_OUT_MASK,
 824                  AXP717_LDO1_OUTPUT_CONTROL, BIT(0)),
 825         AXP_DESC(AXP717, CLDO2, "cldo2", "cldoin", 500, 3500, 100,
 826                  AXP717_CLDO2_CONTROL, AXP717_LDO_V_OUT_MASK,
 827                  AXP717_LDO1_OUTPUT_CONTROL, BIT(1)),
 828         AXP_DESC(AXP717, CLDO3, "cldo3", "cldoin", 500, 3500, 100,
 829                  AXP717_CLDO3_CONTROL, AXP717_LDO_V_OUT_MASK,
 830                  AXP717_LDO1_OUTPUT_CONTROL, BIT(2)),
 831         AXP_DESC(AXP717, CLDO4, "cldo4", "cldoin", 500, 3500, 100,
 832                  AXP717_CLDO4_CONTROL, AXP717_LDO_V_OUT_MASK,
 833                  AXP717_LDO1_OUTPUT_CONTROL, BIT(3)),
 834         AXP_DESC(AXP717, CPUSLDO, "cpusldo", "vin1", 500, 1400, 50,
 835                  AXP717_CPUSLDO_CONTROL, AXP717_LDO_V_OUT_MASK,
 836                  AXP717_LDO1_OUTPUT_CONTROL, BIT(4)),
 837 };
 838
 839 /* DCDC ranges shared with AXP813 */
 840 static const struct linear_range axp803_dcdc234_ranges[] = {
 841         REGULATOR_LINEAR_RANGE(500000,
 842                                AXP803_DCDC234_500mV_START,
 843                                AXP803_DCDC234_500mV_END,
 844                                10000),
 845         REGULATOR_LINEAR_RANGE(1220000,
 846                                AXP803_DCDC234_1220mV_START,
 847                                AXP803_DCDC234_1220mV_END,
 848                                20000),
 849 };
 850
 851 static const struct linear_range axp803_dcdc5_ranges[] = {
 852         REGULATOR_LINEAR_RANGE(800000,
 853                                AXP803_DCDC5_800mV_START,
 854                                AXP803_DCDC5_800mV_END,
 855                                10000),
 856         REGULATOR_LINEAR_RANGE(1140000,
 857                                AXP803_DCDC5_1140mV_START,
 858                                AXP803_DCDC5_1140mV_END,
 859                                20000),
 860 };
 861
 862 static const struct linear_range axp803_dcdc6_ranges[] = {
 863         REGULATOR_LINEAR_RANGE(600000,
 864                                AXP803_DCDC6_600mV_START,
 865                                AXP803_DCDC6_600mV_END,
 866                                10000),
 867         REGULATOR_LINEAR_RANGE(1120000,
 868                                AXP803_DCDC6_1120mV_START,
 869                                AXP803_DCDC6_1120mV_END,
 870                                20000),
 871 };
 872
 873 /* AXP806's CLDO2 and AXP809's DLDO1 share the same range */
 874 static const struct linear_range axp803_dldo2_ranges[] = {
 875         REGULATOR_LINEAR_RANGE(700000,
 876                                AXP803_DLDO2_700mV_START,
 877                                AXP803_DLDO2_700mV_END,
 878                                100000),
 879         REGULATOR_LINEAR_RANGE(3400000,
 880                                AXP803_DLDO2_3400mV_START,
 881                                AXP803_DLDO2_3400mV_END,
 882                                200000),
 883 };
 884
 885 static const struct regulator_desc axp803_regulators[] = {
 886         AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
 887                  AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
 888                  AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
 889         AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2",
 890                         axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 891                         AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
 892                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
 893         AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3",
 894                         axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 895                         AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
 896                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
 897         AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4",
 898                         axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 899                         AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
 900                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
 901         AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5",
 902                         axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
 903                         AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
 904                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
 905         AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6",
 906                         axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
 907                         AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
 908                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
 909         /* secondary switchable output of DCDC1 */
 910         AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL,
 911                     AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
 912         AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
 913                  AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
 914                  AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
 915         AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
 916                  AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
 917                  AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
 918         AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
 919                  AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
 920                  AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
 921         AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
 922                  AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
 923                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
 924         AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin",
 925                         axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
 926                         AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
 927                         AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
 928         AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
 929                  AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
 930                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
 931         AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
 932                  AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
 933                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
 934         AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
 935                  AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
 936                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
 937         AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
 938                  AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
 939                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
 940         AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
 941                  AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
 942                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
 943         AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
 944                  AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
 945                  AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
 946         AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
 947                  AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
 948                  AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
 949         AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
 950                     AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
 951                     AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
 952                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 953         AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
 954                     AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
 955                     AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
 956                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 957         AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000),
 958 };
 959
 960 static const struct linear_range axp806_dcdca_ranges[] = {
 961         REGULATOR_LINEAR_RANGE(600000,
 962                                AXP806_DCDCA_600mV_START,
 963                                AXP806_DCDCA_600mV_END,
 964                                10000),
 965         REGULATOR_LINEAR_RANGE(1120000,
 966                                AXP806_DCDCA_1120mV_START,
 967                                AXP806_DCDCA_1120mV_END,
 968                                20000),
 969 };
 970
 971 static const struct linear_range axp806_dcdcd_ranges[] = {
 972         REGULATOR_LINEAR_RANGE(600000,
 973                                AXP806_DCDCD_600mV_START,
 974                                AXP806_DCDCD_600mV_END,
 975                                20000),
 976         REGULATOR_LINEAR_RANGE(1600000,
 977                                AXP806_DCDCD_1600mV_START,
 978                                AXP806_DCDCD_1600mV_END,
 979                                100000),
 980 };
 981
 982 static const struct regulator_desc axp806_regulators[] = {
 983         AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina",
 984                         axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
 985                         AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK,
 986                         AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK),
 987         AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50,
 988                  AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL_MASK,
 989                  AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK),
 990         AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc",
 991                         axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
 992                         AXP806_DCDCC_V_CTRL, AXP806_DCDCC_V_CTRL_MASK,
 993                         AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCC_MASK),
 994         AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind",
 995                         axp806_dcdcd_ranges, AXP806_DCDCD_NUM_VOLTAGES,
 996                         AXP806_DCDCD_V_CTRL, AXP806_DCDCD_V_CTRL_MASK,
 997                         AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCD_MASK),
 998         AXP_DESC(AXP806, DCDCE, "dcdce", "vine", 1100, 3400, 100,
 999                  AXP806_DCDCE_V_CTRL, AXP806_DCDCE_V_CTRL_MASK,
1000                  AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCE_MASK),
1001         AXP_DESC(AXP806, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
1002                  AXP806_ALDO1_V_CTRL, AXP806_ALDO1_V_CTRL_MASK,
1003                  AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO1_MASK),
1004         AXP_DESC(AXP806, ALDO2, "aldo2", "aldoin", 700, 3400, 100,
1005                  AXP806_ALDO2_V_CTRL, AXP806_ALDO2_V_CTRL_MASK,
1006                  AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO2_MASK),
1007         AXP_DESC(AXP806, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
1008                  AXP806_ALDO3_V_CTRL, AXP806_ALDO3_V_CTRL_MASK,
1009                  AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO3_MASK),
1010         AXP_DESC(AXP806, BLDO1, "bldo1", "bldoin", 700, 1900, 100,
1011                  AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK,
1012                  AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK),
1013         AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100,
1014                  AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL_MASK,
1015                  AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK),
1016         AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100,
1017                  AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK,
1018                  AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO3_MASK),
1019         AXP_DESC(AXP806, BLDO4, "bldo4", "bldoin", 700, 1900, 100,
1020                  AXP806_BLDO4_V_CTRL, AXP806_BLDO4_V_CTRL_MASK,
1021                  AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO4_MASK),
1022         AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100,
1023                  AXP806_CLDO1_V_CTRL, AXP806_CLDO1_V_CTRL_MASK,
1024                  AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO1_MASK),
1025         AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin",
1026                         axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
1027                         AXP806_CLDO2_V_CTRL, AXP806_CLDO2_V_CTRL_MASK,
1028                         AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO2_MASK),
1029         AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100,
1030                  AXP806_CLDO3_V_CTRL, AXP806_CLDO3_V_CTRL_MASK,
1031                  AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO3_MASK),
1032         AXP_DESC_SW(AXP806, SW, "sw", "swin",
1033                     AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_SW_MASK),
1034 };
1035
1036 static const struct linear_range axp809_dcdc4_ranges[] = {
1037         REGULATOR_LINEAR_RANGE(600000,
1038                                AXP809_DCDC4_600mV_START,
1039                                AXP809_DCDC4_600mV_END,
1040                                20000),
1041         REGULATOR_LINEAR_RANGE(1800000,
1042                                AXP809_DCDC4_1800mV_START,
1043                                AXP809_DCDC4_1800mV_END,
1044                                100000),
1045 };
1046
1047 static const struct regulator_desc axp809_regulators[] = {
1048         AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
1049                  AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
1050                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
1051         AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
1052                  AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
1053                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
1054         AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
1055                  AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
1056                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
1057         AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4",
1058                         axp809_dcdc4_ranges, AXP809_DCDC4_NUM_VOLTAGES,
1059                         AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
1060                         AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
1061         AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
1062                  AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
1063                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
1064         /* secondary switchable output of DCDC1 */
1065         AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL,
1066                     AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
1067         /* LDO regulator internally chained to DCDC5 */
1068         AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
1069                  AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
1070                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
1071         AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
1072                  AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
1073                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
1074         AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
1075                  AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
1076                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
1077         AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
1078                  AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
1079                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ALDO3_MASK),
1080         AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin",
1081                         axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
1082                         AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
1083                         AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
1084         AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
1085                  AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
1086                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
1087         AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
1088                  AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
1089                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
1090         AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
1091                  AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
1092                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
1093         AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
1094                  AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
1095                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
1096         /*
1097          * Note the datasheet only guarantees reliable operation up to
1098          * 3.3V, this needs to be enforced via dts provided constraints
1099          */
1100         AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
1101                     AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
1102                     AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
1103                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
1104         /*
1105          * Note the datasheet only guarantees reliable operation up to
1106          * 3.3V, this needs to be enforced via dts provided constraints
1107          */
1108         AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
1109                     AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
1110                     AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
1111                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
1112         AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800),
1113         AXP_DESC_SW(AXP809, SW, "sw", "swin",
1114                     AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_SW_MASK),
1115 };
1116
1117 static const struct regulator_desc axp813_regulators[] = {
1118         AXP_DESC(AXP813, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
1119                  AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
1120                  AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
1121         AXP_DESC_RANGES(AXP813, DCDC2, "dcdc2", "vin2",
1122                         axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
1123                         AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
1124                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
1125         AXP_DESC_RANGES(AXP813, DCDC3, "dcdc3", "vin3",
1126                         axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
1127                         AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
1128                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
1129         AXP_DESC_RANGES(AXP813, DCDC4, "dcdc4", "vin4",
1130                         axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
1131                         AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
1132                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
1133         AXP_DESC_RANGES(AXP813, DCDC5, "dcdc5", "vin5",
1134                         axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
1135                         AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
1136                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
1137         AXP_DESC_RANGES(AXP813, DCDC6, "dcdc6", "vin6",
1138                         axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
1139                         AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
1140                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
1141         AXP_DESC_RANGES(AXP813, DCDC7, "dcdc7", "vin7",
1142                         axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
1143                         AXP813_DCDC7_V_OUT, AXP813_DCDC7_V_OUT_MASK,
1144                         AXP22X_PWR_OUT_CTRL1, AXP813_PWR_OUT_DCDC7_MASK),
1145         AXP_DESC(AXP813, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
1146                  AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
1147                  AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
1148         AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
1149                  AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
1150                  AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
1151         AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
1152                  AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
1153                  AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
1154         AXP_DESC(AXP813, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
1155                  AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
1156                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
1157         AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin",
1158                         axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
1159                         AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
1160                         AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
1161         AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
1162                  AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
1163                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
1164         AXP_DESC(AXP813, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
1165                  AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
1166                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
1167         AXP_DESC(AXP813, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
1168                  AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
1169                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
1170         AXP_DESC(AXP813, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
1171                  AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
1172                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
1173         AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
1174                  AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
1175                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
1176         /* to do / check ... */
1177         AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
1178                  AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
1179                  AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
1180         AXP_DESC(AXP813, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
1181                  AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
1182                  AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
1183         /*
1184          * TODO: FLDO3 = {DCDC5, FLDOIN} / 2
1185          *
1186          * This means FLDO3 effectively switches supplies at runtime,
1187          * something the regulator subsystem does not support.
1188          */
1189         AXP_DESC_FIXED(AXP813, RTC_LDO, "rtc-ldo", "ips", 1800),
1190         AXP_DESC_IO(AXP813, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
1191                     AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
1192                     AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
1193                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
1194         AXP_DESC_IO(AXP813, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
1195                     AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
1196                     AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
1197                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
1198         AXP_DESC_SW(AXP813, SW, "sw", "swin",
1199                     AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
1200 };
1201
1202 static const struct linear_range axp15060_dcdc234_ranges[] = {
1203         REGULATOR_LINEAR_RANGE(500000,
1204                                AXP15060_DCDC234_500mV_START,
1205                                AXP15060_DCDC234_500mV_END,
1206                                10000),
1207         REGULATOR_LINEAR_RANGE(1220000,
1208                                AXP15060_DCDC234_1220mV_START,
1209                                AXP15060_DCDC234_1220mV_END,
1210                                20000),
1211 };
1212
1213 static const struct linear_range axp15060_dcdc5_ranges[] = {
1214         REGULATOR_LINEAR_RANGE(800000,
1215                                AXP15060_DCDC5_800mV_START,
1216                                AXP15060_DCDC5_800mV_END,
1217                                10000),
1218         REGULATOR_LINEAR_RANGE(1140000,
1219                                AXP15060_DCDC5_1140mV_START,
1220                                AXP15060_DCDC5_1140mV_END,
1221                                20000),
1222 };
1223
1224 static const struct regulator_desc axp15060_regulators[] = {
1225         AXP_DESC(AXP15060, DCDC1, "dcdc1", "vin1", 1500, 3400, 100,
1226                  AXP15060_DCDC1_V_CTRL, AXP15060_DCDC1_V_CTRL_MASK,
1227                  AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC1_MASK),
1228         AXP_DESC_RANGES(AXP15060, DCDC2, "dcdc2", "vin2",
1229                         axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES,
1230                         AXP15060_DCDC2_V_CTRL, AXP15060_DCDC2_V_CTRL_MASK,
1231                         AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC2_MASK),
1232         AXP_DESC_RANGES(AXP15060, DCDC3, "dcdc3", "vin3",
1233                         axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES,
1234                         AXP15060_DCDC3_V_CTRL, AXP15060_DCDC3_V_CTRL_MASK,
1235                         AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC3_MASK),
1236         AXP_DESC_RANGES(AXP15060, DCDC4, "dcdc4", "vin4",
1237                         axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES,
1238                         AXP15060_DCDC4_V_CTRL, AXP15060_DCDC4_V_CTRL_MASK,
1239                         AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC4_MASK),
1240         AXP_DESC_RANGES(AXP15060, DCDC5, "dcdc5", "vin5",
1241                         axp15060_dcdc5_ranges, AXP15060_DCDC5_NUM_VOLTAGES,
1242                         AXP15060_DCDC5_V_CTRL, AXP15060_DCDC5_V_CTRL_MASK,
1243                         AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC5_MASK),
1244         AXP_DESC(AXP15060, DCDC6, "dcdc6", "vin6", 500, 3400, 100,
1245                  AXP15060_DCDC6_V_CTRL, AXP15060_DCDC6_V_CTRL_MASK,
1246                  AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC6_MASK),
1247         AXP_DESC(AXP15060, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
1248                  AXP15060_ALDO1_V_CTRL, AXP15060_ALDO1_V_CTRL_MASK,
1249                  AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO1_MASK),
1250         AXP_DESC(AXP15060, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
1251                  AXP15060_ALDO2_V_CTRL, AXP15060_ALDO2_V_CTRL_MASK,
1252                  AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO2_MASK),
1253         AXP_DESC(AXP15060, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
1254                  AXP15060_ALDO3_V_CTRL, AXP15060_ALDO3_V_CTRL_MASK,
1255                  AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO3_MASK),
1256         AXP_DESC(AXP15060, ALDO4, "aldo4", "aldoin", 700, 3300, 100,
1257                  AXP15060_ALDO4_V_CTRL, AXP15060_ALDO4_V_CTRL_MASK,
1258                  AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO4_MASK),
1259         AXP_DESC(AXP15060, ALDO5, "aldo5", "aldoin", 700, 3300, 100,
1260                  AXP15060_ALDO5_V_CTRL, AXP15060_ALDO5_V_CTRL_MASK,
1261                  AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO5_MASK),
1262         AXP_DESC(AXP15060, BLDO1, "bldo1", "bldoin", 700, 3300, 100,
1263                  AXP15060_BLDO1_V_CTRL, AXP15060_BLDO1_V_CTRL_MASK,
1264                  AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO1_MASK),
1265         AXP_DESC(AXP15060, BLDO2, "bldo2", "bldoin", 700, 3300, 100,
1266                  AXP15060_BLDO2_V_CTRL, AXP15060_BLDO2_V_CTRL_MASK,
1267                  AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO2_MASK),
1268         AXP_DESC(AXP15060, BLDO3, "bldo3", "bldoin", 700, 3300, 100,
1269                  AXP15060_BLDO3_V_CTRL, AXP15060_BLDO3_V_CTRL_MASK,
1270                  AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO3_MASK),
1271         AXP_DESC(AXP15060, BLDO4, "bldo4", "bldoin", 700, 3300, 100,
1272                  AXP15060_BLDO4_V_CTRL, AXP15060_BLDO4_V_CTRL_MASK,
1273                  AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_BLDO4_MASK),
1274         AXP_DESC(AXP15060, BLDO5, "bldo5", "bldoin", 700, 3300, 100,
1275                  AXP15060_BLDO5_V_CTRL, AXP15060_BLDO5_V_CTRL_MASK,
1276                  AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_BLDO5_MASK),
1277         AXP_DESC(AXP15060, CLDO1, "cldo1", "cldoin", 700, 3300, 100,
1278                  AXP15060_CLDO1_V_CTRL, AXP15060_CLDO1_V_CTRL_MASK,
1279                  AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO1_MASK),
1280         AXP_DESC(AXP15060, CLDO2, "cldo2", "cldoin", 700, 3300, 100,
1281                  AXP15060_CLDO2_V_CTRL, AXP15060_CLDO2_V_CTRL_MASK,
1282                  AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO2_MASK),
1283         AXP_DESC(AXP15060, CLDO3, "cldo3", "cldoin", 700, 3300, 100,
1284                  AXP15060_CLDO3_V_CTRL, AXP15060_CLDO3_V_CTRL_MASK,
1285                  AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO3_MASK),
1286         AXP_DESC(AXP15060, CLDO4, "cldo4", "cldoin", 700, 4200, 100,
1287                  AXP15060_CLDO4_V_CTRL, AXP15060_CLDO4_V_CTRL_MASK,
1288                  AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO4_MASK),
1289         /* Supply comes from DCDC5 */
1290         AXP_DESC(AXP15060, CPUSLDO, "cpusldo", NULL, 700, 1400, 50,
1291                  AXP15060_CPUSLDO_V_CTRL, AXP15060_CPUSLDO_V_CTRL_MASK,
1292                  AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CPUSLDO_MASK),
1293         /* Supply comes from DCDC1 */
1294         AXP_DESC_SW(AXP15060, SW, "sw", NULL,
1295                     AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_SW_MASK),
1296         /* Supply comes from ALDO1 */
1297         AXP_DESC_FIXED(AXP15060, RTC_LDO, "rtc-ldo", NULL, 1800),
1298 };
1299
1300 static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
1301 {
1302         struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
1303         unsigned int reg = AXP20X_DCDC_FREQ;
1304         u32 min, max, def, step;
1305
1306         switch (axp20x->variant) {
1307         case AXP202_ID:
1308         case AXP209_ID:
1309                 min = 750;
1310                 max = 1875;
1311                 def = 1500;
1312                 step = 75;
1313                 break;
1314         case AXP803_ID:
1315         case AXP813_ID:
1316                 /*
1317                  * AXP803/AXP813 DCDC work frequency setting has the same
1318                  * range and step as AXP22X, but at a different register.
1319                  * (See include/linux/mfd/axp20x.h)
1320                  */
1321                 reg = AXP803_DCDC_FREQ_CTRL;
1322                 fallthrough;    /* to the check below */
1323         case AXP806_ID:
1324                 /*
1325                  * AXP806 also have DCDC work frequency setting register at a
1326                  * different position.
1327                  */
1328                 if (axp20x->variant == AXP806_ID)
1329                         reg = AXP806_DCDC_FREQ_CTRL;
1330                 fallthrough;
1331         case AXP221_ID:
1332         case AXP223_ID:
1333         case AXP809_ID:
1334                 min = 1800;
1335                 max = 4050;
1336                 def = 3000;
1337                 step = 150;
1338                 break;
1339         case AXP313A_ID:
1340         case AXP717_ID:
1341         case AXP15060_ID:
1342                 /* The DCDC PWM frequency seems to be fixed to 3 MHz. */
1343                 if (dcdcfreq != 0) {
1344                         dev_err(&pdev->dev,
1345                                 "DCDC frequency on this PMIC is fixed to 3 MHz.\n");
1346                         return -EINVAL;
1347                 }
1348
1349                 return 0;
1350         default:
1351                 dev_err(&pdev->dev,
1352                         "Setting DCDC frequency for unsupported AXP variant\n");
1353                 return -EINVAL;
1354         }
1355
1356         if (dcdcfreq == 0)
1357                 dcdcfreq = def;
1358
1359         if (dcdcfreq < min) {
1360                 dcdcfreq = min;
1361                 dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n",
1362                          min);
1363         }
1364
1365         if (dcdcfreq > max) {
1366                 dcdcfreq = max;
1367                 dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n",
1368                          max);
1369         }
1370
1371         dcdcfreq = (dcdcfreq - min) / step;
1372
1373         return regmap_update_bits(axp20x->regmap, reg,
1374                                   AXP20X_FREQ_DCDC_MASK, dcdcfreq);
1375 }
1376
1377 static int axp20x_regulator_parse_dt(struct platform_device *pdev)
1378 {
1379         struct device_node *np, *regulators;
1380         int ret = 0;
1381         u32 dcdcfreq = 0;
1382
1383         np = of_node_get(pdev->dev.parent->of_node);
1384         if (!np)
1385                 return 0;
1386
1387         regulators = of_get_child_by_name(np, "regulators");
1388         if (!regulators) {
1389                 dev_warn(&pdev->dev, "regulators node not found\n");
1390         } else {
1391                 of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq);
1392                 ret = axp20x_set_dcdc_freq(pdev, dcdcfreq);
1393                 if (ret < 0) {
1394                         dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret);
1395                 }
1396                 of_node_put(regulators);
1397         }
1398
1399         of_node_put(np);
1400         return ret;
1401 }
1402
1403 static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode)
1404 {
1405         struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
1406         unsigned int reg = AXP20X_DCDC_MODE;
1407         unsigned int mask;
1408
1409         switch (axp20x->variant) {
1410         case AXP202_ID:
1411         case AXP209_ID:
1412                 if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3))
1413                         return -EINVAL;
1414
1415                 mask = AXP20X_WORKMODE_DCDC2_MASK;
1416                 if (id == AXP20X_DCDC3)
1417                         mask = AXP20X_WORKMODE_DCDC3_MASK;
1418
1419                 workmode <<= ffs(mask) - 1;
1420                 break;
1421
1422         case AXP806_ID:
1423                 /*
1424                  * AXP806 DCDC regulator IDs have the same range as AXP22X.
1425                  * (See include/linux/mfd/axp20x.h)
1426                  */
1427                 reg = AXP806_DCDC_MODE_CTRL2;
1428                 fallthrough;    /* to the check below */
1429         case AXP221_ID:
1430         case AXP223_ID:
1431         case AXP809_ID:
1432                 if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
1433                         return -EINVAL;
1434
1435                 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1);
1436                 workmode <<= id - AXP22X_DCDC1;
1437                 break;
1438
1439         case AXP803_ID:
1440                 if (id < AXP803_DCDC1 || id > AXP803_DCDC6)
1441                         return -EINVAL;
1442
1443                 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP803_DCDC1);
1444                 workmode <<= id - AXP803_DCDC1;
1445                 break;
1446
1447         case AXP813_ID:
1448                 if (id < AXP813_DCDC1 || id > AXP813_DCDC7)
1449                         return -EINVAL;
1450
1451                 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP813_DCDC1);
1452                 workmode <<= id - AXP813_DCDC1;
1453                 break;
1454
1455         case AXP15060_ID:
1456                 reg = AXP15060_DCDC_MODE_CTRL2;
1457                 if (id < AXP15060_DCDC1 || id > AXP15060_DCDC6)
1458                         return -EINVAL;
1459
1460                 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP15060_DCDC1);
1461                 workmode <<= id - AXP15060_DCDC1;
1462                 break;
1463
1464         default:
1465                 /* should not happen */
1466                 WARN_ON(1);
1467                 return -EINVAL;
1468         }
1469
1470         return regmap_update_bits(rdev->regmap, reg, mask, workmode);
1471 }
1472
1473 /*
1474  * This function checks whether a regulator is part of a poly-phase
1475  * output setup based on the registers settings. Returns true if it is.
1476  */
1477 static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id)
1478 {
1479         u32 reg = 0;
1480
1481         /*
1482          * Currently in our supported AXP variants, only AXP803, AXP806,
1483          * AXP813 and AXP15060 have polyphase regulators.
1484          */
1485         switch (axp20x->variant) {
1486         case AXP803_ID:
1487         case AXP813_ID:
1488                 regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, &reg);
1489
1490                 switch (id) {
1491                 case AXP803_DCDC3:
1492                         return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL);
1493                 case AXP803_DCDC6:
1494                         return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL);
1495                 }
1496                 break;
1497
1498         case AXP806_ID:
1499                 regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, &reg);
1500
1501                 switch (id) {
1502                 case AXP806_DCDCB:
1503                         return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1504                                 AXP806_DCDCAB_POLYPHASE_DUAL) ||
1505                                 ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1506                                 AXP806_DCDCABC_POLYPHASE_TRI));
1507                 case AXP806_DCDCC:
1508                         return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1509                                 AXP806_DCDCABC_POLYPHASE_TRI);
1510                 case AXP806_DCDCE:
1511                         return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL);
1512                 }
1513                 break;
1514
1515         case AXP15060_ID:
1516                 regmap_read(axp20x->regmap, AXP15060_DCDC_MODE_CTRL1, &reg);
1517
1518                 switch (id) {
1519                 case AXP15060_DCDC3:
1520                         return !!(reg & AXP15060_DCDC23_POLYPHASE_DUAL_MASK);
1521                 case AXP15060_DCDC6:
1522                         return !!(reg & AXP15060_DCDC46_POLYPHASE_DUAL_MASK);
1523                 }
1524                 break;
1525
1526         default:
1527                 return false;
1528         }
1529
1530         return false;
1531 }
1532
1533 static int axp20x_regulator_probe(struct platform_device *pdev)
1534 {
1535         struct regulator_dev *rdev;
1536         struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
1537         const struct regulator_desc *regulators;
1538         struct regulator_config config = {
1539                 .dev = pdev->dev.parent,
1540                 .regmap = axp20x->regmap,
1541                 .driver_data = axp20x,
1542         };
1543         int ret, i, nregulators;
1544         u32 workmode;
1545         const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name;
1546         const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name;
1547         const char *aldo1_name = axp15060_regulators[AXP15060_ALDO1].name;
1548         bool drivevbus = false;
1549
1550         switch (axp20x->variant) {
1551         case AXP202_ID:
1552         case AXP209_ID:
1553                 regulators = axp20x_regulators;
1554                 nregulators = AXP20X_REG_ID_MAX;
1555                 break;
1556         case AXP221_ID:
1557         case AXP223_ID:
1558                 regulators = axp22x_regulators;
1559                 nregulators = AXP22X_REG_ID_MAX;
1560                 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1561                                                   "x-powers,drive-vbus-en");
1562                 break;
1563         case AXP313A_ID:
1564                 regulators = axp313a_regulators;
1565                 nregulators = AXP313A_REG_ID_MAX;
1566                 break;
1567         case AXP717_ID:
1568                 regulators = axp717_regulators;
1569                 nregulators = AXP717_REG_ID_MAX;
1570                 break;
1571         case AXP803_ID:
1572                 regulators = axp803_regulators;
1573                 nregulators = AXP803_REG_ID_MAX;
1574                 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1575                                                   "x-powers,drive-vbus-en");
1576                 break;
1577         case AXP806_ID:
1578                 regulators = axp806_regulators;
1579                 nregulators = AXP806_REG_ID_MAX;
1580                 break;
1581         case AXP809_ID:
1582                 regulators = axp809_regulators;
1583                 nregulators = AXP809_REG_ID_MAX;
1584                 break;
1585         case AXP813_ID:
1586                 regulators = axp813_regulators;
1587                 nregulators = AXP813_REG_ID_MAX;
1588                 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1589                                                   "x-powers,drive-vbus-en");
1590                 break;
1591         case AXP15060_ID:
1592                 regulators = axp15060_regulators;
1593                 nregulators = AXP15060_REG_ID_MAX;
1594                 break;
1595         default:
1596                 dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n",
1597                         axp20x->variant);
1598                 return -EINVAL;
1599         }
1600
1601         /* This only sets the dcdc freq. Ignore any errors */
1602         axp20x_regulator_parse_dt(pdev);
1603
1604         for (i = 0; i < nregulators; i++) {
1605                 const struct regulator_desc *desc = &regulators[i];
1606                 struct regulator_desc *new_desc;
1607
1608                 /*
1609                  * If this regulator is a slave in a poly-phase setup,
1610                  * skip it, as its controls are bound to the master
1611                  * regulator and won't work.
1612                  */
1613                 if (axp20x_is_polyphase_slave(axp20x, i))
1614                         continue;
1615
1616                 /* Support for AXP813's FLDO3 is not implemented */
1617                 if (axp20x->variant == AXP813_ID && i == AXP813_FLDO3)
1618                         continue;
1619
1620                 /*
1621                  * Regulators DC1SW, DC5LDO and RTCLDO on AXP15060 are
1622                  * connected internally, so we have to handle their supply
1623                  * names separately.
1624                  *
1625                  * We always register the regulators in proper sequence,
1626                  * so the supply names are correctly read. See the last
1627                  * part of this loop to see where we save the DT defined
1628                  * name.
1629                  */
1630                 if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) ||
1631                     (regulators == axp803_regulators && i == AXP803_DC1SW) ||
1632                     (regulators == axp809_regulators && i == AXP809_DC1SW) ||
1633                     (regulators == axp15060_regulators && i == AXP15060_SW)) {
1634                         new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
1635                                                 GFP_KERNEL);
1636                         if (!new_desc)
1637                                 return -ENOMEM;
1638
1639                         *new_desc = regulators[i];
1640                         new_desc->supply_name = dcdc1_name;
1641                         desc = new_desc;
1642                 }
1643
1644                 if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) ||
1645                     (regulators == axp809_regulators && i == AXP809_DC5LDO) ||
1646                     (regulators == axp15060_regulators && i == AXP15060_CPUSLDO)) {
1647                         new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
1648                                                 GFP_KERNEL);
1649                         if (!new_desc)
1650                                 return -ENOMEM;
1651
1652                         *new_desc = regulators[i];
1653                         new_desc->supply_name = dcdc5_name;
1654                         desc = new_desc;
1655                 }
1656
1657
1658                 if (regulators == axp15060_regulators && i == AXP15060_RTC_LDO) {
1659                         new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
1660                                                 GFP_KERNEL);
1661                         if (!new_desc)
1662                                 return -ENOMEM;
1663
1664                         *new_desc = regulators[i];
1665                         new_desc->supply_name = aldo1_name;
1666                         desc = new_desc;
1667                 }
1668
1669                 rdev = devm_regulator_register(&pdev->dev, desc, &config);
1670                 if (IS_ERR(rdev)) {
1671                         dev_err(&pdev->dev, "Failed to register %s\n",
1672                                 regulators[i].name);
1673
1674                         return PTR_ERR(rdev);
1675                 }
1676
1677                 ret = of_property_read_u32(rdev->dev.of_node,
1678                                            "x-powers,dcdc-workmode",
1679                                            &workmode);
1680                 if (!ret) {
1681                         if (axp20x_set_dcdc_workmode(rdev, i, workmode))
1682                                 dev_err(&pdev->dev, "Failed to set workmode on %s\n",
1683                                         rdev->desc->name);
1684                 }
1685
1686                 /*
1687                  * Save AXP22X DCDC1 / DCDC5 / AXP15060 ALDO1 regulator names for later.
1688                  */
1689                 if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) ||
1690                     (regulators == axp809_regulators && i == AXP809_DCDC1) ||
1691                     (regulators == axp15060_regulators && i == AXP15060_DCDC1))
1692                         of_property_read_string(rdev->dev.of_node,
1693                                                 "regulator-name",
1694                                                 &dcdc1_name);
1695
1696                 if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) ||
1697                     (regulators == axp809_regulators && i == AXP809_DCDC5) ||
1698                     (regulators == axp15060_regulators && i == AXP15060_DCDC5))
1699                         of_property_read_string(rdev->dev.of_node,
1700                                                 "regulator-name",
1701                                                 &dcdc5_name);
1702
1703                 if (regulators == axp15060_regulators && i == AXP15060_ALDO1)
1704                         of_property_read_string(rdev->dev.of_node,
1705                                                 "regulator-name",
1706                                                 &aldo1_name);
1707         }
1708
1709         if (drivevbus) {
1710                 /* Change N_VBUSEN sense pin to DRIVEVBUS output pin */
1711                 regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
1712                                    AXP22X_MISC_N_VBUSEN_FUNC, 0);
1713                 rdev = devm_regulator_register(&pdev->dev,
1714                                                &axp22x_drivevbus_regulator,
1715                                                &config);
1716                 if (IS_ERR(rdev)) {
1717                         dev_err(&pdev->dev, "Failed to register drivevbus\n");
1718                         return PTR_ERR(rdev);
1719                 }
1720         }
1721
1722         return 0;
1723 }
1724
1725 static struct platform_driver axp20x_regulator_driver = {
1726         .probe  = axp20x_regulator_probe,
1727         .driver = {
1728                 .name           = "axp20x-regulator",
1729                 .probe_type     = PROBE_PREFER_ASYNCHRONOUS,
1730         },
1731 };
1732
1733 module_platform_driver(axp20x_regulator_driver);
1734
1735 MODULE_LICENSE("GPL v2");
1736 MODULE_AUTHOR("Carlo Caione <[email protected]>");
1737 MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC");
1738 MODULE_ALIAS("platform:axp20x-regulator");