drivers/pinctrl/pinctrl-cy8c95x0.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support
   4  *
   5  * Copyright (C) 2022 9elements GmbH
   6  * Authors: Patrick Rudolph <[email protected]>
   7  *          Naresh Solanki <[email protected]>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/bitmap.h>
  12 #include <linux/cleanup.h>
  13 #include <linux/dmi.h>
  14 #include <linux/gpio/driver.h>
  15 #include <linux/gpio/consumer.h>
  16 #include <linux/i2c.h>
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/mod_devicetable.h>
  20 #include <linux/module.h>
  21 #include <linux/property.h>
  22 #include <linux/regmap.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/seq_file.h>
  25
  26 #include <linux/pinctrl/consumer.h>
  27 #include <linux/pinctrl/pinconf.h>
  28 #include <linux/pinctrl/pinconf-generic.h>
  29 #include <linux/pinctrl/pinctrl.h>
  30 #include <linux/pinctrl/pinmux.h>
  31
  32 /* Fast access registers */
  33 #define CY8C95X0_INPUT          0x00
  34 #define CY8C95X0_OUTPUT         0x08
  35 #define CY8C95X0_INTSTATUS      0x10
  36
  37 #define CY8C95X0_INPUT_(x)      (CY8C95X0_INPUT + (x))
  38 #define CY8C95X0_OUTPUT_(x)     (CY8C95X0_OUTPUT + (x))
  39 #define CY8C95X0_INTSTATUS_(x)  (CY8C95X0_INTSTATUS + (x))
  40
  41 /* Port Select configures the port */
  42 #define CY8C95X0_PORTSEL        0x18
  43 /* Port settings, write PORTSEL first */
  44 #define CY8C95X0_INTMASK        0x19
  45 #define CY8C95X0_PWMSEL         0x1A
  46 #define CY8C95X0_INVERT         0x1B
  47 #define CY8C95X0_DIRECTION      0x1C
  48 /* Drive mode register change state on writing '1' */
  49 #define CY8C95X0_DRV_PU         0x1D
  50 #define CY8C95X0_DRV_PD         0x1E
  51 #define CY8C95X0_DRV_ODH        0x1F
  52 #define CY8C95X0_DRV_ODL        0x20
  53 #define CY8C95X0_DRV_PP_FAST    0x21
  54 #define CY8C95X0_DRV_PP_SLOW    0x22
  55 #define CY8C95X0_DRV_HIZ        0x23
  56 #define CY8C95X0_DEVID          0x2E
  57 #define CY8C95X0_WATCHDOG       0x2F
  58 #define CY8C95X0_COMMAND        0x30
  59
  60 #define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x))
  61
  62 #define MAX_BANK                8
  63 #define BANK_SZ                 8
  64 #define MAX_LINE                (MAX_BANK * BANK_SZ)
  65 #define MUXED_STRIDE            (CY8C95X0_DRV_HIZ - CY8C95X0_INTMASK)
  66 #define CY8C95X0_GPIO_MASK      GENMASK(7, 0)
  67 #define CY8C95X0_VIRTUAL        (CY8C95X0_COMMAND + 1)
  68 #define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) \
  69         (CY8C95X0_VIRTUAL + (x) - CY8C95X0_INTMASK + (p) * MUXED_STRIDE)
  70
  71 static const struct i2c_device_id cy8c95x0_id[] = {
  72         { "cy8c9520", 20, },
  73         { "cy8c9540", 40, },
  74         { "cy8c9560", 60, },
  75         { }
  76 };
  77 MODULE_DEVICE_TABLE(i2c, cy8c95x0_id);
  78
  79 #define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio))
  80
  81 static const struct of_device_id cy8c95x0_dt_ids[] = {
  82         { .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), },
  83         { .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), },
  84         { .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), },
  85         { }
  86 };
  87 MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids);
  88
  89 static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true };
  90
  91 static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = {
  92         { "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
  93         { }
  94 };
  95
  96 static int cy8c95x0_acpi_get_irq(struct device *dev)
  97 {
  98         int ret;
  99
 100         ret = devm_acpi_dev_add_driver_gpios(dev, cy8c95x0_acpi_irq_gpios);
 101         if (ret)
 102                 dev_warn(dev, "can't add GPIO ACPI mapping\n");
 103
 104         ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq", 0);
 105         if (ret < 0)
 106                 return ret;
 107
 108         dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
 109         return ret;
 110 }
 111
 112 static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = {
 113         {
 114                 /*
 115                  * On Intel Galileo Gen 1 board the IRQ pin is provided
 116                  * as an absolute number instead of being relative.
 117                  * Since first controller (gpio-sch.c) and second
 118                  * (gpio-dwapb.c) are at the fixed bases, we may safely
 119                  * refer to the number in the global space to get an IRQ
 120                  * out of it.
 121                  */
 122                 .matches = {
 123                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
 124                 },
 125         },
 126         {}
 127 };
 128
 129 /**
 130  * struct cy8c95x0_pinctrl - driver data
 131  * @regmap:         Device's regmap. Only direct access registers.
 132  * @irq_lock:       IRQ bus lock
 133  * @i2c_lock:       Mutex to hold while using the regmap
 134  * @irq_mask:       I/O bits affected by interrupts
 135  * @irq_trig_raise: I/O bits affected by raising voltage level
 136  * @irq_trig_fall:  I/O bits affected by falling voltage level
 137  * @irq_trig_low:   I/O bits affected by a low voltage level
 138  * @irq_trig_high:  I/O bits affected by a high voltage level
 139  * @push_pull:      I/O bits configured as push pull driver
 140  * @shiftmask:      Mask used to compensate for Gport2 width
 141  * @nport:          Number of Gports in this chip
 142  * @gpio_chip:      gpiolib chip
 143  * @driver_data:    private driver data
 144  * @regulator:      Pointer to the regulator for the IC
 145  * @dev:            struct device
 146  * @pctldev:        pin controller device
 147  * @pinctrl_desc:   pin controller description
 148  * @name:           Chip controller name
 149  * @tpin:           Total number of pins
 150  * @gpio_reset:     GPIO line handler that can reset the IC
 151  */
 152 struct cy8c95x0_pinctrl {
 153         struct regmap *regmap;
 154         struct mutex irq_lock;
 155         struct mutex i2c_lock;
 156         DECLARE_BITMAP(irq_mask, MAX_LINE);
 157         DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
 158         DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
 159         DECLARE_BITMAP(irq_trig_low, MAX_LINE);
 160         DECLARE_BITMAP(irq_trig_high, MAX_LINE);
 161         DECLARE_BITMAP(push_pull, MAX_LINE);
 162         DECLARE_BITMAP(shiftmask, MAX_LINE);
 163         int nport;
 164         struct gpio_chip gpio_chip;
 165         unsigned long driver_data;
 166         struct regulator *regulator;
 167         struct device *dev;
 168         struct pinctrl_dev *pctldev;
 169         struct pinctrl_desc pinctrl_desc;
 170         char name[32];
 171         unsigned int tpin;
 172         struct gpio_desc *gpio_reset;
 173 };
 174
 175 static const struct pinctrl_pin_desc cy8c9560_pins[] = {
 176         PINCTRL_PIN(0, "gp00"),
 177         PINCTRL_PIN(1, "gp01"),
 178         PINCTRL_PIN(2, "gp02"),
 179         PINCTRL_PIN(3, "gp03"),
 180         PINCTRL_PIN(4, "gp04"),
 181         PINCTRL_PIN(5, "gp05"),
 182         PINCTRL_PIN(6, "gp06"),
 183         PINCTRL_PIN(7, "gp07"),
 184
 185         PINCTRL_PIN(8, "gp10"),
 186         PINCTRL_PIN(9, "gp11"),
 187         PINCTRL_PIN(10, "gp12"),
 188         PINCTRL_PIN(11, "gp13"),
 189         PINCTRL_PIN(12, "gp14"),
 190         PINCTRL_PIN(13, "gp15"),
 191         PINCTRL_PIN(14, "gp16"),
 192         PINCTRL_PIN(15, "gp17"),
 193
 194         PINCTRL_PIN(16, "gp20"),
 195         PINCTRL_PIN(17, "gp21"),
 196         PINCTRL_PIN(18, "gp22"),
 197         PINCTRL_PIN(19, "gp23"),
 198
 199         PINCTRL_PIN(20, "gp30"),
 200         PINCTRL_PIN(21, "gp31"),
 201         PINCTRL_PIN(22, "gp32"),
 202         PINCTRL_PIN(23, "gp33"),
 203         PINCTRL_PIN(24, "gp34"),
 204         PINCTRL_PIN(25, "gp35"),
 205         PINCTRL_PIN(26, "gp36"),
 206         PINCTRL_PIN(27, "gp37"),
 207
 208         PINCTRL_PIN(28, "gp40"),
 209         PINCTRL_PIN(29, "gp41"),
 210         PINCTRL_PIN(30, "gp42"),
 211         PINCTRL_PIN(31, "gp43"),
 212         PINCTRL_PIN(32, "gp44"),
 213         PINCTRL_PIN(33, "gp45"),
 214         PINCTRL_PIN(34, "gp46"),
 215         PINCTRL_PIN(35, "gp47"),
 216
 217         PINCTRL_PIN(36, "gp50"),
 218         PINCTRL_PIN(37, "gp51"),
 219         PINCTRL_PIN(38, "gp52"),
 220         PINCTRL_PIN(39, "gp53"),
 221         PINCTRL_PIN(40, "gp54"),
 222         PINCTRL_PIN(41, "gp55"),
 223         PINCTRL_PIN(42, "gp56"),
 224         PINCTRL_PIN(43, "gp57"),
 225
 226         PINCTRL_PIN(44, "gp60"),
 227         PINCTRL_PIN(45, "gp61"),
 228         PINCTRL_PIN(46, "gp62"),
 229         PINCTRL_PIN(47, "gp63"),
 230         PINCTRL_PIN(48, "gp64"),
 231         PINCTRL_PIN(49, "gp65"),
 232         PINCTRL_PIN(50, "gp66"),
 233         PINCTRL_PIN(51, "gp67"),
 234
 235         PINCTRL_PIN(52, "gp70"),
 236         PINCTRL_PIN(53, "gp71"),
 237         PINCTRL_PIN(54, "gp72"),
 238         PINCTRL_PIN(55, "gp73"),
 239         PINCTRL_PIN(56, "gp74"),
 240         PINCTRL_PIN(57, "gp75"),
 241         PINCTRL_PIN(58, "gp76"),
 242         PINCTRL_PIN(59, "gp77"),
 243 };
 244
 245 static const char * const cy8c95x0_groups[] = {
 246         "gp00",
 247         "gp01",
 248         "gp02",
 249         "gp03",
 250         "gp04",
 251         "gp05",
 252         "gp06",
 253         "gp07",
 254
 255         "gp10",
 256         "gp11",
 257         "gp12",
 258         "gp13",
 259         "gp14",
 260         "gp15",
 261         "gp16",
 262         "gp17",
 263
 264         "gp20",
 265         "gp21",
 266         "gp22",
 267         "gp23",
 268
 269         "gp30",
 270         "gp31",
 271         "gp32",
 272         "gp33",
 273         "gp34",
 274         "gp35",
 275         "gp36",
 276         "gp37",
 277
 278         "gp40",
 279         "gp41",
 280         "gp42",
 281         "gp43",
 282         "gp44",
 283         "gp45",
 284         "gp46",
 285         "gp47",
 286
 287         "gp50",
 288         "gp51",
 289         "gp52",
 290         "gp53",
 291         "gp54",
 292         "gp55",
 293         "gp56",
 294         "gp57",
 295
 296         "gp60",
 297         "gp61",
 298         "gp62",
 299         "gp63",
 300         "gp64",
 301         "gp65",
 302         "gp66",
 303         "gp67",
 304
 305         "gp70",
 306         "gp71",
 307         "gp72",
 308         "gp73",
 309         "gp74",
 310         "gp75",
 311         "gp76",
 312         "gp77",
 313 };
 314
 315 static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip,
 316                                      unsigned int pin, bool input);
 317
 318 static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin)
 319 {
 320         /* Account for GPORT2 which only has 4 bits */
 321         return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ;
 322 }
 323
 324 static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin)
 325 {
 326         /* Account for GPORT2 which only has 4 bits */
 327         return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ);
 328 }
 329
 330 static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)
 331 {
 332         if (reg >= CY8C95X0_VIRTUAL)
 333                 return true;
 334
 335         switch (reg) {
 336         case 0x24 ... 0x27:
 337                 return false;
 338         default:
 339                 return true;
 340         }
 341 }
 342
 343 static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg)
 344 {
 345         if (reg >= CY8C95X0_VIRTUAL)
 346                 return true;
 347
 348         switch (reg) {
 349         case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
 350                 return false;
 351         case CY8C95X0_DEVID:
 352                 return false;
 353         case 0x24 ... 0x27:
 354                 return false;
 355         default:
 356                 return true;
 357         }
 358 }
 359
 360 static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg)
 361 {
 362         switch (reg) {
 363         case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
 364         case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
 365         case CY8C95X0_INTMASK:
 366         case CY8C95X0_INVERT:
 367         case CY8C95X0_PWMSEL:
 368         case CY8C95X0_DIRECTION:
 369         case CY8C95X0_DRV_PU:
 370         case CY8C95X0_DRV_PD:
 371         case CY8C95X0_DRV_ODH:
 372         case CY8C95X0_DRV_ODL:
 373         case CY8C95X0_DRV_PP_FAST:
 374         case CY8C95X0_DRV_PP_SLOW:
 375         case CY8C95X0_DRV_HIZ:
 376                 return true;
 377         default:
 378                 return false;
 379         }
 380 }
 381
 382 static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg)
 383 {
 384         switch (reg) {
 385         case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
 386                 return true;
 387         default:
 388                 return false;
 389         }
 390 }
 391
 392 static bool cy8c95x0_muxed_register(unsigned int reg)
 393 {
 394         switch (reg) {
 395         case CY8C95X0_INTMASK:
 396         case CY8C95X0_PWMSEL:
 397         case CY8C95X0_INVERT:
 398         case CY8C95X0_DIRECTION:
 399         case CY8C95X0_DRV_PU:
 400         case CY8C95X0_DRV_PD:
 401         case CY8C95X0_DRV_ODH:
 402         case CY8C95X0_DRV_ODL:
 403         case CY8C95X0_DRV_PP_FAST:
 404         case CY8C95X0_DRV_PP_SLOW:
 405         case CY8C95X0_DRV_HIZ:
 406                 return true;
 407         default:
 408                 return false;
 409         }
 410 }
 411
 412 static bool cy8c95x0_wc_register(unsigned int reg)
 413 {
 414         switch (reg) {
 415         case CY8C95X0_DRV_PU:
 416         case CY8C95X0_DRV_PD:
 417         case CY8C95X0_DRV_ODH:
 418         case CY8C95X0_DRV_ODL:
 419         case CY8C95X0_DRV_PP_FAST:
 420         case CY8C95X0_DRV_PP_SLOW:
 421         case CY8C95X0_DRV_HIZ:
 422                 return true;
 423         default:
 424                 return false;
 425         }
 426 }
 427
 428 static bool cy8c95x0_quick_path_register(unsigned int reg)
 429 {
 430         switch (reg) {
 431         case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
 432         case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
 433         case CY8C95X0_OUTPUT_(0) ... CY8C95X0_OUTPUT_(7):
 434                 return true;
 435         default:
 436                 return false;
 437         }
 438 }
 439
 440 static const struct regmap_range_cfg cy8c95x0_ranges[] = {
 441         {
 442                 .range_min = CY8C95X0_VIRTUAL,
 443                 .range_max = 0,         /* Updated at runtime */
 444                 .selector_reg = CY8C95X0_PORTSEL,
 445                 .selector_mask = 0x07,
 446                 .selector_shift = 0x0,
 447                 .window_start = CY8C95X0_INTMASK,
 448                 .window_len = MUXED_STRIDE,
 449         }
 450 };
 451
 452 static const struct regmap_config cy8c9520_i2c_regmap = {
 453         .reg_bits = 8,
 454         .val_bits = 8,
 455
 456         .readable_reg = cy8c95x0_readable_register,
 457         .writeable_reg = cy8c95x0_writeable_register,
 458         .volatile_reg = cy8c95x0_volatile_register,
 459         .precious_reg = cy8c95x0_precious_register,
 460
 461         .cache_type = REGCACHE_MAPLE,
 462         .ranges = NULL,                 /* Updated at runtime */
 463         .num_ranges = 1,
 464         .max_register = 0,              /* Updated at runtime */
 465         .num_reg_defaults_raw = 0,      /* Updated at runtime */
 466         .use_single_read = true,        /* Workaround for regcache bug */
 467         .disable_locking = true,
 468 };
 469
 470 static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip,
 471                                                    unsigned int reg,
 472                                                    unsigned int port,
 473                                                    unsigned int mask,
 474                                                    unsigned int val,
 475                                                    bool *change, bool async,
 476                                                    bool force)
 477 {
 478         int ret, off, i;
 479
 480         /* Caller should never modify PORTSEL directly */
 481         if (reg == CY8C95X0_PORTSEL)
 482                 return -EINVAL;
 483
 484         /* Registers behind the PORTSEL mux have their own range in regmap */
 485         if (cy8c95x0_muxed_register(reg)) {
 486                 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port);
 487         } else {
 488                 /* Quick path direct access registers honor the port argument */
 489                 if (cy8c95x0_quick_path_register(reg))
 490                         off = reg + port;
 491                 else
 492                         off = reg;
 493         }
 494         guard(mutex)(&chip->i2c_lock);
 495
 496         ret = regmap_update_bits_base(chip->regmap, off, mask, val, change, async, force);
 497         if (ret < 0)
 498                 return ret;
 499
 500         /* Mimic what hardware does and update the cache when a WC bit is written.
 501          * Allows to mark the registers as non-volatile and reduces I/O cycles.
 502          */
 503         if (cy8c95x0_wc_register(reg) && (mask & val)) {
 504                 /* Writing a 1 clears set bits in the other drive mode registers */
 505                 regcache_cache_only(chip->regmap, true);
 506                 for (i = CY8C95X0_DRV_PU; i <= CY8C95X0_DRV_HIZ; i++) {
 507                         if (i == reg)
 508                                 continue;
 509
 510                         off = CY8C95X0_MUX_REGMAP_TO_OFFSET(i, port);
 511                         regmap_clear_bits(chip->regmap, off, mask & val);
 512                 }
 513                 regcache_cache_only(chip->regmap, false);
 514         }
 515
 516         return ret;
 517 }
 518
 519 /**
 520  * cy8c95x0_regmap_write_bits() - writes a register using the regmap cache
 521  * @chip: The pinctrl to work on
 522  * @reg: The register to write to. Can be direct access or muxed register.
 523  *       MUST NOT be the PORTSEL register.
 524  * @port: The port to be used for muxed registers or quick path direct access
 525  *        registers. Otherwise unused.
 526  * @mask: Bitmask to change
 527  * @val: New value for bitmask
 528  *
 529  * This function handles the register writes to the direct access registers and
 530  * the muxed registers while caching all register accesses, internally handling
 531  * the correct state of the PORTSEL register and protecting the access to muxed
 532  * registers.
 533  * The caller must only use this function to change registers behind the PORTSEL mux.
 534  *
 535  * Return: 0 for successful request, else a corresponding error value
 536  */
 537 static int cy8c95x0_regmap_write_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg,
 538                                       unsigned int port, unsigned int mask, unsigned int val)
 539 {
 540         return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, true);
 541 }
 542
 543 /**
 544  * cy8c95x0_regmap_update_bits() - updates a register using the regmap cache
 545  * @chip: The pinctrl to work on
 546  * @reg: The register to write to. Can be direct access or muxed register.
 547  *       MUST NOT be the PORTSEL register.
 548  * @port: The port to be used for muxed registers or quick path direct access
 549  *        registers. Otherwise unused.
 550  * @mask: Bitmask to change
 551  * @val: New value for bitmask
 552  *
 553  * This function handles the register updates to the direct access registers and
 554  * the muxed registers while caching all register accesses, internally handling
 555  * the correct state of the PORTSEL register and protecting the access to muxed
 556  * registers.
 557  * The caller must only use this function to change registers behind the PORTSEL mux.
 558  *
 559  * Return: 0 for successful request, else a corresponding error value
 560  */
 561 static int cy8c95x0_regmap_update_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg,
 562                                        unsigned int port, unsigned int mask, unsigned int val)
 563 {
 564         return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, false);
 565 }
 566
 567 /**
 568  * cy8c95x0_regmap_read() - reads a register using the regmap cache
 569  * @chip: The pinctrl to work on
 570  * @reg: The register to read from. Can be direct access or muxed register.
 571  * @port: The port to be used for muxed registers or quick path direct access
 572  *        registers. Otherwise unused.
 573  * @read_val: Value read from hardware or cache
 574  *
 575  * This function handles the register reads from the direct access registers and
 576  * the muxed registers while caching all register accesses, internally handling
 577  * the correct state of the PORTSEL register and protecting the access to muxed
 578  * registers.
 579  * The caller must only use this function to read registers behind the PORTSEL mux.
 580  *
 581  * Return: 0 for successful request, else a corresponding error value
 582  */
 583 static int cy8c95x0_regmap_read(struct cy8c95x0_pinctrl *chip, unsigned int reg,
 584                                 unsigned int port, unsigned int *read_val)
 585 {
 586         int off, ret;
 587
 588         /* Registers behind the PORTSEL mux have their own range in regmap */
 589         if (cy8c95x0_muxed_register(reg)) {
 590                 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port);
 591         } else {
 592                 /* Quick path direct access registers honor the port argument */
 593                 if (cy8c95x0_quick_path_register(reg))
 594                         off = reg + port;
 595                 else
 596                         off = reg;
 597         }
 598         guard(mutex)(&chip->i2c_lock);
 599
 600         ret = regmap_read(chip->regmap, off, read_val);
 601
 602         return ret;
 603 }
 604
 605 static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
 606                                     unsigned long *val, unsigned long *mask)
 607 {
 608         DECLARE_BITMAP(tmask, MAX_LINE);
 609         DECLARE_BITMAP(tval, MAX_LINE);
 610         int write_val;
 611         int ret = 0;
 612         int i;
 613         u8 bits;
 614
 615         /* Add the 4 bit gap of Gport2 */
 616         bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
 617         bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
 618         bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
 619
 620         bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
 621         bitmap_shift_left(tval, tval, 4, MAX_LINE);
 622         bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
 623
 624         for (i = 0; i < chip->nport; i++) {
 625                 /* Skip over unused banks */
 626                 bits = bitmap_get_value8(tmask, i * BANK_SZ);
 627                 if (!bits)
 628                         continue;
 629
 630                 write_val = bitmap_get_value8(tval, i * BANK_SZ);
 631
 632                 ret = cy8c95x0_regmap_update_bits(chip, reg, i, bits, write_val);
 633                 if (ret < 0)
 634                         goto out;
 635         }
 636 out:
 637
 638         if (ret < 0)
 639                 dev_err(chip->dev, "failed writing register %d, port %d: err %d\n", reg, i, ret);
 640
 641         return ret;
 642 }
 643
 644 static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
 645                                    unsigned long *val, unsigned long *mask)
 646 {
 647         DECLARE_BITMAP(tmask, MAX_LINE);
 648         DECLARE_BITMAP(tval, MAX_LINE);
 649         DECLARE_BITMAP(tmp, MAX_LINE);
 650         int read_val;
 651         int ret = 0;
 652         int i;
 653         u8 bits;
 654
 655         /* Add the 4 bit gap of Gport2 */
 656         bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
 657         bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
 658         bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
 659
 660         bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
 661         bitmap_shift_left(tval, tval, 4, MAX_LINE);
 662         bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
 663
 664         for (i = 0; i < chip->nport; i++) {
 665                 /* Skip over unused banks */
 666                 bits = bitmap_get_value8(tmask, i * BANK_SZ);
 667                 if (!bits)
 668                         continue;
 669
 670                 ret = cy8c95x0_regmap_read(chip, reg, i, &read_val);
 671                 if (ret < 0)
 672                         goto out;
 673
 674                 read_val &= bits;
 675                 read_val |= bitmap_get_value8(tval, i * BANK_SZ) & ~bits;
 676                 bitmap_set_value8(tval, read_val, i * BANK_SZ);
 677         }
 678
 679         /* Fill the 4 bit gap of Gport2 */
 680         bitmap_shift_right(tmp, tval, 4, MAX_LINE);
 681         bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE);
 682
 683 out:
 684         if (ret < 0)
 685                 dev_err(chip->dev, "failed reading register %d, port %d: err %d\n", reg, i, ret);
 686
 687         return ret;
 688 }
 689
 690 static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off)
 691 {
 692         return pinctrl_gpio_direction_input(gc, off);
 693 }
 694
 695 static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc,
 696                                           unsigned int off, int val)
 697 {
 698         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 699         u8 port = cypress_get_port(chip, off);
 700         u8 bit = cypress_get_pin_mask(chip, off);
 701         int ret;
 702
 703         /* Set output level */
 704         ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0);
 705         if (ret)
 706                 return ret;
 707
 708         return pinctrl_gpio_direction_output(gc, off);
 709 }
 710
 711 static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off)
 712 {
 713         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 714         u8 port = cypress_get_port(chip, off);
 715         u8 bit = cypress_get_pin_mask(chip, off);
 716         u32 reg_val;
 717         int ret;
 718
 719         ret = cy8c95x0_regmap_read(chip, CY8C95X0_INPUT, port, &reg_val);
 720         if (ret < 0) {
 721                 /*
 722                  * NOTE:
 723                  * Diagnostic already emitted; that's all we should
 724                  * do unless gpio_*_value_cansleep() calls become different
 725                  * from their nonsleeping siblings (and report faults).
 726                  */
 727                 return 0;
 728         }
 729
 730         return !!(reg_val & bit);
 731 }
 732
 733 static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off,
 734                                     int val)
 735 {
 736         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 737         u8 port = cypress_get_port(chip, off);
 738         u8 bit = cypress_get_pin_mask(chip, off);
 739
 740         cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0);
 741 }
 742
 743 static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off)
 744 {
 745         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 746         u8 port = cypress_get_port(chip, off);
 747         u8 bit = cypress_get_pin_mask(chip, off);
 748         u32 reg_val;
 749         int ret;
 750
 751         ret = cy8c95x0_regmap_read(chip, CY8C95X0_DIRECTION, port, &reg_val);
 752         if (ret < 0)
 753                 goto out;
 754
 755         if (reg_val & bit)
 756                 return GPIO_LINE_DIRECTION_IN;
 757
 758         return GPIO_LINE_DIRECTION_OUT;
 759 out:
 760         return ret;
 761 }
 762
 763 static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip,
 764                                     unsigned int off,
 765                                     unsigned long *config)
 766 {
 767         enum pin_config_param param = pinconf_to_config_param(*config);
 768         u8 port = cypress_get_port(chip, off);
 769         u8 bit = cypress_get_pin_mask(chip, off);
 770         unsigned int reg;
 771         u32 reg_val;
 772         u16 arg = 0;
 773         int ret;
 774
 775         switch (param) {
 776         case PIN_CONFIG_BIAS_PULL_UP:
 777                 reg = CY8C95X0_DRV_PU;
 778                 break;
 779         case PIN_CONFIG_BIAS_PULL_DOWN:
 780                 reg = CY8C95X0_DRV_PD;
 781                 break;
 782         case PIN_CONFIG_BIAS_DISABLE:
 783                 reg = CY8C95X0_DRV_HIZ;
 784                 break;
 785         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 786                 reg = CY8C95X0_DRV_ODL;
 787                 break;
 788         case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 789                 reg = CY8C95X0_DRV_ODH;
 790                 break;
 791         case PIN_CONFIG_DRIVE_PUSH_PULL:
 792                 reg = CY8C95X0_DRV_PP_FAST;
 793                 break;
 794         case PIN_CONFIG_INPUT_ENABLE:
 795                 reg = CY8C95X0_DIRECTION;
 796                 break;
 797         case PIN_CONFIG_MODE_PWM:
 798                 reg = CY8C95X0_PWMSEL;
 799                 break;
 800         case PIN_CONFIG_OUTPUT:
 801                 reg = CY8C95X0_OUTPUT;
 802                 break;
 803         case PIN_CONFIG_OUTPUT_ENABLE:
 804                 reg = CY8C95X0_DIRECTION;
 805                 break;
 806
 807         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 808         case PIN_CONFIG_BIAS_BUS_HOLD:
 809         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 810         case PIN_CONFIG_DRIVE_STRENGTH:
 811         case PIN_CONFIG_DRIVE_STRENGTH_UA:
 812         case PIN_CONFIG_INPUT_DEBOUNCE:
 813         case PIN_CONFIG_INPUT_SCHMITT:
 814         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 815         case PIN_CONFIG_MODE_LOW_POWER:
 816         case PIN_CONFIG_PERSIST_STATE:
 817         case PIN_CONFIG_POWER_SOURCE:
 818         case PIN_CONFIG_SKEW_DELAY:
 819         case PIN_CONFIG_SLEEP_HARDWARE_STATE:
 820         case PIN_CONFIG_SLEW_RATE:
 821         default:
 822                 ret = -ENOTSUPP;
 823                 goto out;
 824         }
 825         /*
 826          * Writing 1 to one of the drive mode registers will automatically
 827          * clear conflicting set bits in the other drive mode registers.
 828          */
 829         ret = cy8c95x0_regmap_read(chip, reg, port, &reg_val);
 830         if (ret < 0)
 831                 goto out;
 832
 833         if (reg_val & bit)
 834                 arg = 1;
 835         if (param == PIN_CONFIG_OUTPUT_ENABLE)
 836                 arg = !arg;
 837
 838         *config = pinconf_to_config_packed(param, (u16)arg);
 839 out:
 840         return ret;
 841 }
 842
 843 static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip,
 844                                     unsigned int off,
 845                                     unsigned long config)
 846 {
 847         u8 port = cypress_get_port(chip, off);
 848         u8 bit = cypress_get_pin_mask(chip, off);
 849         unsigned long param = pinconf_to_config_param(config);
 850         unsigned long arg = pinconf_to_config_argument(config);
 851         unsigned int reg;
 852         int ret;
 853
 854         switch (param) {
 855         case PIN_CONFIG_BIAS_PULL_UP:
 856                 __clear_bit(off, chip->push_pull);
 857                 reg = CY8C95X0_DRV_PU;
 858                 break;
 859         case PIN_CONFIG_BIAS_PULL_DOWN:
 860                 __clear_bit(off, chip->push_pull);
 861                 reg = CY8C95X0_DRV_PD;
 862                 break;
 863         case PIN_CONFIG_BIAS_DISABLE:
 864                 __clear_bit(off, chip->push_pull);
 865                 reg = CY8C95X0_DRV_HIZ;
 866                 break;
 867         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 868                 __clear_bit(off, chip->push_pull);
 869                 reg = CY8C95X0_DRV_ODL;
 870                 break;
 871         case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 872                 __clear_bit(off, chip->push_pull);
 873                 reg = CY8C95X0_DRV_ODH;
 874                 break;
 875         case PIN_CONFIG_DRIVE_PUSH_PULL:
 876                 __set_bit(off, chip->push_pull);
 877                 reg = CY8C95X0_DRV_PP_FAST;
 878                 break;
 879         case PIN_CONFIG_MODE_PWM:
 880                 reg = CY8C95X0_PWMSEL;
 881                 break;
 882         case PIN_CONFIG_OUTPUT_ENABLE:
 883                 ret = cy8c95x0_pinmux_direction(chip, off, !arg);
 884                 goto out;
 885         case PIN_CONFIG_INPUT_ENABLE:
 886                 ret = cy8c95x0_pinmux_direction(chip, off, arg);
 887                 goto out;
 888         default:
 889                 ret = -ENOTSUPP;
 890                 goto out;
 891         }
 892         /*
 893          * Writing 1 to one of the drive mode registers will automatically
 894          * clear conflicting set bits in the other drive mode registers.
 895          */
 896         ret = cy8c95x0_regmap_write_bits(chip, reg, port, bit, bit);
 897 out:
 898         return ret;
 899 }
 900
 901 static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc,
 902                                       unsigned long *mask, unsigned long *bits)
 903 {
 904         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 905
 906         return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask);
 907 }
 908
 909 static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc,
 910                                        unsigned long *mask, unsigned long *bits)
 911 {
 912         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 913
 914         cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask);
 915 }
 916
 917 static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc)
 918 {
 919         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 920         struct device *dev = chip->dev;
 921         int ret;
 922
 923         ret = gpiochip_add_pin_range(gc, dev_name(dev), 0, 0, chip->tpin);
 924         if (ret)
 925                 dev_err(dev, "failed to add GPIO pin range\n");
 926
 927         return ret;
 928 }
 929
 930 static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip)
 931 {
 932         struct gpio_chip *gc = &chip->gpio_chip;
 933
 934         gc->request = gpiochip_generic_request;
 935         gc->free = gpiochip_generic_free;
 936         gc->direction_input  = cy8c95x0_gpio_direction_input;
 937         gc->direction_output = cy8c95x0_gpio_direction_output;
 938         gc->get = cy8c95x0_gpio_get_value;
 939         gc->set = cy8c95x0_gpio_set_value;
 940         gc->get_direction = cy8c95x0_gpio_get_direction;
 941         gc->get_multiple = cy8c95x0_gpio_get_multiple;
 942         gc->set_multiple = cy8c95x0_gpio_set_multiple;
 943         gc->set_config = gpiochip_generic_config;
 944         gc->can_sleep = true;
 945         gc->add_pin_ranges = cy8c95x0_add_pin_ranges;
 946
 947         gc->base = -1;
 948         gc->ngpio = chip->tpin;
 949
 950         gc->parent = chip->dev;
 951         gc->owner = THIS_MODULE;
 952         gc->names = NULL;
 953
 954         gc->label = dev_name(chip->dev);
 955
 956         return devm_gpiochip_add_data(chip->dev, gc, chip);
 957 }
 958
 959 static void cy8c95x0_irq_mask(struct irq_data *d)
 960 {
 961         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 962         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 963         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 964
 965         set_bit(hwirq, chip->irq_mask);
 966         gpiochip_disable_irq(gc, hwirq);
 967 }
 968
 969 static void cy8c95x0_irq_unmask(struct irq_data *d)
 970 {
 971         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 972         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 973         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 974
 975         gpiochip_enable_irq(gc, hwirq);
 976         clear_bit(hwirq, chip->irq_mask);
 977 }
 978
 979 static void cy8c95x0_irq_bus_lock(struct irq_data *d)
 980 {
 981         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 982         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 983
 984         mutex_lock(&chip->irq_lock);
 985 }
 986
 987 static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d)
 988 {
 989         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 990         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 991         DECLARE_BITMAP(ones, MAX_LINE);
 992         DECLARE_BITMAP(irq_mask, MAX_LINE);
 993         DECLARE_BITMAP(reg_direction, MAX_LINE);
 994
 995         bitmap_fill(ones, MAX_LINE);
 996
 997         cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, chip->irq_mask, ones);
 998
 999         /* Switch direction to input if needed */
1000         cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, reg_direction, chip->irq_mask);
1001         bitmap_or(irq_mask, chip->irq_mask, reg_direction, MAX_LINE);
1002         bitmap_complement(irq_mask, irq_mask, MAX_LINE);
1003
1004         /* Look for any newly setup interrupt */
1005         cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, ones, irq_mask);
1006
1007         mutex_unlock(&chip->irq_lock);
1008 }
1009
1010 static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type)
1011 {
1012         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1013         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
1014         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1015         unsigned int trig_type;
1016
1017         switch (type) {
1018         case IRQ_TYPE_EDGE_RISING:
1019         case IRQ_TYPE_EDGE_FALLING:
1020         case IRQ_TYPE_EDGE_BOTH:
1021                 trig_type = type;
1022                 break;
1023         case IRQ_TYPE_LEVEL_HIGH:
1024                 trig_type = IRQ_TYPE_EDGE_RISING;
1025                 break;
1026         case IRQ_TYPE_LEVEL_LOW:
1027                 trig_type = IRQ_TYPE_EDGE_FALLING;
1028                 break;
1029         default:
1030                 dev_err(chip->dev, "irq %d: unsupported type %d\n", d->irq, type);
1031                 return -EINVAL;
1032         }
1033
1034         assign_bit(hwirq, chip->irq_trig_fall, trig_type & IRQ_TYPE_EDGE_FALLING);
1035         assign_bit(hwirq, chip->irq_trig_raise, trig_type & IRQ_TYPE_EDGE_RISING);
1036         assign_bit(hwirq, chip->irq_trig_low, type == IRQ_TYPE_LEVEL_LOW);
1037         assign_bit(hwirq, chip->irq_trig_high, type == IRQ_TYPE_LEVEL_HIGH);
1038
1039         return 0;
1040 }
1041
1042 static void cy8c95x0_irq_shutdown(struct irq_data *d)
1043 {
1044         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1045         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
1046         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1047
1048         clear_bit(hwirq, chip->irq_trig_raise);
1049         clear_bit(hwirq, chip->irq_trig_fall);
1050         clear_bit(hwirq, chip->irq_trig_low);
1051         clear_bit(hwirq, chip->irq_trig_high);
1052 }
1053
1054 static const struct irq_chip cy8c95x0_irqchip = {
1055         .name = "cy8c95x0-irq",
1056         .irq_mask = cy8c95x0_irq_mask,
1057         .irq_unmask = cy8c95x0_irq_unmask,
1058         .irq_bus_lock = cy8c95x0_irq_bus_lock,
1059         .irq_bus_sync_unlock = cy8c95x0_irq_bus_sync_unlock,
1060         .irq_set_type = cy8c95x0_irq_set_type,
1061         .irq_shutdown = cy8c95x0_irq_shutdown,
1062         .flags = IRQCHIP_IMMUTABLE,
1063         GPIOCHIP_IRQ_RESOURCE_HELPERS,
1064 };
1065
1066 static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending)
1067 {
1068         DECLARE_BITMAP(ones, MAX_LINE);
1069         DECLARE_BITMAP(cur_stat, MAX_LINE);
1070         DECLARE_BITMAP(new_stat, MAX_LINE);
1071         DECLARE_BITMAP(trigger, MAX_LINE);
1072
1073         bitmap_fill(ones, MAX_LINE);
1074
1075         /* Read the current interrupt status from the device */
1076         if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INTSTATUS, trigger, ones))
1077                 return false;
1078
1079         /* Check latched inputs */
1080         if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, cur_stat, trigger))
1081                 return false;
1082
1083         /* Apply filter for rising/falling edge selection */
1084         bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise,
1085                        cur_stat, MAX_LINE);
1086
1087         bitmap_and(pending, new_stat, trigger, MAX_LINE);
1088
1089         return !bitmap_empty(pending, MAX_LINE);
1090 }
1091
1092 static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid)
1093 {
1094         struct cy8c95x0_pinctrl *chip = devid;
1095         struct gpio_chip *gc = &chip->gpio_chip;
1096         DECLARE_BITMAP(pending, MAX_LINE);
1097         int nested_irq, level;
1098         bool ret;
1099
1100         ret = cy8c95x0_irq_pending(chip, pending);
1101         if (!ret)
1102                 return IRQ_RETVAL(0);
1103
1104         ret = 0;
1105         for_each_set_bit(level, pending, MAX_LINE) {
1106                 /* Already accounted for 4bit gap in GPort2 */
1107                 nested_irq = irq_find_mapping(gc->irq.domain, level);
1108
1109                 if (unlikely(nested_irq <= 0)) {
1110                         dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
1111                         continue;
1112                 }
1113
1114                 if (test_bit(level, chip->irq_trig_low))
1115                         while (!cy8c95x0_gpio_get_value(gc, level))
1116                                 handle_nested_irq(nested_irq);
1117                 else if (test_bit(level, chip->irq_trig_high))
1118                         while (cy8c95x0_gpio_get_value(gc, level))
1119                                 handle_nested_irq(nested_irq);
1120                 else
1121                         handle_nested_irq(nested_irq);
1122
1123                 ret = 1;
1124         }
1125
1126         return IRQ_RETVAL(ret);
1127 }
1128
1129 static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
1130 {
1131         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1132
1133         return chip->tpin;
1134 }
1135
1136 static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
1137                                                    unsigned int group)
1138 {
1139         return cy8c95x0_groups[group];
1140 }
1141
1142 static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
1143                                            unsigned int group,
1144                                            const unsigned int **pins,
1145                                            unsigned int *num_pins)
1146 {
1147         *pins = &cy8c9560_pins[group].number;
1148         *num_pins = 1;
1149         return 0;
1150 }
1151
1152 static const char *cy8c95x0_get_fname(unsigned int selector)
1153 {
1154         if (selector == 0)
1155                 return "gpio";
1156         else
1157                 return "pwm";
1158 }
1159
1160 static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1161                                   unsigned int pin)
1162 {
1163         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1164         DECLARE_BITMAP(mask, MAX_LINE);
1165         DECLARE_BITMAP(pwm, MAX_LINE);
1166
1167         bitmap_zero(mask, MAX_LINE);
1168         __set_bit(pin, mask);
1169
1170         if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) {
1171                 seq_puts(s, "not available");
1172                 return;
1173         }
1174
1175         seq_printf(s, "MODE:%s", cy8c95x0_get_fname(test_bit(pin, pwm)));
1176 }
1177
1178 static const struct pinctrl_ops cy8c95x0_pinctrl_ops = {
1179         .get_groups_count = cy8c95x0_pinctrl_get_groups_count,
1180         .get_group_name = cy8c95x0_pinctrl_get_group_name,
1181         .get_group_pins = cy8c95x0_pinctrl_get_group_pins,
1182 #ifdef CONFIG_OF
1183         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1184         .dt_free_map = pinconf_generic_dt_free_map,
1185 #endif
1186         .pin_dbg_show = cy8c95x0_pin_dbg_show,
1187 };
1188
1189 static const char *cy8c95x0_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector)
1190 {
1191         return cy8c95x0_get_fname(selector);
1192 }
1193
1194 static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev)
1195 {
1196         return 2;
1197 }
1198
1199 static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector,
1200                                         const char * const **groups,
1201                                         unsigned int * const num_groups)
1202 {
1203         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1204
1205         *groups = cy8c95x0_groups;
1206         *num_groups = chip->tpin;
1207         return 0;
1208 }
1209
1210 static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode)
1211 {
1212         u8 port = cypress_get_port(chip, off);
1213         u8 bit = cypress_get_pin_mask(chip, off);
1214
1215         return cy8c95x0_regmap_write_bits(chip, CY8C95X0_PWMSEL, port, bit, mode ? bit : 0);
1216 }
1217
1218 static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip,
1219                                 unsigned int selector, unsigned int group)
1220 {
1221         u8 port = cypress_get_port(chip, group);
1222         u8 bit = cypress_get_pin_mask(chip, group);
1223         int ret;
1224
1225         ret = cy8c95x0_set_mode(chip, group, selector);
1226         if (ret < 0)
1227                 return ret;
1228
1229         if (selector == 0)
1230                 return 0;
1231
1232         /* Set direction to output & set output to 1 so that PWM can work */
1233         ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, bit);
1234         if (ret < 0)
1235                 return ret;
1236
1237         return cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, bit);
1238 }
1239
1240 static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
1241                             unsigned int group)
1242 {
1243         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1244
1245         return cy8c95x0_pinmux_mode(chip, selector, group);
1246 }
1247
1248 static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev,
1249                                         struct pinctrl_gpio_range *range,
1250                                         unsigned int pin)
1251 {
1252         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1253
1254         return cy8c95x0_set_mode(chip, pin, false);
1255 }
1256
1257 static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip,
1258                                      unsigned int pin, bool input)
1259 {
1260         u8 port = cypress_get_port(chip, pin);
1261         u8 bit = cypress_get_pin_mask(chip, pin);
1262         int ret;
1263
1264         ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, input ? bit : 0);
1265         if (ret)
1266                 return ret;
1267
1268         /*
1269          * Disable driving the pin by forcing it to HighZ. Only setting
1270          * the direction register isn't sufficient in Push-Pull mode.
1271          */
1272         if (input && test_bit(pin, chip->push_pull)) {
1273                 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DRV_HIZ, port, bit, bit);
1274                 if (ret)
1275                         return ret;
1276
1277                 __clear_bit(pin, chip->push_pull);
1278         }
1279
1280         return 0;
1281 }
1282
1283 static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev,
1284                                        struct pinctrl_gpio_range *range,
1285                                        unsigned int pin, bool input)
1286 {
1287         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1288
1289         return cy8c95x0_pinmux_direction(chip, pin, input);
1290 }
1291
1292 static const struct pinmux_ops cy8c95x0_pmxops = {
1293         .get_functions_count = cy8c95x0_get_functions_count,
1294         .get_function_name = cy8c95x0_get_function_name,
1295         .get_function_groups = cy8c95x0_get_function_groups,
1296         .set_mux = cy8c95x0_set_mux,
1297         .gpio_request_enable = cy8c95x0_gpio_request_enable,
1298         .gpio_set_direction = cy8c95x0_gpio_set_direction,
1299         .strict = true,
1300 };
1301
1302 static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1303                                 unsigned long *config)
1304 {
1305         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1306
1307         return cy8c95x0_gpio_get_pincfg(chip, pin, config);
1308 }
1309
1310 static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1311                                 unsigned long *configs, unsigned int num_configs)
1312 {
1313         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1314         int ret = 0;
1315         int i;
1316
1317         for (i = 0; i < num_configs; i++) {
1318                 ret = cy8c95x0_gpio_set_pincfg(chip, pin, configs[i]);
1319                 if (ret)
1320                         return ret;
1321         }
1322
1323         return ret;
1324 }
1325
1326 static const struct pinconf_ops cy8c95x0_pinconf_ops = {
1327         .pin_config_get = cy8c95x0_pinconf_get,
1328         .pin_config_set = cy8c95x0_pinconf_set,
1329         .is_generic = true,
1330 };
1331
1332 static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq)
1333 {
1334         struct gpio_irq_chip *girq = &chip->gpio_chip.irq;
1335         DECLARE_BITMAP(pending_irqs, MAX_LINE);
1336         int ret;
1337
1338         mutex_init(&chip->irq_lock);
1339
1340         bitmap_zero(pending_irqs, MAX_LINE);
1341
1342         /* Read IRQ status register to clear all pending interrupts */
1343         ret = cy8c95x0_irq_pending(chip, pending_irqs);
1344         if (ret) {
1345                 dev_err(chip->dev, "failed to clear irq status register\n");
1346                 return ret;
1347         }
1348
1349         /* Mask all interrupts */
1350         bitmap_fill(chip->irq_mask, MAX_LINE);
1351
1352         gpio_irq_chip_set_chip(girq, &cy8c95x0_irqchip);
1353
1354         /* This will let us handle the parent IRQ in the driver */
1355         girq->parent_handler = NULL;
1356         girq->num_parents = 0;
1357         girq->parents = NULL;
1358         girq->default_type = IRQ_TYPE_NONE;
1359         girq->handler = handle_simple_irq;
1360         girq->threaded = true;
1361
1362         ret = devm_request_threaded_irq(chip->dev, irq,
1363                                         NULL, cy8c95x0_irq_handler,
1364                                         IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_HIGH,
1365                                         dev_name(chip->dev), chip);
1366         if (ret) {
1367                 dev_err(chip->dev, "failed to request irq %d\n", irq);
1368                 return ret;
1369         }
1370         dev_info(chip->dev, "Registered threaded IRQ\n");
1371
1372         return 0;
1373 }
1374
1375 static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip)
1376 {
1377         struct pinctrl_desc *pd = &chip->pinctrl_desc;
1378
1379         pd->pctlops = &cy8c95x0_pinctrl_ops;
1380         pd->confops = &cy8c95x0_pinconf_ops;
1381         pd->pmxops = &cy8c95x0_pmxops;
1382         pd->name = dev_name(chip->dev);
1383         pd->pins = cy8c9560_pins;
1384         pd->npins = chip->tpin;
1385         pd->owner = THIS_MODULE;
1386
1387         chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip);
1388         if (IS_ERR(chip->pctldev))
1389                 return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev),
1390                         "can't register controller\n");
1391
1392         return 0;
1393 }
1394
1395 static int cy8c95x0_detect(struct i2c_client *client,
1396                            struct i2c_board_info *info)
1397 {
1398         struct i2c_adapter *adapter = client->adapter;
1399         int ret;
1400         const char *name;
1401
1402         if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1403                 return -ENODEV;
1404
1405         ret = i2c_smbus_read_byte_data(client, CY8C95X0_DEVID);
1406         if (ret < 0)
1407                 return ret;
1408         switch (ret & GENMASK(7, 4)) {
1409         case 0x20:
1410                 name = cy8c95x0_id[0].name;
1411                 break;
1412         case 0x40:
1413                 name = cy8c95x0_id[1].name;
1414                 break;
1415         case 0x60:
1416                 name = cy8c95x0_id[2].name;
1417                 break;
1418         default:
1419                 return -ENODEV;
1420         }
1421
1422         dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr);
1423         strscpy(info->type, name, I2C_NAME_SIZE);
1424
1425         return 0;
1426 }
1427
1428 static int cy8c95x0_probe(struct i2c_client *client)
1429 {
1430         struct cy8c95x0_pinctrl *chip;
1431         struct regmap_config regmap_conf;
1432         struct regmap_range_cfg regmap_range_conf;
1433         struct regulator *reg;
1434         int ret;
1435
1436         chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
1437         if (!chip)
1438                 return -ENOMEM;
1439
1440         chip->dev = &client->dev;
1441
1442         /* Set the device type */
1443         chip->driver_data = (uintptr_t)i2c_get_match_data(client);
1444         if (!chip->driver_data)
1445                 return -ENODEV;
1446
1447         i2c_set_clientdata(client, chip);
1448
1449         chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK;
1450         chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ);
1451
1452         memcpy(&regmap_range_conf, &cy8c95x0_ranges[0], sizeof(regmap_range_conf));
1453
1454         switch (chip->tpin) {
1455         case 20:
1456                 strscpy(chip->name, cy8c95x0_id[0].name, I2C_NAME_SIZE);
1457                 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE;
1458                 break;
1459         case 40:
1460                 strscpy(chip->name, cy8c95x0_id[1].name, I2C_NAME_SIZE);
1461                 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE;
1462                 break;
1463         case 60:
1464                 strscpy(chip->name, cy8c95x0_id[2].name, I2C_NAME_SIZE);
1465                 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE;
1466                 break;
1467         default:
1468                 return -ENODEV;
1469         }
1470
1471         reg = devm_regulator_get(&client->dev, "vdd");
1472         if (IS_ERR(reg)) {
1473                 if (PTR_ERR(reg) == -EPROBE_DEFER)
1474                         return -EPROBE_DEFER;
1475         } else {
1476                 ret = regulator_enable(reg);
1477                 if (ret) {
1478                         dev_err(&client->dev, "failed to enable regulator vdd: %d\n", ret);
1479                         return ret;
1480                 }
1481                 chip->regulator = reg;
1482         }
1483
1484         /* bring the chip out of reset if reset pin is provided */
1485         chip->gpio_reset = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH);
1486         if (IS_ERR(chip->gpio_reset)) {
1487                 ret = dev_err_probe(chip->dev, PTR_ERR(chip->gpio_reset),
1488                                     "Failed to get GPIO 'reset'\n");
1489                 goto err_exit;
1490         } else if (chip->gpio_reset) {
1491                 usleep_range(1000, 2000);
1492                 gpiod_set_value_cansleep(chip->gpio_reset, 0);
1493                 usleep_range(250000, 300000);
1494
1495                 gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET");
1496         }
1497
1498         /* Regmap for direct and paged registers */
1499         memcpy(&regmap_conf, &cy8c9520_i2c_regmap, sizeof(regmap_conf));
1500         regmap_conf.ranges = &regmap_range_conf;
1501         regmap_conf.max_register = regmap_range_conf.range_max;
1502         regmap_conf.num_reg_defaults_raw = regmap_range_conf.range_max;
1503
1504         chip->regmap = devm_regmap_init_i2c(client, &regmap_conf);
1505         if (IS_ERR(chip->regmap)) {
1506                 ret = PTR_ERR(chip->regmap);
1507                 goto err_exit;
1508         }
1509
1510         bitmap_zero(chip->push_pull, MAX_LINE);
1511         bitmap_zero(chip->shiftmask, MAX_LINE);
1512         bitmap_set(chip->shiftmask, 0, 20);
1513         mutex_init(&chip->i2c_lock);
1514
1515         if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) {
1516                 ret = cy8c95x0_acpi_get_irq(&client->dev);
1517                 if (ret > 0)
1518                         client->irq = ret;
1519         }
1520
1521         if (client->irq) {
1522                 ret = cy8c95x0_irq_setup(chip, client->irq);
1523                 if (ret)
1524                         goto err_exit;
1525         }
1526
1527         ret = cy8c95x0_setup_pinctrl(chip);
1528         if (ret)
1529                 goto err_exit;
1530
1531         ret = cy8c95x0_setup_gpiochip(chip);
1532         if (ret)
1533                 goto err_exit;
1534
1535         return 0;
1536
1537 err_exit:
1538         if (!IS_ERR_OR_NULL(chip->regulator))
1539                 regulator_disable(chip->regulator);
1540         return ret;
1541 }
1542
1543 static void cy8c95x0_remove(struct i2c_client *client)
1544 {
1545         struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(client);
1546
1547         if (!IS_ERR_OR_NULL(chip->regulator))
1548                 regulator_disable(chip->regulator);
1549 }
1550
1551 static const struct acpi_device_id cy8c95x0_acpi_ids[] = {
1552         { "INT3490", 40, },
1553         { }
1554 };
1555 MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids);
1556
1557 static struct i2c_driver cy8c95x0_driver = {
1558         .driver = {
1559                 .name   = "cy8c95x0-pinctrl",
1560                 .of_match_table = cy8c95x0_dt_ids,
1561                 .acpi_match_table = cy8c95x0_acpi_ids,
1562         },
1563         .probe          = cy8c95x0_probe,
1564         .remove         = cy8c95x0_remove,
1565         .id_table       = cy8c95x0_id,
1566         .detect         = cy8c95x0_detect,
1567 };
1568 module_i2c_driver(cy8c95x0_driver);
1569
1570 MODULE_AUTHOR("Patrick Rudolph <[email protected]>");
1571 MODULE_AUTHOR("Naresh Solanki <[email protected]>");
1572 MODULE_DESCRIPTION("Pinctrl driver for CY8C95X0");
1573 MODULE_LICENSE("GPL");