drivers/perf/arm-cmn.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (C) 2016-2020 Arm Limited
   3 // CMN-600 Coherent Mesh Network PMU driver
   4
   5 #include <linux/acpi.h>
   6 #include <linux/bitfield.h>
   7 #include <linux/bitops.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/io.h>
  11 #include <linux/io-64-nonatomic-lo-hi.h>
  12 #include <linux/kernel.h>
  13 #include <linux/list.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/perf_event.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19 #include <linux/sort.h>
  20
  21 /* Common register stuff */
  22 #define CMN_NODE_INFO                   0x0000
  23 #define CMN_NI_NODE_TYPE                GENMASK_ULL(15, 0)
  24 #define CMN_NI_NODE_ID                  GENMASK_ULL(31, 16)
  25 #define CMN_NI_LOGICAL_ID               GENMASK_ULL(47, 32)
  26
  27 #define CMN_NODEID_DEVID(reg)           ((reg) & 3)
  28 #define CMN_NODEID_EXT_DEVID(reg)       ((reg) & 1)
  29 #define CMN_NODEID_PID(reg)             (((reg) >> 2) & 1)
  30 #define CMN_NODEID_EXT_PID(reg)         (((reg) >> 1) & 3)
  31 #define CMN_NODEID_1x1_PID(reg)         (((reg) >> 2) & 7)
  32 #define CMN_NODEID_X(reg, bits)         ((reg) >> (3 + (bits)))
  33 #define CMN_NODEID_Y(reg, bits)         (((reg) >> 3) & ((1U << (bits)) - 1))
  34
  35 #define CMN_CHILD_INFO                  0x0080
  36 #define CMN_CI_CHILD_COUNT              GENMASK_ULL(15, 0)
  37 #define CMN_CI_CHILD_PTR_OFFSET         GENMASK_ULL(31, 16)
  38
  39 #define CMN_CHILD_NODE_ADDR             GENMASK(29, 0)
  40 #define CMN_CHILD_NODE_EXTERNAL         BIT(31)
  41
  42 #define CMN_MAX_DIMENSION               12
  43 #define CMN_MAX_XPS                     (CMN_MAX_DIMENSION * CMN_MAX_DIMENSION)
  44 #define CMN_MAX_DTMS                    (CMN_MAX_XPS + (CMN_MAX_DIMENSION - 1) * 4)
  45
  46 /* The CFG node has various info besides the discovery tree */
  47 #define CMN_CFGM_PERIPH_ID_01           0x0008
  48 #define CMN_CFGM_PID0_PART_0            GENMASK_ULL(7, 0)
  49 #define CMN_CFGM_PID1_PART_1            GENMASK_ULL(35, 32)
  50 #define CMN_CFGM_PERIPH_ID_23           0x0010
  51 #define CMN_CFGM_PID2_REVISION          GENMASK_ULL(7, 4)
  52
  53 #define CMN_CFGM_INFO_GLOBAL            0x900
  54 #define CMN_INFO_MULTIPLE_DTM_EN        BIT_ULL(63)
  55 #define CMN_INFO_RSP_VC_NUM             GENMASK_ULL(53, 52)
  56 #define CMN_INFO_DAT_VC_NUM             GENMASK_ULL(51, 50)
  57
  58 #define CMN_CFGM_INFO_GLOBAL_1          0x908
  59 #define CMN_INFO_SNP_VC_NUM             GENMASK_ULL(3, 2)
  60 #define CMN_INFO_REQ_VC_NUM             GENMASK_ULL(1, 0)
  61
  62 /* XPs also have some local topology info which has uses too */
  63 #define CMN_MXP__CONNECT_INFO(p)        (0x0008 + 8 * (p))
  64 #define CMN__CONNECT_INFO_DEVICE_TYPE   GENMASK_ULL(4, 0)
  65
  66 #define CMN_MAX_PORTS                   6
  67 #define CI700_CONNECT_INFO_P2_5_OFFSET  0x10
  68
  69 /* PMU registers occupy the 3rd 4KB page of each node's region */
  70 #define CMN_PMU_OFFSET                  0x2000
  71
  72 /* For most nodes, this is all there is */
  73 #define CMN_PMU_EVENT_SEL               0x000
  74 #define CMN__PMU_CBUSY_SNTHROTTLE_SEL   GENMASK_ULL(44, 42)
  75 #define CMN__PMU_SN_HOME_SEL            GENMASK_ULL(40, 39)
  76 #define CMN__PMU_HBT_LBT_SEL            GENMASK_ULL(38, 37)
  77 #define CMN__PMU_CLASS_OCCUP_ID         GENMASK_ULL(36, 35)
  78 /* Technically this is 4 bits wide on DNs, but we only use 2 there anyway */
  79 #define CMN__PMU_OCCUP1_ID              GENMASK_ULL(34, 32)
  80
  81 /* HN-Ps are weird... */
  82 #define CMN_HNP_PMU_EVENT_SEL           0x008
  83
  84 /* DTMs live in the PMU space of XP registers */
  85 #define CMN_DTM_WPn(n)                  (0x1A0 + (n) * 0x18)
  86 #define CMN_DTM_WPn_CONFIG(n)           (CMN_DTM_WPn(n) + 0x00)
  87 #define CMN_DTM_WPn_CONFIG_WP_CHN_NUM   GENMASK_ULL(20, 19)
  88 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL2  GENMASK_ULL(18, 17)
  89 #define CMN_DTM_WPn_CONFIG_WP_COMBINE   BIT(9)
  90 #define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(8)
  91 #define CMN600_WPn_CONFIG_WP_COMBINE    BIT(6)
  92 #define CMN600_WPn_CONFIG_WP_EXCLUSIVE  BIT(5)
  93 #define CMN_DTM_WPn_CONFIG_WP_GRP       GENMASK_ULL(5, 4)
  94 #define CMN_DTM_WPn_CONFIG_WP_CHN_SEL   GENMASK_ULL(3, 1)
  95 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL   BIT(0)
  96 #define CMN_DTM_WPn_VAL(n)              (CMN_DTM_WPn(n) + 0x08)
  97 #define CMN_DTM_WPn_MASK(n)             (CMN_DTM_WPn(n) + 0x10)
  98
  99 #define CMN_DTM_PMU_CONFIG              0x210
 100 #define CMN__PMEVCNT0_INPUT_SEL         GENMASK_ULL(37, 32)
 101 #define CMN__PMEVCNT0_INPUT_SEL_WP      0x00
 102 #define CMN__PMEVCNT0_INPUT_SEL_XP      0x04
 103 #define CMN__PMEVCNT0_INPUT_SEL_DEV     0x10
 104 #define CMN__PMEVCNT0_GLOBAL_NUM        GENMASK_ULL(18, 16)
 105 #define CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(n)       ((n) * 4)
 106 #define CMN__PMEVCNT_PAIRED(n)          BIT(4 + (n))
 107 #define CMN__PMEVCNT23_COMBINED         BIT(2)
 108 #define CMN__PMEVCNT01_COMBINED         BIT(1)
 109 #define CMN_DTM_PMU_CONFIG_PMU_EN       BIT(0)
 110
 111 #define CMN_DTM_PMEVCNT                 0x220
 112
 113 #define CMN_DTM_PMEVCNTSR               0x240
 114
 115 #define CMN650_DTM_UNIT_INFO            0x0910
 116 #define CMN_DTM_UNIT_INFO               0x0960
 117 #define CMN_DTM_UNIT_INFO_DTC_DOMAIN    GENMASK_ULL(1, 0)
 118
 119 #define CMN_DTM_NUM_COUNTERS            4
 120 /* Want more local counters? Why not replicate the whole DTM! Ugh... */
 121 #define CMN_DTM_OFFSET(n)               ((n) * 0x200)
 122
 123 /* The DTC node is where the magic happens */
 124 #define CMN_DT_DTC_CTL                  0x0a00
 125 #define CMN_DT_DTC_CTL_DT_EN            BIT(0)
 126
 127 /* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */
 128 #define _CMN_DT_CNT_REG(n)              ((((n) / 2) * 4 + (n) % 2) * 4)
 129 #define CMN_DT_PMEVCNT(n)               (CMN_PMU_OFFSET + _CMN_DT_CNT_REG(n))
 130 #define CMN_DT_PMCCNTR                  (CMN_PMU_OFFSET + 0x40)
 131
 132 #define CMN_DT_PMEVCNTSR(n)             (CMN_PMU_OFFSET + 0x50 + _CMN_DT_CNT_REG(n))
 133 #define CMN_DT_PMCCNTRSR                (CMN_PMU_OFFSET + 0x90)
 134
 135 #define CMN_DT_PMCR                     (CMN_PMU_OFFSET + 0x100)
 136 #define CMN_DT_PMCR_PMU_EN              BIT(0)
 137 #define CMN_DT_PMCR_CNTR_RST            BIT(5)
 138 #define CMN_DT_PMCR_OVFL_INTR_EN        BIT(6)
 139
 140 #define CMN_DT_PMOVSR                   (CMN_PMU_OFFSET + 0x118)
 141 #define CMN_DT_PMOVSR_CLR               (CMN_PMU_OFFSET + 0x120)
 142
 143 #define CMN_DT_PMSSR                    (CMN_PMU_OFFSET + 0x128)
 144 #define CMN_DT_PMSSR_SS_STATUS(n)       BIT(n)
 145
 146 #define CMN_DT_PMSRR                    (CMN_PMU_OFFSET + 0x130)
 147 #define CMN_DT_PMSRR_SS_REQ             BIT(0)
 148
 149 #define CMN_DT_NUM_COUNTERS             8
 150 #define CMN_MAX_DTCS                    4
 151
 152 /*
 153  * Even in the worst case a DTC counter can't wrap in fewer than 2^42 cycles,
 154  * so throwing away one bit to make overflow handling easy is no big deal.
 155  */
 156 #define CMN_COUNTER_INIT                0x80000000
 157 /* Similarly for the 40-bit cycle counter */
 158 #define CMN_CC_INIT                     0x8000000000ULL
 159
 160
 161 /* Event attributes */
 162 #define CMN_CONFIG_TYPE                 GENMASK_ULL(15, 0)
 163 #define CMN_CONFIG_EVENTID              GENMASK_ULL(26, 16)
 164 #define CMN_CONFIG_OCCUPID              GENMASK_ULL(30, 27)
 165 #define CMN_CONFIG_BYNODEID             BIT_ULL(31)
 166 #define CMN_CONFIG_NODEID               GENMASK_ULL(47, 32)
 167
 168 #define CMN_EVENT_TYPE(event)           FIELD_GET(CMN_CONFIG_TYPE, (event)->attr.config)
 169 #define CMN_EVENT_EVENTID(event)        FIELD_GET(CMN_CONFIG_EVENTID, (event)->attr.config)
 170 #define CMN_EVENT_OCCUPID(event)        FIELD_GET(CMN_CONFIG_OCCUPID, (event)->attr.config)
 171 #define CMN_EVENT_BYNODEID(event)       FIELD_GET(CMN_CONFIG_BYNODEID, (event)->attr.config)
 172 #define CMN_EVENT_NODEID(event)         FIELD_GET(CMN_CONFIG_NODEID, (event)->attr.config)
 173
 174 #define CMN_CONFIG_WP_COMBINE           GENMASK_ULL(30, 27)
 175 #define CMN_CONFIG_WP_DEV_SEL           GENMASK_ULL(50, 48)
 176 #define CMN_CONFIG_WP_CHN_SEL           GENMASK_ULL(55, 51)
 177 #define CMN_CONFIG_WP_GRP               GENMASK_ULL(57, 56)
 178 #define CMN_CONFIG_WP_EXCLUSIVE         BIT_ULL(58)
 179 #define CMN_CONFIG1_WP_VAL              GENMASK_ULL(63, 0)
 180 #define CMN_CONFIG2_WP_MASK             GENMASK_ULL(63, 0)
 181
 182 #define CMN_EVENT_WP_COMBINE(event)     FIELD_GET(CMN_CONFIG_WP_COMBINE, (event)->attr.config)
 183 #define CMN_EVENT_WP_DEV_SEL(event)     FIELD_GET(CMN_CONFIG_WP_DEV_SEL, (event)->attr.config)
 184 #define CMN_EVENT_WP_CHN_SEL(event)     FIELD_GET(CMN_CONFIG_WP_CHN_SEL, (event)->attr.config)
 185 #define CMN_EVENT_WP_GRP(event)         FIELD_GET(CMN_CONFIG_WP_GRP, (event)->attr.config)
 186 #define CMN_EVENT_WP_EXCLUSIVE(event)   FIELD_GET(CMN_CONFIG_WP_EXCLUSIVE, (event)->attr.config)
 187 #define CMN_EVENT_WP_VAL(event)         FIELD_GET(CMN_CONFIG1_WP_VAL, (event)->attr.config1)
 188 #define CMN_EVENT_WP_MASK(event)        FIELD_GET(CMN_CONFIG2_WP_MASK, (event)->attr.config2)
 189
 190 /* Made-up event IDs for watchpoint direction */
 191 #define CMN_WP_UP                       0
 192 #define CMN_WP_DOWN                     2
 193
 194
 195 /* Internal values for encoding event support */
 196 enum cmn_model {
 197         CMN600 = 1,
 198         CMN650 = 2,
 199         CMN700 = 4,
 200         CI700 = 8,
 201         /* ...and then we can use bitmap tricks for commonality */
 202         CMN_ANY = -1,
 203         NOT_CMN600 = -2,
 204         CMN_650ON = CMN650 | CMN700,
 205 };
 206
 207 /* Actual part numbers and revision IDs defined by the hardware */
 208 enum cmn_part {
 209         PART_CMN600 = 0x434,
 210         PART_CMN650 = 0x436,
 211         PART_CMN700 = 0x43c,
 212         PART_CI700 = 0x43a,
 213 };
 214
 215 /* CMN-600 r0px shouldn't exist in silicon, thankfully */
 216 enum cmn_revision {
 217         REV_CMN600_R1P0,
 218         REV_CMN600_R1P1,
 219         REV_CMN600_R1P2,
 220         REV_CMN600_R1P3,
 221         REV_CMN600_R2P0,
 222         REV_CMN600_R3P0,
 223         REV_CMN600_R3P1,
 224         REV_CMN650_R0P0 = 0,
 225         REV_CMN650_R1P0,
 226         REV_CMN650_R1P1,
 227         REV_CMN650_R2P0,
 228         REV_CMN650_R1P2,
 229         REV_CMN700_R0P0 = 0,
 230         REV_CMN700_R1P0,
 231         REV_CMN700_R2P0,
 232         REV_CMN700_R3P0,
 233         REV_CI700_R0P0 = 0,
 234         REV_CI700_R1P0,
 235         REV_CI700_R2P0,
 236 };
 237
 238 enum cmn_node_type {
 239         CMN_TYPE_INVALID,
 240         CMN_TYPE_DVM,
 241         CMN_TYPE_CFG,
 242         CMN_TYPE_DTC,
 243         CMN_TYPE_HNI,
 244         CMN_TYPE_HNF,
 245         CMN_TYPE_XP,
 246         CMN_TYPE_SBSX,
 247         CMN_TYPE_MPAM_S,
 248         CMN_TYPE_MPAM_NS,
 249         CMN_TYPE_RNI,
 250         CMN_TYPE_RND = 0xd,
 251         CMN_TYPE_RNSAM = 0xf,
 252         CMN_TYPE_MTSX,
 253         CMN_TYPE_HNP,
 254         CMN_TYPE_CXRA = 0x100,
 255         CMN_TYPE_CXHA,
 256         CMN_TYPE_CXLA,
 257         CMN_TYPE_CCRA,
 258         CMN_TYPE_CCHA,
 259         CMN_TYPE_CCLA,
 260         CMN_TYPE_CCLA_RNI,
 261         CMN_TYPE_HNS = 0x200,
 262         CMN_TYPE_HNS_MPAM_S,
 263         CMN_TYPE_HNS_MPAM_NS,
 264         /* Not a real node type */
 265         CMN_TYPE_WP = 0x7770
 266 };
 267
 268 enum cmn_filter_select {
 269         SEL_NONE = -1,
 270         SEL_OCCUP1ID,
 271         SEL_CLASS_OCCUP_ID,
 272         SEL_CBUSY_SNTHROTTLE_SEL,
 273         SEL_HBT_LBT_SEL,
 274         SEL_SN_HOME_SEL,
 275         SEL_MAX
 276 };
 277
 278 struct arm_cmn_node {
 279         void __iomem *pmu_base;
 280         u16 id, logid;
 281         enum cmn_node_type type;
 282
 283         u8 dtm;
 284         s8 dtc;
 285         /* DN/HN-F/CXHA */
 286         struct {
 287                 u8 val : 4;
 288                 u8 count : 4;
 289         } occupid[SEL_MAX];
 290         union {
 291                 u8 event[4];
 292                 __le32 event_sel;
 293                 u16 event_w[4];
 294                 __le64 event_sel_w;
 295         };
 296 };
 297
 298 struct arm_cmn_dtm {
 299         void __iomem *base;
 300         u32 pmu_config_low;
 301         union {
 302                 u8 input_sel[4];
 303                 __le32 pmu_config_high;
 304         };
 305         s8 wp_event[4];
 306 };
 307
 308 struct arm_cmn_dtc {
 309         void __iomem *base;
 310         int irq;
 311         int irq_friend;
 312         bool cc_active;
 313
 314         struct perf_event *counters[CMN_DT_NUM_COUNTERS];
 315         struct perf_event *cycles;
 316 };
 317
 318 #define CMN_STATE_DISABLED      BIT(0)
 319 #define CMN_STATE_TXN           BIT(1)
 320
 321 struct arm_cmn {
 322         struct device *dev;
 323         void __iomem *base;
 324         unsigned int state;
 325
 326         enum cmn_revision rev;
 327         enum cmn_part part;
 328         u8 mesh_x;
 329         u8 mesh_y;
 330         u16 num_xps;
 331         u16 num_dns;
 332         bool multi_dtm;
 333         u8 ports_used;
 334         struct {
 335                 unsigned int rsp_vc_num : 2;
 336                 unsigned int dat_vc_num : 2;
 337                 unsigned int snp_vc_num : 2;
 338                 unsigned int req_vc_num : 2;
 339         };
 340
 341         struct arm_cmn_node *xps;
 342         struct arm_cmn_node *dns;
 343
 344         struct arm_cmn_dtm *dtms;
 345         struct arm_cmn_dtc *dtc;
 346         unsigned int num_dtcs;
 347
 348         int cpu;
 349         struct hlist_node cpuhp_node;
 350
 351         struct pmu pmu;
 352         struct dentry *debug;
 353 };
 354
 355 #define to_cmn(p)       container_of(p, struct arm_cmn, pmu)
 356
 357 static int arm_cmn_hp_state;
 358
 359 struct arm_cmn_nodeid {
 360         u8 x;
 361         u8 y;
 362         u8 port;
 363         u8 dev;
 364 };
 365
 366 static int arm_cmn_xyidbits(const struct arm_cmn *cmn)
 367 {
 368         return fls((cmn->mesh_x - 1) | (cmn->mesh_y - 1) | 2);
 369 }
 370
 371 static struct arm_cmn_nodeid arm_cmn_nid(const struct arm_cmn *cmn, u16 id)
 372 {
 373         struct arm_cmn_nodeid nid;
 374
 375         if (cmn->num_xps == 1) {
 376                 nid.x = 0;
 377                 nid.y = 0;
 378                 nid.port = CMN_NODEID_1x1_PID(id);
 379                 nid.dev = CMN_NODEID_DEVID(id);
 380         } else {
 381                 int bits = arm_cmn_xyidbits(cmn);
 382
 383                 nid.x = CMN_NODEID_X(id, bits);
 384                 nid.y = CMN_NODEID_Y(id, bits);
 385                 if (cmn->ports_used & 0xc) {
 386                         nid.port = CMN_NODEID_EXT_PID(id);
 387                         nid.dev = CMN_NODEID_EXT_DEVID(id);
 388                 } else {
 389                         nid.port = CMN_NODEID_PID(id);
 390                         nid.dev = CMN_NODEID_DEVID(id);
 391                 }
 392         }
 393         return nid;
 394 }
 395
 396 static struct arm_cmn_node *arm_cmn_node_to_xp(const struct arm_cmn *cmn,
 397                                                const struct arm_cmn_node *dn)
 398 {
 399         struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id);
 400         int xp_idx = cmn->mesh_x * nid.y + nid.x;
 401
 402         return cmn->xps + xp_idx;
 403 }
 404 static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn,
 405                                          enum cmn_node_type type)
 406 {
 407         struct arm_cmn_node *dn;
 408
 409         for (dn = cmn->dns; dn->type; dn++)
 410                 if (dn->type == type)
 411                         return dn;
 412         return NULL;
 413 }
 414
 415 static enum cmn_model arm_cmn_model(const struct arm_cmn *cmn)
 416 {
 417         switch (cmn->part) {
 418         case PART_CMN600:
 419                 return CMN600;
 420         case PART_CMN650:
 421                 return CMN650;
 422         case PART_CMN700:
 423                 return CMN700;
 424         case PART_CI700:
 425                 return CI700;
 426         default:
 427                 return 0;
 428         };
 429 }
 430
 431 static u32 arm_cmn_device_connect_info(const struct arm_cmn *cmn,
 432                                        const struct arm_cmn_node *xp, int port)
 433 {
 434         int offset = CMN_MXP__CONNECT_INFO(port);
 435
 436         if (port >= 2) {
 437                 if (cmn->part == PART_CMN600 || cmn->part == PART_CMN650)
 438                         return 0;
 439                 /*
 440                  * CI-700 may have extra ports, but still has the
 441                  * mesh_port_connect_info registers in the way.
 442                  */
 443                 if (cmn->part == PART_CI700)
 444                         offset += CI700_CONNECT_INFO_P2_5_OFFSET;
 445         }
 446
 447         return readl_relaxed(xp->pmu_base - CMN_PMU_OFFSET + offset);
 448 }
 449
 450 static struct dentry *arm_cmn_debugfs;
 451
 452 #ifdef CONFIG_DEBUG_FS
 453 static const char *arm_cmn_device_type(u8 type)
 454 {
 455         switch(FIELD_GET(CMN__CONNECT_INFO_DEVICE_TYPE, type)) {
 456                 case 0x00: return "        |";
 457                 case 0x01: return "  RN-I  |";
 458                 case 0x02: return "  RN-D  |";
 459                 case 0x04: return " RN-F_B |";
 460                 case 0x05: return "RN-F_B_E|";
 461                 case 0x06: return " RN-F_A |";
 462                 case 0x07: return "RN-F_A_E|";
 463                 case 0x08: return "  HN-T  |";
 464                 case 0x09: return "  HN-I  |";
 465                 case 0x0a: return "  HN-D  |";
 466                 case 0x0b: return "  HN-P  |";
 467                 case 0x0c: return "  SN-F  |";
 468                 case 0x0d: return "  SBSX  |";
 469                 case 0x0e: return "  HN-F  |";
 470                 case 0x0f: return " SN-F_E |";
 471                 case 0x10: return " SN-F_D |";
 472                 case 0x11: return "  CXHA  |";
 473                 case 0x12: return "  CXRA  |";
 474                 case 0x13: return "  CXRH  |";
 475                 case 0x14: return " RN-F_D |";
 476                 case 0x15: return "RN-F_D_E|";
 477                 case 0x16: return " RN-F_C |";
 478                 case 0x17: return "RN-F_C_E|";
 479                 case 0x18: return " RN-F_E |";
 480                 case 0x19: return "RN-F_E_E|";
 481                 case 0x1c: return "  MTSX  |";
 482                 case 0x1d: return "  HN-V  |";
 483                 case 0x1e: return "  CCG   |";
 484                 default:   return "  ????  |";
 485         }
 486 }
 487
 488 static void arm_cmn_show_logid(struct seq_file *s, int x, int y, int p, int d)
 489 {
 490         struct arm_cmn *cmn = s->private;
 491         struct arm_cmn_node *dn;
 492
 493         for (dn = cmn->dns; dn->type; dn++) {
 494                 struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id);
 495                 int pad = dn->logid < 10;
 496
 497                 if (dn->type == CMN_TYPE_XP)
 498                         continue;
 499                 /* Ignore the extra components that will overlap on some ports */
 500                 if (dn->type < CMN_TYPE_HNI)
 501                         continue;
 502
 503                 if (nid.x != x || nid.y != y || nid.port != p || nid.dev != d)
 504                         continue;
 505
 506                 seq_printf(s, " %*c#%-*d  |", pad + 1, ' ', 3 - pad, dn->logid);
 507                 return;
 508         }
 509         seq_puts(s, "        |");
 510 }
 511
 512 static int arm_cmn_map_show(struct seq_file *s, void *data)
 513 {
 514         struct arm_cmn *cmn = s->private;
 515         int x, y, p, pmax = fls(cmn->ports_used);
 516
 517         seq_puts(s, "     X");
 518         for (x = 0; x < cmn->mesh_x; x++)
 519                 seq_printf(s, "    %-2d   ", x);
 520         seq_puts(s, "\nY P D+");
 521         y = cmn->mesh_y;
 522         while (y--) {
 523                 int xp_base = cmn->mesh_x * y;
 524                 u8 port[CMN_MAX_PORTS][CMN_MAX_DIMENSION];
 525
 526                 for (x = 0; x < cmn->mesh_x; x++)
 527                         seq_puts(s, "--------+");
 528
 529                 seq_printf(s, "\n%-2d   |", y);
 530                 for (x = 0; x < cmn->mesh_x; x++) {
 531                         struct arm_cmn_node *xp = cmn->xps + xp_base + x;
 532
 533                         for (p = 0; p < CMN_MAX_PORTS; p++)
 534                                 port[p][x] = arm_cmn_device_connect_info(cmn, xp, p);
 535                         seq_printf(s, " XP #%-3d|", xp_base + x);
 536                 }
 537
 538                 seq_puts(s, "\n     |");
 539                 for (x = 0; x < cmn->mesh_x; x++) {
 540                         s8 dtc = cmn->xps[xp_base + x].dtc;
 541
 542                         if (dtc < 0)
 543                                 seq_puts(s, " DTC ?? |");
 544                         else
 545                                 seq_printf(s, " DTC %d  |", dtc);
 546                 }
 547                 seq_puts(s, "\n     |");
 548                 for (x = 0; x < cmn->mesh_x; x++)
 549                         seq_puts(s, "........|");
 550
 551                 for (p = 0; p < pmax; p++) {
 552                         seq_printf(s, "\n  %d  |", p);
 553                         for (x = 0; x < cmn->mesh_x; x++)
 554                                 seq_puts(s, arm_cmn_device_type(port[p][x]));
 555                         seq_puts(s, "\n    0|");
 556                         for (x = 0; x < cmn->mesh_x; x++)
 557                                 arm_cmn_show_logid(s, x, y, p, 0);
 558                         seq_puts(s, "\n    1|");
 559                         for (x = 0; x < cmn->mesh_x; x++)
 560                                 arm_cmn_show_logid(s, x, y, p, 1);
 561                 }
 562                 seq_puts(s, "\n-----+");
 563         }
 564         for (x = 0; x < cmn->mesh_x; x++)
 565                 seq_puts(s, "--------+");
 566         seq_puts(s, "\n");
 567         return 0;
 568 }
 569 DEFINE_SHOW_ATTRIBUTE(arm_cmn_map);
 570
 571 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id)
 572 {
 573         const char *name  = "map";
 574
 575         if (id > 0)
 576                 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "map_%d", id);
 577         if (!name)
 578                 return;
 579
 580         cmn->debug = debugfs_create_file(name, 0444, arm_cmn_debugfs, cmn, &arm_cmn_map_fops);
 581 }
 582 #else
 583 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) {}
 584 #endif
 585
 586 struct arm_cmn_hw_event {
 587         struct arm_cmn_node *dn;
 588         u64 dtm_idx[4];
 589         s8 dtc_idx[CMN_MAX_DTCS];
 590         u8 num_dns;
 591         u8 dtm_offset;
 592
 593         /*
 594          * WP config registers are divided to UP and DOWN events. We need to
 595          * keep to track only one of them.
 596          */
 597         DECLARE_BITMAP(wp_idx, CMN_MAX_XPS);
 598
 599         bool wide_sel;
 600         enum cmn_filter_select filter_sel;
 601 };
 602
 603 #define for_each_hw_dn(hw, dn, i) \
 604         for (i = 0, dn = hw->dn; i < hw->num_dns; i++, dn++)
 605
 606 /* @i is the DTC number, @idx is the counter index on that DTC */
 607 #define for_each_hw_dtc_idx(hw, i, idx) \
 608         for (int i = 0, idx; i < CMN_MAX_DTCS; i++) if ((idx = hw->dtc_idx[i]) >= 0)
 609
 610 static struct arm_cmn_hw_event *to_cmn_hw(struct perf_event *event)
 611 {
 612         BUILD_BUG_ON(sizeof(struct arm_cmn_hw_event) > offsetof(struct hw_perf_event, target));
 613         return (struct arm_cmn_hw_event *)&event->hw;
 614 }
 615
 616 static void arm_cmn_set_index(u64 x[], unsigned int pos, unsigned int val)
 617 {
 618         x[pos / 32] |= (u64)val << ((pos % 32) * 2);
 619 }
 620
 621 static unsigned int arm_cmn_get_index(u64 x[], unsigned int pos)
 622 {
 623         return (x[pos / 32] >> ((pos % 32) * 2)) & 3;
 624 }
 625
 626 static void arm_cmn_set_wp_idx(unsigned long *wp_idx, unsigned int pos, bool val)
 627 {
 628         if (val)
 629                 set_bit(pos, wp_idx);
 630 }
 631
 632 static unsigned int arm_cmn_get_wp_idx(unsigned long *wp_idx, unsigned int pos)
 633 {
 634         return test_bit(pos, wp_idx);
 635 }
 636
 637 struct arm_cmn_event_attr {
 638         struct device_attribute attr;
 639         enum cmn_model model;
 640         enum cmn_node_type type;
 641         enum cmn_filter_select fsel;
 642         u16 eventid;
 643         u8 occupid;
 644 };
 645
 646 struct arm_cmn_format_attr {
 647         struct device_attribute attr;
 648         u64 field;
 649         int config;
 650 };
 651
 652 #define _CMN_EVENT_ATTR(_model, _name, _type, _eventid, _occupid, _fsel)\
 653         (&((struct arm_cmn_event_attr[]) {{                             \
 654                 .attr = __ATTR(_name, 0444, arm_cmn_event_show, NULL),  \
 655                 .model = _model,                                        \
 656                 .type = _type,                                          \
 657                 .eventid = _eventid,                                    \
 658                 .occupid = _occupid,                                    \
 659                 .fsel = _fsel,                                          \
 660         }})[0].attr.attr)
 661 #define CMN_EVENT_ATTR(_model, _name, _type, _eventid)                  \
 662         _CMN_EVENT_ATTR(_model, _name, _type, _eventid, 0, SEL_NONE)
 663
 664 static ssize_t arm_cmn_event_show(struct device *dev,
 665                                   struct device_attribute *attr, char *buf)
 666 {
 667         struct arm_cmn_event_attr *eattr;
 668
 669         eattr = container_of(attr, typeof(*eattr), attr);
 670
 671         if (eattr->type == CMN_TYPE_DTC)
 672                 return sysfs_emit(buf, "type=0x%x\n", eattr->type);
 673
 674         if (eattr->type == CMN_TYPE_WP)
 675                 return sysfs_emit(buf,
 676                                   "type=0x%x,eventid=0x%x,wp_dev_sel=?,wp_chn_sel=?,wp_grp=?,wp_val=?,wp_mask=?\n",
 677                                   eattr->type, eattr->eventid);
 678
 679         if (eattr->fsel > SEL_NONE)
 680                 return sysfs_emit(buf, "type=0x%x,eventid=0x%x,occupid=0x%x\n",
 681                                   eattr->type, eattr->eventid, eattr->occupid);
 682
 683         return sysfs_emit(buf, "type=0x%x,eventid=0x%x\n", eattr->type,
 684                           eattr->eventid);
 685 }
 686
 687 static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj,
 688                                              struct attribute *attr,
 689                                              int unused)
 690 {
 691         struct device *dev = kobj_to_dev(kobj);
 692         struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
 693         struct arm_cmn_event_attr *eattr;
 694         enum cmn_node_type type;
 695         u16 eventid;
 696
 697         eattr = container_of(attr, typeof(*eattr), attr.attr);
 698
 699         if (!(eattr->model & arm_cmn_model(cmn)))
 700                 return 0;
 701
 702         type = eattr->type;
 703         eventid = eattr->eventid;
 704
 705         /* Watchpoints aren't nodes, so avoid confusion */
 706         if (type == CMN_TYPE_WP)
 707                 return attr->mode;
 708
 709         /* Hide XP events for unused interfaces/channels */
 710         if (type == CMN_TYPE_XP) {
 711                 unsigned int intf = (eventid >> 2) & 7;
 712                 unsigned int chan = eventid >> 5;
 713
 714                 if ((intf & 4) && !(cmn->ports_used & BIT(intf & 3)))
 715                         return 0;
 716
 717                 if (chan == 4 && cmn->part == PART_CMN600)
 718                         return 0;
 719
 720                 if ((chan == 5 && cmn->rsp_vc_num < 2) ||
 721                     (chan == 6 && cmn->dat_vc_num < 2) ||
 722                     (chan == 7 && cmn->snp_vc_num < 2) ||
 723                     (chan == 8 && cmn->req_vc_num < 2))
 724                         return 0;
 725         }
 726
 727         /* Revision-specific differences */
 728         if (cmn->part == PART_CMN600) {
 729                 if (cmn->rev < REV_CMN600_R1P3) {
 730                         if (type == CMN_TYPE_CXRA && eventid > 0x10)
 731                                 return 0;
 732                 }
 733                 if (cmn->rev < REV_CMN600_R1P2) {
 734                         if (type == CMN_TYPE_HNF && eventid == 0x1b)
 735                                 return 0;
 736                         if (type == CMN_TYPE_CXRA || type == CMN_TYPE_CXHA)
 737                                 return 0;
 738                 }
 739         } else if (cmn->part == PART_CMN650) {
 740                 if (cmn->rev < REV_CMN650_R2P0 || cmn->rev == REV_CMN650_R1P2) {
 741                         if (type == CMN_TYPE_HNF && eventid > 0x22)
 742                                 return 0;
 743                         if (type == CMN_TYPE_SBSX && eventid == 0x17)
 744                                 return 0;
 745                         if (type == CMN_TYPE_RNI && eventid > 0x10)
 746                                 return 0;
 747                 }
 748         } else if (cmn->part == PART_CMN700) {
 749                 if (cmn->rev < REV_CMN700_R2P0) {
 750                         if (type == CMN_TYPE_HNF && eventid > 0x2c)
 751                                 return 0;
 752                         if (type == CMN_TYPE_CCHA && eventid > 0x74)
 753                                 return 0;
 754                         if (type == CMN_TYPE_CCLA && eventid > 0x27)
 755                                 return 0;
 756                 }
 757                 if (cmn->rev < REV_CMN700_R1P0) {
 758                         if (type == CMN_TYPE_HNF && eventid > 0x2b)
 759                                 return 0;
 760                 }
 761         }
 762
 763         if (!arm_cmn_node(cmn, type))
 764                 return 0;
 765
 766         return attr->mode;
 767 }
 768
 769 #define _CMN_EVENT_DVM(_model, _name, _event, _occup, _fsel)    \
 770         _CMN_EVENT_ATTR(_model, dn_##_name, CMN_TYPE_DVM, _event, _occup, _fsel)
 771 #define CMN_EVENT_DTC(_name)                                    \
 772         CMN_EVENT_ATTR(CMN_ANY, dtc_##_name, CMN_TYPE_DTC, 0)
 773 #define CMN_EVENT_HNF(_model, _name, _event)                    \
 774         CMN_EVENT_ATTR(_model, hnf_##_name, CMN_TYPE_HNF, _event)
 775 #define CMN_EVENT_HNI(_name, _event)                            \
 776         CMN_EVENT_ATTR(CMN_ANY, hni_##_name, CMN_TYPE_HNI, _event)
 777 #define CMN_EVENT_HNP(_name, _event)                            \
 778         CMN_EVENT_ATTR(CMN_ANY, hnp_##_name, CMN_TYPE_HNP, _event)
 779 #define __CMN_EVENT_XP(_name, _event)                           \
 780         CMN_EVENT_ATTR(CMN_ANY, mxp_##_name, CMN_TYPE_XP, _event)
 781 #define CMN_EVENT_SBSX(_model, _name, _event)                   \
 782         CMN_EVENT_ATTR(_model, sbsx_##_name, CMN_TYPE_SBSX, _event)
 783 #define CMN_EVENT_RNID(_model, _name, _event)                   \
 784         CMN_EVENT_ATTR(_model, rnid_##_name, CMN_TYPE_RNI, _event)
 785 #define CMN_EVENT_MTSX(_name, _event)                           \
 786         CMN_EVENT_ATTR(CMN_ANY, mtsx_##_name, CMN_TYPE_MTSX, _event)
 787 #define CMN_EVENT_CXRA(_model, _name, _event)                           \
 788         CMN_EVENT_ATTR(_model, cxra_##_name, CMN_TYPE_CXRA, _event)
 789 #define CMN_EVENT_CXHA(_name, _event)                           \
 790         CMN_EVENT_ATTR(CMN_ANY, cxha_##_name, CMN_TYPE_CXHA, _event)
 791 #define CMN_EVENT_CCRA(_name, _event)                           \
 792         CMN_EVENT_ATTR(CMN_ANY, ccra_##_name, CMN_TYPE_CCRA, _event)
 793 #define CMN_EVENT_CCHA(_name, _event)                           \
 794         CMN_EVENT_ATTR(CMN_ANY, ccha_##_name, CMN_TYPE_CCHA, _event)
 795 #define CMN_EVENT_CCLA(_name, _event)                           \
 796         CMN_EVENT_ATTR(CMN_ANY, ccla_##_name, CMN_TYPE_CCLA, _event)
 797 #define CMN_EVENT_CCLA_RNI(_name, _event)                               \
 798         CMN_EVENT_ATTR(CMN_ANY, ccla_rni_##_name, CMN_TYPE_CCLA_RNI, _event)
 799 #define CMN_EVENT_HNS(_name, _event)                            \
 800         CMN_EVENT_ATTR(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event)
 801
 802 #define CMN_EVENT_DVM(_model, _name, _event)                    \
 803         _CMN_EVENT_DVM(_model, _name, _event, 0, SEL_NONE)
 804 #define CMN_EVENT_DVM_OCC(_model, _name, _event)                        \
 805         _CMN_EVENT_DVM(_model, _name##_all, _event, 0, SEL_OCCUP1ID),   \
 806         _CMN_EVENT_DVM(_model, _name##_dvmop, _event, 1, SEL_OCCUP1ID), \
 807         _CMN_EVENT_DVM(_model, _name##_dvmsync, _event, 2, SEL_OCCUP1ID)
 808
 809 #define CMN_EVENT_HN_OCC(_model, _name, _type, _event)          \
 810         _CMN_EVENT_ATTR(_model, _name##_all, _type, _event, 0, SEL_OCCUP1ID), \
 811         _CMN_EVENT_ATTR(_model, _name##_read, _type, _event, 1, SEL_OCCUP1ID), \
 812         _CMN_EVENT_ATTR(_model, _name##_write, _type, _event, 2, SEL_OCCUP1ID), \
 813         _CMN_EVENT_ATTR(_model, _name##_atomic, _type, _event, 3, SEL_OCCUP1ID), \
 814         _CMN_EVENT_ATTR(_model, _name##_stash, _type, _event, 4, SEL_OCCUP1ID)
 815 #define CMN_EVENT_HN_CLS(_model, _name, _type, _event)                  \
 816         _CMN_EVENT_ATTR(_model, _name##_class0, _type, _event, 0, SEL_CLASS_OCCUP_ID), \
 817         _CMN_EVENT_ATTR(_model, _name##_class1, _type, _event, 1, SEL_CLASS_OCCUP_ID), \
 818         _CMN_EVENT_ATTR(_model, _name##_class2, _type, _event, 2, SEL_CLASS_OCCUP_ID), \
 819         _CMN_EVENT_ATTR(_model, _name##_class3, _type, _event, 3, SEL_CLASS_OCCUP_ID)
 820 #define CMN_EVENT_HN_SNT(_model, _name, _type, _event)                  \
 821         _CMN_EVENT_ATTR(_model, _name##_all, _type, _event, 0, SEL_CBUSY_SNTHROTTLE_SEL), \
 822         _CMN_EVENT_ATTR(_model, _name##_group0_read, _type, _event, 1, SEL_CBUSY_SNTHROTTLE_SEL), \
 823         _CMN_EVENT_ATTR(_model, _name##_group0_write, _type, _event, 2, SEL_CBUSY_SNTHROTTLE_SEL), \
 824         _CMN_EVENT_ATTR(_model, _name##_group1_read, _type, _event, 3, SEL_CBUSY_SNTHROTTLE_SEL), \
 825         _CMN_EVENT_ATTR(_model, _name##_group1_write, _type, _event, 4, SEL_CBUSY_SNTHROTTLE_SEL), \
 826         _CMN_EVENT_ATTR(_model, _name##_read, _type, _event, 5, SEL_CBUSY_SNTHROTTLE_SEL), \
 827         _CMN_EVENT_ATTR(_model, _name##_write, _type, _event, 6, SEL_CBUSY_SNTHROTTLE_SEL)
 828
 829 #define CMN_EVENT_HNF_OCC(_model, _name, _event)                        \
 830         CMN_EVENT_HN_OCC(_model, hnf_##_name, CMN_TYPE_HNF, _event)
 831 #define CMN_EVENT_HNF_CLS(_model, _name, _event)                        \
 832         CMN_EVENT_HN_CLS(_model, hnf_##_name, CMN_TYPE_HNF, _event)
 833 #define CMN_EVENT_HNF_SNT(_model, _name, _event)                        \
 834         CMN_EVENT_HN_SNT(_model, hnf_##_name, CMN_TYPE_HNF, _event)
 835
 836 #define CMN_EVENT_HNS_OCC(_name, _event)                                \
 837         CMN_EVENT_HN_OCC(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event),   \
 838         _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_rxsnp, CMN_TYPE_HNS, _event, 5, SEL_OCCUP1ID), \
 839         _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_lbt, CMN_TYPE_HNS, _event, 6, SEL_OCCUP1ID), \
 840         _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_hbt, CMN_TYPE_HNS, _event, 7, SEL_OCCUP1ID)
 841 #define CMN_EVENT_HNS_CLS( _name, _event)                               \
 842         CMN_EVENT_HN_CLS(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event)
 843 #define CMN_EVENT_HNS_SNT(_name, _event)                                \
 844         CMN_EVENT_HN_SNT(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event)
 845 #define CMN_EVENT_HNS_HBT(_name, _event)                                \
 846         _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_all, CMN_TYPE_HNS, _event, 0, SEL_HBT_LBT_SEL), \
 847         _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_hbt, CMN_TYPE_HNS, _event, 1, SEL_HBT_LBT_SEL), \
 848         _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_lbt, CMN_TYPE_HNS, _event, 2, SEL_HBT_LBT_SEL)
 849 #define CMN_EVENT_HNS_SNH(_name, _event)                                \
 850         _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_all, CMN_TYPE_HNS, _event, 0, SEL_SN_HOME_SEL), \
 851         _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_sn, CMN_TYPE_HNS, _event, 1, SEL_SN_HOME_SEL), \
 852         _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_home, CMN_TYPE_HNS, _event, 2, SEL_SN_HOME_SEL)
 853
 854 #define _CMN_EVENT_XP_MESH(_name, _event)                       \
 855         __CMN_EVENT_XP(e_##_name, (_event) | (0 << 2)),         \
 856         __CMN_EVENT_XP(w_##_name, (_event) | (1 << 2)),         \
 857         __CMN_EVENT_XP(n_##_name, (_event) | (2 << 2)),         \
 858         __CMN_EVENT_XP(s_##_name, (_event) | (3 << 2))
 859
 860 #define _CMN_EVENT_XP_PORT(_name, _event)                       \
 861         __CMN_EVENT_XP(p0_##_name, (_event) | (4 << 2)),        \
 862         __CMN_EVENT_XP(p1_##_name, (_event) | (5 << 2)),        \
 863         __CMN_EVENT_XP(p2_##_name, (_event) | (6 << 2)),        \
 864         __CMN_EVENT_XP(p3_##_name, (_event) | (7 << 2))
 865
 866 #define _CMN_EVENT_XP(_name, _event)                            \
 867         _CMN_EVENT_XP_MESH(_name, _event),                      \
 868         _CMN_EVENT_XP_PORT(_name, _event)
 869
 870 /* Good thing there are only 3 fundamental XP events... */
 871 #define CMN_EVENT_XP(_name, _event)                             \
 872         _CMN_EVENT_XP(req_##_name, (_event) | (0 << 5)),        \
 873         _CMN_EVENT_XP(rsp_##_name, (_event) | (1 << 5)),        \
 874         _CMN_EVENT_XP(snp_##_name, (_event) | (2 << 5)),        \
 875         _CMN_EVENT_XP(dat_##_name, (_event) | (3 << 5)),        \
 876         _CMN_EVENT_XP(pub_##_name, (_event) | (4 << 5)),        \
 877         _CMN_EVENT_XP(rsp2_##_name, (_event) | (5 << 5)),       \
 878         _CMN_EVENT_XP(dat2_##_name, (_event) | (6 << 5)),       \
 879         _CMN_EVENT_XP(snp2_##_name, (_event) | (7 << 5)),       \
 880         _CMN_EVENT_XP(req2_##_name, (_event) | (8 << 5))
 881
 882 #define CMN_EVENT_XP_DAT(_name, _event)                         \
 883         _CMN_EVENT_XP_PORT(dat_##_name, (_event) | (3 << 5)),   \
 884         _CMN_EVENT_XP_PORT(dat2_##_name, (_event) | (6 << 5))
 885
 886
 887 static struct attribute *arm_cmn_event_attrs[] = {
 888         CMN_EVENT_DTC(cycles),
 889
 890         /*
 891          * DVM node events conflict with HN-I events in the equivalent PMU
 892          * slot, but our lazy short-cut of using the DTM counter index for
 893          * the PMU index as well happens to avoid that by construction.
 894          */
 895         CMN_EVENT_DVM(CMN600, rxreq_dvmop,              0x01),
 896         CMN_EVENT_DVM(CMN600, rxreq_dvmsync,            0x02),
 897         CMN_EVENT_DVM(CMN600, rxreq_dvmop_vmid_filtered, 0x03),
 898         CMN_EVENT_DVM(CMN600, rxreq_retried,            0x04),
 899         CMN_EVENT_DVM_OCC(CMN600, rxreq_trk_occupancy,  0x05),
 900         CMN_EVENT_DVM(NOT_CMN600, dvmop_tlbi,           0x01),
 901         CMN_EVENT_DVM(NOT_CMN600, dvmop_bpi,            0x02),
 902         CMN_EVENT_DVM(NOT_CMN600, dvmop_pici,           0x03),
 903         CMN_EVENT_DVM(NOT_CMN600, dvmop_vici,           0x04),
 904         CMN_EVENT_DVM(NOT_CMN600, dvmsync,              0x05),
 905         CMN_EVENT_DVM(NOT_CMN600, vmid_filtered,        0x06),
 906         CMN_EVENT_DVM(NOT_CMN600, rndop_filtered,       0x07),
 907         CMN_EVENT_DVM(NOT_CMN600, retry,                0x08),
 908         CMN_EVENT_DVM(NOT_CMN600, txsnp_flitv,          0x09),
 909         CMN_EVENT_DVM(NOT_CMN600, txsnp_stall,          0x0a),
 910         CMN_EVENT_DVM(NOT_CMN600, trkfull,              0x0b),
 911         CMN_EVENT_DVM_OCC(NOT_CMN600, trk_occupancy,    0x0c),
 912         CMN_EVENT_DVM_OCC(CMN700, trk_occupancy_cxha,   0x0d),
 913         CMN_EVENT_DVM_OCC(CMN700, trk_occupancy_pdn,    0x0e),
 914         CMN_EVENT_DVM(CMN700, trk_alloc,                0x0f),
 915         CMN_EVENT_DVM(CMN700, trk_cxha_alloc,           0x10),
 916         CMN_EVENT_DVM(CMN700, trk_pdn_alloc,            0x11),
 917         CMN_EVENT_DVM(CMN700, txsnp_stall_limit,        0x12),
 918         CMN_EVENT_DVM(CMN700, rxsnp_stall_starv,        0x13),
 919         CMN_EVENT_DVM(CMN700, txsnp_sync_stall_op,      0x14),
 920
 921         CMN_EVENT_HNF(CMN_ANY, cache_miss,              0x01),
 922         CMN_EVENT_HNF(CMN_ANY, slc_sf_cache_access,     0x02),
 923         CMN_EVENT_HNF(CMN_ANY, cache_fill,              0x03),
 924         CMN_EVENT_HNF(CMN_ANY, pocq_retry,              0x04),
 925         CMN_EVENT_HNF(CMN_ANY, pocq_reqs_recvd,         0x05),
 926         CMN_EVENT_HNF(CMN_ANY, sf_hit,                  0x06),
 927         CMN_EVENT_HNF(CMN_ANY, sf_evictions,            0x07),
 928         CMN_EVENT_HNF(CMN_ANY, dir_snoops_sent,         0x08),
 929         CMN_EVENT_HNF(CMN_ANY, brd_snoops_sent,         0x09),
 930         CMN_EVENT_HNF(CMN_ANY, slc_eviction,            0x0a),
 931         CMN_EVENT_HNF(CMN_ANY, slc_fill_invalid_way,    0x0b),
 932         CMN_EVENT_HNF(CMN_ANY, mc_retries,              0x0c),
 933         CMN_EVENT_HNF(CMN_ANY, mc_reqs,                 0x0d),
 934         CMN_EVENT_HNF(CMN_ANY, qos_hh_retry,            0x0e),
 935         CMN_EVENT_HNF_OCC(CMN_ANY, qos_pocq_occupancy,  0x0f),
 936         CMN_EVENT_HNF(CMN_ANY, pocq_addrhaz,            0x10),
 937         CMN_EVENT_HNF(CMN_ANY, pocq_atomic_addrhaz,     0x11),
 938         CMN_EVENT_HNF(CMN_ANY, ld_st_swp_adq_full,      0x12),
 939         CMN_EVENT_HNF(CMN_ANY, cmp_adq_full,            0x13),
 940         CMN_EVENT_HNF(CMN_ANY, txdat_stall,             0x14),
 941         CMN_EVENT_HNF(CMN_ANY, txrsp_stall,             0x15),
 942         CMN_EVENT_HNF(CMN_ANY, seq_full,                0x16),
 943         CMN_EVENT_HNF(CMN_ANY, seq_hit,                 0x17),
 944         CMN_EVENT_HNF(CMN_ANY, snp_sent,                0x18),
 945         CMN_EVENT_HNF(CMN_ANY, sfbi_dir_snp_sent,       0x19),
 946         CMN_EVENT_HNF(CMN_ANY, sfbi_brd_snp_sent,       0x1a),
 947         CMN_EVENT_HNF(CMN_ANY, snp_sent_untrk,          0x1b),
 948         CMN_EVENT_HNF(CMN_ANY, intv_dirty,              0x1c),
 949         CMN_EVENT_HNF(CMN_ANY, stash_snp_sent,          0x1d),
 950         CMN_EVENT_HNF(CMN_ANY, stash_data_pull,         0x1e),
 951         CMN_EVENT_HNF(CMN_ANY, snp_fwded,               0x1f),
 952         CMN_EVENT_HNF(NOT_CMN600, atomic_fwd,           0x20),
 953         CMN_EVENT_HNF(NOT_CMN600, mpam_hardlim,         0x21),
 954         CMN_EVENT_HNF(NOT_CMN600, mpam_softlim,         0x22),
 955         CMN_EVENT_HNF(CMN_650ON, snp_sent_cluster,      0x23),
 956         CMN_EVENT_HNF(CMN_650ON, sf_imprecise_evict,    0x24),
 957         CMN_EVENT_HNF(CMN_650ON, sf_evict_shared_line,  0x25),
 958         CMN_EVENT_HNF_CLS(CMN700, pocq_class_occup,     0x26),
 959         CMN_EVENT_HNF_CLS(CMN700, pocq_class_retry,     0x27),
 960         CMN_EVENT_HNF_CLS(CMN700, class_mc_reqs,        0x28),
 961         CMN_EVENT_HNF_CLS(CMN700, class_cgnt_cmin,      0x29),
 962         CMN_EVENT_HNF_SNT(CMN700, sn_throttle,          0x2a),
 963         CMN_EVENT_HNF_SNT(CMN700, sn_throttle_min,      0x2b),
 964         CMN_EVENT_HNF(CMN700, sf_precise_to_imprecise,  0x2c),
 965         CMN_EVENT_HNF(CMN700, snp_intv_cln,             0x2d),
 966         CMN_EVENT_HNF(CMN700, nc_excl,                  0x2e),
 967         CMN_EVENT_HNF(CMN700, excl_mon_ovfl,            0x2f),
 968
 969         CMN_EVENT_HNI(rrt_rd_occ_cnt_ovfl,              0x20),
 970         CMN_EVENT_HNI(rrt_wr_occ_cnt_ovfl,              0x21),
 971         CMN_EVENT_HNI(rdt_rd_occ_cnt_ovfl,              0x22),
 972         CMN_EVENT_HNI(rdt_wr_occ_cnt_ovfl,              0x23),
 973         CMN_EVENT_HNI(wdb_occ_cnt_ovfl,                 0x24),
 974         CMN_EVENT_HNI(rrt_rd_alloc,                     0x25),
 975         CMN_EVENT_HNI(rrt_wr_alloc,                     0x26),
 976         CMN_EVENT_HNI(rdt_rd_alloc,                     0x27),
 977         CMN_EVENT_HNI(rdt_wr_alloc,                     0x28),
 978         CMN_EVENT_HNI(wdb_alloc,                        0x29),
 979         CMN_EVENT_HNI(txrsp_retryack,                   0x2a),
 980         CMN_EVENT_HNI(arvalid_no_arready,               0x2b),
 981         CMN_EVENT_HNI(arready_no_arvalid,               0x2c),
 982         CMN_EVENT_HNI(awvalid_no_awready,               0x2d),
 983         CMN_EVENT_HNI(awready_no_awvalid,               0x2e),
 984         CMN_EVENT_HNI(wvalid_no_wready,                 0x2f),
 985         CMN_EVENT_HNI(txdat_stall,                      0x30),
 986         CMN_EVENT_HNI(nonpcie_serialization,            0x31),
 987         CMN_EVENT_HNI(pcie_serialization,               0x32),
 988
 989         /*
 990          * HN-P events squat on top of the HN-I similarly to DVM events, except
 991          * for being crammed into the same physical node as well. And of course
 992          * where would the fun be if the same events were in the same order...
 993          */
 994         CMN_EVENT_HNP(rrt_wr_occ_cnt_ovfl,              0x01),
 995         CMN_EVENT_HNP(rdt_wr_occ_cnt_ovfl,              0x02),
 996         CMN_EVENT_HNP(wdb_occ_cnt_ovfl,                 0x03),
 997         CMN_EVENT_HNP(rrt_wr_alloc,                     0x04),
 998         CMN_EVENT_HNP(rdt_wr_alloc,                     0x05),
 999         CMN_EVENT_HNP(wdb_alloc,                        0x06),
1000         CMN_EVENT_HNP(awvalid_no_awready,               0x07),
1001         CMN_EVENT_HNP(awready_no_awvalid,               0x08),
1002         CMN_EVENT_HNP(wvalid_no_wready,                 0x09),
1003         CMN_EVENT_HNP(rrt_rd_occ_cnt_ovfl,              0x11),
1004         CMN_EVENT_HNP(rdt_rd_occ_cnt_ovfl,              0x12),
1005         CMN_EVENT_HNP(rrt_rd_alloc,                     0x13),
1006         CMN_EVENT_HNP(rdt_rd_alloc,                     0x14),
1007         CMN_EVENT_HNP(arvalid_no_arready,               0x15),
1008         CMN_EVENT_HNP(arready_no_arvalid,               0x16),
1009
1010         CMN_EVENT_XP(txflit_valid,                      0x01),
1011         CMN_EVENT_XP(txflit_stall,                      0x02),
1012         CMN_EVENT_XP_DAT(partial_dat_flit,              0x03),
1013         /* We treat watchpoints as a special made-up class of XP events */
1014         CMN_EVENT_ATTR(CMN_ANY, watchpoint_up, CMN_TYPE_WP, CMN_WP_UP),
1015         CMN_EVENT_ATTR(CMN_ANY, watchpoint_down, CMN_TYPE_WP, CMN_WP_DOWN),
1016
1017         CMN_EVENT_SBSX(CMN_ANY, rd_req,                 0x01),
1018         CMN_EVENT_SBSX(CMN_ANY, wr_req,                 0x02),
1019         CMN_EVENT_SBSX(CMN_ANY, cmo_req,                0x03),
1020         CMN_EVENT_SBSX(CMN_ANY, txrsp_retryack,         0x04),
1021         CMN_EVENT_SBSX(CMN_ANY, txdat_flitv,            0x05),
1022         CMN_EVENT_SBSX(CMN_ANY, txrsp_flitv,            0x06),
1023         CMN_EVENT_SBSX(CMN_ANY, rd_req_trkr_occ_cnt_ovfl, 0x11),
1024         CMN_EVENT_SBSX(CMN_ANY, wr_req_trkr_occ_cnt_ovfl, 0x12),
1025         CMN_EVENT_SBSX(CMN_ANY, cmo_req_trkr_occ_cnt_ovfl, 0x13),
1026         CMN_EVENT_SBSX(CMN_ANY, wdb_occ_cnt_ovfl,       0x14),
1027         CMN_EVENT_SBSX(CMN_ANY, rd_axi_trkr_occ_cnt_ovfl, 0x15),
1028         CMN_EVENT_SBSX(CMN_ANY, cmo_axi_trkr_occ_cnt_ovfl, 0x16),
1029         CMN_EVENT_SBSX(NOT_CMN600, rdb_occ_cnt_ovfl,    0x17),
1030         CMN_EVENT_SBSX(CMN_ANY, arvalid_no_arready,     0x21),
1031         CMN_EVENT_SBSX(CMN_ANY, awvalid_no_awready,     0x22),
1032         CMN_EVENT_SBSX(CMN_ANY, wvalid_no_wready,       0x23),
1033         CMN_EVENT_SBSX(CMN_ANY, txdat_stall,            0x24),
1034         CMN_EVENT_SBSX(CMN_ANY, txrsp_stall,            0x25),
1035
1036         CMN_EVENT_RNID(CMN_ANY, s0_rdata_beats,         0x01),
1037         CMN_EVENT_RNID(CMN_ANY, s1_rdata_beats,         0x02),
1038         CMN_EVENT_RNID(CMN_ANY, s2_rdata_beats,         0x03),
1039         CMN_EVENT_RNID(CMN_ANY, rxdat_flits,            0x04),
1040         CMN_EVENT_RNID(CMN_ANY, txdat_flits,            0x05),
1041         CMN_EVENT_RNID(CMN_ANY, txreq_flits_total,      0x06),
1042         CMN_EVENT_RNID(CMN_ANY, txreq_flits_retried,    0x07),
1043         CMN_EVENT_RNID(CMN_ANY, rrt_occ_ovfl,           0x08),
1044         CMN_EVENT_RNID(CMN_ANY, wrt_occ_ovfl,           0x09),
1045         CMN_EVENT_RNID(CMN_ANY, txreq_flits_replayed,   0x0a),
1046         CMN_EVENT_RNID(CMN_ANY, wrcancel_sent,          0x0b),
1047         CMN_EVENT_RNID(CMN_ANY, s0_wdata_beats,         0x0c),
1048         CMN_EVENT_RNID(CMN_ANY, s1_wdata_beats,         0x0d),
1049         CMN_EVENT_RNID(CMN_ANY, s2_wdata_beats,         0x0e),
1050         CMN_EVENT_RNID(CMN_ANY, rrt_alloc,              0x0f),
1051         CMN_EVENT_RNID(CMN_ANY, wrt_alloc,              0x10),
1052         CMN_EVENT_RNID(CMN600, rdb_unord,               0x11),
1053         CMN_EVENT_RNID(CMN600, rdb_replay,              0x12),
1054         CMN_EVENT_RNID(CMN600, rdb_hybrid,              0x13),
1055         CMN_EVENT_RNID(CMN600, rdb_ord,                 0x14),
1056         CMN_EVENT_RNID(NOT_CMN600, padb_occ_ovfl,       0x11),
1057         CMN_EVENT_RNID(NOT_CMN600, rpdb_occ_ovfl,       0x12),
1058         CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice1, 0x13),
1059         CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice2, 0x14),
1060         CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice3, 0x15),
1061         CMN_EVENT_RNID(NOT_CMN600, wrt_throttled,       0x16),
1062         CMN_EVENT_RNID(CMN700, ldb_full,                0x17),
1063         CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice0, 0x18),
1064         CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice1, 0x19),
1065         CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice2, 0x1a),
1066         CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice3, 0x1b),
1067         CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice0, 0x1c),
1068         CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice1, 0x1d),
1069         CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice2, 0x1e),
1070         CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice3, 0x1f),
1071         CMN_EVENT_RNID(CMN700, rrt_burst_alloc,         0x20),
1072         CMN_EVENT_RNID(CMN700, awid_hash,               0x21),
1073         CMN_EVENT_RNID(CMN700, atomic_alloc,            0x22),
1074         CMN_EVENT_RNID(CMN700, atomic_occ_ovfl,         0x23),
1075
1076         CMN_EVENT_MTSX(tc_lookup,                       0x01),
1077         CMN_EVENT_MTSX(tc_fill,                         0x02),
1078         CMN_EVENT_MTSX(tc_miss,                         0x03),
1079         CMN_EVENT_MTSX(tdb_forward,                     0x04),
1080         CMN_EVENT_MTSX(tcq_hazard,                      0x05),
1081         CMN_EVENT_MTSX(tcq_rd_alloc,                    0x06),
1082         CMN_EVENT_MTSX(tcq_wr_alloc,                    0x07),
1083         CMN_EVENT_MTSX(tcq_cmo_alloc,                   0x08),
1084         CMN_EVENT_MTSX(axi_rd_req,                      0x09),
1085         CMN_EVENT_MTSX(axi_wr_req,                      0x0a),
1086         CMN_EVENT_MTSX(tcq_occ_cnt_ovfl,                0x0b),
1087         CMN_EVENT_MTSX(tdb_occ_cnt_ovfl,                0x0c),
1088
1089         CMN_EVENT_CXRA(CMN_ANY, rht_occ,                0x01),
1090         CMN_EVENT_CXRA(CMN_ANY, sht_occ,                0x02),
1091         CMN_EVENT_CXRA(CMN_ANY, rdb_occ,                0x03),
1092         CMN_EVENT_CXRA(CMN_ANY, wdb_occ,                0x04),
1093         CMN_EVENT_CXRA(CMN_ANY, ssb_occ,                0x05),
1094         CMN_EVENT_CXRA(CMN_ANY, snp_bcasts,             0x06),
1095         CMN_EVENT_CXRA(CMN_ANY, req_chains,             0x07),
1096         CMN_EVENT_CXRA(CMN_ANY, req_chain_avglen,       0x08),
1097         CMN_EVENT_CXRA(CMN_ANY, chirsp_stalls,          0x09),
1098         CMN_EVENT_CXRA(CMN_ANY, chidat_stalls,          0x0a),
1099         CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link0, 0x0b),
1100         CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link1, 0x0c),
1101         CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link2, 0x0d),
1102         CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link0, 0x0e),
1103         CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link1, 0x0f),
1104         CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link2, 0x10),
1105         CMN_EVENT_CXRA(CMN_ANY, external_chirsp_stalls, 0x11),
1106         CMN_EVENT_CXRA(CMN_ANY, external_chidat_stalls, 0x12),
1107         CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link0, 0x13),
1108         CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link1, 0x14),
1109         CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link2, 0x15),
1110
1111         CMN_EVENT_CXHA(rddatbyp,                        0x21),
1112         CMN_EVENT_CXHA(chirsp_up_stall,                 0x22),
1113         CMN_EVENT_CXHA(chidat_up_stall,                 0x23),
1114         CMN_EVENT_CXHA(snppcrd_link0_stall,             0x24),
1115         CMN_EVENT_CXHA(snppcrd_link1_stall,             0x25),
1116         CMN_EVENT_CXHA(snppcrd_link2_stall,             0x26),
1117         CMN_EVENT_CXHA(reqtrk_occ,                      0x27),
1118         CMN_EVENT_CXHA(rdb_occ,                         0x28),
1119         CMN_EVENT_CXHA(rdbyp_occ,                       0x29),
1120         CMN_EVENT_CXHA(wdb_occ,                         0x2a),
1121         CMN_EVENT_CXHA(snptrk_occ,                      0x2b),
1122         CMN_EVENT_CXHA(sdb_occ,                         0x2c),
1123         CMN_EVENT_CXHA(snphaz_occ,                      0x2d),
1124
1125         CMN_EVENT_CCRA(rht_occ,                         0x41),
1126         CMN_EVENT_CCRA(sht_occ,                         0x42),
1127         CMN_EVENT_CCRA(rdb_occ,                         0x43),
1128         CMN_EVENT_CCRA(wdb_occ,                         0x44),
1129         CMN_EVENT_CCRA(ssb_occ,                         0x45),
1130         CMN_EVENT_CCRA(snp_bcasts,                      0x46),
1131         CMN_EVENT_CCRA(req_chains,                      0x47),
1132         CMN_EVENT_CCRA(req_chain_avglen,                0x48),
1133         CMN_EVENT_CCRA(chirsp_stalls,                   0x49),
1134         CMN_EVENT_CCRA(chidat_stalls,                   0x4a),
1135         CMN_EVENT_CCRA(cxreq_pcrd_stalls_link0,         0x4b),
1136         CMN_EVENT_CCRA(cxreq_pcrd_stalls_link1,         0x4c),
1137         CMN_EVENT_CCRA(cxreq_pcrd_stalls_link2,         0x4d),
1138         CMN_EVENT_CCRA(cxdat_pcrd_stalls_link0,         0x4e),
1139         CMN_EVENT_CCRA(cxdat_pcrd_stalls_link1,         0x4f),
1140         CMN_EVENT_CCRA(cxdat_pcrd_stalls_link2,         0x50),
1141         CMN_EVENT_CCRA(external_chirsp_stalls,          0x51),
1142         CMN_EVENT_CCRA(external_chidat_stalls,          0x52),
1143         CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link0,        0x53),
1144         CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link1,        0x54),
1145         CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link2,        0x55),
1146         CMN_EVENT_CCRA(rht_alloc,                       0x56),
1147         CMN_EVENT_CCRA(sht_alloc,                       0x57),
1148         CMN_EVENT_CCRA(rdb_alloc,                       0x58),
1149         CMN_EVENT_CCRA(wdb_alloc,                       0x59),
1150         CMN_EVENT_CCRA(ssb_alloc,                       0x5a),
1151
1152         CMN_EVENT_CCHA(rddatbyp,                        0x61),
1153         CMN_EVENT_CCHA(chirsp_up_stall,                 0x62),
1154         CMN_EVENT_CCHA(chidat_up_stall,                 0x63),
1155         CMN_EVENT_CCHA(snppcrd_link0_stall,             0x64),
1156         CMN_EVENT_CCHA(snppcrd_link1_stall,             0x65),
1157         CMN_EVENT_CCHA(snppcrd_link2_stall,             0x66),
1158         CMN_EVENT_CCHA(reqtrk_occ,                      0x67),
1159         CMN_EVENT_CCHA(rdb_occ,                         0x68),
1160         CMN_EVENT_CCHA(rdbyp_occ,                       0x69),
1161         CMN_EVENT_CCHA(wdb_occ,                         0x6a),
1162         CMN_EVENT_CCHA(snptrk_occ,                      0x6b),
1163         CMN_EVENT_CCHA(sdb_occ,                         0x6c),
1164         CMN_EVENT_CCHA(snphaz_occ,                      0x6d),
1165         CMN_EVENT_CCHA(reqtrk_alloc,                    0x6e),
1166         CMN_EVENT_CCHA(rdb_alloc,                       0x6f),
1167         CMN_EVENT_CCHA(rdbyp_alloc,                     0x70),
1168         CMN_EVENT_CCHA(wdb_alloc,                       0x71),
1169         CMN_EVENT_CCHA(snptrk_alloc,                    0x72),
1170         CMN_EVENT_CCHA(sdb_alloc,                       0x73),
1171         CMN_EVENT_CCHA(snphaz_alloc,                    0x74),
1172         CMN_EVENT_CCHA(pb_rhu_req_occ,                  0x75),
1173         CMN_EVENT_CCHA(pb_rhu_req_alloc,                0x76),
1174         CMN_EVENT_CCHA(pb_rhu_pcie_req_occ,             0x77),
1175         CMN_EVENT_CCHA(pb_rhu_pcie_req_alloc,           0x78),
1176         CMN_EVENT_CCHA(pb_pcie_wr_req_occ,              0x79),
1177         CMN_EVENT_CCHA(pb_pcie_wr_req_alloc,            0x7a),
1178         CMN_EVENT_CCHA(pb_pcie_reg_req_occ,             0x7b),
1179         CMN_EVENT_CCHA(pb_pcie_reg_req_alloc,           0x7c),
1180         CMN_EVENT_CCHA(pb_pcie_rsvd_req_occ,            0x7d),
1181         CMN_EVENT_CCHA(pb_pcie_rsvd_req_alloc,          0x7e),
1182         CMN_EVENT_CCHA(pb_rhu_dat_occ,                  0x7f),
1183         CMN_EVENT_CCHA(pb_rhu_dat_alloc,                0x80),
1184         CMN_EVENT_CCHA(pb_rhu_pcie_dat_occ,             0x81),
1185         CMN_EVENT_CCHA(pb_rhu_pcie_dat_alloc,           0x82),
1186         CMN_EVENT_CCHA(pb_pcie_wr_dat_occ,              0x83),
1187         CMN_EVENT_CCHA(pb_pcie_wr_dat_alloc,            0x84),
1188
1189         CMN_EVENT_CCLA(rx_cxs,                          0x21),
1190         CMN_EVENT_CCLA(tx_cxs,                          0x22),
1191         CMN_EVENT_CCLA(rx_cxs_avg_size,                 0x23),
1192         CMN_EVENT_CCLA(tx_cxs_avg_size,                 0x24),
1193         CMN_EVENT_CCLA(tx_cxs_lcrd_backpressure,        0x25),
1194         CMN_EVENT_CCLA(link_crdbuf_occ,                 0x26),
1195         CMN_EVENT_CCLA(link_crdbuf_alloc,               0x27),
1196         CMN_EVENT_CCLA(pfwd_rcvr_cxs,                   0x28),
1197         CMN_EVENT_CCLA(pfwd_sndr_num_flits,             0x29),
1198         CMN_EVENT_CCLA(pfwd_sndr_stalls_static_crd,     0x2a),
1199         CMN_EVENT_CCLA(pfwd_sndr_stalls_dynmaic_crd,    0x2b),
1200
1201         CMN_EVENT_HNS_HBT(cache_miss,                   0x01),
1202         CMN_EVENT_HNS_HBT(slc_sf_cache_access,          0x02),
1203         CMN_EVENT_HNS_HBT(cache_fill,                   0x03),
1204         CMN_EVENT_HNS_HBT(pocq_retry,                   0x04),
1205         CMN_EVENT_HNS_HBT(pocq_reqs_recvd,              0x05),
1206         CMN_EVENT_HNS_HBT(sf_hit,                       0x06),
1207         CMN_EVENT_HNS_HBT(sf_evictions,                 0x07),
1208         CMN_EVENT_HNS(dir_snoops_sent,                  0x08),
1209         CMN_EVENT_HNS(brd_snoops_sent,                  0x09),
1210         CMN_EVENT_HNS_HBT(slc_eviction,                 0x0a),
1211         CMN_EVENT_HNS_HBT(slc_fill_invalid_way,         0x0b),
1212         CMN_EVENT_HNS(mc_retries_local,                 0x0c),
1213         CMN_EVENT_HNS_SNH(mc_reqs_local,                0x0d),
1214         CMN_EVENT_HNS(qos_hh_retry,                     0x0e),
1215         CMN_EVENT_HNS_OCC(qos_pocq_occupancy,           0x0f),
1216         CMN_EVENT_HNS(pocq_addrhaz,                     0x10),
1217         CMN_EVENT_HNS(pocq_atomic_addrhaz,              0x11),
1218         CMN_EVENT_HNS(ld_st_swp_adq_full,               0x12),
1219         CMN_EVENT_HNS(cmp_adq_full,                     0x13),
1220         CMN_EVENT_HNS(txdat_stall,                      0x14),
1221         CMN_EVENT_HNS(txrsp_stall,                      0x15),
1222         CMN_EVENT_HNS(seq_full,                         0x16),
1223         CMN_EVENT_HNS(seq_hit,                          0x17),
1224         CMN_EVENT_HNS(snp_sent,                         0x18),
1225         CMN_EVENT_HNS(sfbi_dir_snp_sent,                0x19),
1226         CMN_EVENT_HNS(sfbi_brd_snp_sent,                0x1a),
1227         CMN_EVENT_HNS(intv_dirty,                       0x1c),
1228         CMN_EVENT_HNS(stash_snp_sent,                   0x1d),
1229         CMN_EVENT_HNS(stash_data_pull,                  0x1e),
1230         CMN_EVENT_HNS(snp_fwded,                        0x1f),
1231         CMN_EVENT_HNS(atomic_fwd,                       0x20),
1232         CMN_EVENT_HNS(mpam_hardlim,                     0x21),
1233         CMN_EVENT_HNS(mpam_softlim,                     0x22),
1234         CMN_EVENT_HNS(snp_sent_cluster,                 0x23),
1235         CMN_EVENT_HNS(sf_imprecise_evict,               0x24),
1236         CMN_EVENT_HNS(sf_evict_shared_line,             0x25),
1237         CMN_EVENT_HNS_CLS(pocq_class_occup,             0x26),
1238         CMN_EVENT_HNS_CLS(pocq_class_retry,             0x27),
1239         CMN_EVENT_HNS_CLS(class_mc_reqs_local,          0x28),
1240         CMN_EVENT_HNS_CLS(class_cgnt_cmin,              0x29),
1241         CMN_EVENT_HNS_SNT(sn_throttle,                  0x2a),
1242         CMN_EVENT_HNS_SNT(sn_throttle_min,              0x2b),
1243         CMN_EVENT_HNS(sf_precise_to_imprecise,          0x2c),
1244         CMN_EVENT_HNS(snp_intv_cln,                     0x2d),
1245         CMN_EVENT_HNS(nc_excl,                          0x2e),
1246         CMN_EVENT_HNS(excl_mon_ovfl,                    0x2f),
1247         CMN_EVENT_HNS(snp_req_recvd,                    0x30),
1248         CMN_EVENT_HNS(snp_req_byp_pocq,                 0x31),
1249         CMN_EVENT_HNS(dir_ccgha_snp_sent,               0x32),
1250         CMN_EVENT_HNS(brd_ccgha_snp_sent,               0x33),
1251         CMN_EVENT_HNS(ccgha_snp_stall,                  0x34),
1252         CMN_EVENT_HNS(lbt_req_hardlim,                  0x35),
1253         CMN_EVENT_HNS(hbt_req_hardlim,                  0x36),
1254         CMN_EVENT_HNS(sf_reupdate,                      0x37),
1255         CMN_EVENT_HNS(excl_sf_imprecise,                0x38),
1256         CMN_EVENT_HNS(snp_pocq_addrhaz,                 0x39),
1257         CMN_EVENT_HNS(mc_retries_remote,                0x3a),
1258         CMN_EVENT_HNS_SNH(mc_reqs_remote,               0x3b),
1259         CMN_EVENT_HNS_CLS(class_mc_reqs_remote,         0x3c),
1260
1261         NULL
1262 };
1263
1264 static const struct attribute_group arm_cmn_event_attrs_group = {
1265         .name = "events",
1266         .attrs = arm_cmn_event_attrs,
1267         .is_visible = arm_cmn_event_attr_is_visible,
1268 };
1269
1270 static ssize_t arm_cmn_format_show(struct device *dev,
1271                                    struct device_attribute *attr, char *buf)
1272 {
1273         struct arm_cmn_format_attr *fmt = container_of(attr, typeof(*fmt), attr);
1274         int lo = __ffs(fmt->field), hi = __fls(fmt->field);
1275
1276         if (lo == hi)
1277                 return sysfs_emit(buf, "config:%d\n", lo);
1278
1279         if (!fmt->config)
1280                 return sysfs_emit(buf, "config:%d-%d\n", lo, hi);
1281
1282         return sysfs_emit(buf, "config%d:%d-%d\n", fmt->config, lo, hi);
1283 }
1284
1285 #define _CMN_FORMAT_ATTR(_name, _cfg, _fld)                             \
1286         (&((struct arm_cmn_format_attr[]) {{                            \
1287                 .attr = __ATTR(_name, 0444, arm_cmn_format_show, NULL), \
1288                 .config = _cfg,                                         \
1289                 .field = _fld,                                          \
1290         }})[0].attr.attr)
1291 #define CMN_FORMAT_ATTR(_name, _fld)    _CMN_FORMAT_ATTR(_name, 0, _fld)
1292
1293 static struct attribute *arm_cmn_format_attrs[] = {
1294         CMN_FORMAT_ATTR(type, CMN_CONFIG_TYPE),
1295         CMN_FORMAT_ATTR(eventid, CMN_CONFIG_EVENTID),
1296         CMN_FORMAT_ATTR(occupid, CMN_CONFIG_OCCUPID),
1297         CMN_FORMAT_ATTR(bynodeid, CMN_CONFIG_BYNODEID),
1298         CMN_FORMAT_ATTR(nodeid, CMN_CONFIG_NODEID),
1299
1300         CMN_FORMAT_ATTR(wp_dev_sel, CMN_CONFIG_WP_DEV_SEL),
1301         CMN_FORMAT_ATTR(wp_chn_sel, CMN_CONFIG_WP_CHN_SEL),
1302         CMN_FORMAT_ATTR(wp_grp, CMN_CONFIG_WP_GRP),
1303         CMN_FORMAT_ATTR(wp_exclusive, CMN_CONFIG_WP_EXCLUSIVE),
1304         CMN_FORMAT_ATTR(wp_combine, CMN_CONFIG_WP_COMBINE),
1305
1306         _CMN_FORMAT_ATTR(wp_val, 1, CMN_CONFIG1_WP_VAL),
1307         _CMN_FORMAT_ATTR(wp_mask, 2, CMN_CONFIG2_WP_MASK),
1308
1309         NULL
1310 };
1311
1312 static const struct attribute_group arm_cmn_format_attrs_group = {
1313         .name = "format",
1314         .attrs = arm_cmn_format_attrs,
1315 };
1316
1317 static ssize_t arm_cmn_cpumask_show(struct device *dev,
1318                                     struct device_attribute *attr, char *buf)
1319 {
1320         struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
1321
1322         return cpumap_print_to_pagebuf(true, buf, cpumask_of(cmn->cpu));
1323 }
1324
1325 static struct device_attribute arm_cmn_cpumask_attr =
1326                 __ATTR(cpumask, 0444, arm_cmn_cpumask_show, NULL);
1327
1328 static ssize_t arm_cmn_identifier_show(struct device *dev,
1329                                        struct device_attribute *attr, char *buf)
1330 {
1331         struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
1332
1333         return sysfs_emit(buf, "%03x%02x\n", cmn->part, cmn->rev);
1334 }
1335
1336 static struct device_attribute arm_cmn_identifier_attr =
1337                 __ATTR(identifier, 0444, arm_cmn_identifier_show, NULL);
1338
1339 static struct attribute *arm_cmn_other_attrs[] = {
1340         &arm_cmn_cpumask_attr.attr,
1341         &arm_cmn_identifier_attr.attr,
1342         NULL,
1343 };
1344
1345 static const struct attribute_group arm_cmn_other_attrs_group = {
1346         .attrs = arm_cmn_other_attrs,
1347 };
1348
1349 static const struct attribute_group *arm_cmn_attr_groups[] = {
1350         &arm_cmn_event_attrs_group,
1351         &arm_cmn_format_attrs_group,
1352         &arm_cmn_other_attrs_group,
1353         NULL
1354 };
1355
1356 static int arm_cmn_find_free_wp_idx(struct arm_cmn_dtm *dtm,
1357                                     struct perf_event *event)
1358 {
1359         int wp_idx = CMN_EVENT_EVENTID(event);
1360
1361         if (dtm->wp_event[wp_idx] >= 0)
1362                 if (dtm->wp_event[++wp_idx] >= 0)
1363                         return -ENOSPC;
1364
1365         return wp_idx;
1366 }
1367
1368 static int arm_cmn_get_assigned_wp_idx(struct perf_event *event,
1369                                        struct arm_cmn_hw_event *hw,
1370                                        unsigned int pos)
1371 {
1372         return CMN_EVENT_EVENTID(event) + arm_cmn_get_wp_idx(hw->wp_idx, pos);
1373 }
1374
1375 static void arm_cmn_claim_wp_idx(struct arm_cmn_dtm *dtm,
1376                                  struct perf_event *event,
1377                                  unsigned int dtc, int wp_idx,
1378                                  unsigned int pos)
1379 {
1380         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1381
1382         dtm->wp_event[wp_idx] = hw->dtc_idx[dtc];
1383         arm_cmn_set_wp_idx(hw->wp_idx, pos, wp_idx - CMN_EVENT_EVENTID(event));
1384 }
1385
1386 static u32 arm_cmn_wp_config(struct perf_event *event, int wp_idx)
1387 {
1388         u32 config;
1389         u32 dev = CMN_EVENT_WP_DEV_SEL(event);
1390         u32 chn = CMN_EVENT_WP_CHN_SEL(event);
1391         u32 grp = CMN_EVENT_WP_GRP(event);
1392         u32 exc = CMN_EVENT_WP_EXCLUSIVE(event);
1393         u32 combine = CMN_EVENT_WP_COMBINE(event);
1394         bool is_cmn600 = to_cmn(event->pmu)->part == PART_CMN600;
1395
1396         /* CMN-600 supports only primary and secondary matching groups */
1397         if (is_cmn600)
1398                 grp &= 1;
1399
1400         config = FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL, dev) |
1401                  FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_CHN_SEL, chn) |
1402                  FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_GRP, grp) |
1403                  FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL2, dev >> 1);
1404         if (exc)
1405                 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_EXCLUSIVE :
1406                                       CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE;
1407
1408         /*  wp_combine is available only on WP0 and WP2 */
1409         if (combine && !(wp_idx & 0x1))
1410                 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_COMBINE :
1411                                       CMN_DTM_WPn_CONFIG_WP_COMBINE;
1412         return config;
1413 }
1414
1415 static void arm_cmn_set_state(struct arm_cmn *cmn, u32 state)
1416 {
1417         if (!cmn->state)
1418                 writel_relaxed(0, cmn->dtc[0].base + CMN_DT_PMCR);
1419         cmn->state |= state;
1420 }
1421
1422 static void arm_cmn_clear_state(struct arm_cmn *cmn, u32 state)
1423 {
1424         cmn->state &= ~state;
1425         if (!cmn->state)
1426                 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN,
1427                                cmn->dtc[0].base + CMN_DT_PMCR);
1428 }
1429
1430 static void arm_cmn_pmu_enable(struct pmu *pmu)
1431 {
1432         arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_DISABLED);
1433 }
1434
1435 static void arm_cmn_pmu_disable(struct pmu *pmu)
1436 {
1437         arm_cmn_set_state(to_cmn(pmu), CMN_STATE_DISABLED);
1438 }
1439
1440 static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw,
1441                             bool snapshot)
1442 {
1443         struct arm_cmn_dtm *dtm = NULL;
1444         struct arm_cmn_node *dn;
1445         unsigned int i, offset, dtm_idx;
1446         u64 reg, count = 0;
1447
1448         offset = snapshot ? CMN_DTM_PMEVCNTSR : CMN_DTM_PMEVCNT;
1449         for_each_hw_dn(hw, dn, i) {
1450                 if (dtm != &cmn->dtms[dn->dtm]) {
1451                         dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset;
1452                         reg = readq_relaxed(dtm->base + offset);
1453                 }
1454                 dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1455                 count += (u16)(reg >> (dtm_idx * 16));
1456         }
1457         return count;
1458 }
1459
1460 static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc)
1461 {
1462         u64 val = readq_relaxed(dtc->base + CMN_DT_PMCCNTR);
1463
1464         writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR);
1465         return (val - CMN_CC_INIT) & ((CMN_CC_INIT << 1) - 1);
1466 }
1467
1468 static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx)
1469 {
1470         u32 val, pmevcnt = CMN_DT_PMEVCNT(idx);
1471
1472         val = readl_relaxed(dtc->base + pmevcnt);
1473         writel_relaxed(CMN_COUNTER_INIT, dtc->base + pmevcnt);
1474         return val - CMN_COUNTER_INIT;
1475 }
1476
1477 static void arm_cmn_init_counter(struct perf_event *event)
1478 {
1479         struct arm_cmn *cmn = to_cmn(event->pmu);
1480         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1481         u64 count;
1482
1483         for_each_hw_dtc_idx(hw, i, idx) {
1484                 writel_relaxed(CMN_COUNTER_INIT, cmn->dtc[i].base + CMN_DT_PMEVCNT(idx));
1485                 cmn->dtc[i].counters[idx] = event;
1486         }
1487
1488         count = arm_cmn_read_dtm(cmn, hw, false);
1489         local64_set(&event->hw.prev_count, count);
1490 }
1491
1492 static void arm_cmn_event_read(struct perf_event *event)
1493 {
1494         struct arm_cmn *cmn = to_cmn(event->pmu);
1495         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1496         u64 delta, new, prev;
1497         unsigned long flags;
1498
1499         if (CMN_EVENT_TYPE(event) == CMN_TYPE_DTC) {
1500                 delta = arm_cmn_read_cc(cmn->dtc + hw->dtc_idx[0]);
1501                 local64_add(delta, &event->count);
1502                 return;
1503         }
1504         new = arm_cmn_read_dtm(cmn, hw, false);
1505         prev = local64_xchg(&event->hw.prev_count, new);
1506
1507         delta = new - prev;
1508
1509         local_irq_save(flags);
1510         for_each_hw_dtc_idx(hw, i, idx) {
1511                 new = arm_cmn_read_counter(cmn->dtc + i, idx);
1512                 delta += new << 16;
1513         }
1514         local_irq_restore(flags);
1515         local64_add(delta, &event->count);
1516 }
1517
1518 static int arm_cmn_set_event_sel_hi(struct arm_cmn_node *dn,
1519                                     enum cmn_filter_select fsel, u8 occupid)
1520 {
1521         u64 reg;
1522
1523         if (fsel == SEL_NONE)
1524                 return 0;
1525
1526         if (!dn->occupid[fsel].count) {
1527                 dn->occupid[fsel].val = occupid;
1528                 reg = FIELD_PREP(CMN__PMU_CBUSY_SNTHROTTLE_SEL,
1529                                  dn->occupid[SEL_CBUSY_SNTHROTTLE_SEL].val) |
1530                       FIELD_PREP(CMN__PMU_SN_HOME_SEL,
1531                                  dn->occupid[SEL_SN_HOME_SEL].val) |
1532                       FIELD_PREP(CMN__PMU_HBT_LBT_SEL,
1533                                  dn->occupid[SEL_HBT_LBT_SEL].val) |
1534                       FIELD_PREP(CMN__PMU_CLASS_OCCUP_ID,
1535                                  dn->occupid[SEL_CLASS_OCCUP_ID].val) |
1536                       FIELD_PREP(CMN__PMU_OCCUP1_ID,
1537                                  dn->occupid[SEL_OCCUP1ID].val);
1538                 writel_relaxed(reg >> 32, dn->pmu_base + CMN_PMU_EVENT_SEL + 4);
1539         } else if (dn->occupid[fsel].val != occupid) {
1540                 return -EBUSY;
1541         }
1542         dn->occupid[fsel].count++;
1543         return 0;
1544 }
1545
1546 static void arm_cmn_set_event_sel_lo(struct arm_cmn_node *dn, int dtm_idx,
1547                                      int eventid, bool wide_sel)
1548 {
1549         if (wide_sel) {
1550                 dn->event_w[dtm_idx] = eventid;
1551                 writeq_relaxed(le64_to_cpu(dn->event_sel_w), dn->pmu_base + CMN_PMU_EVENT_SEL);
1552         } else {
1553                 dn->event[dtm_idx] = eventid;
1554                 writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL);
1555         }
1556 }
1557
1558 static void arm_cmn_event_start(struct perf_event *event, int flags)
1559 {
1560         struct arm_cmn *cmn = to_cmn(event->pmu);
1561         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1562         struct arm_cmn_node *dn;
1563         enum cmn_node_type type = CMN_EVENT_TYPE(event);
1564         int i;
1565
1566         if (type == CMN_TYPE_DTC) {
1567                 i = hw->dtc_idx[0];
1568                 writeq_relaxed(CMN_CC_INIT, cmn->dtc[i].base + CMN_DT_PMCCNTR);
1569                 cmn->dtc[i].cc_active = true;
1570         } else if (type == CMN_TYPE_WP) {
1571                 u64 val = CMN_EVENT_WP_VAL(event);
1572                 u64 mask = CMN_EVENT_WP_MASK(event);
1573
1574                 for_each_hw_dn(hw, dn, i) {
1575                         void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset);
1576                         int wp_idx = arm_cmn_get_assigned_wp_idx(event, hw, i);
1577
1578                         writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx));
1579                         writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx));
1580                 }
1581         } else for_each_hw_dn(hw, dn, i) {
1582                 int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1583
1584                 arm_cmn_set_event_sel_lo(dn, dtm_idx, CMN_EVENT_EVENTID(event),
1585                                          hw->wide_sel);
1586         }
1587 }
1588
1589 static void arm_cmn_event_stop(struct perf_event *event, int flags)
1590 {
1591         struct arm_cmn *cmn = to_cmn(event->pmu);
1592         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1593         struct arm_cmn_node *dn;
1594         enum cmn_node_type type = CMN_EVENT_TYPE(event);
1595         int i;
1596
1597         if (type == CMN_TYPE_DTC) {
1598                 i = hw->dtc_idx[0];
1599                 cmn->dtc[i].cc_active = false;
1600         } else if (type == CMN_TYPE_WP) {
1601                 for_each_hw_dn(hw, dn, i) {
1602                         void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset);
1603                         int wp_idx = arm_cmn_get_assigned_wp_idx(event, hw, i);
1604
1605                         writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx));
1606                         writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx));
1607                 }
1608         } else for_each_hw_dn(hw, dn, i) {
1609                 int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1610
1611                 arm_cmn_set_event_sel_lo(dn, dtm_idx, 0, hw->wide_sel);
1612         }
1613
1614         arm_cmn_event_read(event);
1615 }
1616
1617 struct arm_cmn_val {
1618         u8 dtm_count[CMN_MAX_DTMS];
1619         u8 occupid[CMN_MAX_DTMS][SEL_MAX];
1620         u8 wp[CMN_MAX_DTMS][4];
1621         u8 wp_combine[CMN_MAX_DTMS][2];
1622         int dtc_count[CMN_MAX_DTCS];
1623         bool cycles;
1624 };
1625
1626 static int arm_cmn_val_find_free_wp_config(struct perf_event *event,
1627                                           struct arm_cmn_val *val, int dtm)
1628 {
1629         int wp_idx = CMN_EVENT_EVENTID(event);
1630
1631         if (val->wp[dtm][wp_idx])
1632                 if (val->wp[dtm][++wp_idx])
1633                         return -ENOSPC;
1634
1635         return wp_idx;
1636 }
1637
1638 static void arm_cmn_val_add_event(struct arm_cmn *cmn, struct arm_cmn_val *val,
1639                                   struct perf_event *event)
1640 {
1641         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1642         struct arm_cmn_node *dn;
1643         enum cmn_node_type type;
1644         int i;
1645
1646         if (is_software_event(event))
1647                 return;
1648
1649         type = CMN_EVENT_TYPE(event);
1650         if (type == CMN_TYPE_DTC) {
1651                 val->cycles = true;
1652                 return;
1653         }
1654
1655         for_each_hw_dtc_idx(hw, dtc, idx)
1656                 val->dtc_count[dtc]++;
1657
1658         for_each_hw_dn(hw, dn, i) {
1659                 int wp_idx, dtm = dn->dtm, sel = hw->filter_sel;
1660
1661                 val->dtm_count[dtm]++;
1662
1663                 if (sel > SEL_NONE)
1664                         val->occupid[dtm][sel] = CMN_EVENT_OCCUPID(event) + 1;
1665
1666                 if (type != CMN_TYPE_WP)
1667                         continue;
1668
1669                 wp_idx = arm_cmn_val_find_free_wp_config(event, val, dtm);
1670                 val->wp[dtm][wp_idx] = 1;
1671                 val->wp_combine[dtm][wp_idx >> 1] += !!CMN_EVENT_WP_COMBINE(event);
1672         }
1673 }
1674
1675 static int arm_cmn_validate_group(struct arm_cmn *cmn, struct perf_event *event)
1676 {
1677         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1678         struct arm_cmn_node *dn;
1679         struct perf_event *sibling, *leader = event->group_leader;
1680         enum cmn_node_type type;
1681         struct arm_cmn_val *val;
1682         int i, ret = -EINVAL;
1683
1684         if (leader == event)
1685                 return 0;
1686
1687         if (event->pmu != leader->pmu && !is_software_event(leader))
1688                 return -EINVAL;
1689
1690         val = kzalloc(sizeof(*val), GFP_KERNEL);
1691         if (!val)
1692                 return -ENOMEM;
1693
1694         arm_cmn_val_add_event(cmn, val, leader);
1695
1696         for_each_sibling_event(sibling, leader)
1697                 arm_cmn_val_add_event(cmn, val, sibling);
1698
1699         type = CMN_EVENT_TYPE(event);
1700         if (type == CMN_TYPE_DTC) {
1701                 ret = val->cycles ? -EINVAL : 0;
1702                 goto done;
1703         }
1704
1705         for (i = 0; i < CMN_MAX_DTCS; i++)
1706                 if (val->dtc_count[i] == CMN_DT_NUM_COUNTERS)
1707                         goto done;
1708
1709         for_each_hw_dn(hw, dn, i) {
1710                 int wp_idx, dtm = dn->dtm, sel = hw->filter_sel;
1711
1712                 if (val->dtm_count[dtm] == CMN_DTM_NUM_COUNTERS)
1713                         goto done;
1714
1715                 if (sel > SEL_NONE && val->occupid[dtm][sel] &&
1716                     val->occupid[dtm][sel] != CMN_EVENT_OCCUPID(event) + 1)
1717                         goto done;
1718
1719                 if (type != CMN_TYPE_WP)
1720                         continue;
1721
1722                 wp_idx = arm_cmn_val_find_free_wp_config(event, val, dtm);
1723                 if (wp_idx < 0)
1724                         goto done;
1725
1726                 if (wp_idx & 1 &&
1727                     val->wp_combine[dtm][wp_idx >> 1] != !!CMN_EVENT_WP_COMBINE(event))
1728                         goto done;
1729         }
1730
1731         ret = 0;
1732 done:
1733         kfree(val);
1734         return ret;
1735 }
1736
1737 static enum cmn_filter_select arm_cmn_filter_sel(const struct arm_cmn *cmn,
1738                                                  enum cmn_node_type type,
1739                                                  unsigned int eventid)
1740 {
1741         struct arm_cmn_event_attr *e;
1742         enum cmn_model model = arm_cmn_model(cmn);
1743
1744         for (int i = 0; i < ARRAY_SIZE(arm_cmn_event_attrs) - 1; i++) {
1745                 e = container_of(arm_cmn_event_attrs[i], typeof(*e), attr.attr);
1746                 if (e->model & model && e->type == type && e->eventid == eventid)
1747                         return e->fsel;
1748         }
1749         return SEL_NONE;
1750 }
1751
1752
1753 static int arm_cmn_event_init(struct perf_event *event)
1754 {
1755         struct arm_cmn *cmn = to_cmn(event->pmu);
1756         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1757         struct arm_cmn_node *dn;
1758         enum cmn_node_type type;
1759         bool bynodeid;
1760         u16 nodeid, eventid;
1761
1762         if (event->attr.type != event->pmu->type)
1763                 return -ENOENT;
1764
1765         if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
1766                 return -EINVAL;
1767
1768         event->cpu = cmn->cpu;
1769         if (event->cpu < 0)
1770                 return -EINVAL;
1771
1772         type = CMN_EVENT_TYPE(event);
1773         /* DTC events (i.e. cycles) already have everything they need */
1774         if (type == CMN_TYPE_DTC)
1775                 return arm_cmn_validate_group(cmn, event);
1776
1777         eventid = CMN_EVENT_EVENTID(event);
1778         /* For watchpoints we need the actual XP node here */
1779         if (type == CMN_TYPE_WP) {
1780                 type = CMN_TYPE_XP;
1781                 /* ...and we need a "real" direction */
1782                 if (eventid != CMN_WP_UP && eventid != CMN_WP_DOWN)
1783                         return -EINVAL;
1784                 /* ...but the DTM may depend on which port we're watching */
1785                 if (cmn->multi_dtm)
1786                         hw->dtm_offset = CMN_EVENT_WP_DEV_SEL(event) / 2;
1787         } else if (type == CMN_TYPE_XP && cmn->part == PART_CMN700) {
1788                 hw->wide_sel = true;
1789         }
1790
1791         /* This is sufficiently annoying to recalculate, so cache it */
1792         hw->filter_sel = arm_cmn_filter_sel(cmn, type, eventid);
1793
1794         bynodeid = CMN_EVENT_BYNODEID(event);
1795         nodeid = CMN_EVENT_NODEID(event);
1796
1797         hw->dn = arm_cmn_node(cmn, type);
1798         if (!hw->dn)
1799                 return -EINVAL;
1800
1801         memset(hw->dtc_idx, -1, sizeof(hw->dtc_idx));
1802         for (dn = hw->dn; dn->type == type; dn++) {
1803                 if (bynodeid && dn->id != nodeid) {
1804                         hw->dn++;
1805                         continue;
1806                 }
1807                 hw->num_dns++;
1808                 if (dn->dtc < 0)
1809                         memset(hw->dtc_idx, 0, cmn->num_dtcs);
1810                 else
1811                         hw->dtc_idx[dn->dtc] = 0;
1812
1813                 if (bynodeid)
1814                         break;
1815         }
1816
1817         if (!hw->num_dns) {
1818                 struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, nodeid);
1819
1820                 dev_dbg(cmn->dev, "invalid node 0x%x (%d,%d,%d,%d) type 0x%x\n",
1821                         nodeid, nid.x, nid.y, nid.port, nid.dev, type);
1822                 return -EINVAL;
1823         }
1824
1825         return arm_cmn_validate_group(cmn, event);
1826 }
1827
1828 static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event,
1829                                 int i)
1830 {
1831         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1832         enum cmn_node_type type = CMN_EVENT_TYPE(event);
1833
1834         while (i--) {
1835                 struct arm_cmn_dtm *dtm = &cmn->dtms[hw->dn[i].dtm] + hw->dtm_offset;
1836                 unsigned int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1837
1838                 if (type == CMN_TYPE_WP) {
1839                         int wp_idx = arm_cmn_get_assigned_wp_idx(event, hw, i);
1840
1841                         dtm->wp_event[wp_idx] = -1;
1842                 }
1843
1844                 if (hw->filter_sel > SEL_NONE)
1845                         hw->dn[i].occupid[hw->filter_sel].count--;
1846
1847                 dtm->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx);
1848                 writel_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG);
1849         }
1850         memset(hw->dtm_idx, 0, sizeof(hw->dtm_idx));
1851         memset(hw->wp_idx, 0, sizeof(hw->wp_idx));
1852
1853         for_each_hw_dtc_idx(hw, j, idx)
1854                 cmn->dtc[j].counters[idx] = NULL;
1855 }
1856
1857 static int arm_cmn_event_add(struct perf_event *event, int flags)
1858 {
1859         struct arm_cmn *cmn = to_cmn(event->pmu);
1860         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1861         struct arm_cmn_node *dn;
1862         enum cmn_node_type type = CMN_EVENT_TYPE(event);
1863         unsigned int input_sel, i = 0;
1864
1865         if (type == CMN_TYPE_DTC) {
1866                 while (cmn->dtc[i].cycles)
1867                         if (++i == cmn->num_dtcs)
1868                                 return -ENOSPC;
1869
1870                 cmn->dtc[i].cycles = event;
1871                 hw->dtc_idx[0] = i;
1872
1873                 if (flags & PERF_EF_START)
1874                         arm_cmn_event_start(event, 0);
1875                 return 0;
1876         }
1877
1878         /* Grab the global counters first... */
1879         for_each_hw_dtc_idx(hw, j, idx) {
1880                 if (cmn->part == PART_CMN600 && j > 0) {
1881                         idx = hw->dtc_idx[0];
1882                 } else {
1883                         idx = 0;
1884                         while (cmn->dtc[j].counters[idx])
1885                                 if (++idx == CMN_DT_NUM_COUNTERS)
1886                                         return -ENOSPC;
1887                 }
1888                 hw->dtc_idx[j] = idx;
1889         }
1890
1891         /* ...then the local counters to feed them */
1892         for_each_hw_dn(hw, dn, i) {
1893                 struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset;
1894                 unsigned int dtm_idx, shift, d = max_t(int, dn->dtc, 0);
1895                 u64 reg;
1896
1897                 dtm_idx = 0;
1898                 while (dtm->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx))
1899                         if (++dtm_idx == CMN_DTM_NUM_COUNTERS)
1900                                 goto free_dtms;
1901
1902                 if (type == CMN_TYPE_XP) {
1903                         input_sel = CMN__PMEVCNT0_INPUT_SEL_XP + dtm_idx;
1904                 } else if (type == CMN_TYPE_WP) {
1905                         int tmp, wp_idx;
1906                         u32 cfg;
1907
1908                         wp_idx = arm_cmn_find_free_wp_idx(dtm, event);
1909                         if (wp_idx < 0)
1910                                 goto free_dtms;
1911
1912                         cfg = arm_cmn_wp_config(event, wp_idx);
1913
1914                         tmp = dtm->wp_event[wp_idx ^ 1];
1915                         if (tmp >= 0 && CMN_EVENT_WP_COMBINE(event) !=
1916                                         CMN_EVENT_WP_COMBINE(cmn->dtc[d].counters[tmp]))
1917                                 goto free_dtms;
1918
1919                         input_sel = CMN__PMEVCNT0_INPUT_SEL_WP + wp_idx;
1920
1921                         arm_cmn_claim_wp_idx(dtm, event, d, wp_idx, i);
1922                         writel_relaxed(cfg, dtm->base + CMN_DTM_WPn_CONFIG(wp_idx));
1923                 } else {
1924                         struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id);
1925
1926                         if (cmn->multi_dtm)
1927                                 nid.port %= 2;
1928
1929                         input_sel = CMN__PMEVCNT0_INPUT_SEL_DEV + dtm_idx +
1930                                     (nid.port << 4) + (nid.dev << 2);
1931
1932                         if (arm_cmn_set_event_sel_hi(dn, hw->filter_sel, CMN_EVENT_OCCUPID(event)))
1933                                 goto free_dtms;
1934                 }
1935
1936                 arm_cmn_set_index(hw->dtm_idx, i, dtm_idx);
1937
1938                 dtm->input_sel[dtm_idx] = input_sel;
1939                 shift = CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(dtm_idx);
1940                 dtm->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift);
1941                 dtm->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, hw->dtc_idx[d]) << shift;
1942                 dtm->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx);
1943                 reg = (u64)le32_to_cpu(dtm->pmu_config_high) << 32 | dtm->pmu_config_low;
1944                 writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG);
1945         }
1946
1947         /* Go go go! */
1948         arm_cmn_init_counter(event);
1949
1950         if (flags & PERF_EF_START)
1951                 arm_cmn_event_start(event, 0);
1952
1953         return 0;
1954
1955 free_dtms:
1956         arm_cmn_event_clear(cmn, event, i);
1957         return -ENOSPC;
1958 }
1959
1960 static void arm_cmn_event_del(struct perf_event *event, int flags)
1961 {
1962         struct arm_cmn *cmn = to_cmn(event->pmu);
1963         struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1964         enum cmn_node_type type = CMN_EVENT_TYPE(event);
1965
1966         arm_cmn_event_stop(event, PERF_EF_UPDATE);
1967
1968         if (type == CMN_TYPE_DTC)
1969                 cmn->dtc[hw->dtc_idx[0]].cycles = NULL;
1970         else
1971                 arm_cmn_event_clear(cmn, event, hw->num_dns);
1972 }
1973
1974 /*
1975  * We stop the PMU for both add and read, to avoid skew across DTM counters.
1976  * In theory we could use snapshots to read without stopping, but then it
1977  * becomes a lot trickier to deal with overlow and racing against interrupts,
1978  * plus it seems they don't work properly on some hardware anyway :(
1979  */
1980 static void arm_cmn_start_txn(struct pmu *pmu, unsigned int flags)
1981 {
1982         arm_cmn_set_state(to_cmn(pmu), CMN_STATE_TXN);
1983 }
1984
1985 static void arm_cmn_end_txn(struct pmu *pmu)
1986 {
1987         arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_TXN);
1988 }
1989
1990 static int arm_cmn_commit_txn(struct pmu *pmu)
1991 {
1992         arm_cmn_end_txn(pmu);
1993         return 0;
1994 }
1995
1996 static void arm_cmn_migrate(struct arm_cmn *cmn, unsigned int cpu)
1997 {
1998         unsigned int i;
1999
2000         perf_pmu_migrate_context(&cmn->pmu, cmn->cpu, cpu);
2001         for (i = 0; i < cmn->num_dtcs; i++)
2002                 irq_set_affinity(cmn->dtc[i].irq, cpumask_of(cpu));
2003         cmn->cpu = cpu;
2004 }
2005
2006 static int arm_cmn_pmu_online_cpu(unsigned int cpu, struct hlist_node *cpuhp_node)
2007 {
2008         struct arm_cmn *cmn;
2009         int node;
2010
2011         cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node);
2012         node = dev_to_node(cmn->dev);
2013         if (node != NUMA_NO_NODE && cpu_to_node(cmn->cpu) != node && cpu_to_node(cpu) == node)
2014                 arm_cmn_migrate(cmn, cpu);
2015         return 0;
2016 }
2017
2018 static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *cpuhp_node)
2019 {
2020         struct arm_cmn *cmn;
2021         unsigned int target;
2022         int node;
2023
2024         cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node);
2025         if (cpu != cmn->cpu)
2026                 return 0;
2027
2028         node = dev_to_node(cmn->dev);
2029
2030         target = cpumask_any_and_but(cpumask_of_node(node), cpu_online_mask, cpu);
2031         if (target >= nr_cpu_ids)
2032                 target = cpumask_any_but(cpu_online_mask, cpu);
2033
2034         if (target < nr_cpu_ids)
2035                 arm_cmn_migrate(cmn, target);
2036
2037         return 0;
2038 }
2039
2040 static irqreturn_t arm_cmn_handle_irq(int irq, void *dev_id)
2041 {
2042         struct arm_cmn_dtc *dtc = dev_id;
2043         irqreturn_t ret = IRQ_NONE;
2044
2045         for (;;) {
2046                 u32 status = readl_relaxed(dtc->base + CMN_DT_PMOVSR);
2047                 u64 delta;
2048                 int i;
2049
2050                 for (i = 0; i < CMN_DT_NUM_COUNTERS; i++) {
2051                         if (status & (1U << i)) {
2052                                 ret = IRQ_HANDLED;
2053                                 if (WARN_ON(!dtc->counters[i]))
2054                                         continue;
2055                                 delta = (u64)arm_cmn_read_counter(dtc, i) << 16;
2056                                 local64_add(delta, &dtc->counters[i]->count);
2057                         }
2058                 }
2059
2060                 if (status & (1U << CMN_DT_NUM_COUNTERS)) {
2061                         ret = IRQ_HANDLED;
2062                         if (dtc->cc_active && !WARN_ON(!dtc->cycles)) {
2063                                 delta = arm_cmn_read_cc(dtc);
2064                                 local64_add(delta, &dtc->cycles->count);
2065                         }
2066                 }
2067
2068                 writel_relaxed(status, dtc->base + CMN_DT_PMOVSR_CLR);
2069
2070                 if (!dtc->irq_friend)
2071                         return ret;
2072                 dtc += dtc->irq_friend;
2073         }
2074 }
2075
2076 /* We can reasonably accommodate DTCs of the same CMN sharing IRQs */
2077 static int arm_cmn_init_irqs(struct arm_cmn *cmn)
2078 {
2079         int i, j, irq, err;
2080
2081         for (i = 0; i < cmn->num_dtcs; i++) {
2082                 irq = cmn->dtc[i].irq;
2083                 for (j = i; j--; ) {
2084                         if (cmn->dtc[j].irq == irq) {
2085                                 cmn->dtc[j].irq_friend = i - j;
2086                                 goto next;
2087                         }
2088                 }
2089                 err = devm_request_irq(cmn->dev, irq, arm_cmn_handle_irq,
2090                                        IRQF_NOBALANCING | IRQF_NO_THREAD,
2091                                        dev_name(cmn->dev), &cmn->dtc[i]);
2092                 if (err)
2093                         return err;
2094
2095                 err = irq_set_affinity(irq, cpumask_of(cmn->cpu));
2096                 if (err)
2097                         return err;
2098         next:
2099                 ; /* isn't C great? */
2100         }
2101         return 0;
2102 }
2103
2104 static void arm_cmn_init_dtm(struct arm_cmn_dtm *dtm, struct arm_cmn_node *xp, int idx)
2105 {
2106         int i;
2107
2108         dtm->base = xp->pmu_base + CMN_DTM_OFFSET(idx);
2109         dtm->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN;
2110         writeq_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG);
2111         for (i = 0; i < 4; i++) {
2112                 dtm->wp_event[i] = -1;
2113                 writeq_relaxed(0, dtm->base + CMN_DTM_WPn_MASK(i));
2114                 writeq_relaxed(~0ULL, dtm->base + CMN_DTM_WPn_VAL(i));
2115         }
2116 }
2117
2118 static int arm_cmn_init_dtc(struct arm_cmn *cmn, struct arm_cmn_node *dn, int idx)
2119 {
2120         struct arm_cmn_dtc *dtc = cmn->dtc + idx;
2121
2122         dtc->base = dn->pmu_base - CMN_PMU_OFFSET;
2123         dtc->irq = platform_get_irq(to_platform_device(cmn->dev), idx);
2124         if (dtc->irq < 0)
2125                 return dtc->irq;
2126
2127         writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL);
2128         writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, dtc->base + CMN_DT_PMCR);
2129         writeq_relaxed(0, dtc->base + CMN_DT_PMCCNTR);
2130         writel_relaxed(0x1ff, dtc->base + CMN_DT_PMOVSR_CLR);
2131
2132         return 0;
2133 }
2134
2135 static int arm_cmn_node_cmp(const void *a, const void *b)
2136 {
2137         const struct arm_cmn_node *dna = a, *dnb = b;
2138         int cmp;
2139
2140         cmp = dna->type - dnb->type;
2141         if (!cmp)
2142                 cmp = dna->logid - dnb->logid;
2143         return cmp;
2144 }
2145
2146 static int arm_cmn_init_dtcs(struct arm_cmn *cmn)
2147 {
2148         struct arm_cmn_node *dn, *xp;
2149         int dtc_idx = 0;
2150
2151         cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL);
2152         if (!cmn->dtc)
2153                 return -ENOMEM;
2154
2155         sort(cmn->dns, cmn->num_dns, sizeof(cmn->dns[0]), arm_cmn_node_cmp, NULL);
2156
2157         cmn->xps = arm_cmn_node(cmn, CMN_TYPE_XP);
2158
2159         if (cmn->part == PART_CMN600 && cmn->num_dtcs > 1) {
2160                 /* We do at least know that a DTC's XP must be in that DTC's domain */
2161                 dn = arm_cmn_node(cmn, CMN_TYPE_DTC);
2162                 for (int i = 0; i < cmn->num_dtcs; i++)
2163                         arm_cmn_node_to_xp(cmn, dn + i)->dtc = i;
2164         }
2165
2166         for (dn = cmn->dns; dn->type; dn++) {
2167                 if (dn->type == CMN_TYPE_XP)
2168                         continue;
2169
2170                 xp = arm_cmn_node_to_xp(cmn, dn);
2171                 dn->dtc = xp->dtc;
2172                 dn->dtm = xp->dtm;
2173                 if (cmn->multi_dtm)
2174                         dn->dtm += arm_cmn_nid(cmn, dn->id).port / 2;
2175
2176                 if (dn->type == CMN_TYPE_DTC) {
2177                         int err = arm_cmn_init_dtc(cmn, dn, dtc_idx++);
2178
2179                         if (err)
2180                                 return err;
2181                 }
2182
2183                 /* To the PMU, RN-Ds don't add anything over RN-Is, so smoosh them together */
2184                 if (dn->type == CMN_TYPE_RND)
2185                         dn->type = CMN_TYPE_RNI;
2186
2187                 /* We split the RN-I off already, so let the CCLA part match CCLA events */
2188                 if (dn->type == CMN_TYPE_CCLA_RNI)
2189                         dn->type = CMN_TYPE_CCLA;
2190         }
2191
2192         arm_cmn_set_state(cmn, CMN_STATE_DISABLED);
2193
2194         return 0;
2195 }
2196
2197 static unsigned int arm_cmn_dtc_domain(struct arm_cmn *cmn, void __iomem *xp_region)
2198 {
2199         int offset = CMN_DTM_UNIT_INFO;
2200
2201         if (cmn->part == PART_CMN650 || cmn->part == PART_CI700)
2202                 offset = CMN650_DTM_UNIT_INFO;
2203
2204         return FIELD_GET(CMN_DTM_UNIT_INFO_DTC_DOMAIN, readl_relaxed(xp_region + offset));
2205 }
2206
2207 static void arm_cmn_init_node_info(struct arm_cmn *cmn, u32 offset, struct arm_cmn_node *node)
2208 {
2209         int level;
2210         u64 reg = readq_relaxed(cmn->base + offset + CMN_NODE_INFO);
2211
2212         node->type = FIELD_GET(CMN_NI_NODE_TYPE, reg);
2213         node->id = FIELD_GET(CMN_NI_NODE_ID, reg);
2214         node->logid = FIELD_GET(CMN_NI_LOGICAL_ID, reg);
2215
2216         node->pmu_base = cmn->base + offset + CMN_PMU_OFFSET;
2217
2218         if (node->type == CMN_TYPE_CFG)
2219                 level = 0;
2220         else if (node->type == CMN_TYPE_XP)
2221                 level = 1;
2222         else
2223                 level = 2;
2224
2225         dev_dbg(cmn->dev, "node%*c%#06hx%*ctype:%-#6x id:%-4hd off:%#x\n",
2226                         (level * 2) + 1, ' ', node->id, 5 - (level * 2), ' ',
2227                         node->type, node->logid, offset);
2228 }
2229
2230 static enum cmn_node_type arm_cmn_subtype(enum cmn_node_type type)
2231 {
2232         switch (type) {
2233         case CMN_TYPE_HNP:
2234                 return CMN_TYPE_HNI;
2235         case CMN_TYPE_CCLA_RNI:
2236                 return CMN_TYPE_RNI;
2237         default:
2238                 return CMN_TYPE_INVALID;
2239         }
2240 }
2241
2242 static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset)
2243 {
2244         void __iomem *cfg_region;
2245         struct arm_cmn_node cfg, *dn;
2246         struct arm_cmn_dtm *dtm;
2247         enum cmn_part part;
2248         u16 child_count, child_poff;
2249         u32 xp_offset[CMN_MAX_XPS];
2250         u64 reg;
2251         int i, j;
2252         size_t sz;
2253
2254         arm_cmn_init_node_info(cmn, rgn_offset, &cfg);
2255         if (cfg.type != CMN_TYPE_CFG)
2256                 return -ENODEV;
2257
2258         cfg_region = cmn->base + rgn_offset;
2259
2260         reg = readq_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_01);
2261         part = FIELD_GET(CMN_CFGM_PID0_PART_0, reg);
2262         part |= FIELD_GET(CMN_CFGM_PID1_PART_1, reg) << 8;
2263         if (cmn->part && cmn->part != part)
2264                 dev_warn(cmn->dev,
2265                          "Firmware binding mismatch: expected part number 0x%x, found 0x%x\n",
2266                          cmn->part, part);
2267         cmn->part = part;
2268         if (!arm_cmn_model(cmn))
2269                 dev_warn(cmn->dev, "Unknown part number: 0x%x\n", part);
2270
2271         reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_23);
2272         cmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg);
2273
2274         reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL);
2275         cmn->multi_dtm = reg & CMN_INFO_MULTIPLE_DTM_EN;
2276         cmn->rsp_vc_num = FIELD_GET(CMN_INFO_RSP_VC_NUM, reg);
2277         cmn->dat_vc_num = FIELD_GET(CMN_INFO_DAT_VC_NUM, reg);
2278
2279         reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL_1);
2280         cmn->snp_vc_num = FIELD_GET(CMN_INFO_SNP_VC_NUM, reg);
2281         cmn->req_vc_num = FIELD_GET(CMN_INFO_REQ_VC_NUM, reg);
2282
2283         reg = readq_relaxed(cfg_region + CMN_CHILD_INFO);
2284         child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg);
2285         child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg);
2286
2287         cmn->num_xps = child_count;
2288         cmn->num_dns = cmn->num_xps;
2289
2290         /* Pass 1: visit the XPs, enumerate their children */
2291         for (i = 0; i < cmn->num_xps; i++) {
2292                 reg = readq_relaxed(cfg_region + child_poff + i * 8);
2293                 xp_offset[i] = reg & CMN_CHILD_NODE_ADDR;
2294
2295                 reg = readq_relaxed(cmn->base + xp_offset[i] + CMN_CHILD_INFO);
2296                 cmn->num_dns += FIELD_GET(CMN_CI_CHILD_COUNT, reg);
2297         }
2298
2299         /*
2300          * Some nodes effectively have two separate types, which we'll handle
2301          * by creating one of each internally. For a (very) safe initial upper
2302          * bound, account for double the number of non-XP nodes.
2303          */
2304         dn = devm_kcalloc(cmn->dev, cmn->num_dns * 2 - cmn->num_xps,
2305                           sizeof(*dn), GFP_KERNEL);
2306         if (!dn)
2307                 return -ENOMEM;
2308
2309         /* Initial safe upper bound on DTMs for any possible mesh layout */
2310         i = cmn->num_xps;
2311         if (cmn->multi_dtm)
2312                 i += cmn->num_xps + 1;
2313         dtm = devm_kcalloc(cmn->dev, i, sizeof(*dtm), GFP_KERNEL);
2314         if (!dtm)
2315                 return -ENOMEM;
2316
2317         /* Pass 2: now we can actually populate the nodes */
2318         cmn->dns = dn;
2319         cmn->dtms = dtm;
2320         for (i = 0; i < cmn->num_xps; i++) {
2321                 void __iomem *xp_region = cmn->base + xp_offset[i];
2322                 struct arm_cmn_node *xp = dn++;
2323                 unsigned int xp_ports = 0;
2324
2325                 arm_cmn_init_node_info(cmn, xp_offset[i], xp);
2326                 /*
2327                  * Thanks to the order in which XP logical IDs seem to be
2328                  * assigned, we can handily infer the mesh X dimension by
2329                  * looking out for the XP at (0,1) without needing to know
2330                  * the exact node ID format, which we can later derive.
2331                  */
2332                 if (xp->id == (1 << 3))
2333                         cmn->mesh_x = xp->logid;
2334
2335                 if (cmn->part == PART_CMN600)
2336                         xp->dtc = -1;
2337                 else
2338                         xp->dtc = arm_cmn_dtc_domain(cmn, xp_region);
2339
2340                 xp->dtm = dtm - cmn->dtms;
2341                 arm_cmn_init_dtm(dtm++, xp, 0);
2342                 /*
2343                  * Keeping track of connected ports will let us filter out
2344                  * unnecessary XP events easily. We can also reliably infer the
2345                  * "extra device ports" configuration for the node ID format
2346                  * from this, since in that case we will see at least one XP
2347                  * with port 2 connected, for the HN-D.
2348                  */
2349                 for (int p = 0; p < CMN_MAX_PORTS; p++)
2350                         if (arm_cmn_device_connect_info(cmn, xp, p))
2351                                 xp_ports |= BIT(p);
2352
2353                 if (cmn->multi_dtm && (xp_ports & 0xc))
2354                         arm_cmn_init_dtm(dtm++, xp, 1);
2355                 if (cmn->multi_dtm && (xp_ports & 0x30))
2356                         arm_cmn_init_dtm(dtm++, xp, 2);
2357
2358                 cmn->ports_used |= xp_ports;
2359
2360                 reg = readq_relaxed(xp_region + CMN_CHILD_INFO);
2361                 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg);
2362                 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg);
2363
2364                 for (j = 0; j < child_count; j++) {
2365                         reg = readq_relaxed(xp_region + child_poff + j * 8);
2366                         /*
2367                          * Don't even try to touch anything external, since in general
2368                          * we haven't a clue how to power up arbitrary CHI requesters.
2369                          * As of CMN-600r1 these could only be RN-SAMs or CXLAs,
2370                          * neither of which have any PMU events anyway.
2371                          * (Actually, CXLAs do seem to have grown some events in r1p2,
2372                          * but they don't go to regular XP DTMs, and they depend on
2373                          * secure configuration which we can't easily deal with)
2374                          */
2375                         if (reg & CMN_CHILD_NODE_EXTERNAL) {
2376                                 dev_dbg(cmn->dev, "ignoring external node %llx\n", reg);
2377                                 continue;
2378                         }
2379                         /*
2380                          * AmpereOneX erratum AC04_MESH_1 makes some XPs report a bogus
2381                          * child count larger than the number of valid child pointers.
2382                          * A child offset of 0 can only occur on CMN-600; otherwise it
2383                          * would imply the root node being its own grandchild, which
2384                          * we can safely dismiss in general.
2385                          */
2386                         if (reg == 0 && cmn->part != PART_CMN600) {
2387                                 dev_dbg(cmn->dev, "bogus child pointer?\n");
2388                                 continue;
2389                         }
2390
2391                         arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, dn);
2392
2393                         switch (dn->type) {
2394                         case CMN_TYPE_DTC:
2395                                 cmn->num_dtcs++;
2396                                 dn++;
2397                                 break;
2398                         /* These guys have PMU events */
2399                         case CMN_TYPE_DVM:
2400                         case CMN_TYPE_HNI:
2401                         case CMN_TYPE_HNF:
2402                         case CMN_TYPE_SBSX:
2403                         case CMN_TYPE_RNI:
2404                         case CMN_TYPE_RND:
2405                         case CMN_TYPE_MTSX:
2406                         case CMN_TYPE_CXRA:
2407                         case CMN_TYPE_CXHA:
2408                         case CMN_TYPE_CCRA:
2409                         case CMN_TYPE_CCHA:
2410                         case CMN_TYPE_CCLA:
2411                         case CMN_TYPE_HNS:
2412                                 dn++;
2413                                 break;
2414                         /* Nothing to see here */
2415                         case CMN_TYPE_MPAM_S:
2416                         case CMN_TYPE_MPAM_NS:
2417                         case CMN_TYPE_RNSAM:
2418                         case CMN_TYPE_CXLA:
2419                         case CMN_TYPE_HNS_MPAM_S:
2420                         case CMN_TYPE_HNS_MPAM_NS:
2421                                 break;
2422                         /*
2423                          * Split "optimised" combination nodes into separate
2424                          * types for the different event sets. Offsetting the
2425                          * base address lets us handle the second pmu_event_sel
2426                          * register via the normal mechanism later.
2427                          */
2428                         case CMN_TYPE_HNP:
2429                         case CMN_TYPE_CCLA_RNI:
2430                                 dn[1] = dn[0];
2431                                 dn[0].pmu_base += CMN_HNP_PMU_EVENT_SEL;
2432                                 dn[1].type = arm_cmn_subtype(dn->type);
2433                                 dn += 2;
2434                                 break;
2435                         /* Something has gone horribly wrong */
2436                         default:
2437                                 dev_err(cmn->dev, "invalid device node type: 0x%x\n", dn->type);
2438                                 return -ENODEV;
2439                         }
2440                 }
2441         }
2442
2443         /* Correct for any nodes we added or skipped */
2444         cmn->num_dns = dn - cmn->dns;
2445
2446         /* Cheeky +1 to help terminate pointer-based iteration later */
2447         sz = (void *)(dn + 1) - (void *)cmn->dns;
2448         dn = devm_krealloc(cmn->dev, cmn->dns, sz, GFP_KERNEL);
2449         if (dn)
2450                 cmn->dns = dn;
2451
2452         sz = (void *)dtm - (void *)cmn->dtms;
2453         dtm = devm_krealloc(cmn->dev, cmn->dtms, sz, GFP_KERNEL);
2454         if (dtm)
2455                 cmn->dtms = dtm;
2456
2457         /*
2458          * If mesh_x wasn't set during discovery then we never saw
2459          * an XP at (0,1), thus we must have an Nx1 configuration.
2460          */
2461         if (!cmn->mesh_x)
2462                 cmn->mesh_x = cmn->num_xps;
2463         cmn->mesh_y = cmn->num_xps / cmn->mesh_x;
2464
2465         /* 1x1 config plays havoc with XP event encodings */
2466         if (cmn->num_xps == 1)
2467                 dev_warn(cmn->dev, "1x1 config not fully supported, translate XP events manually\n");
2468
2469         dev_dbg(cmn->dev, "periph_id part 0x%03x revision %d\n", cmn->part, cmn->rev);
2470         reg = cmn->ports_used;
2471         dev_dbg(cmn->dev, "mesh %dx%d, ID width %d, ports %6pbl%s\n",
2472                 cmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn), &reg,
2473                 cmn->multi_dtm ? ", multi-DTM" : "");
2474
2475         return 0;
2476 }
2477
2478 static int arm_cmn600_acpi_probe(struct platform_device *pdev, struct arm_cmn *cmn)
2479 {
2480         struct resource *cfg, *root;
2481
2482         cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2483         if (!cfg)
2484                 return -EINVAL;
2485
2486         root = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2487         if (!root)
2488                 return -EINVAL;
2489
2490         if (!resource_contains(cfg, root))
2491                 swap(cfg, root);
2492         /*
2493          * Note that devm_ioremap_resource() is dumb and won't let the platform
2494          * device claim cfg when the ACPI companion device has already claimed
2495          * root within it. But since they *are* already both claimed in the
2496          * appropriate name, we don't really need to do it again here anyway.
2497          */
2498         cmn->base = devm_ioremap(cmn->dev, cfg->start, resource_size(cfg));
2499         if (!cmn->base)
2500                 return -ENOMEM;
2501
2502         return root->start - cfg->start;
2503 }
2504
2505 static int arm_cmn600_of_probe(struct device_node *np)
2506 {
2507         u32 rootnode;
2508
2509         return of_property_read_u32(np, "arm,root-node", &rootnode) ?: rootnode;
2510 }
2511
2512 static int arm_cmn_probe(struct platform_device *pdev)
2513 {
2514         struct arm_cmn *cmn;
2515         const char *name;
2516         static atomic_t id;
2517         int err, rootnode, this_id;
2518
2519         cmn = devm_kzalloc(&pdev->dev, sizeof(*cmn), GFP_KERNEL);
2520         if (!cmn)
2521                 return -ENOMEM;
2522
2523         cmn->dev = &pdev->dev;
2524         cmn->part = (unsigned long)device_get_match_data(cmn->dev);
2525         platform_set_drvdata(pdev, cmn);
2526
2527         if (cmn->part == PART_CMN600 && has_acpi_companion(cmn->dev)) {
2528                 rootnode = arm_cmn600_acpi_probe(pdev, cmn);
2529         } else {
2530                 rootnode = 0;
2531                 cmn->base = devm_platform_ioremap_resource(pdev, 0);
2532                 if (IS_ERR(cmn->base))
2533                         return PTR_ERR(cmn->base);
2534                 if (cmn->part == PART_CMN600)
2535                         rootnode = arm_cmn600_of_probe(pdev->dev.of_node);
2536         }
2537         if (rootnode < 0)
2538                 return rootnode;
2539
2540         err = arm_cmn_discover(cmn, rootnode);
2541         if (err)
2542                 return err;
2543
2544         err = arm_cmn_init_dtcs(cmn);
2545         if (err)
2546                 return err;
2547
2548         err = arm_cmn_init_irqs(cmn);
2549         if (err)
2550                 return err;
2551
2552         cmn->cpu = cpumask_local_spread(0, dev_to_node(cmn->dev));
2553         cmn->pmu = (struct pmu) {
2554                 .module = THIS_MODULE,
2555                 .parent = cmn->dev,
2556                 .attr_groups = arm_cmn_attr_groups,
2557                 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
2558                 .task_ctx_nr = perf_invalid_context,
2559                 .pmu_enable = arm_cmn_pmu_enable,
2560                 .pmu_disable = arm_cmn_pmu_disable,
2561                 .event_init = arm_cmn_event_init,
2562                 .add = arm_cmn_event_add,
2563                 .del = arm_cmn_event_del,
2564                 .start = arm_cmn_event_start,
2565                 .stop = arm_cmn_event_stop,
2566                 .read = arm_cmn_event_read,
2567                 .start_txn = arm_cmn_start_txn,
2568                 .commit_txn = arm_cmn_commit_txn,
2569                 .cancel_txn = arm_cmn_end_txn,
2570         };
2571
2572         this_id = atomic_fetch_inc(&id);
2573         name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", this_id);
2574         if (!name)
2575                 return -ENOMEM;
2576
2577         err = cpuhp_state_add_instance(arm_cmn_hp_state, &cmn->cpuhp_node);
2578         if (err)
2579                 return err;
2580
2581         err = perf_pmu_register(&cmn->pmu, name, -1);
2582         if (err)
2583                 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node);
2584         else
2585                 arm_cmn_debugfs_init(cmn, this_id);
2586
2587         return err;
2588 }
2589
2590 static void arm_cmn_remove(struct platform_device *pdev)
2591 {
2592         struct arm_cmn *cmn = platform_get_drvdata(pdev);
2593
2594         writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL);
2595
2596         perf_pmu_unregister(&cmn->pmu);
2597         cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node);
2598         debugfs_remove(cmn->debug);
2599 }
2600
2601 #ifdef CONFIG_OF
2602 static const struct of_device_id arm_cmn_of_match[] = {
2603         { .compatible = "arm,cmn-600", .data = (void *)PART_CMN600 },
2604         { .compatible = "arm,cmn-650" },
2605         { .compatible = "arm,cmn-700" },
2606         { .compatible = "arm,ci-700" },
2607         {}
2608 };
2609 MODULE_DEVICE_TABLE(of, arm_cmn_of_match);
2610 #endif
2611
2612 #ifdef CONFIG_ACPI
2613 static const struct acpi_device_id arm_cmn_acpi_match[] = {
2614         { "ARMHC600", PART_CMN600 },
2615         { "ARMHC650" },
2616         { "ARMHC700" },
2617         {}
2618 };
2619 MODULE_DEVICE_TABLE(acpi, arm_cmn_acpi_match);
2620 #endif
2621
2622 static struct platform_driver arm_cmn_driver = {
2623         .driver = {
2624                 .name = "arm-cmn",
2625                 .of_match_table = of_match_ptr(arm_cmn_of_match),
2626                 .acpi_match_table = ACPI_PTR(arm_cmn_acpi_match),
2627         },
2628         .probe = arm_cmn_probe,
2629         .remove_new = arm_cmn_remove,
2630 };
2631
2632 static int __init arm_cmn_init(void)
2633 {
2634         int ret;
2635
2636         ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
2637                                       "perf/arm/cmn:online",
2638                                       arm_cmn_pmu_online_cpu,
2639                                       arm_cmn_pmu_offline_cpu);
2640         if (ret < 0)
2641                 return ret;
2642
2643         arm_cmn_hp_state = ret;
2644         arm_cmn_debugfs = debugfs_create_dir("arm-cmn", NULL);
2645
2646         ret = platform_driver_register(&arm_cmn_driver);
2647         if (ret) {
2648                 cpuhp_remove_multi_state(arm_cmn_hp_state);
2649                 debugfs_remove(arm_cmn_debugfs);
2650         }
2651         return ret;
2652 }
2653
2654 static void __exit arm_cmn_exit(void)
2655 {
2656         platform_driver_unregister(&arm_cmn_driver);
2657         cpuhp_remove_multi_state(arm_cmn_hp_state);
2658         debugfs_remove(arm_cmn_debugfs);
2659 }
2660
2661 module_init(arm_cmn_init);
2662 module_exit(arm_cmn_exit);
2663
2664 MODULE_AUTHOR("Robin Murphy <[email protected]>");
2665 MODULE_DESCRIPTION("Arm CMN-600 PMU driver");
2666 MODULE_LICENSE("GPL v2");