drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26
  27 #include <linux/firmware.h>
  28 #include <linux/module.h>
  29 #include <linux/pci.h>
  30 #include <drm/drm_drv.h>
  31
  32 #include "amdgpu.h"
  33 #include "amdgpu_pm.h"
  34 #include "amdgpu_vcn.h"
  35 #include "soc15d.h"
  36
  37 /* Firmware Names */
  38 #define FIRMWARE_RAVEN          "amdgpu/raven_vcn.bin"
  39 #define FIRMWARE_PICASSO        "amdgpu/picasso_vcn.bin"
  40 #define FIRMWARE_RAVEN2         "amdgpu/raven2_vcn.bin"
  41 #define FIRMWARE_ARCTURUS       "amdgpu/arcturus_vcn.bin"
  42 #define FIRMWARE_RENOIR         "amdgpu/renoir_vcn.bin"
  43 #define FIRMWARE_GREEN_SARDINE  "amdgpu/green_sardine_vcn.bin"
  44 #define FIRMWARE_NAVI10         "amdgpu/navi10_vcn.bin"
  45 #define FIRMWARE_NAVI14         "amdgpu/navi14_vcn.bin"
  46 #define FIRMWARE_NAVI12         "amdgpu/navi12_vcn.bin"
  47 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin"
  48 #define FIRMWARE_NAVY_FLOUNDER  "amdgpu/navy_flounder_vcn.bin"
  49 #define FIRMWARE_VANGOGH        "amdgpu/vangogh_vcn.bin"
  50 #define FIRMWARE_DIMGREY_CAVEFISH       "amdgpu/dimgrey_cavefish_vcn.bin"
  51 #define FIRMWARE_ALDEBARAN      "amdgpu/aldebaran_vcn.bin"
  52 #define FIRMWARE_BEIGE_GOBY     "amdgpu/beige_goby_vcn.bin"
  53 #define FIRMWARE_YELLOW_CARP    "amdgpu/yellow_carp_vcn.bin"
  54
  55 MODULE_FIRMWARE(FIRMWARE_RAVEN);
  56 MODULE_FIRMWARE(FIRMWARE_PICASSO);
  57 MODULE_FIRMWARE(FIRMWARE_RAVEN2);
  58 MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
  59 MODULE_FIRMWARE(FIRMWARE_RENOIR);
  60 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE);
  61 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN);
  62 MODULE_FIRMWARE(FIRMWARE_NAVI10);
  63 MODULE_FIRMWARE(FIRMWARE_NAVI14);
  64 MODULE_FIRMWARE(FIRMWARE_NAVI12);
  65 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID);
  66 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER);
  67 MODULE_FIRMWARE(FIRMWARE_VANGOGH);
  68 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH);
  69 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY);
  70 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP);
  71
  72 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
  73
  74 int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
  75 {
  76         unsigned long bo_size;
  77         const char *fw_name;
  78         const struct common_firmware_header *hdr;
  79         unsigned char fw_check;
  80         int i, r;
  81
  82         INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
  83         mutex_init(&adev->vcn.vcn_pg_lock);
  84         mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
  85         atomic_set(&adev->vcn.total_submission_cnt, 0);
  86         for (i = 0; i < adev->vcn.num_vcn_inst; i++)
  87                 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
  88
  89         switch (adev->asic_type) {
  90         case CHIP_RAVEN:
  91                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
  92                         fw_name = FIRMWARE_RAVEN2;
  93                 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
  94                         fw_name = FIRMWARE_PICASSO;
  95                 else
  96                         fw_name = FIRMWARE_RAVEN;
  97                 break;
  98         case CHIP_ARCTURUS:
  99                 fw_name = FIRMWARE_ARCTURUS;
 100                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 101                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 102                         adev->vcn.indirect_sram = true;
 103                 break;
 104         case CHIP_RENOIR:
 105                 if (adev->apu_flags & AMD_APU_IS_RENOIR)
 106                         fw_name = FIRMWARE_RENOIR;
 107                 else
 108                         fw_name = FIRMWARE_GREEN_SARDINE;
 109
 110                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 111                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 112                         adev->vcn.indirect_sram = true;
 113                 break;
 114         case CHIP_ALDEBARAN:
 115                 fw_name = FIRMWARE_ALDEBARAN;
 116                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 117                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 118                         adev->vcn.indirect_sram = true;
 119                 break;
 120         case CHIP_NAVI10:
 121                 fw_name = FIRMWARE_NAVI10;
 122                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 123                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 124                         adev->vcn.indirect_sram = true;
 125                 break;
 126         case CHIP_NAVI14:
 127                 fw_name = FIRMWARE_NAVI14;
 128                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 129                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 130                         adev->vcn.indirect_sram = true;
 131                 break;
 132         case CHIP_NAVI12:
 133                 fw_name = FIRMWARE_NAVI12;
 134                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 135                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 136                         adev->vcn.indirect_sram = true;
 137                 break;
 138         case CHIP_SIENNA_CICHLID:
 139                 fw_name = FIRMWARE_SIENNA_CICHLID;
 140                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 141                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 142                         adev->vcn.indirect_sram = true;
 143                 break;
 144         case CHIP_NAVY_FLOUNDER:
 145                 fw_name = FIRMWARE_NAVY_FLOUNDER;
 146                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 147                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 148                         adev->vcn.indirect_sram = true;
 149                 break;
 150         case CHIP_VANGOGH:
 151                 fw_name = FIRMWARE_VANGOGH;
 152                 break;
 153         case CHIP_DIMGREY_CAVEFISH:
 154                 fw_name = FIRMWARE_DIMGREY_CAVEFISH;
 155                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 156                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 157                         adev->vcn.indirect_sram = true;
 158                 break;
 159         case CHIP_BEIGE_GOBY:
 160                 fw_name = FIRMWARE_BEIGE_GOBY;
 161                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 162                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 163                         adev->vcn.indirect_sram = true;
 164                 break;
 165         case CHIP_YELLOW_CARP:
 166                 fw_name = FIRMWARE_YELLOW_CARP;
 167                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 168                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 169                         adev->vcn.indirect_sram = true;
 170                 break;
 171         default:
 172                 return -EINVAL;
 173         }
 174
 175         r = request_firmware(&adev->vcn.fw, fw_name, adev->dev);
 176         if (r) {
 177                 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n",
 178                         fw_name);
 179                 return r;
 180         }
 181
 182         r = amdgpu_ucode_validate(adev->vcn.fw);
 183         if (r) {
 184                 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n",
 185                         fw_name);
 186                 release_firmware(adev->vcn.fw);
 187                 adev->vcn.fw = NULL;
 188                 return r;
 189         }
 190
 191         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 192         adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
 193
 194         /* Bit 20-23, it is encode major and non-zero for new naming convention.
 195          * This field is part of version minor and DRM_DISABLED_FLAG in old naming
 196          * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
 197          * is zero in old naming convention, this field is always zero so far.
 198          * These four bits are used to tell which naming convention is present.
 199          */
 200         fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
 201         if (fw_check) {
 202                 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
 203
 204                 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
 205                 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
 206                 enc_major = fw_check;
 207                 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
 208                 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
 209                 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n",
 210                         enc_major, enc_minor, dec_ver, vep, fw_rev);
 211         } else {
 212                 unsigned int version_major, version_minor, family_id;
 213
 214                 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 215                 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 216                 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 217                 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n",
 218                         version_major, version_minor, family_id);
 219         }
 220
 221         bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
 222         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 223                 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 224         bo_size += AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
 225
 226         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 227                 if (adev->vcn.harvest_config & (1 << i))
 228                         continue;
 229
 230                 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
 231                                                 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo,
 232                                                 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr);
 233                 if (r) {
 234                         dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
 235                         return r;
 236                 }
 237
 238                 adev->vcn.inst[i].fw_shared_cpu_addr = adev->vcn.inst[i].cpu_addr +
 239                                 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
 240                 adev->vcn.inst[i].fw_shared_gpu_addr = adev->vcn.inst[i].gpu_addr +
 241                                 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
 242
 243                 if (adev->vcn.indirect_sram) {
 244                         r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
 245                                         AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo,
 246                                         &adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr);
 247                         if (r) {
 248                                 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);
 249                                 return r;
 250                         }
 251                 }
 252         }
 253
 254         return 0;
 255 }
 256
 257 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 258 {
 259         int i, j;
 260
 261         cancel_delayed_work_sync(&adev->vcn.idle_work);
 262
 263         for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
 264                 if (adev->vcn.harvest_config & (1 << j))
 265                         continue;
 266
 267                 if (adev->vcn.indirect_sram) {
 268                         amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo,
 269                                                   &adev->vcn.inst[j].dpg_sram_gpu_addr,
 270                                                   (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr);
 271                 }
 272                 kvfree(adev->vcn.inst[j].saved_bo);
 273
 274                 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
 275                                           &adev->vcn.inst[j].gpu_addr,
 276                                           (void **)&adev->vcn.inst[j].cpu_addr);
 277
 278                 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
 279
 280                 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
 281                         amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
 282         }
 283
 284         release_firmware(adev->vcn.fw);
 285         mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
 286         mutex_destroy(&adev->vcn.vcn_pg_lock);
 287
 288         return 0;
 289 }
 290
 291 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
 292 {
 293         unsigned size;
 294         void *ptr;
 295         int i, idx;
 296
 297         cancel_delayed_work_sync(&adev->vcn.idle_work);
 298
 299         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 300                 if (adev->vcn.harvest_config & (1 << i))
 301                         continue;
 302                 if (adev->vcn.inst[i].vcpu_bo == NULL)
 303                         return 0;
 304
 305                 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
 306                 ptr = adev->vcn.inst[i].cpu_addr;
 307
 308                 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
 309                 if (!adev->vcn.inst[i].saved_bo)
 310                         return -ENOMEM;
 311
 312                 if (drm_dev_enter(&adev->ddev, &idx)) {
 313                         memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
 314                         drm_dev_exit(idx);
 315                 }
 316         }
 317         return 0;
 318 }
 319
 320 int amdgpu_vcn_resume(struct amdgpu_device *adev)
 321 {
 322         unsigned size;
 323         void *ptr;
 324         int i, idx;
 325
 326         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 327                 if (adev->vcn.harvest_config & (1 << i))
 328                         continue;
 329                 if (adev->vcn.inst[i].vcpu_bo == NULL)
 330                         return -EINVAL;
 331
 332                 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
 333                 ptr = adev->vcn.inst[i].cpu_addr;
 334
 335                 if (adev->vcn.inst[i].saved_bo != NULL) {
 336                         if (drm_dev_enter(&adev->ddev, &idx)) {
 337                                 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
 338                                 drm_dev_exit(idx);
 339                         }
 340                         kvfree(adev->vcn.inst[i].saved_bo);
 341                         adev->vcn.inst[i].saved_bo = NULL;
 342                 } else {
 343                         const struct common_firmware_header *hdr;
 344                         unsigned offset;
 345
 346                         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 347                         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 348                                 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 349                                 if (drm_dev_enter(&adev->ddev, &idx)) {
 350                                         memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
 351                                                     le32_to_cpu(hdr->ucode_size_bytes));
 352                                         drm_dev_exit(idx);
 353                                 }
 354                                 size -= le32_to_cpu(hdr->ucode_size_bytes);
 355                                 ptr += le32_to_cpu(hdr->ucode_size_bytes);
 356                         }
 357                         memset_io(ptr, 0, size);
 358                 }
 359         }
 360         return 0;
 361 }
 362
 363 static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
 364 {
 365         struct amdgpu_device *adev =
 366                 container_of(work, struct amdgpu_device, vcn.idle_work.work);
 367         unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
 368         unsigned int i, j;
 369         int r = 0;
 370
 371         for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
 372                 if (adev->vcn.harvest_config & (1 << j))
 373                         continue;
 374
 375                 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 376                         fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
 377                 }
 378
 379                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
 380                         struct dpg_pause_state new_state;
 381
 382                         if (fence[j] ||
 383                                 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt)))
 384                                 new_state.fw_based = VCN_DPG_STATE__PAUSE;
 385                         else
 386                                 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 387
 388                         adev->vcn.pause_dpg_mode(adev, j, &new_state);
 389                 }
 390
 391                 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
 392                 fences += fence[j];
 393         }
 394
 395         if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
 396                 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 397                        AMD_PG_STATE_GATE);
 398                 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
 399                                 false);
 400                 if (r)
 401                         dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r);
 402         } else {
 403                 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 404         }
 405 }
 406
 407 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 408 {
 409         struct amdgpu_device *adev = ring->adev;
 410         int r = 0;
 411
 412         atomic_inc(&adev->vcn.total_submission_cnt);
 413
 414         if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
 415                 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
 416                                 true);
 417                 if (r)
 418                         dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r);
 419         }
 420
 421         mutex_lock(&adev->vcn.vcn_pg_lock);
 422         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 423                AMD_PG_STATE_UNGATE);
 424
 425         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
 426                 struct dpg_pause_state new_state;
 427
 428                 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) {
 429                         atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
 430                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
 431                 } else {
 432                         unsigned int fences = 0;
 433                         unsigned int i;
 434
 435                         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
 436                                 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
 437
 438                         if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt))
 439                                 new_state.fw_based = VCN_DPG_STATE__PAUSE;
 440                         else
 441                                 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 442                 }
 443
 444                 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state);
 445         }
 446         mutex_unlock(&adev->vcn.vcn_pg_lock);
 447 }
 448
 449 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
 450 {
 451         if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
 452                 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
 453                 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
 454
 455         atomic_dec(&ring->adev->vcn.total_submission_cnt);
 456
 457         schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 458 }
 459
 460 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
 461 {
 462         struct amdgpu_device *adev = ring->adev;
 463         uint32_t tmp = 0;
 464         unsigned i;
 465         int r;
 466
 467         /* VCN in SRIOV does not support direct register read/write */
 468         if (amdgpu_sriov_vf(adev))
 469                 return 0;
 470
 471         WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
 472         r = amdgpu_ring_alloc(ring, 3);
 473         if (r)
 474                 return r;
 475         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
 476         amdgpu_ring_write(ring, 0xDEADBEEF);
 477         amdgpu_ring_commit(ring);
 478         for (i = 0; i < adev->usec_timeout; i++) {
 479                 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
 480                 if (tmp == 0xDEADBEEF)
 481                         break;
 482                 udelay(1);
 483         }
 484
 485         if (i >= adev->usec_timeout)
 486                 r = -ETIMEDOUT;
 487
 488         return r;
 489 }
 490
 491 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
 492 {
 493         struct amdgpu_device *adev = ring->adev;
 494         uint32_t rptr;
 495         unsigned int i;
 496         int r;
 497
 498         if (amdgpu_sriov_vf(adev))
 499                 return 0;
 500
 501         r = amdgpu_ring_alloc(ring, 16);
 502         if (r)
 503                 return r;
 504
 505         rptr = amdgpu_ring_get_rptr(ring);
 506
 507         amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
 508         amdgpu_ring_commit(ring);
 509
 510         for (i = 0; i < adev->usec_timeout; i++) {
 511                 if (amdgpu_ring_get_rptr(ring) != rptr)
 512                         break;
 513                 udelay(1);
 514         }
 515
 516         if (i >= adev->usec_timeout)
 517                 r = -ETIMEDOUT;
 518
 519         return r;
 520 }
 521
 522 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
 523                                    struct amdgpu_bo *bo,
 524                                    struct dma_fence **fence)
 525 {
 526         struct amdgpu_device *adev = ring->adev;
 527         struct dma_fence *f = NULL;
 528         struct amdgpu_job *job;
 529         struct amdgpu_ib *ib;
 530         uint64_t addr;
 531         void *msg = NULL;
 532         int i, r;
 533
 534         r = amdgpu_job_alloc_with_ib(adev, 64,
 535                                         AMDGPU_IB_POOL_DIRECT, &job);
 536         if (r)
 537                 goto err;
 538
 539         ib = &job->ibs[0];
 540         addr = amdgpu_bo_gpu_offset(bo);
 541         msg = amdgpu_bo_kptr(bo);
 542         ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
 543         ib->ptr[1] = addr;
 544         ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
 545         ib->ptr[3] = addr >> 32;
 546         ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
 547         ib->ptr[5] = 0;
 548         for (i = 6; i < 16; i += 2) {
 549                 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
 550                 ib->ptr[i+1] = 0;
 551         }
 552         ib->length_dw = 16;
 553
 554         r = amdgpu_job_submit_direct(job, ring, &f);
 555         if (r)
 556                 goto err_free;
 557
 558         amdgpu_bo_fence(bo, f, false);
 559         amdgpu_bo_unreserve(bo);
 560         amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg);
 561
 562         if (fence)
 563                 *fence = dma_fence_get(f);
 564         dma_fence_put(f);
 565
 566         return 0;
 567
 568 err_free:
 569         amdgpu_job_free(job);
 570
 571 err:
 572         amdgpu_bo_unreserve(bo);
 573         amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg);
 574         return r;
 575 }
 576
 577 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 578                                          struct amdgpu_bo **bo)
 579 {
 580         struct amdgpu_device *adev = ring->adev;
 581         uint32_t *msg;
 582         int r, i;
 583
 584         *bo = NULL;
 585         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
 586                                       AMDGPU_GEM_DOMAIN_VRAM,
 587                                       bo, NULL, (void **)&msg);
 588         if (r)
 589                 return r;
 590
 591         msg[0] = cpu_to_le32(0x00000028);
 592         msg[1] = cpu_to_le32(0x00000038);
 593         msg[2] = cpu_to_le32(0x00000001);
 594         msg[3] = cpu_to_le32(0x00000000);
 595         msg[4] = cpu_to_le32(handle);
 596         msg[5] = cpu_to_le32(0x00000000);
 597         msg[6] = cpu_to_le32(0x00000001);
 598         msg[7] = cpu_to_le32(0x00000028);
 599         msg[8] = cpu_to_le32(0x00000010);
 600         msg[9] = cpu_to_le32(0x00000000);
 601         msg[10] = cpu_to_le32(0x00000007);
 602         msg[11] = cpu_to_le32(0x00000000);
 603         msg[12] = cpu_to_le32(0x00000780);
 604         msg[13] = cpu_to_le32(0x00000440);
 605         for (i = 14; i < 1024; ++i)
 606                 msg[i] = cpu_to_le32(0x0);
 607
 608         return 0;
 609 }
 610
 611 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 612                                           struct amdgpu_bo **bo)
 613 {
 614         struct amdgpu_device *adev = ring->adev;
 615         uint32_t *msg;
 616         int r, i;
 617
 618         *bo = NULL;
 619         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
 620                                       AMDGPU_GEM_DOMAIN_VRAM,
 621                                       bo, NULL, (void **)&msg);
 622         if (r)
 623                 return r;
 624
 625         msg[0] = cpu_to_le32(0x00000028);
 626         msg[1] = cpu_to_le32(0x00000018);
 627         msg[2] = cpu_to_le32(0x00000000);
 628         msg[3] = cpu_to_le32(0x00000002);
 629         msg[4] = cpu_to_le32(handle);
 630         msg[5] = cpu_to_le32(0x00000000);
 631         for (i = 6; i < 1024; ++i)
 632                 msg[i] = cpu_to_le32(0x0);
 633
 634         return 0;
 635 }
 636
 637 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 638 {
 639         struct dma_fence *fence = NULL;
 640         struct amdgpu_bo *bo;
 641         long r;
 642
 643         r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo);
 644         if (r)
 645                 goto error;
 646
 647         r = amdgpu_vcn_dec_send_msg(ring, bo, NULL);
 648         if (r)
 649                 goto error;
 650         r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo);
 651         if (r)
 652                 goto error;
 653
 654         r = amdgpu_vcn_dec_send_msg(ring, bo, &fence);
 655         if (r)
 656                 goto error;
 657
 658         r = dma_fence_wait_timeout(fence, false, timeout);
 659         if (r == 0)
 660                 r = -ETIMEDOUT;
 661         else if (r > 0)
 662                 r = 0;
 663
 664         dma_fence_put(fence);
 665 error:
 666         return r;
 667 }
 668
 669 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
 670                                    struct amdgpu_bo *bo,
 671                                    struct dma_fence **fence)
 672 {
 673         struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
 674         const unsigned int ib_size_dw = 64;
 675         struct amdgpu_device *adev = ring->adev;
 676         struct dma_fence *f = NULL;
 677         struct amdgpu_job *job;
 678         struct amdgpu_ib *ib;
 679         uint64_t addr;
 680         int i, r;
 681
 682         r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4,
 683                                 AMDGPU_IB_POOL_DIRECT, &job);
 684         if (r)
 685                 goto err;
 686
 687         ib = &job->ibs[0];
 688         addr = amdgpu_bo_gpu_offset(bo);
 689         ib->length_dw = 0;
 690
 691         ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
 692         ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
 693         decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
 694         ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
 695         memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
 696
 697         decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
 698         decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
 699         decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
 700
 701         for (i = ib->length_dw; i < ib_size_dw; ++i)
 702                 ib->ptr[i] = 0x0;
 703
 704         r = amdgpu_job_submit_direct(job, ring, &f);
 705         if (r)
 706                 goto err_free;
 707
 708         amdgpu_bo_fence(bo, f, false);
 709         amdgpu_bo_unreserve(bo);
 710         amdgpu_bo_unref(&bo);
 711
 712         if (fence)
 713                 *fence = dma_fence_get(f);
 714         dma_fence_put(f);
 715
 716         return 0;
 717
 718 err_free:
 719         amdgpu_job_free(job);
 720
 721 err:
 722         amdgpu_bo_unreserve(bo);
 723         amdgpu_bo_unref(&bo);
 724         return r;
 725 }
 726
 727 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 728 {
 729         struct dma_fence *fence = NULL;
 730         struct amdgpu_bo *bo;
 731         long r;
 732
 733         r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo);
 734         if (r)
 735                 goto error;
 736
 737         r = amdgpu_vcn_dec_sw_send_msg(ring, bo, NULL);
 738         if (r)
 739                 goto error;
 740         r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo);
 741         if (r)
 742                 goto error;
 743
 744         r = amdgpu_vcn_dec_sw_send_msg(ring, bo, &fence);
 745         if (r)
 746                 goto error;
 747
 748         r = dma_fence_wait_timeout(fence, false, timeout);
 749         if (r == 0)
 750                 r = -ETIMEDOUT;
 751         else if (r > 0)
 752                 r = 0;
 753
 754         dma_fence_put(fence);
 755 error:
 756         return r;
 757 }
 758
 759 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
 760 {
 761         struct amdgpu_device *adev = ring->adev;
 762         uint32_t rptr;
 763         unsigned i;
 764         int r;
 765
 766         if (amdgpu_sriov_vf(adev))
 767                 return 0;
 768
 769         r = amdgpu_ring_alloc(ring, 16);
 770         if (r)
 771                 return r;
 772
 773         rptr = amdgpu_ring_get_rptr(ring);
 774
 775         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
 776         amdgpu_ring_commit(ring);
 777
 778         for (i = 0; i < adev->usec_timeout; i++) {
 779                 if (amdgpu_ring_get_rptr(ring) != rptr)
 780                         break;
 781                 udelay(1);
 782         }
 783
 784         if (i >= adev->usec_timeout)
 785                 r = -ETIMEDOUT;
 786
 787         return r;
 788 }
 789
 790 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 791                                          struct amdgpu_bo *bo,
 792                                          struct dma_fence **fence)
 793 {
 794         const unsigned ib_size_dw = 16;
 795         struct amdgpu_job *job;
 796         struct amdgpu_ib *ib;
 797         struct dma_fence *f = NULL;
 798         uint64_t addr;
 799         int i, r;
 800
 801         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
 802                                         AMDGPU_IB_POOL_DIRECT, &job);
 803         if (r)
 804                 return r;
 805
 806         ib = &job->ibs[0];
 807         addr = amdgpu_bo_gpu_offset(bo);
 808
 809         ib->length_dw = 0;
 810         ib->ptr[ib->length_dw++] = 0x00000018;
 811         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 812         ib->ptr[ib->length_dw++] = handle;
 813         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 814         ib->ptr[ib->length_dw++] = addr;
 815         ib->ptr[ib->length_dw++] = 0x0000000b;
 816
 817         ib->ptr[ib->length_dw++] = 0x00000014;
 818         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 819         ib->ptr[ib->length_dw++] = 0x0000001c;
 820         ib->ptr[ib->length_dw++] = 0x00000000;
 821         ib->ptr[ib->length_dw++] = 0x00000000;
 822
 823         ib->ptr[ib->length_dw++] = 0x00000008;
 824         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 825
 826         for (i = ib->length_dw; i < ib_size_dw; ++i)
 827                 ib->ptr[i] = 0x0;
 828
 829         r = amdgpu_job_submit_direct(job, ring, &f);
 830         if (r)
 831                 goto err;
 832
 833         if (fence)
 834                 *fence = dma_fence_get(f);
 835         dma_fence_put(f);
 836
 837         return 0;
 838
 839 err:
 840         amdgpu_job_free(job);
 841         return r;
 842 }
 843
 844 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 845                                           struct amdgpu_bo *bo,
 846                                           struct dma_fence **fence)
 847 {
 848         const unsigned ib_size_dw = 16;
 849         struct amdgpu_job *job;
 850         struct amdgpu_ib *ib;
 851         struct dma_fence *f = NULL;
 852         uint64_t addr;
 853         int i, r;
 854
 855         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
 856                                         AMDGPU_IB_POOL_DIRECT, &job);
 857         if (r)
 858                 return r;
 859
 860         ib = &job->ibs[0];
 861         addr = amdgpu_bo_gpu_offset(bo);
 862
 863         ib->length_dw = 0;
 864         ib->ptr[ib->length_dw++] = 0x00000018;
 865         ib->ptr[ib->length_dw++] = 0x00000001;
 866         ib->ptr[ib->length_dw++] = handle;
 867         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 868         ib->ptr[ib->length_dw++] = addr;
 869         ib->ptr[ib->length_dw++] = 0x0000000b;
 870
 871         ib->ptr[ib->length_dw++] = 0x00000014;
 872         ib->ptr[ib->length_dw++] = 0x00000002;
 873         ib->ptr[ib->length_dw++] = 0x0000001c;
 874         ib->ptr[ib->length_dw++] = 0x00000000;
 875         ib->ptr[ib->length_dw++] = 0x00000000;
 876
 877         ib->ptr[ib->length_dw++] = 0x00000008;
 878         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 879
 880         for (i = ib->length_dw; i < ib_size_dw; ++i)
 881                 ib->ptr[i] = 0x0;
 882
 883         r = amdgpu_job_submit_direct(job, ring, &f);
 884         if (r)
 885                 goto err;
 886
 887         if (fence)
 888                 *fence = dma_fence_get(f);
 889         dma_fence_put(f);
 890
 891         return 0;
 892
 893 err:
 894         amdgpu_job_free(job);
 895         return r;
 896 }
 897
 898 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 899 {
 900         struct dma_fence *fence = NULL;
 901         struct amdgpu_bo *bo = NULL;
 902         long r;
 903
 904         r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
 905                                       AMDGPU_GEM_DOMAIN_VRAM,
 906                                       &bo, NULL, NULL);
 907         if (r)
 908                 return r;
 909
 910         r = amdgpu_vcn_enc_get_create_msg(ring, 1, bo, NULL);
 911         if (r)
 912                 goto error;
 913
 914         r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, bo, &fence);
 915         if (r)
 916                 goto error;
 917
 918         r = dma_fence_wait_timeout(fence, false, timeout);
 919         if (r == 0)
 920                 r = -ETIMEDOUT;
 921         else if (r > 0)
 922                 r = 0;
 923
 924 error:
 925         dma_fence_put(fence);
 926         amdgpu_bo_unreserve(bo);
 927         amdgpu_bo_free_kernel(&bo, NULL, NULL);
 928
 929         return r;
 930 }