drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/pagemap.h>
  36 #include <linux/sched/task.h>
  37 #include <linux/sched/mm.h>
  38 #include <linux/seq_file.h>
  39 #include <linux/slab.h>
  40 #include <linux/swap.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/dma-buf.h>
  43 #include <linux/sizes.h>
  44
  45 #include <drm/ttm/ttm_bo_api.h>
  46 #include <drm/ttm/ttm_bo_driver.h>
  47 #include <drm/ttm/ttm_placement.h>
  48 #include <drm/ttm/ttm_range_manager.h>
  49
  50 #include <drm/amdgpu_drm.h>
  51
  52 #include "amdgpu.h"
  53 #include "amdgpu_object.h"
  54 #include "amdgpu_trace.h"
  55 #include "amdgpu_amdkfd.h"
  56 #include "amdgpu_sdma.h"
  57 #include "amdgpu_ras.h"
  58 #include "amdgpu_atomfirmware.h"
  59 #include "amdgpu_res_cursor.h"
  60 #include "bif/bif_4_1_d.h"
  61
  62 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  63
  64 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
  65                                    struct ttm_tt *ttm,
  66                                    struct ttm_resource *bo_mem);
  67 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
  68                                       struct ttm_tt *ttm);
  69
  70 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  71                                     unsigned int type,
  72                                     uint64_t size_in_page)
  73 {
  74         return ttm_range_man_init(&adev->mman.bdev, type,
  75                                   false, size_in_page);
  76 }
  77
  78 /**
  79  * amdgpu_evict_flags - Compute placement flags
  80  *
  81  * @bo: The buffer object to evict
  82  * @placement: Possible destination(s) for evicted BO
  83  *
  84  * Fill in placement data when ttm_bo_evict() is called
  85  */
  86 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  87                                 struct ttm_placement *placement)
  88 {
  89         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  90         struct amdgpu_bo *abo;
  91         static const struct ttm_place placements = {
  92                 .fpfn = 0,
  93                 .lpfn = 0,
  94                 .mem_type = TTM_PL_SYSTEM,
  95                 .flags = 0
  96         };
  97
  98         /* Don't handle scatter gather BOs */
  99         if (bo->type == ttm_bo_type_sg) {
 100                 placement->num_placement = 0;
 101                 placement->num_busy_placement = 0;
 102                 return;
 103         }
 104
 105         /* Object isn't an AMDGPU object so ignore */
 106         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 107                 placement->placement = &placements;
 108                 placement->busy_placement = &placements;
 109                 placement->num_placement = 1;
 110                 placement->num_busy_placement = 1;
 111                 return;
 112         }
 113
 114         abo = ttm_to_amdgpu_bo(bo);
 115         if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) {
 116                 struct dma_fence *fence;
 117                 struct dma_resv *resv = &bo->base._resv;
 118
 119                 rcu_read_lock();
 120                 fence = rcu_dereference(resv->fence_excl);
 121                 if (fence && !fence->ops->signaled)
 122                         dma_fence_enable_sw_signaling(fence);
 123
 124                 placement->num_placement = 0;
 125                 placement->num_busy_placement = 0;
 126                 rcu_read_unlock();
 127                 return;
 128         }
 129
 130         switch (bo->resource->mem_type) {
 131         case AMDGPU_PL_GDS:
 132         case AMDGPU_PL_GWS:
 133         case AMDGPU_PL_OA:
 134                 placement->num_placement = 0;
 135                 placement->num_busy_placement = 0;
 136                 return;
 137
 138         case TTM_PL_VRAM:
 139                 if (!adev->mman.buffer_funcs_enabled) {
 140                         /* Move to system memory */
 141                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 142                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 143                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 144                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 145
 146                         /* Try evicting to the CPU inaccessible part of VRAM
 147                          * first, but only set GTT as busy placement, so this
 148                          * BO will be evicted to GTT rather than causing other
 149                          * BOs to be evicted from VRAM
 150                          */
 151                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 152                                                          AMDGPU_GEM_DOMAIN_GTT);
 153                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 154                         abo->placements[0].lpfn = 0;
 155                         abo->placement.busy_placement = &abo->placements[1];
 156                         abo->placement.num_busy_placement = 1;
 157                 } else {
 158                         /* Move to GTT memory */
 159                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 160                 }
 161                 break;
 162         case TTM_PL_TT:
 163         case AMDGPU_PL_PREEMPT:
 164         default:
 165                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 166                 break;
 167         }
 168         *placement = abo->placement;
 169 }
 170
 171 /**
 172  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 173  * @bo: buffer object to map
 174  * @mem: memory object to map
 175  * @mm_cur: range to map
 176  * @num_pages: number of pages to map
 177  * @window: which GART window to use
 178  * @ring: DMA ring to use for the copy
 179  * @tmz: if we should setup a TMZ enabled mapping
 180  * @addr: resulting address inside the MC address space
 181  *
 182  * Setup one of the GART windows to access a specific piece of memory or return
 183  * the physical address for local memory.
 184  */
 185 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 186                                  struct ttm_resource *mem,
 187                                  struct amdgpu_res_cursor *mm_cur,
 188                                  unsigned num_pages, unsigned window,
 189                                  struct amdgpu_ring *ring, bool tmz,
 190                                  uint64_t *addr)
 191 {
 192         struct amdgpu_device *adev = ring->adev;
 193         struct amdgpu_job *job;
 194         unsigned num_dw, num_bytes;
 195         struct dma_fence *fence;
 196         uint64_t src_addr, dst_addr;
 197         void *cpu_addr;
 198         uint64_t flags;
 199         unsigned int i;
 200         int r;
 201
 202         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 203                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 204         BUG_ON(mem->mem_type == AMDGPU_PL_PREEMPT);
 205
 206         /* Map only what can't be accessed directly */
 207         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 208                 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
 209                         mm_cur->start;
 210                 return 0;
 211         }
 212
 213         *addr = adev->gmc.gart_start;
 214         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 215                 AMDGPU_GPU_PAGE_SIZE;
 216         *addr += mm_cur->start & ~PAGE_MASK;
 217
 218         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 219         num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
 220
 221         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 222                                      AMDGPU_IB_POOL_DELAYED, &job);
 223         if (r)
 224                 return r;
 225
 226         src_addr = num_dw * 4;
 227         src_addr += job->ibs[0].gpu_addr;
 228
 229         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 230         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 231         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 232                                 dst_addr, num_bytes, false);
 233
 234         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 235         WARN_ON(job->ibs[0].length_dw > num_dw);
 236
 237         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 238         if (tmz)
 239                 flags |= AMDGPU_PTE_TMZ;
 240
 241         cpu_addr = &job->ibs[0].ptr[num_dw];
 242
 243         if (mem->mem_type == TTM_PL_TT) {
 244                 dma_addr_t *dma_addr;
 245
 246                 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
 247                 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags,
 248                                     cpu_addr);
 249                 if (r)
 250                         goto error_free;
 251         } else {
 252                 dma_addr_t dma_address;
 253
 254                 dma_address = mm_cur->start;
 255                 dma_address += adev->vm_manager.vram_base_offset;
 256
 257                 for (i = 0; i < num_pages; ++i) {
 258                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 259                                             &dma_address, flags, cpu_addr);
 260                         if (r)
 261                                 goto error_free;
 262
 263                         dma_address += PAGE_SIZE;
 264                 }
 265         }
 266
 267         r = amdgpu_job_submit(job, &adev->mman.entity,
 268                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 269         if (r)
 270                 goto error_free;
 271
 272         dma_fence_put(fence);
 273
 274         return r;
 275
 276 error_free:
 277         amdgpu_job_free(job);
 278         return r;
 279 }
 280
 281 /**
 282  * amdgpu_ttm_copy_mem_to_mem - Helper function for copy
 283  * @adev: amdgpu device
 284  * @src: buffer/address where to read from
 285  * @dst: buffer/address where to write to
 286  * @size: number of bytes to copy
 287  * @tmz: if a secure copy should be used
 288  * @resv: resv object to sync to
 289  * @f: Returns the last fence if multiple jobs are submitted.
 290  *
 291  * The function copies @size bytes from {src->mem + src->offset} to
 292  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 293  * move and different for a BO to BO copy.
 294  *
 295  */
 296 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 297                                const struct amdgpu_copy_mem *src,
 298                                const struct amdgpu_copy_mem *dst,
 299                                uint64_t size, bool tmz,
 300                                struct dma_resv *resv,
 301                                struct dma_fence **f)
 302 {
 303         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 304                                         AMDGPU_GPU_PAGE_SIZE);
 305
 306         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 307         struct amdgpu_res_cursor src_mm, dst_mm;
 308         struct dma_fence *fence = NULL;
 309         int r = 0;
 310
 311         if (!adev->mman.buffer_funcs_enabled) {
 312                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 313                 return -EINVAL;
 314         }
 315
 316         amdgpu_res_first(src->mem, src->offset, size, &src_mm);
 317         amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
 318
 319         mutex_lock(&adev->mman.gtt_window_lock);
 320         while (src_mm.remaining) {
 321                 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK;
 322                 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK;
 323                 struct dma_fence *next;
 324                 uint32_t cur_size;
 325                 uint64_t from, to;
 326
 327                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 328                  * begins at an offset, then adjust the size accordingly
 329                  */
 330                 cur_size = max(src_page_offset, dst_page_offset);
 331                 cur_size = min(min3(src_mm.size, dst_mm.size, size),
 332                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 333
 334                 /* Map src to window 0 and dst to window 1. */
 335                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
 336                                           PFN_UP(cur_size + src_page_offset),
 337                                           0, ring, tmz, &from);
 338                 if (r)
 339                         goto error;
 340
 341                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
 342                                           PFN_UP(cur_size + dst_page_offset),
 343                                           1, ring, tmz, &to);
 344                 if (r)
 345                         goto error;
 346
 347                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 348                                        resv, &next, false, true, tmz);
 349                 if (r)
 350                         goto error;
 351
 352                 dma_fence_put(fence);
 353                 fence = next;
 354
 355                 amdgpu_res_next(&src_mm, cur_size);
 356                 amdgpu_res_next(&dst_mm, cur_size);
 357         }
 358 error:
 359         mutex_unlock(&adev->mman.gtt_window_lock);
 360         if (f)
 361                 *f = dma_fence_get(fence);
 362         dma_fence_put(fence);
 363         return r;
 364 }
 365
 366 /*
 367  * amdgpu_move_blit - Copy an entire buffer to another buffer
 368  *
 369  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 370  * help move buffers to and from VRAM.
 371  */
 372 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 373                             bool evict,
 374                             struct ttm_resource *new_mem,
 375                             struct ttm_resource *old_mem)
 376 {
 377         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 378         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 379         struct amdgpu_copy_mem src, dst;
 380         struct dma_fence *fence = NULL;
 381         int r;
 382
 383         src.bo = bo;
 384         dst.bo = bo;
 385         src.mem = old_mem;
 386         dst.mem = new_mem;
 387         src.offset = 0;
 388         dst.offset = 0;
 389
 390         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 391                                        new_mem->num_pages << PAGE_SHIFT,
 392                                        amdgpu_bo_encrypted(abo),
 393                                        bo->base.resv, &fence);
 394         if (r)
 395                 goto error;
 396
 397         /* clear the space being freed */
 398         if (old_mem->mem_type == TTM_PL_VRAM &&
 399             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 400                 struct dma_fence *wipe_fence = NULL;
 401
 402                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 403                                        NULL, &wipe_fence);
 404                 if (r) {
 405                         goto error;
 406                 } else if (wipe_fence) {
 407                         dma_fence_put(fence);
 408                         fence = wipe_fence;
 409                 }
 410         }
 411
 412         /* Always block for VM page tables before committing the new location */
 413         if (bo->type == ttm_bo_type_kernel)
 414                 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 415         else
 416                 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 417         dma_fence_put(fence);
 418         return r;
 419
 420 error:
 421         if (fence)
 422                 dma_fence_wait(fence, false);
 423         dma_fence_put(fence);
 424         return r;
 425 }
 426
 427 /*
 428  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 429  *
 430  * Called by amdgpu_bo_move()
 431  */
 432 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 433                                struct ttm_resource *mem)
 434 {
 435         uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT;
 436         struct amdgpu_res_cursor cursor;
 437
 438         if (mem->mem_type == TTM_PL_SYSTEM ||
 439             mem->mem_type == TTM_PL_TT)
 440                 return true;
 441         if (mem->mem_type != TTM_PL_VRAM)
 442                 return false;
 443
 444         amdgpu_res_first(mem, 0, mem_size, &cursor);
 445
 446         /* ttm_resource_ioremap only supports contiguous memory */
 447         if (cursor.size != mem_size)
 448                 return false;
 449
 450         return cursor.start + cursor.size <= adev->gmc.visible_vram_size;
 451 }
 452
 453 /*
 454  * amdgpu_bo_move - Move a buffer object to a new memory location
 455  *
 456  * Called by ttm_bo_handle_move_mem()
 457  */
 458 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 459                           struct ttm_operation_ctx *ctx,
 460                           struct ttm_resource *new_mem,
 461                           struct ttm_place *hop)
 462 {
 463         struct amdgpu_device *adev;
 464         struct amdgpu_bo *abo;
 465         struct ttm_resource *old_mem = bo->resource;
 466         int r;
 467
 468         if (new_mem->mem_type == TTM_PL_TT ||
 469             new_mem->mem_type == AMDGPU_PL_PREEMPT) {
 470                 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 471                 if (r)
 472                         return r;
 473         }
 474
 475         /* Can't move a pinned BO */
 476         abo = ttm_to_amdgpu_bo(bo);
 477         if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
 478                 return -EINVAL;
 479
 480         adev = amdgpu_ttm_adev(bo->bdev);
 481
 482         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 483                 ttm_bo_move_null(bo, new_mem);
 484                 goto out;
 485         }
 486         if (old_mem->mem_type == TTM_PL_SYSTEM &&
 487             (new_mem->mem_type == TTM_PL_TT ||
 488              new_mem->mem_type == AMDGPU_PL_PREEMPT)) {
 489                 ttm_bo_move_null(bo, new_mem);
 490                 goto out;
 491         }
 492         if ((old_mem->mem_type == TTM_PL_TT ||
 493              old_mem->mem_type == AMDGPU_PL_PREEMPT) &&
 494             new_mem->mem_type == TTM_PL_SYSTEM) {
 495                 r = ttm_bo_wait_ctx(bo, ctx);
 496                 if (r)
 497                         return r;
 498
 499                 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 500                 ttm_resource_free(bo, &bo->resource);
 501                 ttm_bo_assign_mem(bo, new_mem);
 502                 goto out;
 503         }
 504
 505         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 506             old_mem->mem_type == AMDGPU_PL_GWS ||
 507             old_mem->mem_type == AMDGPU_PL_OA ||
 508             new_mem->mem_type == AMDGPU_PL_GDS ||
 509             new_mem->mem_type == AMDGPU_PL_GWS ||
 510             new_mem->mem_type == AMDGPU_PL_OA) {
 511                 /* Nothing to save here */
 512                 ttm_bo_move_null(bo, new_mem);
 513                 goto out;
 514         }
 515
 516         if (adev->mman.buffer_funcs_enabled) {
 517                 if (((old_mem->mem_type == TTM_PL_SYSTEM &&
 518                       new_mem->mem_type == TTM_PL_VRAM) ||
 519                      (old_mem->mem_type == TTM_PL_VRAM &&
 520                       new_mem->mem_type == TTM_PL_SYSTEM))) {
 521                         hop->fpfn = 0;
 522                         hop->lpfn = 0;
 523                         hop->mem_type = TTM_PL_TT;
 524                         hop->flags = 0;
 525                         return -EMULTIHOP;
 526                 }
 527
 528                 r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 529         } else {
 530                 r = -ENODEV;
 531         }
 532
 533         if (r) {
 534                 /* Check that all memory is CPU accessible */
 535                 if (!amdgpu_mem_visible(adev, old_mem) ||
 536                     !amdgpu_mem_visible(adev, new_mem)) {
 537                         pr_err("Move buffer fallback to memcpy unavailable\n");
 538                         return r;
 539                 }
 540
 541                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 542                 if (r)
 543                         return r;
 544         }
 545
 546         if (bo->type == ttm_bo_type_device &&
 547             new_mem->mem_type == TTM_PL_VRAM &&
 548             old_mem->mem_type != TTM_PL_VRAM) {
 549                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 550                  * accesses the BO after it's moved.
 551                  */
 552                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 553         }
 554
 555 out:
 556         /* update statistics */
 557         atomic64_add(bo->base.size, &adev->num_bytes_moved);
 558         amdgpu_bo_move_notify(bo, evict, new_mem);
 559         return 0;
 560 }
 561
 562 /*
 563  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 564  *
 565  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 566  */
 567 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
 568                                      struct ttm_resource *mem)
 569 {
 570         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 571         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 572
 573         switch (mem->mem_type) {
 574         case TTM_PL_SYSTEM:
 575                 /* system memory */
 576                 return 0;
 577         case TTM_PL_TT:
 578         case AMDGPU_PL_PREEMPT:
 579                 break;
 580         case TTM_PL_VRAM:
 581                 mem->bus.offset = mem->start << PAGE_SHIFT;
 582                 /* check if it's visible */
 583                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 584                         return -EINVAL;
 585
 586                 if (adev->mman.aper_base_kaddr &&
 587                     mem->placement & TTM_PL_FLAG_CONTIGUOUS)
 588                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 589                                         mem->bus.offset;
 590
 591                 mem->bus.offset += adev->gmc.aper_base;
 592                 mem->bus.is_iomem = true;
 593                 if (adev->gmc.xgmi.connected_to_cpu)
 594                         mem->bus.caching = ttm_cached;
 595                 else
 596                         mem->bus.caching = ttm_write_combined;
 597                 break;
 598         default:
 599                 return -EINVAL;
 600         }
 601         return 0;
 602 }
 603
 604 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 605                                            unsigned long page_offset)
 606 {
 607         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 608         struct amdgpu_res_cursor cursor;
 609
 610         amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0,
 611                          &cursor);
 612         return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
 613 }
 614
 615 /**
 616  * amdgpu_ttm_domain_start - Returns GPU start address
 617  * @adev: amdgpu device object
 618  * @type: type of the memory
 619  *
 620  * Returns:
 621  * GPU start address of a memory domain
 622  */
 623
 624 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 625 {
 626         switch (type) {
 627         case TTM_PL_TT:
 628                 return adev->gmc.gart_start;
 629         case TTM_PL_VRAM:
 630                 return adev->gmc.vram_start;
 631         }
 632
 633         return 0;
 634 }
 635
 636 /*
 637  * TTM backend functions.
 638  */
 639 struct amdgpu_ttm_tt {
 640         struct ttm_tt   ttm;
 641         struct drm_gem_object   *gobj;
 642         u64                     offset;
 643         uint64_t                userptr;
 644         struct task_struct      *usertask;
 645         uint32_t                userflags;
 646         bool                    bound;
 647 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 648         struct hmm_range        *range;
 649 #endif
 650 };
 651
 652 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 653 /*
 654  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 655  * memory and start HMM tracking CPU page table update
 656  *
 657  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 658  * once afterwards to stop HMM tracking
 659  */
 660 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 661 {
 662         struct ttm_tt *ttm = bo->tbo.ttm;
 663         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 664         unsigned long start = gtt->userptr;
 665         struct vm_area_struct *vma;
 666         struct mm_struct *mm;
 667         bool readonly;
 668         int r = 0;
 669
 670         mm = bo->notifier.mm;
 671         if (unlikely(!mm)) {
 672                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 673                 return -EFAULT;
 674         }
 675
 676         /* Another get_user_pages is running at the same time?? */
 677         if (WARN_ON(gtt->range))
 678                 return -EFAULT;
 679
 680         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 681                 return -ESRCH;
 682
 683         mmap_read_lock(mm);
 684         vma = find_vma(mm, start);
 685         mmap_read_unlock(mm);
 686         if (unlikely(!vma || start < vma->vm_start)) {
 687                 r = -EFAULT;
 688                 goto out_putmm;
 689         }
 690         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 691                 vma->vm_file)) {
 692                 r = -EPERM;
 693                 goto out_putmm;
 694         }
 695
 696         readonly = amdgpu_ttm_tt_is_readonly(ttm);
 697         r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start,
 698                                        ttm->num_pages, &gtt->range, readonly,
 699                                        false);
 700 out_putmm:
 701         mmput(mm);
 702
 703         return r;
 704 }
 705
 706 /*
 707  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 708  * Check if the pages backing this ttm range have been invalidated
 709  *
 710  * Returns: true if pages are still valid
 711  */
 712 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 713 {
 714         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 715         bool r = false;
 716
 717         if (!gtt || !gtt->userptr)
 718                 return false;
 719
 720         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
 721                 gtt->userptr, ttm->num_pages);
 722
 723         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
 724                 "No user pages to check\n");
 725
 726         if (gtt->range) {
 727                 /*
 728                  * FIXME: Must always hold notifier_lock for this, and must
 729                  * not ignore the return code.
 730                  */
 731                 r = amdgpu_hmm_range_get_pages_done(gtt->range);
 732                 gtt->range = NULL;
 733         }
 734
 735         return !r;
 736 }
 737 #endif
 738
 739 /*
 740  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 741  *
 742  * Called by amdgpu_cs_list_validate(). This creates the page list
 743  * that backs user memory and will ultimately be mapped into the device
 744  * address space.
 745  */
 746 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 747 {
 748         unsigned long i;
 749
 750         for (i = 0; i < ttm->num_pages; ++i)
 751                 ttm->pages[i] = pages ? pages[i] : NULL;
 752 }
 753
 754 /*
 755  * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
 756  *
 757  * Called by amdgpu_ttm_backend_bind()
 758  **/
 759 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
 760                                      struct ttm_tt *ttm)
 761 {
 762         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 763         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 764         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 765         enum dma_data_direction direction = write ?
 766                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 767         int r;
 768
 769         /* Allocate an SG array and squash pages into it */
 770         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 771                                       (u64)ttm->num_pages << PAGE_SHIFT,
 772                                       GFP_KERNEL);
 773         if (r)
 774                 goto release_sg;
 775
 776         /* Map SG to device */
 777         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 778         if (r)
 779                 goto release_sg;
 780
 781         /* convert SG to linear array of pages and dma addresses */
 782         drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 783                                        ttm->num_pages);
 784
 785         return 0;
 786
 787 release_sg:
 788         kfree(ttm->sg);
 789         ttm->sg = NULL;
 790         return r;
 791 }
 792
 793 /*
 794  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 795  */
 796 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
 797                                         struct ttm_tt *ttm)
 798 {
 799         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 800         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 801         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 802         enum dma_data_direction direction = write ?
 803                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 804
 805         /* double check that we don't free the table twice */
 806         if (!ttm->sg || !ttm->sg->sgl)
 807                 return;
 808
 809         /* unmap the pages mapped to the device */
 810         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 811         sg_free_table(ttm->sg);
 812
 813 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 814         if (gtt->range) {
 815                 unsigned long i;
 816
 817                 for (i = 0; i < ttm->num_pages; i++) {
 818                         if (ttm->pages[i] !=
 819                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
 820                                 break;
 821                 }
 822
 823                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
 824         }
 825 #endif
 826 }
 827
 828 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 829                                 struct ttm_buffer_object *tbo,
 830                                 uint64_t flags)
 831 {
 832         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 833         struct ttm_tt *ttm = tbo->ttm;
 834         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 835         int r;
 836
 837         if (amdgpu_bo_encrypted(abo))
 838                 flags |= AMDGPU_PTE_TMZ;
 839
 840         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
 841                 uint64_t page_idx = 1;
 842
 843                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 844                                 ttm->pages, gtt->ttm.dma_address, flags);
 845                 if (r)
 846                         goto gart_bind_fail;
 847
 848                 /* The memory type of the first page defaults to UC. Now
 849                  * modify the memory type to NC from the second page of
 850                  * the BO onward.
 851                  */
 852                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
 853                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
 854
 855                 r = amdgpu_gart_bind(adev,
 856                                 gtt->offset + (page_idx << PAGE_SHIFT),
 857                                 ttm->num_pages - page_idx,
 858                                 &ttm->pages[page_idx],
 859                                 &(gtt->ttm.dma_address[page_idx]), flags);
 860         } else {
 861                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 862                                      ttm->pages, gtt->ttm.dma_address, flags);
 863         }
 864
 865 gart_bind_fail:
 866         if (r)
 867                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
 868                           ttm->num_pages, gtt->offset);
 869
 870         return r;
 871 }
 872
 873 /*
 874  * amdgpu_ttm_backend_bind - Bind GTT memory
 875  *
 876  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
 877  * This handles binding GTT memory to the device address space.
 878  */
 879 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
 880                                    struct ttm_tt *ttm,
 881                                    struct ttm_resource *bo_mem)
 882 {
 883         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 884         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 885         uint64_t flags;
 886         int r = 0;
 887
 888         if (!bo_mem)
 889                 return -EINVAL;
 890
 891         if (gtt->bound)
 892                 return 0;
 893
 894         if (gtt->userptr) {
 895                 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
 896                 if (r) {
 897                         DRM_ERROR("failed to pin userptr\n");
 898                         return r;
 899                 }
 900         } else if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
 901                 if (!ttm->sg) {
 902                         struct dma_buf_attachment *attach;
 903                         struct sg_table *sgt;
 904
 905                         attach = gtt->gobj->import_attach;
 906                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
 907                         if (IS_ERR(sgt))
 908                                 return PTR_ERR(sgt);
 909
 910                         ttm->sg = sgt;
 911                 }
 912
 913                 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 914                                                ttm->num_pages);
 915         }
 916
 917         if (!ttm->num_pages) {
 918                 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
 919                      ttm->num_pages, bo_mem, ttm);
 920         }
 921
 922         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 923             bo_mem->mem_type == AMDGPU_PL_GWS ||
 924             bo_mem->mem_type == AMDGPU_PL_OA)
 925                 return -EINVAL;
 926
 927         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
 928                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
 929                 return 0;
 930         }
 931
 932         /* compute PTE flags relevant to this BO memory */
 933         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
 934
 935         /* bind pages into GART page tables */
 936         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 937         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 938                 ttm->pages, gtt->ttm.dma_address, flags);
 939
 940         if (r)
 941                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
 942                           ttm->num_pages, gtt->offset);
 943         gtt->bound = true;
 944         return r;
 945 }
 946
 947 /*
 948  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
 949  * through AGP or GART aperture.
 950  *
 951  * If bo is accessible through AGP aperture, then use AGP aperture
 952  * to access bo; otherwise allocate logical space in GART aperture
 953  * and map bo to GART aperture.
 954  */
 955 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 956 {
 957         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 958         struct ttm_operation_ctx ctx = { false, false };
 959         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
 960         struct ttm_placement placement;
 961         struct ttm_place placements;
 962         struct ttm_resource *tmp;
 963         uint64_t addr, flags;
 964         int r;
 965
 966         if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET)
 967                 return 0;
 968
 969         addr = amdgpu_gmc_agp_addr(bo);
 970         if (addr != AMDGPU_BO_INVALID_OFFSET) {
 971                 bo->resource->start = addr >> PAGE_SHIFT;
 972                 return 0;
 973         }
 974
 975         /* allocate GART space */
 976         placement.num_placement = 1;
 977         placement.placement = &placements;
 978         placement.num_busy_placement = 1;
 979         placement.busy_placement = &placements;
 980         placements.fpfn = 0;
 981         placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 982         placements.mem_type = TTM_PL_TT;
 983         placements.flags = bo->resource->placement;
 984
 985         r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
 986         if (unlikely(r))
 987                 return r;
 988
 989         /* compute PTE flags for this buffer object */
 990         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
 991
 992         /* Bind pages */
 993         gtt->offset = (u64)tmp->start << PAGE_SHIFT;
 994         r = amdgpu_ttm_gart_bind(adev, bo, flags);
 995         if (unlikely(r)) {
 996                 ttm_resource_free(bo, &tmp);
 997                 return r;
 998         }
 999
1000         amdgpu_gart_invalidate_tlb(adev);
1001         ttm_resource_free(bo, &bo->resource);
1002         ttm_bo_assign_mem(bo, tmp);
1003
1004         return 0;
1005 }
1006
1007 /*
1008  * amdgpu_ttm_recover_gart - Rebind GTT pages
1009  *
1010  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1011  * rebind GTT pages during a GPU reset.
1012  */
1013 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1014 {
1015         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1016         uint64_t flags;
1017         int r;
1018
1019         if (!tbo->ttm)
1020                 return 0;
1021
1022         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource);
1023         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1024
1025         return r;
1026 }
1027
1028 /*
1029  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1030  *
1031  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1032  * ttm_tt_destroy().
1033  */
1034 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
1035                                       struct ttm_tt *ttm)
1036 {
1037         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1038         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1039         int r;
1040
1041         /* if the pages have userptr pinning then clear that first */
1042         if (gtt->userptr) {
1043                 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1044         } else if (ttm->sg && gtt->gobj->import_attach) {
1045                 struct dma_buf_attachment *attach;
1046
1047                 attach = gtt->gobj->import_attach;
1048                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1049                 ttm->sg = NULL;
1050         }
1051
1052         if (!gtt->bound)
1053                 return;
1054
1055         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1056                 return;
1057
1058         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1059         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1060         if (r)
1061                 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n",
1062                           gtt->ttm.num_pages, gtt->offset);
1063         gtt->bound = false;
1064 }
1065
1066 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1067                                        struct ttm_tt *ttm)
1068 {
1069         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1070
1071         amdgpu_ttm_backend_unbind(bdev, ttm);
1072         ttm_tt_destroy_common(bdev, ttm);
1073         if (gtt->usertask)
1074                 put_task_struct(gtt->usertask);
1075
1076         ttm_tt_fini(&gtt->ttm);
1077         kfree(gtt);
1078 }
1079
1080 /**
1081  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1082  *
1083  * @bo: The buffer object to create a GTT ttm_tt object around
1084  * @page_flags: Page flags to be added to the ttm_tt object
1085  *
1086  * Called by ttm_tt_create().
1087  */
1088 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1089                                            uint32_t page_flags)
1090 {
1091         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1092         struct amdgpu_ttm_tt *gtt;
1093         enum ttm_caching caching;
1094
1095         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1096         if (gtt == NULL) {
1097                 return NULL;
1098         }
1099         gtt->gobj = &bo->base;
1100
1101         if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1102                 caching = ttm_write_combined;
1103         else
1104                 caching = ttm_cached;
1105
1106         /* allocate space for the uninitialized page entries */
1107         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1108                 kfree(gtt);
1109                 return NULL;
1110         }
1111         return &gtt->ttm;
1112 }
1113
1114 /*
1115  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1116  *
1117  * Map the pages of a ttm_tt object to an address space visible
1118  * to the underlying device.
1119  */
1120 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1121                                   struct ttm_tt *ttm,
1122                                   struct ttm_operation_ctx *ctx)
1123 {
1124         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1125         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1126
1127         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1128         if (gtt && gtt->userptr) {
1129                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1130                 if (!ttm->sg)
1131                         return -ENOMEM;
1132
1133                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1134                 return 0;
1135         }
1136
1137         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1138                 return 0;
1139
1140         return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1141 }
1142
1143 /*
1144  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1145  *
1146  * Unmaps pages of a ttm_tt object from the device address space and
1147  * unpopulates the page array backing it.
1148  */
1149 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1150                                      struct ttm_tt *ttm)
1151 {
1152         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1153         struct amdgpu_device *adev;
1154
1155         if (gtt && gtt->userptr) {
1156                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1157                 kfree(ttm->sg);
1158                 ttm->sg = NULL;
1159                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1160                 return;
1161         }
1162
1163         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1164                 return;
1165
1166         adev = amdgpu_ttm_adev(bdev);
1167         return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1168 }
1169
1170 /**
1171  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1172  * task
1173  *
1174  * @bo: The ttm_buffer_object to bind this userptr to
1175  * @addr:  The address in the current tasks VM space to use
1176  * @flags: Requirements of userptr object.
1177  *
1178  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1179  * to current task
1180  */
1181 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1182                               uint64_t addr, uint32_t flags)
1183 {
1184         struct amdgpu_ttm_tt *gtt;
1185
1186         if (!bo->ttm) {
1187                 /* TODO: We want a separate TTM object type for userptrs */
1188                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1189                 if (bo->ttm == NULL)
1190                         return -ENOMEM;
1191         }
1192
1193         gtt = (void *)bo->ttm;
1194         gtt->userptr = addr;
1195         gtt->userflags = flags;
1196
1197         if (gtt->usertask)
1198                 put_task_struct(gtt->usertask);
1199         gtt->usertask = current->group_leader;
1200         get_task_struct(gtt->usertask);
1201
1202         return 0;
1203 }
1204
1205 /*
1206  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1207  */
1208 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1209 {
1210         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1211
1212         if (gtt == NULL)
1213                 return NULL;
1214
1215         if (gtt->usertask == NULL)
1216                 return NULL;
1217
1218         return gtt->usertask->mm;
1219 }
1220
1221 /*
1222  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1223  * address range for the current task.
1224  *
1225  */
1226 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1227                                   unsigned long end)
1228 {
1229         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1230         unsigned long size;
1231
1232         if (gtt == NULL || !gtt->userptr)
1233                 return false;
1234
1235         /* Return false if no part of the ttm_tt object lies within
1236          * the range
1237          */
1238         size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1239         if (gtt->userptr > end || gtt->userptr + size <= start)
1240                 return false;
1241
1242         return true;
1243 }
1244
1245 /*
1246  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1247  */
1248 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1249 {
1250         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1251
1252         if (gtt == NULL || !gtt->userptr)
1253                 return false;
1254
1255         return true;
1256 }
1257
1258 /*
1259  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1260  */
1261 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1262 {
1263         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1264
1265         if (gtt == NULL)
1266                 return false;
1267
1268         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1269 }
1270
1271 /**
1272  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1273  *
1274  * @ttm: The ttm_tt object to compute the flags for
1275  * @mem: The memory registry backing this ttm_tt object
1276  *
1277  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1278  */
1279 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1280 {
1281         uint64_t flags = 0;
1282
1283         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1284                 flags |= AMDGPU_PTE_VALID;
1285
1286         if (mem && (mem->mem_type == TTM_PL_TT ||
1287                     mem->mem_type == AMDGPU_PL_PREEMPT)) {
1288                 flags |= AMDGPU_PTE_SYSTEM;
1289
1290                 if (ttm->caching == ttm_cached)
1291                         flags |= AMDGPU_PTE_SNOOPED;
1292         }
1293
1294         if (mem && mem->mem_type == TTM_PL_VRAM &&
1295                         mem->bus.caching == ttm_cached)
1296                 flags |= AMDGPU_PTE_SNOOPED;
1297
1298         return flags;
1299 }
1300
1301 /**
1302  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1303  *
1304  * @adev: amdgpu_device pointer
1305  * @ttm: The ttm_tt object to compute the flags for
1306  * @mem: The memory registry backing this ttm_tt object
1307  *
1308  * Figure out the flags to use for a VM PTE (Page Table Entry).
1309  */
1310 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1311                                  struct ttm_resource *mem)
1312 {
1313         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1314
1315         flags |= adev->gart.gart_pte_flags;
1316         flags |= AMDGPU_PTE_READABLE;
1317
1318         if (!amdgpu_ttm_tt_is_readonly(ttm))
1319                 flags |= AMDGPU_PTE_WRITEABLE;
1320
1321         return flags;
1322 }
1323
1324 /*
1325  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1326  * object.
1327  *
1328  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1329  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1330  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1331  * used to clean out a memory space.
1332  */
1333 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1334                                             const struct ttm_place *place)
1335 {
1336         unsigned long num_pages = bo->resource->num_pages;
1337         struct amdgpu_res_cursor cursor;
1338         struct dma_resv_list *flist;
1339         struct dma_fence *f;
1340         int i;
1341
1342         /* Swapout? */
1343         if (bo->resource->mem_type == TTM_PL_SYSTEM)
1344                 return true;
1345
1346         if (bo->type == ttm_bo_type_kernel &&
1347             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1348                 return false;
1349
1350         /* If bo is a KFD BO, check if the bo belongs to the current process.
1351          * If true, then return false as any KFD process needs all its BOs to
1352          * be resident to run successfully
1353          */
1354         flist = dma_resv_shared_list(bo->base.resv);
1355         if (flist) {
1356                 for (i = 0; i < flist->shared_count; ++i) {
1357                         f = rcu_dereference_protected(flist->shared[i],
1358                                 dma_resv_held(bo->base.resv));
1359                         if (amdkfd_fence_check_mm(f, current->mm))
1360                                 return false;
1361                 }
1362         }
1363
1364         switch (bo->resource->mem_type) {
1365         case AMDGPU_PL_PREEMPT:
1366                 /* Preemptible BOs don't own system resources managed by the
1367                  * driver (pages, VRAM, GART space). They point to resources
1368                  * owned by someone else (e.g. pageable memory in user mode
1369                  * or a DMABuf). They are used in a preemptible context so we
1370                  * can guarantee no deadlocks and good QoS in case of MMU
1371                  * notifiers or DMABuf move notifiers from the resource owner.
1372                  */
1373                 return false;
1374         case TTM_PL_TT:
1375                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1376                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1377                         return false;
1378                 return true;
1379
1380         case TTM_PL_VRAM:
1381                 /* Check each drm MM node individually */
1382                 amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT,
1383                                  &cursor);
1384                 while (cursor.remaining) {
1385                         if (place->fpfn < PFN_DOWN(cursor.start + cursor.size)
1386                             && !(place->lpfn &&
1387                                  place->lpfn <= PFN_DOWN(cursor.start)))
1388                                 return true;
1389
1390                         amdgpu_res_next(&cursor, cursor.size);
1391                 }
1392                 return false;
1393
1394         default:
1395                 break;
1396         }
1397
1398         return ttm_bo_eviction_valuable(bo, place);
1399 }
1400
1401 /**
1402  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1403  *
1404  * @bo:  The buffer object to read/write
1405  * @offset:  Offset into buffer object
1406  * @buf:  Secondary buffer to write/read from
1407  * @len: Length in bytes of access
1408  * @write:  true if writing
1409  *
1410  * This is used to access VRAM that backs a buffer object via MMIO
1411  * access for debugging purposes.
1412  */
1413 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1414                                     unsigned long offset, void *buf, int len,
1415                                     int write)
1416 {
1417         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1418         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1419         struct amdgpu_res_cursor cursor;
1420         unsigned long flags;
1421         uint32_t value = 0;
1422         int ret = 0;
1423
1424         if (bo->resource->mem_type != TTM_PL_VRAM)
1425                 return -EIO;
1426
1427         amdgpu_res_first(bo->resource, offset, len, &cursor);
1428         while (cursor.remaining) {
1429                 uint64_t aligned_pos = cursor.start & ~(uint64_t)3;
1430                 uint64_t bytes = 4 - (cursor.start & 3);
1431                 uint32_t shift = (cursor.start & 3) * 8;
1432                 uint32_t mask = 0xffffffff << shift;
1433
1434                 if (cursor.size < bytes) {
1435                         mask &= 0xffffffff >> (bytes - cursor.size) * 8;
1436                         bytes = cursor.size;
1437                 }
1438
1439                 if (mask != 0xffffffff) {
1440                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1441                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1442                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1443                         value = RREG32_NO_KIQ(mmMM_DATA);
1444                         if (write) {
1445                                 value &= ~mask;
1446                                 value |= (*(uint32_t *)buf << shift) & mask;
1447                                 WREG32_NO_KIQ(mmMM_DATA, value);
1448                         }
1449                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1450                         if (!write) {
1451                                 value = (value & mask) >> shift;
1452                                 memcpy(buf, &value, bytes);
1453                         }
1454                 } else {
1455                         bytes = cursor.size & ~0x3ULL;
1456                         amdgpu_device_vram_access(adev, cursor.start,
1457                                                   (uint32_t *)buf, bytes,
1458                                                   write);
1459                 }
1460
1461                 ret += bytes;
1462                 buf = (uint8_t *)buf + bytes;
1463                 amdgpu_res_next(&cursor, bytes);
1464         }
1465
1466         return ret;
1467 }
1468
1469 static void
1470 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1471 {
1472         amdgpu_bo_move_notify(bo, false, NULL);
1473 }
1474
1475 static struct ttm_device_funcs amdgpu_bo_driver = {
1476         .ttm_tt_create = &amdgpu_ttm_tt_create,
1477         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1478         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1479         .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1480         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1481         .evict_flags = &amdgpu_evict_flags,
1482         .move = &amdgpu_bo_move,
1483         .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1484         .release_notify = &amdgpu_bo_release_notify,
1485         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1486         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1487         .access_memory = &amdgpu_ttm_access_memory,
1488         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1489 };
1490
1491 /*
1492  * Firmware Reservation functions
1493  */
1494 /**
1495  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1496  *
1497  * @adev: amdgpu_device pointer
1498  *
1499  * free fw reserved vram if it has been reserved.
1500  */
1501 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1502 {
1503         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1504                 NULL, &adev->mman.fw_vram_usage_va);
1505 }
1506
1507 /**
1508  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1509  *
1510  * @adev: amdgpu_device pointer
1511  *
1512  * create bo vram reservation from fw.
1513  */
1514 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1515 {
1516         uint64_t vram_size = adev->gmc.visible_vram_size;
1517
1518         adev->mman.fw_vram_usage_va = NULL;
1519         adev->mman.fw_vram_usage_reserved_bo = NULL;
1520
1521         if (adev->mman.fw_vram_usage_size == 0 ||
1522             adev->mman.fw_vram_usage_size > vram_size)
1523                 return 0;
1524
1525         return amdgpu_bo_create_kernel_at(adev,
1526                                           adev->mman.fw_vram_usage_start_offset,
1527                                           adev->mman.fw_vram_usage_size,
1528                                           AMDGPU_GEM_DOMAIN_VRAM,
1529                                           &adev->mman.fw_vram_usage_reserved_bo,
1530                                           &adev->mman.fw_vram_usage_va);
1531 }
1532
1533 /*
1534  * Memoy training reservation functions
1535  */
1536
1537 /**
1538  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1539  *
1540  * @adev: amdgpu_device pointer
1541  *
1542  * free memory training reserved vram if it has been reserved.
1543  */
1544 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1545 {
1546         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1547
1548         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1549         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1550         ctx->c2p_bo = NULL;
1551
1552         return 0;
1553 }
1554
1555 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1556 {
1557         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1558
1559         memset(ctx, 0, sizeof(*ctx));
1560
1561         ctx->c2p_train_data_offset =
1562                 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1563         ctx->p2c_train_data_offset =
1564                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1565         ctx->train_data_size =
1566                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1567
1568         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1569                         ctx->train_data_size,
1570                         ctx->p2c_train_data_offset,
1571                         ctx->c2p_train_data_offset);
1572 }
1573
1574 /*
1575  * reserve TMR memory at the top of VRAM which holds
1576  * IP Discovery data and is protected by PSP.
1577  */
1578 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1579 {
1580         int ret;
1581         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1582         bool mem_train_support = false;
1583
1584         if (!amdgpu_sriov_vf(adev)) {
1585                 if (amdgpu_atomfirmware_mem_training_supported(adev))
1586                         mem_train_support = true;
1587                 else
1588                         DRM_DEBUG("memory training does not support!\n");
1589         }
1590
1591         /*
1592          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1593          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1594          *
1595          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1596          * discovery data and G6 memory training data respectively
1597          */
1598         adev->mman.discovery_tmr_size =
1599                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1600         if (!adev->mman.discovery_tmr_size)
1601                 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1602
1603         if (mem_train_support) {
1604                 /* reserve vram for mem train according to TMR location */
1605                 amdgpu_ttm_training_data_block_init(adev);
1606                 ret = amdgpu_bo_create_kernel_at(adev,
1607                                          ctx->c2p_train_data_offset,
1608                                          ctx->train_data_size,
1609                                          AMDGPU_GEM_DOMAIN_VRAM,
1610                                          &ctx->c2p_bo,
1611                                          NULL);
1612                 if (ret) {
1613                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1614                         amdgpu_ttm_training_reserve_vram_fini(adev);
1615                         return ret;
1616                 }
1617                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1618         }
1619
1620         ret = amdgpu_bo_create_kernel_at(adev,
1621                                 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1622                                 adev->mman.discovery_tmr_size,
1623                                 AMDGPU_GEM_DOMAIN_VRAM,
1624                                 &adev->mman.discovery_memory,
1625                                 NULL);
1626         if (ret) {
1627                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1628                 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1629                 return ret;
1630         }
1631
1632         return 0;
1633 }
1634
1635 /*
1636  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1637  * gtt/vram related fields.
1638  *
1639  * This initializes all of the memory space pools that the TTM layer
1640  * will need such as the GTT space (system memory mapped to the device),
1641  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1642  * can be mapped per VMID.
1643  */
1644 int amdgpu_ttm_init(struct amdgpu_device *adev)
1645 {
1646         uint64_t gtt_size;
1647         int r;
1648         u64 vis_vram_limit;
1649
1650         mutex_init(&adev->mman.gtt_window_lock);
1651
1652         /* No others user of address space so set it to 0 */
1653         r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1654                                adev_to_drm(adev)->anon_inode->i_mapping,
1655                                adev_to_drm(adev)->vma_offset_manager,
1656                                adev->need_swiotlb,
1657                                dma_addressing_limited(adev->dev));
1658         if (r) {
1659                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1660                 return r;
1661         }
1662         adev->mman.initialized = true;
1663
1664         /* Initialize VRAM pool with all of VRAM divided into pages */
1665         r = amdgpu_vram_mgr_init(adev);
1666         if (r) {
1667                 DRM_ERROR("Failed initializing VRAM heap.\n");
1668                 return r;
1669         }
1670
1671         /* Reduce size of CPU-visible VRAM if requested */
1672         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1673         if (amdgpu_vis_vram_limit > 0 &&
1674             vis_vram_limit <= adev->gmc.visible_vram_size)
1675                 adev->gmc.visible_vram_size = vis_vram_limit;
1676
1677         /* Change the size here instead of the init above so only lpfn is affected */
1678         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1679 #ifdef CONFIG_64BIT
1680 #ifdef CONFIG_X86
1681         if (adev->gmc.xgmi.connected_to_cpu)
1682                 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1683                                 adev->gmc.visible_vram_size);
1684
1685         else
1686 #endif
1687                 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1688                                 adev->gmc.visible_vram_size);
1689 #endif
1690
1691         /*
1692          *The reserved vram for firmware must be pinned to the specified
1693          *place on the VRAM, so reserve it early.
1694          */
1695         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1696         if (r) {
1697                 return r;
1698         }
1699
1700         /*
1701          * only NAVI10 and onwards ASIC support for IP discovery.
1702          * If IP discovery enabled, a block of memory should be
1703          * reserved for IP discovey.
1704          */
1705         if (adev->mman.discovery_bin) {
1706                 r = amdgpu_ttm_reserve_tmr(adev);
1707                 if (r)
1708                         return r;
1709         }
1710
1711         /* allocate memory as required for VGA
1712          * This is used for VGA emulation and pre-OS scanout buffers to
1713          * avoid display artifacts while transitioning between pre-OS
1714          * and driver.  */
1715         r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1716                                        AMDGPU_GEM_DOMAIN_VRAM,
1717                                        &adev->mman.stolen_vga_memory,
1718                                        NULL);
1719         if (r)
1720                 return r;
1721         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1722                                        adev->mman.stolen_extended_size,
1723                                        AMDGPU_GEM_DOMAIN_VRAM,
1724                                        &adev->mman.stolen_extended_memory,
1725                                        NULL);
1726         if (r)
1727                 return r;
1728         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset,
1729                                        adev->mman.stolen_reserved_size,
1730                                        AMDGPU_GEM_DOMAIN_VRAM,
1731                                        &adev->mman.stolen_reserved_memory,
1732                                        NULL);
1733         if (r)
1734                 return r;
1735
1736         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1737                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1738
1739         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1740          * or whatever the user passed on module init */
1741         if (amdgpu_gtt_size == -1) {
1742                 struct sysinfo si;
1743
1744                 si_meminfo(&si);
1745                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1746                                adev->gmc.mc_vram_size),
1747                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1748         }
1749         else
1750                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1751
1752         /* Initialize GTT memory pool */
1753         r = amdgpu_gtt_mgr_init(adev, gtt_size);
1754         if (r) {
1755                 DRM_ERROR("Failed initializing GTT heap.\n");
1756                 return r;
1757         }
1758         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1759                  (unsigned)(gtt_size / (1024 * 1024)));
1760
1761         /* Initialize preemptible memory pool */
1762         r = amdgpu_preempt_mgr_init(adev);
1763         if (r) {
1764                 DRM_ERROR("Failed initializing PREEMPT heap.\n");
1765                 return r;
1766         }
1767
1768         /* Initialize various on-chip memory pools */
1769         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1770         if (r) {
1771                 DRM_ERROR("Failed initializing GDS heap.\n");
1772                 return r;
1773         }
1774
1775         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1776         if (r) {
1777                 DRM_ERROR("Failed initializing gws heap.\n");
1778                 return r;
1779         }
1780
1781         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1782         if (r) {
1783                 DRM_ERROR("Failed initializing oa heap.\n");
1784                 return r;
1785         }
1786
1787         return 0;
1788 }
1789
1790 /*
1791  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1792  */
1793 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1794 {
1795         if (!adev->mman.initialized)
1796                 return;
1797
1798         amdgpu_ttm_training_reserve_vram_fini(adev);
1799         /* return the stolen vga memory back to VRAM */
1800         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1801         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1802         /* return the IP Discovery TMR memory back to VRAM */
1803         amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1804         if (adev->mman.stolen_reserved_size)
1805                 amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory,
1806                                       NULL, NULL);
1807         amdgpu_ttm_fw_reserve_vram_fini(adev);
1808
1809         amdgpu_vram_mgr_fini(adev);
1810         amdgpu_gtt_mgr_fini(adev);
1811         amdgpu_preempt_mgr_fini(adev);
1812         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
1813         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
1814         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
1815         ttm_device_fini(&adev->mman.bdev);
1816         adev->mman.initialized = false;
1817         DRM_INFO("amdgpu: ttm finalized\n");
1818 }
1819
1820 /**
1821  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1822  *
1823  * @adev: amdgpu_device pointer
1824  * @enable: true when we can use buffer functions.
1825  *
1826  * Enable/disable use of buffer functions during suspend/resume. This should
1827  * only be called at bootup or when userspace isn't running.
1828  */
1829 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1830 {
1831         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1832         uint64_t size;
1833         int r;
1834
1835         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
1836             adev->mman.buffer_funcs_enabled == enable)
1837                 return;
1838
1839         if (enable) {
1840                 struct amdgpu_ring *ring;
1841                 struct drm_gpu_scheduler *sched;
1842
1843                 ring = adev->mman.buffer_funcs_ring;
1844                 sched = &ring->sched;
1845                 r = drm_sched_entity_init(&adev->mman.entity,
1846                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
1847                                           1, NULL);
1848                 if (r) {
1849                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1850                                   r);
1851                         return;
1852                 }
1853         } else {
1854                 drm_sched_entity_destroy(&adev->mman.entity);
1855                 dma_fence_put(man->move);
1856                 man->move = NULL;
1857         }
1858
1859         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1860         if (enable)
1861                 size = adev->gmc.real_vram_size;
1862         else
1863                 size = adev->gmc.visible_vram_size;
1864         man->size = size >> PAGE_SHIFT;
1865         adev->mman.buffer_funcs_enabled = enable;
1866 }
1867
1868 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1869                        uint64_t dst_offset, uint32_t byte_count,
1870                        struct dma_resv *resv,
1871                        struct dma_fence **fence, bool direct_submit,
1872                        bool vm_needs_flush, bool tmz)
1873 {
1874         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
1875                 AMDGPU_IB_POOL_DELAYED;
1876         struct amdgpu_device *adev = ring->adev;
1877         struct amdgpu_job *job;
1878
1879         uint32_t max_bytes;
1880         unsigned num_loops, num_dw;
1881         unsigned i;
1882         int r;
1883
1884         if (direct_submit && !ring->sched.ready) {
1885                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1886                 return -EINVAL;
1887         }
1888
1889         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1890         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1891         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
1892
1893         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
1894         if (r)
1895                 return r;
1896
1897         if (vm_needs_flush) {
1898                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
1899                                         adev->gmc.pdb0_bo : adev->gart.bo);
1900                 job->vm_needs_flush = true;
1901         }
1902         if (resv) {
1903                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1904                                      AMDGPU_SYNC_ALWAYS,
1905                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1906                 if (r) {
1907                         DRM_ERROR("sync failed (%d).\n", r);
1908                         goto error_free;
1909                 }
1910         }
1911
1912         for (i = 0; i < num_loops; i++) {
1913                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1914
1915                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1916                                         dst_offset, cur_size_in_bytes, tmz);
1917
1918                 src_offset += cur_size_in_bytes;
1919                 dst_offset += cur_size_in_bytes;
1920                 byte_count -= cur_size_in_bytes;
1921         }
1922
1923         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1924         WARN_ON(job->ibs[0].length_dw > num_dw);
1925         if (direct_submit)
1926                 r = amdgpu_job_submit_direct(job, ring, fence);
1927         else
1928                 r = amdgpu_job_submit(job, &adev->mman.entity,
1929                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1930         if (r)
1931                 goto error_free;
1932
1933         return r;
1934
1935 error_free:
1936         amdgpu_job_free(job);
1937         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1938         return r;
1939 }
1940
1941 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1942                        uint32_t src_data,
1943                        struct dma_resv *resv,
1944                        struct dma_fence **fence)
1945 {
1946         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1947         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1948         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1949
1950         struct amdgpu_res_cursor cursor;
1951         unsigned int num_loops, num_dw;
1952         uint64_t num_bytes;
1953
1954         struct amdgpu_job *job;
1955         int r;
1956
1957         if (!adev->mman.buffer_funcs_enabled) {
1958                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1959                 return -EINVAL;
1960         }
1961
1962         if (bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT) {
1963                 DRM_ERROR("Trying to clear preemptible memory.\n");
1964                 return -EINVAL;
1965         }
1966
1967         if (bo->tbo.resource->mem_type == TTM_PL_TT) {
1968                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
1969                 if (r)
1970                         return r;
1971         }
1972
1973         num_bytes = bo->tbo.resource->num_pages << PAGE_SHIFT;
1974         num_loops = 0;
1975
1976         amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor);
1977         while (cursor.remaining) {
1978                 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes);
1979                 amdgpu_res_next(&cursor, cursor.size);
1980         }
1981         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1982
1983         /* for IB padding */
1984         num_dw += 64;
1985
1986         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
1987                                      &job);
1988         if (r)
1989                 return r;
1990
1991         if (resv) {
1992                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1993                                      AMDGPU_SYNC_ALWAYS,
1994                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1995                 if (r) {
1996                         DRM_ERROR("sync failed (%d).\n", r);
1997                         goto error_free;
1998                 }
1999         }
2000
2001         amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor);
2002         while (cursor.remaining) {
2003                 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes);
2004                 uint64_t dst_addr = cursor.start;
2005
2006                 dst_addr += amdgpu_ttm_domain_start(adev,
2007                                                     bo->tbo.resource->mem_type);
2008                 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
2009                                         cur_size);
2010
2011                 amdgpu_res_next(&cursor, cur_size);
2012         }
2013
2014         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2015         WARN_ON(job->ibs[0].length_dw > num_dw);
2016         r = amdgpu_job_submit(job, &adev->mman.entity,
2017                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2018         if (r)
2019                 goto error_free;
2020
2021         return 0;
2022
2023 error_free:
2024         amdgpu_job_free(job);
2025         return r;
2026 }
2027
2028 #if defined(CONFIG_DEBUG_FS)
2029
2030 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused)
2031 {
2032         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2033         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2034                                                             TTM_PL_VRAM);
2035         struct drm_printer p = drm_seq_file_printer(m);
2036
2037         man->func->debug(man, &p);
2038         return 0;
2039 }
2040
2041 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2042 {
2043         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2044
2045         return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2046 }
2047
2048 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused)
2049 {
2050         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2051         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2052                                                             TTM_PL_TT);
2053         struct drm_printer p = drm_seq_file_printer(m);
2054
2055         man->func->debug(man, &p);
2056         return 0;
2057 }
2058
2059 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused)
2060 {
2061         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2062         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2063                                                             AMDGPU_PL_GDS);
2064         struct drm_printer p = drm_seq_file_printer(m);
2065
2066         man->func->debug(man, &p);
2067         return 0;
2068 }
2069
2070 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused)
2071 {
2072         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2073         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2074                                                             AMDGPU_PL_GWS);
2075         struct drm_printer p = drm_seq_file_printer(m);
2076
2077         man->func->debug(man, &p);
2078         return 0;
2079 }
2080
2081 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused)
2082 {
2083         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2084         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2085                                                             AMDGPU_PL_OA);
2086         struct drm_printer p = drm_seq_file_printer(m);
2087
2088         man->func->debug(man, &p);
2089         return 0;
2090 }
2091
2092 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table);
2093 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table);
2094 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table);
2095 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table);
2096 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table);
2097 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2098
2099 /*
2100  * amdgpu_ttm_vram_read - Linear read access to VRAM
2101  *
2102  * Accesses VRAM via MMIO for debugging purposes.
2103  */
2104 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2105                                     size_t size, loff_t *pos)
2106 {
2107         struct amdgpu_device *adev = file_inode(f)->i_private;
2108         ssize_t result = 0;
2109
2110         if (size & 0x3 || *pos & 0x3)
2111                 return -EINVAL;
2112
2113         if (*pos >= adev->gmc.mc_vram_size)
2114                 return -ENXIO;
2115
2116         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2117         while (size) {
2118                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2119                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2120
2121                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2122                 if (copy_to_user(buf, value, bytes))
2123                         return -EFAULT;
2124
2125                 result += bytes;
2126                 buf += bytes;
2127                 *pos += bytes;
2128                 size -= bytes;
2129         }
2130
2131         return result;
2132 }
2133
2134 /*
2135  * amdgpu_ttm_vram_write - Linear write access to VRAM
2136  *
2137  * Accesses VRAM via MMIO for debugging purposes.
2138  */
2139 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2140                                     size_t size, loff_t *pos)
2141 {
2142         struct amdgpu_device *adev = file_inode(f)->i_private;
2143         ssize_t result = 0;
2144         int r;
2145
2146         if (size & 0x3 || *pos & 0x3)
2147                 return -EINVAL;
2148
2149         if (*pos >= adev->gmc.mc_vram_size)
2150                 return -ENXIO;
2151
2152         while (size) {
2153                 unsigned long flags;
2154                 uint32_t value;
2155
2156                 if (*pos >= adev->gmc.mc_vram_size)
2157                         return result;
2158
2159                 r = get_user(value, (uint32_t *)buf);
2160                 if (r)
2161                         return r;
2162
2163                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2164                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2165                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2166                 WREG32_NO_KIQ(mmMM_DATA, value);
2167                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2168
2169                 result += 4;
2170                 buf += 4;
2171                 *pos += 4;
2172                 size -= 4;
2173         }
2174
2175         return result;
2176 }
2177
2178 static const struct file_operations amdgpu_ttm_vram_fops = {
2179         .owner = THIS_MODULE,
2180         .read = amdgpu_ttm_vram_read,
2181         .write = amdgpu_ttm_vram_write,
2182         .llseek = default_llseek,
2183 };
2184
2185 /*
2186  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2187  *
2188  * This function is used to read memory that has been mapped to the
2189  * GPU and the known addresses are not physical addresses but instead
2190  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2191  */
2192 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2193                                  size_t size, loff_t *pos)
2194 {
2195         struct amdgpu_device *adev = file_inode(f)->i_private;
2196         struct iommu_domain *dom;
2197         ssize_t result = 0;
2198         int r;
2199
2200         /* retrieve the IOMMU domain if any for this device */
2201         dom = iommu_get_domain_for_dev(adev->dev);
2202
2203         while (size) {
2204                 phys_addr_t addr = *pos & PAGE_MASK;
2205                 loff_t off = *pos & ~PAGE_MASK;
2206                 size_t bytes = PAGE_SIZE - off;
2207                 unsigned long pfn;
2208                 struct page *p;
2209                 void *ptr;
2210
2211                 bytes = bytes < size ? bytes : size;
2212
2213                 /* Translate the bus address to a physical address.  If
2214                  * the domain is NULL it means there is no IOMMU active
2215                  * and the address translation is the identity
2216                  */
2217                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2218
2219                 pfn = addr >> PAGE_SHIFT;
2220                 if (!pfn_valid(pfn))
2221                         return -EPERM;
2222
2223                 p = pfn_to_page(pfn);
2224                 if (p->mapping != adev->mman.bdev.dev_mapping)
2225                         return -EPERM;
2226
2227                 ptr = kmap(p);
2228                 r = copy_to_user(buf, ptr + off, bytes);
2229                 kunmap(p);
2230                 if (r)
2231                         return -EFAULT;
2232
2233                 size -= bytes;
2234                 *pos += bytes;
2235                 result += bytes;
2236         }
2237
2238         return result;
2239 }
2240
2241 /*
2242  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2243  *
2244  * This function is used to write memory that has been mapped to the
2245  * GPU and the known addresses are not physical addresses but instead
2246  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2247  */
2248 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2249                                  size_t size, loff_t *pos)
2250 {
2251         struct amdgpu_device *adev = file_inode(f)->i_private;
2252         struct iommu_domain *dom;
2253         ssize_t result = 0;
2254         int r;
2255
2256         dom = iommu_get_domain_for_dev(adev->dev);
2257
2258         while (size) {
2259                 phys_addr_t addr = *pos & PAGE_MASK;
2260                 loff_t off = *pos & ~PAGE_MASK;
2261                 size_t bytes = PAGE_SIZE - off;
2262                 unsigned long pfn;
2263                 struct page *p;
2264                 void *ptr;
2265
2266                 bytes = bytes < size ? bytes : size;
2267
2268                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2269
2270                 pfn = addr >> PAGE_SHIFT;
2271                 if (!pfn_valid(pfn))
2272                         return -EPERM;
2273
2274                 p = pfn_to_page(pfn);
2275                 if (p->mapping != adev->mman.bdev.dev_mapping)
2276                         return -EPERM;
2277
2278                 ptr = kmap(p);
2279                 r = copy_from_user(ptr + off, buf, bytes);
2280                 kunmap(p);
2281                 if (r)
2282                         return -EFAULT;
2283
2284                 size -= bytes;
2285                 *pos += bytes;
2286                 result += bytes;
2287         }
2288
2289         return result;
2290 }
2291
2292 static const struct file_operations amdgpu_ttm_iomem_fops = {
2293         .owner = THIS_MODULE,
2294         .read = amdgpu_iomem_read,
2295         .write = amdgpu_iomem_write,
2296         .llseek = default_llseek
2297 };
2298
2299 #endif
2300
2301 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2302 {
2303 #if defined(CONFIG_DEBUG_FS)
2304         struct drm_minor *minor = adev_to_drm(adev)->primary;
2305         struct dentry *root = minor->debugfs_root;
2306
2307         debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2308                                  &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2309         debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2310                             &amdgpu_ttm_iomem_fops);
2311         debugfs_create_file("amdgpu_vram_mm", 0444, root, adev,
2312                             &amdgpu_mm_vram_table_fops);
2313         debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev,
2314                             &amdgpu_mm_tt_table_fops);
2315         debugfs_create_file("amdgpu_gds_mm", 0444, root, adev,
2316                             &amdgpu_mm_gds_table_fops);
2317         debugfs_create_file("amdgpu_gws_mm", 0444, root, adev,
2318                             &amdgpu_mm_gws_table_fops);
2319         debugfs_create_file("amdgpu_oa_mm", 0444, root, adev,
2320                             &amdgpu_mm_oa_table_fops);
2321         debugfs_create_file("ttm_page_pool", 0444, root, adev,
2322                             &amdgpu_ttm_page_pool_fops);
2323 #endif
2324 }