drivers/gpu/drm/msm/msm_gpu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <[email protected]>
   5  */
   6
   7 #include "drm/drm_drv.h"
   8
   9 #include "msm_gpu.h"
  10 #include "msm_gem.h"
  11 #include "msm_mmu.h"
  12 #include "msm_fence.h"
  13 #include "msm_gpu_trace.h"
  14 #include "adreno/adreno_gpu.h"
  15
  16 #include <generated/utsrelease.h>
  17 #include <linux/string_helpers.h>
  18 #include <linux/devcoredump.h>
  19 #include <linux/sched/task.h>
  20
  21 /*
  22  * Power Management:
  23  */
  24
  25 static int enable_pwrrail(struct msm_gpu *gpu)
  26 {
  27         struct drm_device *dev = gpu->dev;
  28         int ret = 0;
  29
  30         if (gpu->gpu_reg) {
  31                 ret = regulator_enable(gpu->gpu_reg);
  32                 if (ret) {
  33                         DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
  34                         return ret;
  35                 }
  36         }
  37
  38         if (gpu->gpu_cx) {
  39                 ret = regulator_enable(gpu->gpu_cx);
  40                 if (ret) {
  41                         DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
  42                         return ret;
  43                 }
  44         }
  45
  46         return 0;
  47 }
  48
  49 static int disable_pwrrail(struct msm_gpu *gpu)
  50 {
  51         if (gpu->gpu_cx)
  52                 regulator_disable(gpu->gpu_cx);
  53         if (gpu->gpu_reg)
  54                 regulator_disable(gpu->gpu_reg);
  55         return 0;
  56 }
  57
  58 static int enable_clk(struct msm_gpu *gpu)
  59 {
  60         if (gpu->core_clk && gpu->fast_rate)
  61                 clk_set_rate(gpu->core_clk, gpu->fast_rate);
  62
  63         /* Set the RBBM timer rate to 19.2Mhz */
  64         if (gpu->rbbmtimer_clk)
  65                 clk_set_rate(gpu->rbbmtimer_clk, 19200000);
  66
  67         return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
  68 }
  69
  70 static int disable_clk(struct msm_gpu *gpu)
  71 {
  72         clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
  73
  74         /*
  75          * Set the clock to a deliberately low rate. On older targets the clock
  76          * speed had to be non zero to avoid problems. On newer targets this
  77          * will be rounded down to zero anyway so it all works out.
  78          */
  79         if (gpu->core_clk)
  80                 clk_set_rate(gpu->core_clk, 27000000);
  81
  82         if (gpu->rbbmtimer_clk)
  83                 clk_set_rate(gpu->rbbmtimer_clk, 0);
  84
  85         return 0;
  86 }
  87
  88 static int enable_axi(struct msm_gpu *gpu)
  89 {
  90         return clk_prepare_enable(gpu->ebi1_clk);
  91 }
  92
  93 static int disable_axi(struct msm_gpu *gpu)
  94 {
  95         clk_disable_unprepare(gpu->ebi1_clk);
  96         return 0;
  97 }
  98
  99 int msm_gpu_pm_resume(struct msm_gpu *gpu)
 100 {
 101         int ret;
 102
 103         DBG("%s", gpu->name);
 104         trace_msm_gpu_resume(0);
 105
 106         ret = enable_pwrrail(gpu);
 107         if (ret)
 108                 return ret;
 109
 110         ret = enable_clk(gpu);
 111         if (ret)
 112                 return ret;
 113
 114         ret = enable_axi(gpu);
 115         if (ret)
 116                 return ret;
 117
 118         msm_devfreq_resume(gpu);
 119
 120         gpu->needs_hw_init = true;
 121
 122         return 0;
 123 }
 124
 125 int msm_gpu_pm_suspend(struct msm_gpu *gpu)
 126 {
 127         int ret;
 128
 129         DBG("%s", gpu->name);
 130         trace_msm_gpu_suspend(0);
 131
 132         msm_devfreq_suspend(gpu);
 133
 134         ret = disable_axi(gpu);
 135         if (ret)
 136                 return ret;
 137
 138         ret = disable_clk(gpu);
 139         if (ret)
 140                 return ret;
 141
 142         ret = disable_pwrrail(gpu);
 143         if (ret)
 144                 return ret;
 145
 146         gpu->suspend_count++;
 147
 148         return 0;
 149 }
 150
 151 void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx,
 152                          struct drm_printer *p)
 153 {
 154         drm_printf(p, "drm-driver:\t%s\n", gpu->dev->driver->name);
 155         drm_printf(p, "drm-client-id:\t%u\n", ctx->seqno);
 156         drm_printf(p, "drm-engine-gpu:\t%llu ns\n", ctx->elapsed_ns);
 157         drm_printf(p, "drm-cycles-gpu:\t%llu\n", ctx->cycles);
 158         drm_printf(p, "drm-maxfreq-gpu:\t%u Hz\n", gpu->fast_rate);
 159 }
 160
 161 int msm_gpu_hw_init(struct msm_gpu *gpu)
 162 {
 163         int ret;
 164
 165         WARN_ON(!mutex_is_locked(&gpu->lock));
 166
 167         if (!gpu->needs_hw_init)
 168                 return 0;
 169
 170         disable_irq(gpu->irq);
 171         ret = gpu->funcs->hw_init(gpu);
 172         if (!ret)
 173                 gpu->needs_hw_init = false;
 174         enable_irq(gpu->irq);
 175
 176         return ret;
 177 }
 178
 179 #ifdef CONFIG_DEV_COREDUMP
 180 static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset,
 181                 size_t count, void *data, size_t datalen)
 182 {
 183         struct msm_gpu *gpu = data;
 184         struct drm_print_iterator iter;
 185         struct drm_printer p;
 186         struct msm_gpu_state *state;
 187
 188         state = msm_gpu_crashstate_get(gpu);
 189         if (!state)
 190                 return 0;
 191
 192         iter.data = buffer;
 193         iter.offset = 0;
 194         iter.start = offset;
 195         iter.remain = count;
 196
 197         p = drm_coredump_printer(&iter);
 198
 199         drm_printf(&p, "---\n");
 200         drm_printf(&p, "kernel: " UTS_RELEASE "\n");
 201         drm_printf(&p, "module: " KBUILD_MODNAME "\n");
 202         drm_printf(&p, "time: %lld.%09ld\n",
 203                 state->time.tv_sec, state->time.tv_nsec);
 204         if (state->comm)
 205                 drm_printf(&p, "comm: %s\n", state->comm);
 206         if (state->cmd)
 207                 drm_printf(&p, "cmdline: %s\n", state->cmd);
 208
 209         gpu->funcs->show(gpu, state, &p);
 210
 211         msm_gpu_crashstate_put(gpu);
 212
 213         return count - iter.remain;
 214 }
 215
 216 static void msm_gpu_devcoredump_free(void *data)
 217 {
 218         struct msm_gpu *gpu = data;
 219
 220         msm_gpu_crashstate_put(gpu);
 221 }
 222
 223 static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
 224                 struct msm_gem_object *obj, u64 iova, bool full)
 225 {
 226         struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos];
 227
 228         /* Don't record write only objects */
 229         state_bo->size = obj->base.size;
 230         state_bo->iova = iova;
 231
 232         BUILD_BUG_ON(sizeof(state_bo->name) != sizeof(obj->name));
 233
 234         memcpy(state_bo->name, obj->name, sizeof(state_bo->name));
 235
 236         if (full) {
 237                 void *ptr;
 238
 239                 state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL);
 240                 if (!state_bo->data)
 241                         goto out;
 242
 243                 msm_gem_lock(&obj->base);
 244                 ptr = msm_gem_get_vaddr_active(&obj->base);
 245                 msm_gem_unlock(&obj->base);
 246                 if (IS_ERR(ptr)) {
 247                         kvfree(state_bo->data);
 248                         state_bo->data = NULL;
 249                         goto out;
 250                 }
 251
 252                 memcpy(state_bo->data, ptr, obj->base.size);
 253                 msm_gem_put_vaddr(&obj->base);
 254         }
 255 out:
 256         state->nr_bos++;
 257 }
 258
 259 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
 260                 struct msm_gem_submit *submit, char *comm, char *cmd)
 261 {
 262         struct msm_gpu_state *state;
 263
 264         /* Check if the target supports capturing crash state */
 265         if (!gpu->funcs->gpu_state_get)
 266                 return;
 267
 268         /* Only save one crash state at a time */
 269         if (gpu->crashstate)
 270                 return;
 271
 272         state = gpu->funcs->gpu_state_get(gpu);
 273         if (IS_ERR_OR_NULL(state))
 274                 return;
 275
 276         /* Fill in the additional crash state information */
 277         state->comm = kstrdup(comm, GFP_KERNEL);
 278         state->cmd = kstrdup(cmd, GFP_KERNEL);
 279         state->fault_info = gpu->fault_info;
 280
 281         if (submit) {
 282                 int i;
 283
 284                 state->bos = kcalloc(submit->nr_bos,
 285                         sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
 286
 287                 for (i = 0; state->bos && i < submit->nr_bos; i++) {
 288                         msm_gpu_crashstate_get_bo(state, submit->bos[i].obj,
 289                                                   submit->bos[i].iova,
 290                                                   should_dump(submit, i));
 291                 }
 292         }
 293
 294         /* Set the active crash state to be dumped on failure */
 295         gpu->crashstate = state;
 296
 297         /* FIXME: Release the crashstate if this errors out? */
 298         dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL,
 299                 msm_gpu_devcoredump_read, msm_gpu_devcoredump_free);
 300 }
 301 #else
 302 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
 303                 struct msm_gem_submit *submit, char *comm, char *cmd)
 304 {
 305 }
 306 #endif
 307
 308 /*
 309  * Hangcheck detection for locked gpu:
 310  */
 311
 312 static struct msm_gem_submit *
 313 find_submit(struct msm_ringbuffer *ring, uint32_t fence)
 314 {
 315         struct msm_gem_submit *submit;
 316         unsigned long flags;
 317
 318         spin_lock_irqsave(&ring->submit_lock, flags);
 319         list_for_each_entry(submit, &ring->submits, node) {
 320                 if (submit->seqno == fence) {
 321                         spin_unlock_irqrestore(&ring->submit_lock, flags);
 322                         return submit;
 323                 }
 324         }
 325         spin_unlock_irqrestore(&ring->submit_lock, flags);
 326
 327         return NULL;
 328 }
 329
 330 static void retire_submits(struct msm_gpu *gpu);
 331
 332 static void get_comm_cmdline(struct msm_gem_submit *submit, char **comm, char **cmd)
 333 {
 334         struct msm_file_private *ctx = submit->queue->ctx;
 335         struct task_struct *task;
 336
 337         /* Note that kstrdup will return NULL if argument is NULL: */
 338         *comm = kstrdup(ctx->comm, GFP_KERNEL);
 339         *cmd  = kstrdup(ctx->cmdline, GFP_KERNEL);
 340
 341         task = get_pid_task(submit->pid, PIDTYPE_PID);
 342         if (!task)
 343                 return;
 344
 345         if (!*comm)
 346                 *comm = kstrdup(task->comm, GFP_KERNEL);
 347
 348         if (!*cmd)
 349                 *cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
 350
 351         put_task_struct(task);
 352 }
 353
 354 static void recover_worker(struct kthread_work *work)
 355 {
 356         struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
 357         struct drm_device *dev = gpu->dev;
 358         struct msm_drm_private *priv = dev->dev_private;
 359         struct msm_gem_submit *submit;
 360         struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
 361         char *comm = NULL, *cmd = NULL;
 362         int i;
 363
 364         mutex_lock(&gpu->lock);
 365
 366         DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name);
 367
 368         submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
 369         if (submit) {
 370                 /* Increment the fault counts */
 371                 submit->queue->faults++;
 372                 if (submit->aspace)
 373                         submit->aspace->faults++;
 374
 375                 get_comm_cmdline(submit, &comm, &cmd);
 376
 377                 if (comm && cmd) {
 378                         DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n",
 379                                 gpu->name, comm, cmd);
 380
 381                         msm_rd_dump_submit(priv->hangrd, submit,
 382                                 "offending task: %s (%s)", comm, cmd);
 383                 } else {
 384                         msm_rd_dump_submit(priv->hangrd, submit, NULL);
 385                 }
 386         } else {
 387                 /*
 388                  * We couldn't attribute this fault to any particular context,
 389                  * so increment the global fault count instead.
 390                  */
 391                 gpu->global_faults++;
 392         }
 393
 394         /* Record the crash state */
 395         pm_runtime_get_sync(&gpu->pdev->dev);
 396         msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
 397         pm_runtime_put_sync(&gpu->pdev->dev);
 398
 399         kfree(cmd);
 400         kfree(comm);
 401
 402         /*
 403          * Update all the rings with the latest and greatest fence.. this
 404          * needs to happen after msm_rd_dump_submit() to ensure that the
 405          * bo's referenced by the offending submit are still around.
 406          */
 407         for (i = 0; i < gpu->nr_rings; i++) {
 408                 struct msm_ringbuffer *ring = gpu->rb[i];
 409
 410                 uint32_t fence = ring->memptrs->fence;
 411
 412                 /*
 413                  * For the current (faulting?) ring/submit advance the fence by
 414                  * one more to clear the faulting submit
 415                  */
 416                 if (ring == cur_ring)
 417                         ring->memptrs->fence = ++fence;
 418
 419                 msm_update_fence(ring->fctx, fence);
 420         }
 421
 422         if (msm_gpu_active(gpu)) {
 423                 /* retire completed submits, plus the one that hung: */
 424                 retire_submits(gpu);
 425
 426                 pm_runtime_get_sync(&gpu->pdev->dev);
 427                 gpu->funcs->recover(gpu);
 428                 pm_runtime_put_sync(&gpu->pdev->dev);
 429
 430                 /*
 431                  * Replay all remaining submits starting with highest priority
 432                  * ring
 433                  */
 434                 for (i = 0; i < gpu->nr_rings; i++) {
 435                         struct msm_ringbuffer *ring = gpu->rb[i];
 436                         unsigned long flags;
 437
 438                         spin_lock_irqsave(&ring->submit_lock, flags);
 439                         list_for_each_entry(submit, &ring->submits, node)
 440                                 gpu->funcs->submit(gpu, submit);
 441                         spin_unlock_irqrestore(&ring->submit_lock, flags);
 442                 }
 443         }
 444
 445         mutex_unlock(&gpu->lock);
 446
 447         msm_gpu_retire(gpu);
 448 }
 449
 450 static void fault_worker(struct kthread_work *work)
 451 {
 452         struct msm_gpu *gpu = container_of(work, struct msm_gpu, fault_work);
 453         struct msm_gem_submit *submit;
 454         struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
 455         char *comm = NULL, *cmd = NULL;
 456
 457         mutex_lock(&gpu->lock);
 458
 459         submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
 460         if (submit && submit->fault_dumped)
 461                 goto resume_smmu;
 462
 463         if (submit) {
 464                 get_comm_cmdline(submit, &comm, &cmd);
 465
 466                 /*
 467                  * When we get GPU iova faults, we can get 1000s of them,
 468                  * but we really only want to log the first one.
 469                  */
 470                 submit->fault_dumped = true;
 471         }
 472
 473         /* Record the crash state */
 474         pm_runtime_get_sync(&gpu->pdev->dev);
 475         msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
 476         pm_runtime_put_sync(&gpu->pdev->dev);
 477
 478         kfree(cmd);
 479         kfree(comm);
 480
 481 resume_smmu:
 482         memset(&gpu->fault_info, 0, sizeof(gpu->fault_info));
 483         gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
 484
 485         mutex_unlock(&gpu->lock);
 486 }
 487
 488 static void hangcheck_timer_reset(struct msm_gpu *gpu)
 489 {
 490         struct msm_drm_private *priv = gpu->dev->dev_private;
 491         mod_timer(&gpu->hangcheck_timer,
 492                         round_jiffies_up(jiffies + msecs_to_jiffies(priv->hangcheck_period)));
 493 }
 494
 495 static void hangcheck_handler(struct timer_list *t)
 496 {
 497         struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
 498         struct drm_device *dev = gpu->dev;
 499         struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
 500         uint32_t fence = ring->memptrs->fence;
 501
 502         if (fence != ring->hangcheck_fence) {
 503                 /* some progress has been made.. ya! */
 504                 ring->hangcheck_fence = fence;
 505         } else if (fence_before(fence, ring->fctx->last_fence)) {
 506                 /* no progress and not done.. hung! */
 507                 ring->hangcheck_fence = fence;
 508                 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n",
 509                                 gpu->name, ring->id);
 510                 DRM_DEV_ERROR(dev->dev, "%s:     completed fence: %u\n",
 511                                 gpu->name, fence);
 512                 DRM_DEV_ERROR(dev->dev, "%s:     submitted fence: %u\n",
 513                                 gpu->name, ring->fctx->last_fence);
 514
 515                 kthread_queue_work(gpu->worker, &gpu->recover_work);
 516         }
 517
 518         /* if still more pending work, reset the hangcheck timer: */
 519         if (fence_after(ring->fctx->last_fence, ring->hangcheck_fence))
 520                 hangcheck_timer_reset(gpu);
 521
 522         /* workaround for missing irq: */
 523         msm_gpu_retire(gpu);
 524 }
 525
 526 /*
 527  * Performance Counters:
 528  */
 529
 530 /* called under perf_lock */
 531 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
 532 {
 533         uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
 534         int i, n = min(ncntrs, gpu->num_perfcntrs);
 535
 536         /* read current values: */
 537         for (i = 0; i < gpu->num_perfcntrs; i++)
 538                 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
 539
 540         /* update cntrs: */
 541         for (i = 0; i < n; i++)
 542                 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
 543
 544         /* save current values: */
 545         for (i = 0; i < gpu->num_perfcntrs; i++)
 546                 gpu->last_cntrs[i] = current_cntrs[i];
 547
 548         return n;
 549 }
 550
 551 static void update_sw_cntrs(struct msm_gpu *gpu)
 552 {
 553         ktime_t time;
 554         uint32_t elapsed;
 555         unsigned long flags;
 556
 557         spin_lock_irqsave(&gpu->perf_lock, flags);
 558         if (!gpu->perfcntr_active)
 559                 goto out;
 560
 561         time = ktime_get();
 562         elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
 563
 564         gpu->totaltime += elapsed;
 565         if (gpu->last_sample.active)
 566                 gpu->activetime += elapsed;
 567
 568         gpu->last_sample.active = msm_gpu_active(gpu);
 569         gpu->last_sample.time = time;
 570
 571 out:
 572         spin_unlock_irqrestore(&gpu->perf_lock, flags);
 573 }
 574
 575 void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
 576 {
 577         unsigned long flags;
 578
 579         pm_runtime_get_sync(&gpu->pdev->dev);
 580
 581         spin_lock_irqsave(&gpu->perf_lock, flags);
 582         /* we could dynamically enable/disable perfcntr registers too.. */
 583         gpu->last_sample.active = msm_gpu_active(gpu);
 584         gpu->last_sample.time = ktime_get();
 585         gpu->activetime = gpu->totaltime = 0;
 586         gpu->perfcntr_active = true;
 587         update_hw_cntrs(gpu, 0, NULL);
 588         spin_unlock_irqrestore(&gpu->perf_lock, flags);
 589 }
 590
 591 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
 592 {
 593         gpu->perfcntr_active = false;
 594         pm_runtime_put_sync(&gpu->pdev->dev);
 595 }
 596
 597 /* returns -errno or # of cntrs sampled */
 598 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
 599                 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs)
 600 {
 601         unsigned long flags;
 602         int ret;
 603
 604         spin_lock_irqsave(&gpu->perf_lock, flags);
 605
 606         if (!gpu->perfcntr_active) {
 607                 ret = -EINVAL;
 608                 goto out;
 609         }
 610
 611         *activetime = gpu->activetime;
 612         *totaltime = gpu->totaltime;
 613
 614         gpu->activetime = gpu->totaltime = 0;
 615
 616         ret = update_hw_cntrs(gpu, ncntrs, cntrs);
 617
 618 out:
 619         spin_unlock_irqrestore(&gpu->perf_lock, flags);
 620
 621         return ret;
 622 }
 623
 624 /*
 625  * Cmdstream submission/retirement:
 626  */
 627
 628 static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
 629                 struct msm_gem_submit *submit)
 630 {
 631         int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
 632         volatile struct msm_gpu_submit_stats *stats;
 633         u64 elapsed, clock = 0, cycles;
 634         unsigned long flags;
 635
 636         stats = &ring->memptrs->stats[index];
 637         /* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */
 638         elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000;
 639         do_div(elapsed, 192);
 640
 641         cycles = stats->cpcycles_end - stats->cpcycles_start;
 642
 643         /* Calculate the clock frequency from the number of CP cycles */
 644         if (elapsed) {
 645                 clock = cycles * 1000;
 646                 do_div(clock, elapsed);
 647         }
 648
 649         submit->queue->ctx->elapsed_ns += elapsed;
 650         submit->queue->ctx->cycles     += cycles;
 651
 652         trace_msm_gpu_submit_retired(submit, elapsed, clock,
 653                 stats->alwayson_start, stats->alwayson_end);
 654
 655         msm_submit_retire(submit);
 656
 657         pm_runtime_mark_last_busy(&gpu->pdev->dev);
 658
 659         spin_lock_irqsave(&ring->submit_lock, flags);
 660         list_del(&submit->node);
 661         spin_unlock_irqrestore(&ring->submit_lock, flags);
 662
 663         /* Update devfreq on transition from active->idle: */
 664         mutex_lock(&gpu->active_lock);
 665         gpu->active_submits--;
 666         WARN_ON(gpu->active_submits < 0);
 667         if (!gpu->active_submits)
 668                 msm_devfreq_idle(gpu);
 669         mutex_unlock(&gpu->active_lock);
 670
 671         pm_runtime_put_autosuspend(&gpu->pdev->dev);
 672
 673         msm_gem_submit_put(submit);
 674 }
 675
 676 static void retire_submits(struct msm_gpu *gpu)
 677 {
 678         int i;
 679
 680         /* Retire the commits starting with highest priority */
 681         for (i = 0; i < gpu->nr_rings; i++) {
 682                 struct msm_ringbuffer *ring = gpu->rb[i];
 683
 684                 while (true) {
 685                         struct msm_gem_submit *submit = NULL;
 686                         unsigned long flags;
 687
 688                         spin_lock_irqsave(&ring->submit_lock, flags);
 689                         submit = list_first_entry_or_null(&ring->submits,
 690                                         struct msm_gem_submit, node);
 691                         spin_unlock_irqrestore(&ring->submit_lock, flags);
 692
 693                         /*
 694                          * If no submit, we are done.  If submit->fence hasn't
 695                          * been signalled, then later submits are not signalled
 696                          * either, so we are also done.
 697                          */
 698                         if (submit && dma_fence_is_signaled(submit->hw_fence)) {
 699                                 retire_submit(gpu, ring, submit);
 700                         } else {
 701                                 break;
 702                         }
 703                 }
 704         }
 705
 706         wake_up_all(&gpu->retire_event);
 707 }
 708
 709 static void retire_worker(struct kthread_work *work)
 710 {
 711         struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
 712
 713         retire_submits(gpu);
 714 }
 715
 716 /* call from irq handler to schedule work to retire bo's */
 717 void msm_gpu_retire(struct msm_gpu *gpu)
 718 {
 719         int i;
 720
 721         for (i = 0; i < gpu->nr_rings; i++)
 722                 msm_update_fence(gpu->rb[i]->fctx, gpu->rb[i]->memptrs->fence);
 723
 724         kthread_queue_work(gpu->worker, &gpu->retire_work);
 725         update_sw_cntrs(gpu);
 726 }
 727
 728 /* add bo's to gpu's ring, and kick gpu: */
 729 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
 730 {
 731         struct drm_device *dev = gpu->dev;
 732         struct msm_drm_private *priv = dev->dev_private;
 733         struct msm_ringbuffer *ring = submit->ring;
 734         unsigned long flags;
 735
 736         WARN_ON(!mutex_is_locked(&gpu->lock));
 737
 738         pm_runtime_get_sync(&gpu->pdev->dev);
 739
 740         msm_gpu_hw_init(gpu);
 741
 742         submit->seqno = submit->hw_fence->seqno;
 743
 744         msm_rd_dump_submit(priv->rd, submit, NULL);
 745
 746         update_sw_cntrs(gpu);
 747
 748         /*
 749          * ring->submits holds a ref to the submit, to deal with the case
 750          * that a submit completes before msm_ioctl_gem_submit() returns.
 751          */
 752         msm_gem_submit_get(submit);
 753
 754         spin_lock_irqsave(&ring->submit_lock, flags);
 755         list_add_tail(&submit->node, &ring->submits);
 756         spin_unlock_irqrestore(&ring->submit_lock, flags);
 757
 758         /* Update devfreq on transition from idle->active: */
 759         mutex_lock(&gpu->active_lock);
 760         if (!gpu->active_submits)
 761                 msm_devfreq_active(gpu);
 762         gpu->active_submits++;
 763         mutex_unlock(&gpu->active_lock);
 764
 765         gpu->funcs->submit(gpu, submit);
 766         gpu->cur_ctx_seqno = submit->queue->ctx->seqno;
 767
 768         hangcheck_timer_reset(gpu);
 769 }
 770
 771 /*
 772  * Init/Cleanup:
 773  */
 774
 775 static irqreturn_t irq_handler(int irq, void *data)
 776 {
 777         struct msm_gpu *gpu = data;
 778         return gpu->funcs->irq(gpu);
 779 }
 780
 781 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
 782 {
 783         int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks);
 784
 785         if (ret < 1) {
 786                 gpu->nr_clocks = 0;
 787                 return ret;
 788         }
 789
 790         gpu->nr_clocks = ret;
 791
 792         gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
 793                 gpu->nr_clocks, "core");
 794
 795         gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
 796                 gpu->nr_clocks, "rbbmtimer");
 797
 798         return 0;
 799 }
 800
 801 /* Return a new address space for a msm_drm_private instance */
 802 struct msm_gem_address_space *
 803 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task)
 804 {
 805         struct msm_gem_address_space *aspace = NULL;
 806         if (!gpu)
 807                 return NULL;
 808
 809         /*
 810          * If the target doesn't support private address spaces then return
 811          * the global one
 812          */
 813         if (gpu->funcs->create_private_address_space) {
 814                 aspace = gpu->funcs->create_private_address_space(gpu);
 815                 if (!IS_ERR(aspace))
 816                         aspace->pid = get_pid(task_pid(task));
 817         }
 818
 819         if (IS_ERR_OR_NULL(aspace))
 820                 aspace = msm_gem_address_space_get(gpu->aspace);
 821
 822         return aspace;
 823 }
 824
 825 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 826                 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
 827                 const char *name, struct msm_gpu_config *config)
 828 {
 829         int i, ret, nr_rings = config->nr_rings;
 830         void *memptrs;
 831         uint64_t memptrs_iova;
 832
 833         if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
 834                 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
 835
 836         gpu->dev = drm;
 837         gpu->funcs = funcs;
 838         gpu->name = name;
 839
 840         gpu->worker = kthread_create_worker(0, "gpu-worker");
 841         if (IS_ERR(gpu->worker)) {
 842                 ret = PTR_ERR(gpu->worker);
 843                 gpu->worker = NULL;
 844                 goto fail;
 845         }
 846
 847         sched_set_fifo_low(gpu->worker->task);
 848
 849         INIT_LIST_HEAD(&gpu->active_list);
 850         mutex_init(&gpu->active_lock);
 851         mutex_init(&gpu->lock);
 852         init_waitqueue_head(&gpu->retire_event);
 853         kthread_init_work(&gpu->retire_work, retire_worker);
 854         kthread_init_work(&gpu->recover_work, recover_worker);
 855         kthread_init_work(&gpu->fault_work, fault_worker);
 856
 857         timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
 858
 859         spin_lock_init(&gpu->perf_lock);
 860
 861
 862         /* Map registers: */
 863         gpu->mmio = msm_ioremap(pdev, config->ioname);
 864         if (IS_ERR(gpu->mmio)) {
 865                 ret = PTR_ERR(gpu->mmio);
 866                 goto fail;
 867         }
 868
 869         /* Get Interrupt: */
 870         gpu->irq = platform_get_irq(pdev, 0);
 871         if (gpu->irq < 0) {
 872                 ret = gpu->irq;
 873                 DRM_DEV_ERROR(drm->dev, "failed to get irq: %d\n", ret);
 874                 goto fail;
 875         }
 876
 877         ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
 878                         IRQF_TRIGGER_HIGH, "gpu-irq", gpu);
 879         if (ret) {
 880                 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
 881                 goto fail;
 882         }
 883
 884         ret = get_clocks(pdev, gpu);
 885         if (ret)
 886                 goto fail;
 887
 888         gpu->ebi1_clk = msm_clk_get(pdev, "bus");
 889         DBG("ebi1_clk: %p", gpu->ebi1_clk);
 890         if (IS_ERR(gpu->ebi1_clk))
 891                 gpu->ebi1_clk = NULL;
 892
 893         /* Acquire regulators: */
 894         gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
 895         DBG("gpu_reg: %p", gpu->gpu_reg);
 896         if (IS_ERR(gpu->gpu_reg))
 897                 gpu->gpu_reg = NULL;
 898
 899         gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
 900         DBG("gpu_cx: %p", gpu->gpu_cx);
 901         if (IS_ERR(gpu->gpu_cx))
 902                 gpu->gpu_cx = NULL;
 903
 904         gpu->pdev = pdev;
 905         platform_set_drvdata(pdev, &gpu->adreno_smmu);
 906
 907         msm_devfreq_init(gpu);
 908
 909
 910         gpu->aspace = gpu->funcs->create_address_space(gpu, pdev);
 911
 912         if (gpu->aspace == NULL)
 913                 DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
 914         else if (IS_ERR(gpu->aspace)) {
 915                 ret = PTR_ERR(gpu->aspace);
 916                 goto fail;
 917         }
 918
 919         memptrs = msm_gem_kernel_new(drm,
 920                 sizeof(struct msm_rbmemptrs) * nr_rings,
 921                 check_apriv(gpu, MSM_BO_WC), gpu->aspace, &gpu->memptrs_bo,
 922                 &memptrs_iova);
 923
 924         if (IS_ERR(memptrs)) {
 925                 ret = PTR_ERR(memptrs);
 926                 DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret);
 927                 goto fail;
 928         }
 929
 930         msm_gem_object_set_name(gpu->memptrs_bo, "memptrs");
 931
 932         if (nr_rings > ARRAY_SIZE(gpu->rb)) {
 933                 DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n",
 934                         ARRAY_SIZE(gpu->rb));
 935                 nr_rings = ARRAY_SIZE(gpu->rb);
 936         }
 937
 938         /* Create ringbuffer(s): */
 939         for (i = 0; i < nr_rings; i++) {
 940                 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
 941
 942                 if (IS_ERR(gpu->rb[i])) {
 943                         ret = PTR_ERR(gpu->rb[i]);
 944                         DRM_DEV_ERROR(drm->dev,
 945                                 "could not create ringbuffer %d: %d\n", i, ret);
 946                         goto fail;
 947                 }
 948
 949                 memptrs += sizeof(struct msm_rbmemptrs);
 950                 memptrs_iova += sizeof(struct msm_rbmemptrs);
 951         }
 952
 953         gpu->nr_rings = nr_rings;
 954
 955         refcount_set(&gpu->sysprof_active, 1);
 956
 957         return 0;
 958
 959 fail:
 960         for (i = 0; i < ARRAY_SIZE(gpu->rb); i++)  {
 961                 msm_ringbuffer_destroy(gpu->rb[i]);
 962                 gpu->rb[i] = NULL;
 963         }
 964
 965         msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
 966
 967         platform_set_drvdata(pdev, NULL);
 968         return ret;
 969 }
 970
 971 void msm_gpu_cleanup(struct msm_gpu *gpu)
 972 {
 973         int i;
 974
 975         DBG("%s", gpu->name);
 976
 977         WARN_ON(!list_empty(&gpu->active_list));
 978
 979         for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
 980                 msm_ringbuffer_destroy(gpu->rb[i]);
 981                 gpu->rb[i] = NULL;
 982         }
 983
 984         msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
 985
 986         if (!IS_ERR_OR_NULL(gpu->aspace)) {
 987                 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu);
 988                 msm_gem_address_space_put(gpu->aspace);
 989         }
 990
 991         if (gpu->worker) {
 992                 kthread_destroy_worker(gpu->worker);
 993         }
 994
 995         msm_devfreq_cleanup(gpu);
 996 }