drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "smuio/smuio_11_0_0_offset.h"
  39 #include "smuio/smuio_11_0_0_sh_mask.h"
  40 #include "navi10_enum.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "soc15_common.h"
  47 #include "clearstate_gfx10.h"
  48 #include "v10_structs.h"
  49 #include "gfx_v10_0.h"
  50 #include "nbio_v2_3.h"
  51
  52 /**
  53  * Navi10 has two graphic rings to share each graphic pipe.
  54  * 1. Primary ring
  55  * 2. Async ring
  56  */
  57 #define GFX10_NUM_GFX_RINGS_NV1X        1
  58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  59 #define GFX10_MEC_HPD_SIZE      2048
  60
  61 #define F32_CE_PROGRAM_RAM_SIZE         65536
  62 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  63
  64 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  70
  71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  73
  74 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  76 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
  97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
  98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
  99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 101
 102 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 103 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 104 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 105 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 106 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 107 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 108 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 109 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 110 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 111 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 112 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 113 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 114
 115 //CC_GC_SA_UNIT_DISABLE
 116 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 117 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 118 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 119 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 120 //GC_USER_SA_UNIT_DISABLE
 121 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 122 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 123 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 124 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 125 //PA_SC_ENHANCE_3
 126 #define mmPA_SC_ENHANCE_3                       0x1085
 127 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 128 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 129 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 130
 131 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 132 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 133
 134 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 135 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 136 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 137 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 138 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 139 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 140
 141 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 142 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 143 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 144 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 145 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 146 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 147 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 148 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 149 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 150 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 151 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 152
 153 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 154 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 155 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 156 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 157 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 158 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 159
 160 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 161 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 162 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 163 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 164 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 165 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 166
 167 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 168 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 169 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 170 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 171 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 172 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 173
 174 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 175 {
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 216 };
 217
 218 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 219 {
 220         /* Pending on emulation bring up */
 221 };
 222
 223 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 224 {
 225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1277 };
1278
1279 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1280 {
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1319 };
1320
1321 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1322 {
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1363 };
1364
1365 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1366 {
1367         static void *scratch_reg0;
1368         static void *scratch_reg1;
1369         static void *scratch_reg2;
1370         static void *scratch_reg3;
1371         static void *spare_int;
1372         static uint32_t grbm_cntl;
1373         static uint32_t grbm_idx;
1374         uint32_t i = 0;
1375         uint32_t retries = 50000;
1376
1377         scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1378         scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1379         scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
1380         scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
1381         spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1382
1383         grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1384         grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1385
1386         if (amdgpu_sriov_runtime(adev)) {
1387                 pr_err("shouldn't call rlcg write register during runtime\n");
1388                 return;
1389         }
1390
1391         writel(v, scratch_reg0);
1392         writel(offset | 0x80000000, scratch_reg1);
1393         writel(1, spare_int);
1394         for (i = 0; i < retries; i++) {
1395                 u32 tmp;
1396
1397                 tmp = readl(scratch_reg1);
1398                 if (!(tmp & 0x80000000))
1399                         break;
1400
1401                 udelay(10);
1402         }
1403
1404         if (i >= retries)
1405                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1406 }
1407
1408 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1409 {
1410         /* Pending on emulation bring up */
1411 };
1412
1413 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1414 {
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2035 };
2036
2037 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2038 {
2039         /* Pending on emulation bring up */
2040 };
2041
2042 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2043 {
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3096 };
3097
3098 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3099 {
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3140 };
3141
3142 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3143 {
3144         /* Pending on emulation bring up */
3145 };
3146
3147 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3148 {
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
3187 };
3188
3189 #define DEFAULT_SH_MEM_CONFIG \
3190         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3191          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3192          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3193          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3194
3195
3196 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3197 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3198 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3199 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3200 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3201                                  struct amdgpu_cu_info *cu_info);
3202 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3203 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3204                                    u32 sh_num, u32 instance);
3205 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3206
3207 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3208 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3209 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3210 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3211 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3212 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3213 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3214 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3215 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3216
3217 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3218 {
3219         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3220         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3221                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3222         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3223         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3224         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3225         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3226         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3227         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3228 }
3229
3230 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3231                                  struct amdgpu_ring *ring)
3232 {
3233         struct amdgpu_device *adev = kiq_ring->adev;
3234         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3235         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3236         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3237
3238         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3239         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3240         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3241                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3242                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3243                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3244                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3245                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3246                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3247                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3248                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3249                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3250         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3251         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3252         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3253         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3254         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3255 }
3256
3257 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3258                                    struct amdgpu_ring *ring,
3259                                    enum amdgpu_unmap_queues_action action,
3260                                    u64 gpu_addr, u64 seq)
3261 {
3262         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3263
3264         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3265         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3266                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3267                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3268                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3269                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3270         amdgpu_ring_write(kiq_ring,
3271                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3272
3273         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3274                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3275                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3276                 amdgpu_ring_write(kiq_ring, seq);
3277         } else {
3278                 amdgpu_ring_write(kiq_ring, 0);
3279                 amdgpu_ring_write(kiq_ring, 0);
3280                 amdgpu_ring_write(kiq_ring, 0);
3281         }
3282 }
3283
3284 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3285                                    struct amdgpu_ring *ring,
3286                                    u64 addr,
3287                                    u64 seq)
3288 {
3289         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3290
3291         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3292         amdgpu_ring_write(kiq_ring,
3293                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3294                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3295                           PACKET3_QUERY_STATUS_COMMAND(2));
3296         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3297                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3298                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3299         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3300         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3301         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3302         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3303 }
3304
3305 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3306                                 uint16_t pasid, uint32_t flush_type,
3307                                 bool all_hub)
3308 {
3309         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3310         amdgpu_ring_write(kiq_ring,
3311                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3312                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3313                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3314                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3315 }
3316
3317 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3318         .kiq_set_resources = gfx10_kiq_set_resources,
3319         .kiq_map_queues = gfx10_kiq_map_queues,
3320         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3321         .kiq_query_status = gfx10_kiq_query_status,
3322         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3323         .set_resources_size = 8,
3324         .map_queues_size = 7,
3325         .unmap_queues_size = 6,
3326         .query_status_size = 7,
3327         .invalidate_tlbs_size = 2,
3328 };
3329
3330 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3331 {
3332         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3333 }
3334
3335 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3336 {
3337         switch (adev->asic_type) {
3338         case CHIP_NAVI10:
3339                 soc15_program_register_sequence(adev,
3340                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3341                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3342                 break;
3343         case CHIP_NAVI14:
3344                 soc15_program_register_sequence(adev,
3345                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3346                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3347                 break;
3348         case CHIP_NAVI12:
3349                 soc15_program_register_sequence(adev,
3350                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3351                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3352                 break;
3353         default:
3354                 break;
3355         }
3356 }
3357
3358 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3359 {
3360         switch (adev->asic_type) {
3361         case CHIP_NAVI10:
3362                 soc15_program_register_sequence(adev,
3363                                                 golden_settings_gc_10_1,
3364                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3365                 soc15_program_register_sequence(adev,
3366                                                 golden_settings_gc_10_0_nv10,
3367                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3368                 break;
3369         case CHIP_NAVI14:
3370                 soc15_program_register_sequence(adev,
3371                                                 golden_settings_gc_10_1_1,
3372                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3373                 soc15_program_register_sequence(adev,
3374                                                 golden_settings_gc_10_1_nv14,
3375                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3376                 break;
3377         case CHIP_NAVI12:
3378                 soc15_program_register_sequence(adev,
3379                                                 golden_settings_gc_10_1_2,
3380                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3381                 soc15_program_register_sequence(adev,
3382                                                 golden_settings_gc_10_1_2_nv12,
3383                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3384                 break;
3385         case CHIP_SIENNA_CICHLID:
3386                 soc15_program_register_sequence(adev,
3387                                                 golden_settings_gc_10_3,
3388                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3389                 soc15_program_register_sequence(adev,
3390                                                 golden_settings_gc_10_3_sienna_cichlid,
3391                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3392                 break;
3393         case CHIP_NAVY_FLOUNDER:
3394                 soc15_program_register_sequence(adev,
3395                                                 golden_settings_gc_10_3_2,
3396                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3397                 break;
3398
3399         default:
3400                 break;
3401         }
3402         gfx_v10_0_init_spm_golden_registers(adev);
3403 }
3404
3405 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3406 {
3407         adev->gfx.scratch.num_reg = 8;
3408         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3409         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3410 }
3411
3412 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3413                                        bool wc, uint32_t reg, uint32_t val)
3414 {
3415         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3416         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3417                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3418         amdgpu_ring_write(ring, reg);
3419         amdgpu_ring_write(ring, 0);
3420         amdgpu_ring_write(ring, val);
3421 }
3422
3423 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3424                                   int mem_space, int opt, uint32_t addr0,
3425                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3426                                   uint32_t inv)
3427 {
3428         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3429         amdgpu_ring_write(ring,
3430                           /* memory (1) or register (0) */
3431                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3432                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3433                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3434                            WAIT_REG_MEM_ENGINE(eng_sel)));
3435
3436         if (mem_space)
3437                 BUG_ON(addr0 & 0x3); /* Dword align */
3438         amdgpu_ring_write(ring, addr0);
3439         amdgpu_ring_write(ring, addr1);
3440         amdgpu_ring_write(ring, ref);
3441         amdgpu_ring_write(ring, mask);
3442         amdgpu_ring_write(ring, inv); /* poll interval */
3443 }
3444
3445 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3446 {
3447         struct amdgpu_device *adev = ring->adev;
3448         uint32_t scratch;
3449         uint32_t tmp = 0;
3450         unsigned i;
3451         int r;
3452
3453         r = amdgpu_gfx_scratch_get(adev, &scratch);
3454         if (r) {
3455                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3456                 return r;
3457         }
3458
3459         WREG32(scratch, 0xCAFEDEAD);
3460
3461         r = amdgpu_ring_alloc(ring, 3);
3462         if (r) {
3463                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3464                           ring->idx, r);
3465                 amdgpu_gfx_scratch_free(adev, scratch);
3466                 return r;
3467         }
3468
3469         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3470         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3471         amdgpu_ring_write(ring, 0xDEADBEEF);
3472         amdgpu_ring_commit(ring);
3473
3474         for (i = 0; i < adev->usec_timeout; i++) {
3475                 tmp = RREG32(scratch);
3476                 if (tmp == 0xDEADBEEF)
3477                         break;
3478                 if (amdgpu_emu_mode == 1)
3479                         msleep(1);
3480                 else
3481                         udelay(1);
3482         }
3483
3484         if (i >= adev->usec_timeout)
3485                 r = -ETIMEDOUT;
3486
3487         amdgpu_gfx_scratch_free(adev, scratch);
3488
3489         return r;
3490 }
3491
3492 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3493 {
3494         struct amdgpu_device *adev = ring->adev;
3495         struct amdgpu_ib ib;
3496         struct dma_fence *f = NULL;
3497         unsigned index;
3498         uint64_t gpu_addr;
3499         uint32_t tmp;
3500         long r;
3501
3502         r = amdgpu_device_wb_get(adev, &index);
3503         if (r)
3504                 return r;
3505
3506         gpu_addr = adev->wb.gpu_addr + (index * 4);
3507         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3508         memset(&ib, 0, sizeof(ib));
3509         r = amdgpu_ib_get(adev, NULL, 16,
3510                                         AMDGPU_IB_POOL_DIRECT, &ib);
3511         if (r)
3512                 goto err1;
3513
3514         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3515         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3516         ib.ptr[2] = lower_32_bits(gpu_addr);
3517         ib.ptr[3] = upper_32_bits(gpu_addr);
3518         ib.ptr[4] = 0xDEADBEEF;
3519         ib.length_dw = 5;
3520
3521         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3522         if (r)
3523                 goto err2;
3524
3525         r = dma_fence_wait_timeout(f, false, timeout);
3526         if (r == 0) {
3527                 r = -ETIMEDOUT;
3528                 goto err2;
3529         } else if (r < 0) {
3530                 goto err2;
3531         }
3532
3533         tmp = adev->wb.wb[index];
3534         if (tmp == 0xDEADBEEF)
3535                 r = 0;
3536         else
3537                 r = -EINVAL;
3538 err2:
3539         amdgpu_ib_free(adev, &ib, NULL);
3540         dma_fence_put(f);
3541 err1:
3542         amdgpu_device_wb_free(adev, index);
3543         return r;
3544 }
3545
3546 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3547 {
3548         release_firmware(adev->gfx.pfp_fw);
3549         adev->gfx.pfp_fw = NULL;
3550         release_firmware(adev->gfx.me_fw);
3551         adev->gfx.me_fw = NULL;
3552         release_firmware(adev->gfx.ce_fw);
3553         adev->gfx.ce_fw = NULL;
3554         release_firmware(adev->gfx.rlc_fw);
3555         adev->gfx.rlc_fw = NULL;
3556         release_firmware(adev->gfx.mec_fw);
3557         adev->gfx.mec_fw = NULL;
3558         release_firmware(adev->gfx.mec2_fw);
3559         adev->gfx.mec2_fw = NULL;
3560
3561         kfree(adev->gfx.rlc.register_list_format);
3562 }
3563
3564 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3565 {
3566         adev->gfx.cp_fw_write_wait = false;
3567
3568         switch (adev->asic_type) {
3569         case CHIP_NAVI10:
3570         case CHIP_NAVI12:
3571         case CHIP_NAVI14:
3572                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3573                     (adev->gfx.me_feature_version >= 27) &&
3574                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3575                     (adev->gfx.pfp_feature_version >= 27) &&
3576                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3577                     (adev->gfx.mec_feature_version >= 27))
3578                         adev->gfx.cp_fw_write_wait = true;
3579                 break;
3580         case CHIP_SIENNA_CICHLID:
3581         case CHIP_NAVY_FLOUNDER:
3582                 adev->gfx.cp_fw_write_wait = true;
3583                 break;
3584         default:
3585                 break;
3586         }
3587
3588         if (!adev->gfx.cp_fw_write_wait)
3589                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3590 }
3591
3592
3593 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3594 {
3595         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3596
3597         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3598         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3599         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3600         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3601         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3602         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3603         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3604         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3605         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3606         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3607         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3608         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3609         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3610         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3611                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3612 }
3613
3614 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3615 {
3616         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3617
3618         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3619         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3620         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3621         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3622         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3623 }
3624
3625 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3626 {
3627         bool ret = false;
3628
3629         switch (adev->pdev->revision) {
3630         case 0xc2:
3631         case 0xc3:
3632                 ret = true;
3633                 break;
3634         default:
3635                 ret = false;
3636                 break;
3637         }
3638
3639         return ret ;
3640 }
3641
3642 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3643 {
3644         switch (adev->asic_type) {
3645         case CHIP_NAVI10:
3646                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3647                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3648                 break;
3649         case CHIP_NAVY_FLOUNDER:
3650                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3651                 break;
3652         default:
3653                 break;
3654         }
3655 }
3656
3657 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3658 {
3659         const char *chip_name;
3660         char fw_name[40];
3661         char wks[10];
3662         int err;
3663         struct amdgpu_firmware_info *info = NULL;
3664         const struct common_firmware_header *header = NULL;
3665         const struct gfx_firmware_header_v1_0 *cp_hdr;
3666         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3667         unsigned int *tmp = NULL;
3668         unsigned int i = 0;
3669         uint16_t version_major;
3670         uint16_t version_minor;
3671
3672         DRM_DEBUG("\n");
3673
3674         memset(wks, 0, sizeof(wks));
3675         switch (adev->asic_type) {
3676         case CHIP_NAVI10:
3677                 chip_name = "navi10";
3678                 break;
3679         case CHIP_NAVI14:
3680                 chip_name = "navi14";
3681                 if (!(adev->pdev->device == 0x7340 &&
3682                       adev->pdev->revision != 0x00))
3683                         snprintf(wks, sizeof(wks), "_wks");
3684                 break;
3685         case CHIP_NAVI12:
3686                 chip_name = "navi12";
3687                 break;
3688         case CHIP_SIENNA_CICHLID:
3689                 chip_name = "sienna_cichlid";
3690                 break;
3691         case CHIP_NAVY_FLOUNDER:
3692                 chip_name = "navy_flounder";
3693                 break;
3694         default:
3695                 BUG();
3696         }
3697
3698         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3699         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3700         if (err)
3701                 goto out;
3702         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3703         if (err)
3704                 goto out;
3705         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3706         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3707         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3708
3709         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3710         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3711         if (err)
3712                 goto out;
3713         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3714         if (err)
3715                 goto out;
3716         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3717         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3718         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3719
3720         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3721         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3722         if (err)
3723                 goto out;
3724         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3725         if (err)
3726                 goto out;
3727         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3728         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3729         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3730
3731         if (!amdgpu_sriov_vf(adev)) {
3732                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3733                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3734                 if (err)
3735                         goto out;
3736                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3737                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3738                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3739                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3740
3741                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3742                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3743                 adev->gfx.rlc.save_and_restore_offset =
3744                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3745                 adev->gfx.rlc.clear_state_descriptor_offset =
3746                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3747                 adev->gfx.rlc.avail_scratch_ram_locations =
3748                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3749                 adev->gfx.rlc.reg_restore_list_size =
3750                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3751                 adev->gfx.rlc.reg_list_format_start =
3752                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3753                 adev->gfx.rlc.reg_list_format_separate_start =
3754                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3755                 adev->gfx.rlc.starting_offsets_start =
3756                         le32_to_cpu(rlc_hdr->starting_offsets_start);
3757                 adev->gfx.rlc.reg_list_format_size_bytes =
3758                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3759                 adev->gfx.rlc.reg_list_size_bytes =
3760                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3761                 adev->gfx.rlc.register_list_format =
3762                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3763                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3764                 if (!adev->gfx.rlc.register_list_format) {
3765                         err = -ENOMEM;
3766                         goto out;
3767                 }
3768
3769                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3770                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3771                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3772                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
3773
3774                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3775
3776                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3777                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3778                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3779                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3780
3781                 if (version_major == 2) {
3782                         if (version_minor >= 1)
3783                                 gfx_v10_0_init_rlc_ext_microcode(adev);
3784                         if (version_minor == 2)
3785                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
3786                 }
3787         }
3788
3789         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3790         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3791         if (err)
3792                 goto out;
3793         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3794         if (err)
3795                 goto out;
3796         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3797         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3798         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3799
3800         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3801         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3802         if (!err) {
3803                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3804                 if (err)
3805                         goto out;
3806                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3807                 adev->gfx.mec2_fw->data;
3808                 adev->gfx.mec2_fw_version =
3809                 le32_to_cpu(cp_hdr->header.ucode_version);
3810                 adev->gfx.mec2_feature_version =
3811                 le32_to_cpu(cp_hdr->ucode_feature_version);
3812         } else {
3813                 err = 0;
3814                 adev->gfx.mec2_fw = NULL;
3815         }
3816
3817         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3818                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3819                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3820                 info->fw = adev->gfx.pfp_fw;
3821                 header = (const struct common_firmware_header *)info->fw->data;
3822                 adev->firmware.fw_size +=
3823                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3824
3825                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3826                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3827                 info->fw = adev->gfx.me_fw;
3828                 header = (const struct common_firmware_header *)info->fw->data;
3829                 adev->firmware.fw_size +=
3830                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3831
3832                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3833                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3834                 info->fw = adev->gfx.ce_fw;
3835                 header = (const struct common_firmware_header *)info->fw->data;
3836                 adev->firmware.fw_size +=
3837                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3838
3839                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3840                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3841                 info->fw = adev->gfx.rlc_fw;
3842                 if (info->fw) {
3843                         header = (const struct common_firmware_header *)info->fw->data;
3844                         adev->firmware.fw_size +=
3845                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3846                 }
3847                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3848                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3849                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3850                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3851                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3852                         info->fw = adev->gfx.rlc_fw;
3853                         adev->firmware.fw_size +=
3854                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3855
3856                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3857                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3858                         info->fw = adev->gfx.rlc_fw;
3859                         adev->firmware.fw_size +=
3860                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
3861
3862                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
3863                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
3864                         info->fw = adev->gfx.rlc_fw;
3865                         adev->firmware.fw_size +=
3866                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
3867
3868                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
3869                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
3870                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
3871                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
3872                                 info->fw = adev->gfx.rlc_fw;
3873                                 adev->firmware.fw_size +=
3874                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
3875
3876                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
3877                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
3878                                 info->fw = adev->gfx.rlc_fw;
3879                                 adev->firmware.fw_size +=
3880                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
3881                         }
3882                 }
3883
3884                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
3885                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
3886                 info->fw = adev->gfx.mec_fw;
3887                 header = (const struct common_firmware_header *)info->fw->data;
3888                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3889                 adev->firmware.fw_size +=
3890                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3891                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3892
3893                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
3894                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
3895                 info->fw = adev->gfx.mec_fw;
3896                 adev->firmware.fw_size +=
3897                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3898
3899                 if (adev->gfx.mec2_fw) {
3900                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
3901                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
3902                         info->fw = adev->gfx.mec2_fw;
3903                         header = (const struct common_firmware_header *)info->fw->data;
3904                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3905                         adev->firmware.fw_size +=
3906                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3907                                       le32_to_cpu(cp_hdr->jt_size) * 4,
3908                                       PAGE_SIZE);
3909                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
3910                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
3911                         info->fw = adev->gfx.mec2_fw;
3912                         adev->firmware.fw_size +=
3913                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
3914                                       PAGE_SIZE);
3915                 }
3916         }
3917
3918         gfx_v10_0_check_fw_write_wait(adev);
3919 out:
3920         if (err) {
3921                 dev_err(adev->dev,
3922                         "gfx10: Failed to load firmware \"%s\"\n",
3923                         fw_name);
3924                 release_firmware(adev->gfx.pfp_fw);
3925                 adev->gfx.pfp_fw = NULL;
3926                 release_firmware(adev->gfx.me_fw);
3927                 adev->gfx.me_fw = NULL;
3928                 release_firmware(adev->gfx.ce_fw);
3929                 adev->gfx.ce_fw = NULL;
3930                 release_firmware(adev->gfx.rlc_fw);
3931                 adev->gfx.rlc_fw = NULL;
3932                 release_firmware(adev->gfx.mec_fw);
3933                 adev->gfx.mec_fw = NULL;
3934                 release_firmware(adev->gfx.mec2_fw);
3935                 adev->gfx.mec2_fw = NULL;
3936         }
3937
3938         gfx_v10_0_check_gfxoff_flag(adev);
3939
3940         return err;
3941 }
3942
3943 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
3944 {
3945         u32 count = 0;
3946         const struct cs_section_def *sect = NULL;
3947         const struct cs_extent_def *ext = NULL;
3948
3949         /* begin clear state */
3950         count += 2;
3951         /* context control state */
3952         count += 3;
3953
3954         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
3955                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3956                         if (sect->id == SECT_CONTEXT)
3957                                 count += 2 + ext->reg_count;
3958                         else
3959                                 return 0;
3960                 }
3961         }
3962
3963         /* set PA_SC_TILE_STEERING_OVERRIDE */
3964         count += 3;
3965         /* end clear state */
3966         count += 2;
3967         /* clear state */
3968         count += 2;
3969
3970         return count;
3971 }
3972
3973 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
3974                                     volatile u32 *buffer)
3975 {
3976         u32 count = 0, i;
3977         const struct cs_section_def *sect = NULL;
3978         const struct cs_extent_def *ext = NULL;
3979         int ctx_reg_offset;
3980
3981         if (adev->gfx.rlc.cs_data == NULL)
3982                 return;
3983         if (buffer == NULL)
3984                 return;
3985
3986         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3987         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3988
3989         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3990         buffer[count++] = cpu_to_le32(0x80000000);
3991         buffer[count++] = cpu_to_le32(0x80000000);
3992
3993         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3994                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3995                         if (sect->id == SECT_CONTEXT) {
3996                                 buffer[count++] =
3997                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
3998                                 buffer[count++] = cpu_to_le32(ext->reg_index -
3999                                                 PACKET3_SET_CONTEXT_REG_START);
4000                                 for (i = 0; i < ext->reg_count; i++)
4001                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4002                         } else {
4003                                 return;
4004                         }
4005                 }
4006         }
4007
4008         ctx_reg_offset =
4009                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4010         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4011         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4012         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4013
4014         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4015         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4016
4017         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4018         buffer[count++] = cpu_to_le32(0);
4019 }
4020
4021 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4022 {
4023         /* clear state block */
4024         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4025                         &adev->gfx.rlc.clear_state_gpu_addr,
4026                         (void **)&adev->gfx.rlc.cs_ptr);
4027
4028         /* jump table block */
4029         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4030                         &adev->gfx.rlc.cp_table_gpu_addr,
4031                         (void **)&adev->gfx.rlc.cp_table_ptr);
4032 }
4033
4034 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4035 {
4036         const struct cs_section_def *cs_data;
4037         int r;
4038
4039         adev->gfx.rlc.cs_data = gfx10_cs_data;
4040
4041         cs_data = adev->gfx.rlc.cs_data;
4042
4043         if (cs_data) {
4044                 /* init clear state block */
4045                 r = amdgpu_gfx_rlc_init_csb(adev);
4046                 if (r)
4047                         return r;
4048         }
4049
4050         /* init spm vmid with 0xf */
4051         if (adev->gfx.rlc.funcs->update_spm_vmid)
4052                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4053
4054         return 0;
4055 }
4056
4057 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4058 {
4059         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4060         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4061 }
4062
4063 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4064 {
4065         int r;
4066
4067         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4068
4069         amdgpu_gfx_graphics_queue_acquire(adev);
4070
4071         r = gfx_v10_0_init_microcode(adev);
4072         if (r)
4073                 DRM_ERROR("Failed to load gfx firmware!\n");
4074
4075         return r;
4076 }
4077
4078 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4079 {
4080         int r;
4081         u32 *hpd;
4082         const __le32 *fw_data = NULL;
4083         unsigned fw_size;
4084         u32 *fw = NULL;
4085         size_t mec_hpd_size;
4086
4087         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4088
4089         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4090
4091         /* take ownership of the relevant compute queues */
4092         amdgpu_gfx_compute_queue_acquire(adev);
4093         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4094
4095         if (mec_hpd_size) {
4096                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4097                                               AMDGPU_GEM_DOMAIN_GTT,
4098                                               &adev->gfx.mec.hpd_eop_obj,
4099                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4100                                               (void **)&hpd);
4101                 if (r) {
4102                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4103                         gfx_v10_0_mec_fini(adev);
4104                         return r;
4105                 }
4106
4107                 memset(hpd, 0, mec_hpd_size);
4108
4109                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4110                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4111         }
4112
4113         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4114                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4115
4116                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4117                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4118                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4119
4120                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4121                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4122                                               &adev->gfx.mec.mec_fw_obj,
4123                                               &adev->gfx.mec.mec_fw_gpu_addr,
4124                                               (void **)&fw);
4125                 if (r) {
4126                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4127                         gfx_v10_0_mec_fini(adev);
4128                         return r;
4129                 }
4130
4131                 memcpy(fw, fw_data, fw_size);
4132
4133                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4134                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4135         }
4136
4137         return 0;
4138 }
4139
4140 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4141 {
4142         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4143                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4144                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4145         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4146 }
4147
4148 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4149                            uint32_t thread, uint32_t regno,
4150                            uint32_t num, uint32_t *out)
4151 {
4152         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4153                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4154                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4155                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4156                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4157         while (num--)
4158                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4159 }
4160
4161 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4162 {
4163         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4164          * field when performing a select_se_sh so it should be
4165          * zero here */
4166         WARN_ON(simd != 0);
4167
4168         /* type 2 wave data */
4169         dst[(*no_fields)++] = 2;
4170         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4171         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4172         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4173         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4174         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4175         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4176         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4177         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4178         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4179         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4180         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4181         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4182         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4183         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4184         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4185 }
4186
4187 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4188                                      uint32_t wave, uint32_t start,
4189                                      uint32_t size, uint32_t *dst)
4190 {
4191         WARN_ON(simd != 0);
4192
4193         wave_read_regs(
4194                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4195                 dst);
4196 }
4197
4198 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4199                                       uint32_t wave, uint32_t thread,
4200                                       uint32_t start, uint32_t size,
4201                                       uint32_t *dst)
4202 {
4203         wave_read_regs(
4204                 adev, wave, thread,
4205                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4206 }
4207
4208 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4209                                                                           u32 me, u32 pipe, u32 q, u32 vm)
4210  {
4211        nv_grbm_select(adev, me, pipe, q, vm);
4212  }
4213
4214
4215 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4216         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4217         .select_se_sh = &gfx_v10_0_select_se_sh,
4218         .read_wave_data = &gfx_v10_0_read_wave_data,
4219         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4220         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4221         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4222         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4223 };
4224
4225 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4226 {
4227         u32 gb_addr_config;
4228
4229         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4230
4231         switch (adev->asic_type) {
4232         case CHIP_NAVI10:
4233         case CHIP_NAVI14:
4234         case CHIP_NAVI12:
4235                 adev->gfx.config.max_hw_contexts = 8;
4236                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4237                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4238                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4239                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4240                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4241                 break;
4242         case CHIP_SIENNA_CICHLID:
4243         case CHIP_NAVY_FLOUNDER:
4244                 adev->gfx.config.max_hw_contexts = 8;
4245                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4246                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4247                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4248                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4249                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4250                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4251                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4252                 break;
4253         default:
4254                 BUG();
4255                 break;
4256         }
4257
4258         adev->gfx.config.gb_addr_config = gb_addr_config;
4259
4260         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4261                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4262                                       GB_ADDR_CONFIG, NUM_PIPES);
4263
4264         adev->gfx.config.max_tile_pipes =
4265                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4266
4267         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4268                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4269                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4270         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4271                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4272                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4273         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4274                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4275                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4276         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4277                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4278                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4279 }
4280
4281 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4282                                    int me, int pipe, int queue)
4283 {
4284         int r;
4285         struct amdgpu_ring *ring;
4286         unsigned int irq_type;
4287
4288         ring = &adev->gfx.gfx_ring[ring_id];
4289
4290         ring->me = me;
4291         ring->pipe = pipe;
4292         ring->queue = queue;
4293
4294         ring->ring_obj = NULL;
4295         ring->use_doorbell = true;
4296
4297         if (!ring_id)
4298                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4299         else
4300                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4301         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4302
4303         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4304         r = amdgpu_ring_init(adev, ring, 1024,
4305                              &adev->gfx.eop_irq, irq_type,
4306                              AMDGPU_RING_PRIO_DEFAULT);
4307         if (r)
4308                 return r;
4309         return 0;
4310 }
4311
4312 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4313                                        int mec, int pipe, int queue)
4314 {
4315         int r;
4316         unsigned irq_type;
4317         struct amdgpu_ring *ring;
4318         unsigned int hw_prio;
4319
4320         ring = &adev->gfx.compute_ring[ring_id];
4321
4322         /* mec0 is me1 */
4323         ring->me = mec + 1;
4324         ring->pipe = pipe;
4325         ring->queue = queue;
4326
4327         ring->ring_obj = NULL;
4328         ring->use_doorbell = true;
4329         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4330         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4331                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4332         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4333
4334         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4335                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4336                 + ring->pipe;
4337         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
4338                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4339         /* type-2 packets are deprecated on MEC, use type-3 instead */
4340         r = amdgpu_ring_init(adev, ring, 1024,
4341                              &adev->gfx.eop_irq, irq_type, hw_prio);
4342         if (r)
4343                 return r;
4344
4345         return 0;
4346 }
4347
4348 static int gfx_v10_0_sw_init(void *handle)
4349 {
4350         int i, j, k, r, ring_id = 0;
4351         struct amdgpu_kiq *kiq;
4352         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4353
4354         switch (adev->asic_type) {
4355         case CHIP_NAVI10:
4356         case CHIP_NAVI14:
4357         case CHIP_NAVI12:
4358                 adev->gfx.me.num_me = 1;
4359                 adev->gfx.me.num_pipe_per_me = 1;
4360                 adev->gfx.me.num_queue_per_pipe = 1;
4361                 adev->gfx.mec.num_mec = 2;
4362                 adev->gfx.mec.num_pipe_per_mec = 4;
4363                 adev->gfx.mec.num_queue_per_pipe = 8;
4364                 break;
4365         case CHIP_SIENNA_CICHLID:
4366         case CHIP_NAVY_FLOUNDER:
4367                 adev->gfx.me.num_me = 1;
4368                 adev->gfx.me.num_pipe_per_me = 1;
4369                 adev->gfx.me.num_queue_per_pipe = 1;
4370                 adev->gfx.mec.num_mec = 2;
4371                 adev->gfx.mec.num_pipe_per_mec = 4;
4372                 adev->gfx.mec.num_queue_per_pipe = 4;
4373                 break;
4374         default:
4375                 adev->gfx.me.num_me = 1;
4376                 adev->gfx.me.num_pipe_per_me = 1;
4377                 adev->gfx.me.num_queue_per_pipe = 1;
4378                 adev->gfx.mec.num_mec = 1;
4379                 adev->gfx.mec.num_pipe_per_mec = 4;
4380                 adev->gfx.mec.num_queue_per_pipe = 8;
4381                 break;
4382         }
4383
4384         /* KIQ event */
4385         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4386                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4387                               &adev->gfx.kiq.irq);
4388         if (r)
4389                 return r;
4390
4391         /* EOP Event */
4392         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4393                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4394                               &adev->gfx.eop_irq);
4395         if (r)
4396                 return r;
4397
4398         /* Privileged reg */
4399         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4400                               &adev->gfx.priv_reg_irq);
4401         if (r)
4402                 return r;
4403
4404         /* Privileged inst */
4405         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4406                               &adev->gfx.priv_inst_irq);
4407         if (r)
4408                 return r;
4409
4410         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4411
4412         gfx_v10_0_scratch_init(adev);
4413
4414         r = gfx_v10_0_me_init(adev);
4415         if (r)
4416                 return r;
4417
4418         r = gfx_v10_0_rlc_init(adev);
4419         if (r) {
4420                 DRM_ERROR("Failed to init rlc BOs!\n");
4421                 return r;
4422         }
4423
4424         r = gfx_v10_0_mec_init(adev);
4425         if (r) {
4426                 DRM_ERROR("Failed to init MEC BOs!\n");
4427                 return r;
4428         }
4429
4430         /* set up the gfx ring */
4431         for (i = 0; i < adev->gfx.me.num_me; i++) {
4432                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4433                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4434                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4435                                         continue;
4436
4437                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4438                                                             i, k, j);
4439                                 if (r)
4440                                         return r;
4441                                 ring_id++;
4442                         }
4443                 }
4444         }
4445
4446         ring_id = 0;
4447         /* set up the compute queues - allocate horizontally across pipes */
4448         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4449                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4450                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4451                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4452                                                                      j))
4453                                         continue;
4454
4455                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4456                                                                 i, k, j);
4457                                 if (r)
4458                                         return r;
4459
4460                                 ring_id++;
4461                         }
4462                 }
4463         }
4464
4465         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4466         if (r) {
4467                 DRM_ERROR("Failed to init KIQ BOs!\n");
4468                 return r;
4469         }
4470
4471         kiq = &adev->gfx.kiq;
4472         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4473         if (r)
4474                 return r;
4475
4476         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4477         if (r)
4478                 return r;
4479
4480         /* allocate visible FB for rlc auto-loading fw */
4481         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4482                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4483                 if (r)
4484                         return r;
4485         }
4486
4487         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4488
4489         gfx_v10_0_gpu_early_init(adev);
4490
4491         return 0;
4492 }
4493
4494 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4495 {
4496         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4497                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4498                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4499 }
4500
4501 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4502 {
4503         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4504                               &adev->gfx.ce.ce_fw_gpu_addr,
4505                               (void **)&adev->gfx.ce.ce_fw_ptr);
4506 }
4507
4508 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4509 {
4510         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4511                               &adev->gfx.me.me_fw_gpu_addr,
4512                               (void **)&adev->gfx.me.me_fw_ptr);
4513 }
4514
4515 static int gfx_v10_0_sw_fini(void *handle)
4516 {
4517         int i;
4518         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4519
4520         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4521                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4522         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4523                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4524
4525         amdgpu_gfx_mqd_sw_fini(adev);
4526         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4527         amdgpu_gfx_kiq_fini(adev);
4528
4529         gfx_v10_0_pfp_fini(adev);
4530         gfx_v10_0_ce_fini(adev);
4531         gfx_v10_0_me_fini(adev);
4532         gfx_v10_0_rlc_fini(adev);
4533         gfx_v10_0_mec_fini(adev);
4534
4535         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4536                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4537
4538         gfx_v10_0_free_microcode(adev);
4539
4540         return 0;
4541 }
4542
4543 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4544                                    u32 sh_num, u32 instance)
4545 {
4546         u32 data;
4547
4548         if (instance == 0xffffffff)
4549                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4550                                      INSTANCE_BROADCAST_WRITES, 1);
4551         else
4552                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4553                                      instance);
4554
4555         if (se_num == 0xffffffff)
4556                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4557                                      1);
4558         else
4559                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4560
4561         if (sh_num == 0xffffffff)
4562                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4563                                      1);
4564         else
4565                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4566
4567         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4568 }
4569
4570 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4571 {
4572         u32 data, mask;
4573
4574         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4575         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4576
4577         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4578         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4579
4580         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4581                                          adev->gfx.config.max_sh_per_se);
4582
4583         return (~data) & mask;
4584 }
4585
4586 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4587 {
4588         int i, j;
4589         u32 data;
4590         u32 active_rbs = 0;
4591         u32 bitmap;
4592         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4593                                         adev->gfx.config.max_sh_per_se;
4594
4595         mutex_lock(&adev->grbm_idx_mutex);
4596         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4597                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4598                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4599                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
4600                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4601                                 continue;
4602                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4603                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4604                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4605                                                rb_bitmap_width_per_sh);
4606                 }
4607         }
4608         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4609         mutex_unlock(&adev->grbm_idx_mutex);
4610
4611         adev->gfx.config.backend_enable_mask = active_rbs;
4612         adev->gfx.config.num_rbs = hweight32(active_rbs);
4613 }
4614
4615 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4616 {
4617         uint32_t num_sc;
4618         uint32_t enabled_rb_per_sh;
4619         uint32_t active_rb_bitmap;
4620         uint32_t num_rb_per_sc;
4621         uint32_t num_packer_per_sc;
4622         uint32_t pa_sc_tile_steering_override;
4623
4624         /* for ASICs that integrates GFX v10.3
4625          * pa_sc_tile_steering_override should be set to 0 */
4626         if (adev->asic_type == CHIP_SIENNA_CICHLID ||
4627             adev->asic_type == CHIP_NAVY_FLOUNDER)
4628                 return 0;
4629
4630         /* init num_sc */
4631         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4632                         adev->gfx.config.num_sc_per_sh;
4633         /* init num_rb_per_sc */
4634         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4635         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4636         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4637         /* init num_packer_per_sc */
4638         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4639
4640         pa_sc_tile_steering_override = 0;
4641         pa_sc_tile_steering_override |=
4642                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4643                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4644         pa_sc_tile_steering_override |=
4645                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4646                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4647         pa_sc_tile_steering_override |=
4648                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4649                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4650
4651         return pa_sc_tile_steering_override;
4652 }
4653
4654 #define DEFAULT_SH_MEM_BASES    (0x6000)
4655
4656 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4657 {
4658         int i;
4659         uint32_t sh_mem_bases;
4660
4661         /*
4662          * Configure apertures:
4663          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4664          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4665          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4666          */
4667         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4668
4669         mutex_lock(&adev->srbm_mutex);
4670         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4671                 nv_grbm_select(adev, 0, 0, 0, i);
4672                 /* CP and shaders */
4673                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4674                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4675         }
4676         nv_grbm_select(adev, 0, 0, 0, 0);
4677         mutex_unlock(&adev->srbm_mutex);
4678
4679         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4680            acccess. These should be enabled by FW for target VMIDs. */
4681         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4682                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4683                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4684                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4685                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4686         }
4687 }
4688
4689 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4690 {
4691         int vmid;
4692
4693         /*
4694          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4695          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4696          * the driver can enable them for graphics. VMID0 should maintain
4697          * access so that HWS firmware can save/restore entries.
4698          */
4699         for (vmid = 1; vmid < 16; vmid++) {
4700                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4701                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4702                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4703                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4704         }
4705 }
4706
4707
4708 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4709 {
4710         int i, j, k;
4711         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4712         u32 tmp, wgp_active_bitmap = 0;
4713         u32 gcrd_targets_disable_tcp = 0;
4714         u32 utcl_invreq_disable = 0;
4715         /*
4716          * GCRD_TARGETS_DISABLE field contains
4717          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4718          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4719          */
4720         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4721                 2 * max_wgp_per_sh + /* TCP */
4722                 max_wgp_per_sh + /* SQC */
4723                 4); /* GL1C */
4724         /*
4725          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4726          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4727          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4728          */
4729         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4730                 2 * max_wgp_per_sh + /* TCP */
4731                 2 * max_wgp_per_sh + /* SQC */
4732                 4 + /* RMI */
4733                 1); /* SQG */
4734
4735         if (adev->asic_type == CHIP_NAVI10 ||
4736             adev->asic_type == CHIP_NAVI14 ||
4737             adev->asic_type == CHIP_NAVI12) {
4738                 mutex_lock(&adev->grbm_idx_mutex);
4739                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4740                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4741                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4742                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4743                                 /*
4744                                  * Set corresponding TCP bits for the inactive WGPs in
4745                                  * GCRD_SA_TARGETS_DISABLE
4746                                  */
4747                                 gcrd_targets_disable_tcp = 0;
4748                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4749                                 utcl_invreq_disable = 0;
4750
4751                                 for (k = 0; k < max_wgp_per_sh; k++) {
4752                                         if (!(wgp_active_bitmap & (1 << k))) {
4753                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
4754                                                 utcl_invreq_disable |= (3 << (2 * k)) |
4755                                                         (3 << (2 * (max_wgp_per_sh + k)));
4756                                         }
4757                                 }
4758
4759                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4760                                 /* only override TCP & SQC bits */
4761                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4762                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4763                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4764
4765                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4766                                 /* only override TCP bits */
4767                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4768                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4769                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4770                         }
4771                 }
4772
4773                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4774                 mutex_unlock(&adev->grbm_idx_mutex);
4775         }
4776 }
4777
4778 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4779 {
4780         /* TCCs are global (not instanced). */
4781         uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4782                                RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4783
4784         adev->gfx.config.tcc_disabled_mask =
4785                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4786                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4787 }
4788
4789 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4790 {
4791         u32 tmp;
4792         int i;
4793
4794         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4795
4796         gfx_v10_0_setup_rb(adev);
4797         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4798         gfx_v10_0_get_tcc_info(adev);
4799         adev->gfx.config.pa_sc_tile_steering_override =
4800                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4801
4802         /* XXX SH_MEM regs */
4803         /* where to put LDS, scratch, GPUVM in FSA64 space */
4804         mutex_lock(&adev->srbm_mutex);
4805         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4806                 nv_grbm_select(adev, 0, 0, 0, i);
4807                 /* CP and shaders */
4808                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4809                 if (i != 0) {
4810                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4811                                 (adev->gmc.private_aperture_start >> 48));
4812                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4813                                 (adev->gmc.shared_aperture_start >> 48));
4814                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4815                 }
4816         }
4817         nv_grbm_select(adev, 0, 0, 0, 0);
4818
4819         mutex_unlock(&adev->srbm_mutex);
4820
4821         gfx_v10_0_init_compute_vmid(adev);
4822         gfx_v10_0_init_gds_vmid(adev);
4823
4824 }
4825
4826 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4827                                                bool enable)
4828 {
4829         u32 tmp;
4830
4831         if (amdgpu_sriov_vf(adev))
4832                 return;
4833
4834         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
4835
4836         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
4837                             enable ? 1 : 0);
4838         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
4839                             enable ? 1 : 0);
4840         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
4841                             enable ? 1 : 0);
4842         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
4843                             enable ? 1 : 0);
4844
4845         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
4846 }
4847
4848 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
4849 {
4850         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
4851
4852         /* csib */
4853         if (adev->asic_type == CHIP_NAVI12) {
4854                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
4855                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
4856                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
4857                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4858                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4859         } else {
4860                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
4861                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
4862                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
4863                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4864                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4865         }
4866         return 0;
4867 }
4868
4869 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
4870 {
4871         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4872
4873         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
4874         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
4875 }
4876
4877 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
4878 {
4879         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4880         udelay(50);
4881         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4882         udelay(50);
4883 }
4884
4885 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
4886                                              bool enable)
4887 {
4888         uint32_t rlc_pg_cntl;
4889
4890         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
4891
4892         if (!enable) {
4893                 /* RLC_PG_CNTL[23] = 0 (default)
4894                  * RLC will wait for handshake acks with SMU
4895                  * GFXOFF will be enabled
4896                  * RLC_PG_CNTL[23] = 1
4897                  * RLC will not issue any message to SMU
4898                  * hence no handshake between SMU & RLC
4899                  * GFXOFF will be disabled
4900                  */
4901                 rlc_pg_cntl |= 0x800000;
4902         } else
4903                 rlc_pg_cntl &= ~0x800000;
4904         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
4905 }
4906
4907 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
4908 {
4909         /* TODO: enable rlc & smu handshake until smu
4910          * and gfxoff feature works as expected */
4911         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
4912                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
4913
4914         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
4915         udelay(50);
4916 }
4917
4918 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
4919 {
4920         uint32_t tmp;
4921
4922         /* enable Save Restore Machine */
4923         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
4924         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
4925         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
4926         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
4927 }
4928
4929 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
4930 {
4931         const struct rlc_firmware_header_v2_0 *hdr;
4932         const __le32 *fw_data;
4933         unsigned i, fw_size;
4934
4935         if (!adev->gfx.rlc_fw)
4936                 return -EINVAL;
4937
4938         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4939         amdgpu_ucode_print_rlc_hdr(&hdr->header);
4940
4941         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
4942                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4943         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
4944
4945         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
4946                      RLCG_UCODE_LOADING_START_ADDRESS);
4947
4948         for (i = 0; i < fw_size; i++)
4949                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
4950                              le32_to_cpup(fw_data++));
4951
4952         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
4953
4954         return 0;
4955 }
4956
4957 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
4958 {
4959         int r;
4960
4961         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4962
4963                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4964                 if (r)
4965                         return r;
4966
4967                 gfx_v10_0_init_csb(adev);
4968
4969                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
4970                         gfx_v10_0_rlc_enable_srm(adev);
4971         } else {
4972                 if (amdgpu_sriov_vf(adev)) {
4973                         gfx_v10_0_init_csb(adev);
4974                         return 0;
4975                 }
4976
4977                 adev->gfx.rlc.funcs->stop(adev);
4978
4979                 /* disable CG */
4980                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
4981
4982                 /* disable PG */
4983                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
4984
4985                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4986                         /* legacy rlc firmware loading */
4987                         r = gfx_v10_0_rlc_load_microcode(adev);
4988                         if (r)
4989                                 return r;
4990                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4991                         /* rlc backdoor autoload firmware */
4992                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
4993                         if (r)
4994                                 return r;
4995                 }
4996
4997                 gfx_v10_0_init_csb(adev);
4998
4999                 adev->gfx.rlc.funcs->start(adev);
5000
5001                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5002                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5003                         if (r)
5004                                 return r;
5005                 }
5006         }
5007         return 0;
5008 }
5009
5010 static struct {
5011         FIRMWARE_ID     id;
5012         unsigned int    offset;
5013         unsigned int    size;
5014 } rlc_autoload_info[FIRMWARE_ID_MAX];
5015
5016 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5017 {
5018         int ret;
5019         RLC_TABLE_OF_CONTENT *rlc_toc;
5020
5021         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5022                                         AMDGPU_GEM_DOMAIN_GTT,
5023                                         &adev->gfx.rlc.rlc_toc_bo,
5024                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5025                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5026         if (ret) {
5027                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5028                 return ret;
5029         }
5030
5031         /* Copy toc from psp sos fw to rlc toc buffer */
5032         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5033
5034         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5035         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5036                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5037                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5038                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5039                         /* Offset needs 4KB alignment */
5040                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5041                 }
5042
5043                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5044                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5045                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5046
5047                 rlc_toc++;
5048         }
5049
5050         return 0;
5051 }
5052
5053 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5054 {
5055         uint32_t total_size = 0;
5056         FIRMWARE_ID id;
5057         int ret;
5058
5059         ret = gfx_v10_0_parse_rlc_toc(adev);
5060         if (ret) {
5061                 dev_err(adev->dev, "failed to parse rlc toc\n");
5062                 return 0;
5063         }
5064
5065         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5066                 total_size += rlc_autoload_info[id].size;
5067
5068         /* In case the offset in rlc toc ucode is aligned */
5069         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5070                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5071                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5072
5073         return total_size;
5074 }
5075
5076 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5077 {
5078         int r;
5079         uint32_t total_size;
5080
5081         total_size = gfx_v10_0_calc_toc_total_size(adev);
5082
5083         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5084                                       AMDGPU_GEM_DOMAIN_GTT,
5085                                       &adev->gfx.rlc.rlc_autoload_bo,
5086                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5087                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5088         if (r) {
5089                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5090                 return r;
5091         }
5092
5093         return 0;
5094 }
5095
5096 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5097 {
5098         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5099                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5100                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5101         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5102                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5103                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5104 }
5105
5106 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5107                                                        FIRMWARE_ID id,
5108                                                        const void *fw_data,
5109                                                        uint32_t fw_size)
5110 {
5111         uint32_t toc_offset;
5112         uint32_t toc_fw_size;
5113         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5114
5115         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5116                 return;
5117
5118         toc_offset = rlc_autoload_info[id].offset;
5119         toc_fw_size = rlc_autoload_info[id].size;
5120
5121         if (fw_size == 0)
5122                 fw_size = toc_fw_size;
5123
5124         if (fw_size > toc_fw_size)
5125                 fw_size = toc_fw_size;
5126
5127         memcpy(ptr + toc_offset, fw_data, fw_size);
5128
5129         if (fw_size < toc_fw_size)
5130                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5131 }
5132
5133 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5134 {
5135         void *data;
5136         uint32_t size;
5137
5138         data = adev->gfx.rlc.rlc_toc_buf;
5139         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5140
5141         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5142                                                    FIRMWARE_ID_RLC_TOC,
5143                                                    data, size);
5144 }
5145
5146 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5147 {
5148         const __le32 *fw_data;
5149         uint32_t fw_size;
5150         const struct gfx_firmware_header_v1_0 *cp_hdr;
5151         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5152
5153         /* pfp ucode */
5154         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5155                 adev->gfx.pfp_fw->data;
5156         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5157                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5158         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5159         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5160                                                    FIRMWARE_ID_CP_PFP,
5161                                                    fw_data, fw_size);
5162
5163         /* ce ucode */
5164         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5165                 adev->gfx.ce_fw->data;
5166         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5167                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5168         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5169         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5170                                                    FIRMWARE_ID_CP_CE,
5171                                                    fw_data, fw_size);
5172
5173         /* me ucode */
5174         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5175                 adev->gfx.me_fw->data;
5176         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5177                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5178         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5179         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5180                                                    FIRMWARE_ID_CP_ME,
5181                                                    fw_data, fw_size);
5182
5183         /* rlc ucode */
5184         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5185                 adev->gfx.rlc_fw->data;
5186         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5187                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5188         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5189         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5190                                                    FIRMWARE_ID_RLC_G_UCODE,
5191                                                    fw_data, fw_size);
5192
5193         /* mec1 ucode */
5194         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5195                 adev->gfx.mec_fw->data;
5196         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5197                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5198         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5199                 cp_hdr->jt_size * 4;
5200         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5201                                                    FIRMWARE_ID_CP_MEC,
5202                                                    fw_data, fw_size);
5203         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5204 }
5205
5206 /* Temporarily put sdma part here */
5207 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5208 {
5209         const __le32 *fw_data;
5210         uint32_t fw_size;
5211         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5212         int i;
5213
5214         for (i = 0; i < adev->sdma.num_instances; i++) {
5215                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5216                         adev->sdma.instance[i].fw->data;
5217                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5218                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5219                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5220
5221                 if (i == 0) {
5222                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5223                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5224                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5225                                 FIRMWARE_ID_SDMA0_JT,
5226                                 (uint32_t *)fw_data +
5227                                 sdma_hdr->jt_offset,
5228                                 sdma_hdr->jt_size * 4);
5229                 } else if (i == 1) {
5230                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5231                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5232                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5233                                 FIRMWARE_ID_SDMA1_JT,
5234                                 (uint32_t *)fw_data +
5235                                 sdma_hdr->jt_offset,
5236                                 sdma_hdr->jt_size * 4);
5237                 }
5238         }
5239 }
5240
5241 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5242 {
5243         uint32_t rlc_g_offset, rlc_g_size, tmp;
5244         uint64_t gpu_addr;
5245
5246         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5247         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5248         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5249
5250         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5251         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5252         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5253
5254         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5255         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5256         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5257
5258         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5259         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5260                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5261                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5262                 return -EINVAL;
5263         }
5264
5265         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5266         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5267                 DRM_ERROR("RLC ROM should halt itself\n");
5268                 return -EINVAL;
5269         }
5270
5271         return 0;
5272 }
5273
5274 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5275 {
5276         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5277         uint32_t tmp;
5278         int i;
5279         uint64_t addr;
5280
5281         /* Trigger an invalidation of the L1 instruction caches */
5282         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5283         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5284         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5285
5286         /* Wait for invalidation complete */
5287         for (i = 0; i < usec_timeout; i++) {
5288                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5289                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5290                         INVALIDATE_CACHE_COMPLETE))
5291                         break;
5292                 udelay(1);
5293         }
5294
5295         if (i >= usec_timeout) {
5296                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5297                 return -EINVAL;
5298         }
5299
5300         /* Program me ucode address into intruction cache address register */
5301         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5302                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5303         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5304                         lower_32_bits(addr) & 0xFFFFF000);
5305         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5306                         upper_32_bits(addr));
5307
5308         return 0;
5309 }
5310
5311 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5312 {
5313         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5314         uint32_t tmp;
5315         int i;
5316         uint64_t addr;
5317
5318         /* Trigger an invalidation of the L1 instruction caches */
5319         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5320         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5321         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5322
5323         /* Wait for invalidation complete */
5324         for (i = 0; i < usec_timeout; i++) {
5325                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5326                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5327                         INVALIDATE_CACHE_COMPLETE))
5328                         break;
5329                 udelay(1);
5330         }
5331
5332         if (i >= usec_timeout) {
5333                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5334                 return -EINVAL;
5335         }
5336
5337         /* Program ce ucode address into intruction cache address register */
5338         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5339                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5340         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5341                         lower_32_bits(addr) & 0xFFFFF000);
5342         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5343                         upper_32_bits(addr));
5344
5345         return 0;
5346 }
5347
5348 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5349 {
5350         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5351         uint32_t tmp;
5352         int i;
5353         uint64_t addr;
5354
5355         /* Trigger an invalidation of the L1 instruction caches */
5356         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5357         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5358         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5359
5360         /* Wait for invalidation complete */
5361         for (i = 0; i < usec_timeout; i++) {
5362                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5363                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5364                         INVALIDATE_CACHE_COMPLETE))
5365                         break;
5366                 udelay(1);
5367         }
5368
5369         if (i >= usec_timeout) {
5370                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5371                 return -EINVAL;
5372         }
5373
5374         /* Program pfp ucode address into intruction cache address register */
5375         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5376                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5377         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5378                         lower_32_bits(addr) & 0xFFFFF000);
5379         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5380                         upper_32_bits(addr));
5381
5382         return 0;
5383 }
5384
5385 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5386 {
5387         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5388         uint32_t tmp;
5389         int i;
5390         uint64_t addr;
5391
5392         /* Trigger an invalidation of the L1 instruction caches */
5393         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5394         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5395         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5396
5397         /* Wait for invalidation complete */
5398         for (i = 0; i < usec_timeout; i++) {
5399                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5400                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5401                         INVALIDATE_CACHE_COMPLETE))
5402                         break;
5403                 udelay(1);
5404         }
5405
5406         if (i >= usec_timeout) {
5407                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5408                 return -EINVAL;
5409         }
5410
5411         /* Program mec1 ucode address into intruction cache address register */
5412         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5413                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5414         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5415                         lower_32_bits(addr) & 0xFFFFF000);
5416         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5417                         upper_32_bits(addr));
5418
5419         return 0;
5420 }
5421
5422 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5423 {
5424         uint32_t cp_status;
5425         uint32_t bootload_status;
5426         int i, r;
5427
5428         for (i = 0; i < adev->usec_timeout; i++) {
5429                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5430                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5431                 if ((cp_status == 0) &&
5432                     (REG_GET_FIELD(bootload_status,
5433                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5434                         break;
5435                 }
5436                 udelay(1);
5437         }
5438
5439         if (i >= adev->usec_timeout) {
5440                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5441                 return -ETIMEDOUT;
5442         }
5443
5444         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5445                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5446                 if (r)
5447                         return r;
5448
5449                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5450                 if (r)
5451                         return r;
5452
5453                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5454                 if (r)
5455                         return r;
5456
5457                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5458                 if (r)
5459                         return r;
5460         }
5461
5462         return 0;
5463 }
5464
5465 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5466 {
5467         int i;
5468         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5469
5470         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5471         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5472         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5473
5474         if (adev->asic_type == CHIP_NAVI12) {
5475                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5476         } else {
5477                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5478         }
5479
5480         for (i = 0; i < adev->usec_timeout; i++) {
5481                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5482                         break;
5483                 udelay(1);
5484         }
5485
5486         if (i >= adev->usec_timeout)
5487                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5488
5489         return 0;
5490 }
5491
5492 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5493 {
5494         int r;
5495         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5496         const __le32 *fw_data;
5497         unsigned i, fw_size;
5498         uint32_t tmp;
5499         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5500
5501         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5502                 adev->gfx.pfp_fw->data;
5503
5504         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5505
5506         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5507                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5508         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5509
5510         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5511                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5512                                       &adev->gfx.pfp.pfp_fw_obj,
5513                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5514                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5515         if (r) {
5516                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5517                 gfx_v10_0_pfp_fini(adev);
5518                 return r;
5519         }
5520
5521         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5522
5523         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5524         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5525
5526         /* Trigger an invalidation of the L1 instruction caches */
5527         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5528         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5529         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5530
5531         /* Wait for invalidation complete */
5532         for (i = 0; i < usec_timeout; i++) {
5533                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5534                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5535                         INVALIDATE_CACHE_COMPLETE))
5536                         break;
5537                 udelay(1);
5538         }
5539
5540         if (i >= usec_timeout) {
5541                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5542                 return -EINVAL;
5543         }
5544
5545         if (amdgpu_emu_mode == 1)
5546                 adev->nbio.funcs->hdp_flush(adev, NULL);
5547
5548         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5549         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5550         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5551         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5552         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5553         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5554         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5555                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5556         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5557                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5558
5559         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5560
5561         for (i = 0; i < pfp_hdr->jt_size; i++)
5562                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5563                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5564
5565         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5566
5567         return 0;
5568 }
5569
5570 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5571 {
5572         int r;
5573         const struct gfx_firmware_header_v1_0 *ce_hdr;
5574         const __le32 *fw_data;
5575         unsigned i, fw_size;
5576         uint32_t tmp;
5577         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5578
5579         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5580                 adev->gfx.ce_fw->data;
5581
5582         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5583
5584         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5585                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5586         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5587
5588         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5589                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5590                                       &adev->gfx.ce.ce_fw_obj,
5591                                       &adev->gfx.ce.ce_fw_gpu_addr,
5592                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5593         if (r) {
5594                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5595                 gfx_v10_0_ce_fini(adev);
5596                 return r;
5597         }
5598
5599         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5600
5601         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5602         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5603
5604         /* Trigger an invalidation of the L1 instruction caches */
5605         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5606         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5607         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5608
5609         /* Wait for invalidation complete */
5610         for (i = 0; i < usec_timeout; i++) {
5611                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5612                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5613                         INVALIDATE_CACHE_COMPLETE))
5614                         break;
5615                 udelay(1);
5616         }
5617
5618         if (i >= usec_timeout) {
5619                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5620                 return -EINVAL;
5621         }
5622
5623         if (amdgpu_emu_mode == 1)
5624                 adev->nbio.funcs->hdp_flush(adev, NULL);
5625
5626         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5627         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5628         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5629         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5630         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5631         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5632                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5633         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5634                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5635
5636         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5637
5638         for (i = 0; i < ce_hdr->jt_size; i++)
5639                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5640                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5641
5642         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5643
5644         return 0;
5645 }
5646
5647 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5648 {
5649         int r;
5650         const struct gfx_firmware_header_v1_0 *me_hdr;
5651         const __le32 *fw_data;
5652         unsigned i, fw_size;
5653         uint32_t tmp;
5654         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5655
5656         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5657                 adev->gfx.me_fw->data;
5658
5659         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5660
5661         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5662                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5663         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5664
5665         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5666                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5667                                       &adev->gfx.me.me_fw_obj,
5668                                       &adev->gfx.me.me_fw_gpu_addr,
5669                                       (void **)&adev->gfx.me.me_fw_ptr);
5670         if (r) {
5671                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5672                 gfx_v10_0_me_fini(adev);
5673                 return r;
5674         }
5675
5676         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5677
5678         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5679         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5680
5681         /* Trigger an invalidation of the L1 instruction caches */
5682         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5683         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5684         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5685
5686         /* Wait for invalidation complete */
5687         for (i = 0; i < usec_timeout; i++) {
5688                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5689                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5690                         INVALIDATE_CACHE_COMPLETE))
5691                         break;
5692                 udelay(1);
5693         }
5694
5695         if (i >= usec_timeout) {
5696                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5697                 return -EINVAL;
5698         }
5699
5700         if (amdgpu_emu_mode == 1)
5701                 adev->nbio.funcs->hdp_flush(adev, NULL);
5702
5703         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5704         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5705         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5706         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5707         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5708         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5709                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5710         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5711                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5712
5713         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5714
5715         for (i = 0; i < me_hdr->jt_size; i++)
5716                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5717                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5718
5719         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5720
5721         return 0;
5722 }
5723
5724 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5725 {
5726         int r;
5727
5728         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5729                 return -EINVAL;
5730
5731         gfx_v10_0_cp_gfx_enable(adev, false);
5732
5733         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5734         if (r) {
5735                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5736                 return r;
5737         }
5738
5739         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5740         if (r) {
5741                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5742                 return r;
5743         }
5744
5745         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5746         if (r) {
5747                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5748                 return r;
5749         }
5750
5751         return 0;
5752 }
5753
5754 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5755 {
5756         struct amdgpu_ring *ring;
5757         const struct cs_section_def *sect = NULL;
5758         const struct cs_extent_def *ext = NULL;
5759         int r, i;
5760         int ctx_reg_offset;
5761
5762         /* init the CP */
5763         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5764                      adev->gfx.config.max_hw_contexts - 1);
5765         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5766
5767         gfx_v10_0_cp_gfx_enable(adev, true);
5768
5769         ring = &adev->gfx.gfx_ring[0];
5770         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5771         if (r) {
5772                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5773                 return r;
5774         }
5775
5776         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5777         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5778
5779         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5780         amdgpu_ring_write(ring, 0x80000000);
5781         amdgpu_ring_write(ring, 0x80000000);
5782
5783         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5784                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5785                         if (sect->id == SECT_CONTEXT) {
5786                                 amdgpu_ring_write(ring,
5787                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5788                                                           ext->reg_count));
5789                                 amdgpu_ring_write(ring, ext->reg_index -
5790                                                   PACKET3_SET_CONTEXT_REG_START);
5791                                 for (i = 0; i < ext->reg_count; i++)
5792                                         amdgpu_ring_write(ring, ext->extent[i]);
5793                         }
5794                 }
5795         }
5796
5797         ctx_reg_offset =
5798                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5799         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5800         amdgpu_ring_write(ring, ctx_reg_offset);
5801         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5802
5803         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5804         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5805
5806         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5807         amdgpu_ring_write(ring, 0);
5808
5809         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5810         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5811         amdgpu_ring_write(ring, 0x8000);
5812         amdgpu_ring_write(ring, 0x8000);
5813
5814         amdgpu_ring_commit(ring);
5815
5816         /* submit cs packet to copy state 0 to next available state */
5817         if (adev->gfx.num_gfx_rings > 1) {
5818                 /* maximum supported gfx ring is 2 */
5819                 ring = &adev->gfx.gfx_ring[1];
5820                 r = amdgpu_ring_alloc(ring, 2);
5821                 if (r) {
5822                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5823                         return r;
5824                 }
5825
5826                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5827                 amdgpu_ring_write(ring, 0);
5828
5829                 amdgpu_ring_commit(ring);
5830         }
5831         return 0;
5832 }
5833
5834 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
5835                                          CP_PIPE_ID pipe)
5836 {
5837         u32 tmp;
5838
5839         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
5840         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
5841
5842         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
5843 }
5844
5845 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
5846                                           struct amdgpu_ring *ring)
5847 {
5848         u32 tmp;
5849
5850         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
5851         if (ring->use_doorbell) {
5852                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5853                                     DOORBELL_OFFSET, ring->doorbell_index);
5854                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5855                                     DOORBELL_EN, 1);
5856         } else {
5857                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5858                                     DOORBELL_EN, 0);
5859         }
5860         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
5861         switch (adev->asic_type) {
5862         case CHIP_SIENNA_CICHLID:
5863         case CHIP_NAVY_FLOUNDER:
5864                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5865                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
5866                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5867
5868                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5869                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
5870                 break;
5871         default:
5872                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5873                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
5874                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5875
5876                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5877                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
5878                 break;
5879         }
5880 }
5881
5882 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
5883 {
5884         struct amdgpu_ring *ring;
5885         u32 tmp;
5886         u32 rb_bufsz;
5887         u64 rb_addr, rptr_addr, wptr_gpu_addr;
5888         u32 i;
5889
5890         /* Set the write pointer delay */
5891         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
5892
5893         /* set the RB to use vmid 0 */
5894         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
5895
5896         /* Init gfx ring 0 for pipe 0 */
5897         mutex_lock(&adev->srbm_mutex);
5898         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5899
5900         /* Set ring buffer size */
5901         ring = &adev->gfx.gfx_ring[0];
5902         rb_bufsz = order_base_2(ring->ring_size / 8);
5903         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
5904         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
5905 #ifdef __BIG_ENDIAN
5906         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
5907 #endif
5908         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5909
5910         /* Initialize the ring buffer's write pointers */
5911         ring->wptr = 0;
5912         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
5913         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
5914
5915         /* set the wb address wether it's enabled or not */
5916         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5917         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
5918         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5919                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5920
5921         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5922         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5923                      lower_32_bits(wptr_gpu_addr));
5924         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5925                      upper_32_bits(wptr_gpu_addr));
5926
5927         mdelay(1);
5928         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5929
5930         rb_addr = ring->gpu_addr >> 8;
5931         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
5932         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
5933
5934         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
5935
5936         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5937         mutex_unlock(&adev->srbm_mutex);
5938
5939         /* Init gfx ring 1 for pipe 1 */
5940         if (adev->gfx.num_gfx_rings > 1) {
5941                 mutex_lock(&adev->srbm_mutex);
5942                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
5943                 /* maximum supported gfx ring is 2 */
5944                 ring = &adev->gfx.gfx_ring[1];
5945                 rb_bufsz = order_base_2(ring->ring_size / 8);
5946                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
5947                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
5948                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5949                 /* Initialize the ring buffer's write pointers */
5950                 ring->wptr = 0;
5951                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
5952                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
5953                 /* Set the wb address wether it's enabled or not */
5954                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5955                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
5956                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5957                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5958                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5959                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5960                              lower_32_bits(wptr_gpu_addr));
5961                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5962                              upper_32_bits(wptr_gpu_addr));
5963
5964                 mdelay(1);
5965                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5966
5967                 rb_addr = ring->gpu_addr >> 8;
5968                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
5969                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
5970                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
5971
5972                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5973                 mutex_unlock(&adev->srbm_mutex);
5974         }
5975         /* Switch to pipe 0 */
5976         mutex_lock(&adev->srbm_mutex);
5977         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5978         mutex_unlock(&adev->srbm_mutex);
5979
5980         /* start the ring */
5981         gfx_v10_0_cp_gfx_start(adev);
5982
5983         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5984                 ring = &adev->gfx.gfx_ring[i];
5985                 ring->sched.ready = true;
5986         }
5987
5988         return 0;
5989 }
5990
5991 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
5992 {
5993         if (enable) {
5994                 switch (adev->asic_type) {
5995                 case CHIP_SIENNA_CICHLID:
5996                 case CHIP_NAVY_FLOUNDER:
5997                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
5998                         break;
5999                 default:
6000                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6001                         break;
6002                 }
6003         } else {
6004                 switch (adev->asic_type) {
6005                 case CHIP_SIENNA_CICHLID:
6006                 case CHIP_NAVY_FLOUNDER:
6007                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6008                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6009                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6010                         break;
6011                 default:
6012                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6013                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6014                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6015                         break;
6016                 }
6017                 adev->gfx.kiq.ring.sched.ready = false;
6018         }
6019         udelay(50);
6020 }
6021
6022 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6023 {
6024         const struct gfx_firmware_header_v1_0 *mec_hdr;
6025         const __le32 *fw_data;
6026         unsigned i;
6027         u32 tmp;
6028         u32 usec_timeout = 50000; /* Wait for 50 ms */
6029
6030         if (!adev->gfx.mec_fw)
6031                 return -EINVAL;
6032
6033         gfx_v10_0_cp_compute_enable(adev, false);
6034
6035         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6036         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6037
6038         fw_data = (const __le32 *)
6039                 (adev->gfx.mec_fw->data +
6040                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6041
6042         /* Trigger an invalidation of the L1 instruction caches */
6043         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6044         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6045         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6046
6047         /* Wait for invalidation complete */
6048         for (i = 0; i < usec_timeout; i++) {
6049                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6050                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6051                                        INVALIDATE_CACHE_COMPLETE))
6052                         break;
6053                 udelay(1);
6054         }
6055
6056         if (i >= usec_timeout) {
6057                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6058                 return -EINVAL;
6059         }
6060
6061         if (amdgpu_emu_mode == 1)
6062                 adev->nbio.funcs->hdp_flush(adev, NULL);
6063
6064         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6065         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6066         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6067         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6068         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6069
6070         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6071                      0xFFFFF000);
6072         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6073                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6074
6075         /* MEC1 */
6076         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6077
6078         for (i = 0; i < mec_hdr->jt_size; i++)
6079                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6080                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6081
6082         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6083
6084         /*
6085          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6086          * different microcode than MEC1.
6087          */
6088
6089         return 0;
6090 }
6091
6092 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6093 {
6094         uint32_t tmp;
6095         struct amdgpu_device *adev = ring->adev;
6096
6097         /* tell RLC which is KIQ queue */
6098         switch (adev->asic_type) {
6099         case CHIP_SIENNA_CICHLID:
6100         case CHIP_NAVY_FLOUNDER:
6101                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6102                 tmp &= 0xffffff00;
6103                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6104                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6105                 tmp |= 0x80;
6106                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6107                 break;
6108         default:
6109                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6110                 tmp &= 0xffffff00;
6111                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6112                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6113                 tmp |= 0x80;
6114                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6115                 break;
6116         }
6117 }
6118
6119 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6120 {
6121         struct amdgpu_device *adev = ring->adev;
6122         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6123         uint64_t hqd_gpu_addr, wb_gpu_addr;
6124         uint32_t tmp;
6125         uint32_t rb_bufsz;
6126
6127         /* set up gfx hqd wptr */
6128         mqd->cp_gfx_hqd_wptr = 0;
6129         mqd->cp_gfx_hqd_wptr_hi = 0;
6130
6131         /* set the pointer to the MQD */
6132         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6133         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6134
6135         /* set up mqd control */
6136         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6137         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6138         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6139         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6140         mqd->cp_gfx_mqd_control = tmp;
6141
6142         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6143         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6144         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6145         mqd->cp_gfx_hqd_vmid = 0;
6146
6147         /* set up default queue priority level
6148          * 0x0 = low priority, 0x1 = high priority */
6149         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6150         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6151         mqd->cp_gfx_hqd_queue_priority = tmp;
6152
6153         /* set up time quantum */
6154         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6155         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6156         mqd->cp_gfx_hqd_quantum = tmp;
6157
6158         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6159         hqd_gpu_addr = ring->gpu_addr >> 8;
6160         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6161         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6162
6163         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6164         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6165         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6166         mqd->cp_gfx_hqd_rptr_addr_hi =
6167                 upper_32_bits(wb_gpu_addr) & 0xffff;
6168
6169         /* set up rb_wptr_poll addr */
6170         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6171         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6172         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6173
6174         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6175         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6176         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6177         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6178         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6179 #ifdef __BIG_ENDIAN
6180         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6181 #endif
6182         mqd->cp_gfx_hqd_cntl = tmp;
6183
6184         /* set up cp_doorbell_control */
6185         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6186         if (ring->use_doorbell) {
6187                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6188                                     DOORBELL_OFFSET, ring->doorbell_index);
6189                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6190                                     DOORBELL_EN, 1);
6191         } else
6192                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6193                                     DOORBELL_EN, 0);
6194         mqd->cp_rb_doorbell_control = tmp;
6195
6196         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6197         ring->wptr = 0;
6198         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6199
6200         /* active the queue */
6201         mqd->cp_gfx_hqd_active = 1;
6202
6203         return 0;
6204 }
6205
6206 #ifdef BRING_UP_DEBUG
6207 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6208 {
6209         struct amdgpu_device *adev = ring->adev;
6210         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6211
6212         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6213         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6214         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6215
6216         /* set GFX_MQD_BASE */
6217         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6218         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6219
6220         /* set GFX_MQD_CONTROL */
6221         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6222
6223         /* set GFX_HQD_VMID to 0 */
6224         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6225
6226         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6227                         mqd->cp_gfx_hqd_queue_priority);
6228         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6229
6230         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6231         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6232         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6233
6234         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6235         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6236         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6237
6238         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6239         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6240
6241         /* set RB_WPTR_POLL_ADDR */
6242         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6243         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6244
6245         /* set RB_DOORBELL_CONTROL */
6246         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6247
6248         /* active the queue */
6249         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6250
6251         return 0;
6252 }
6253 #endif
6254
6255 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6256 {
6257         struct amdgpu_device *adev = ring->adev;
6258         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6259         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6260
6261         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6262                 memset((void *)mqd, 0, sizeof(*mqd));
6263                 mutex_lock(&adev->srbm_mutex);
6264                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6265                 gfx_v10_0_gfx_mqd_init(ring);
6266 #ifdef BRING_UP_DEBUG
6267                 gfx_v10_0_gfx_queue_init_register(ring);
6268 #endif
6269                 nv_grbm_select(adev, 0, 0, 0, 0);
6270                 mutex_unlock(&adev->srbm_mutex);
6271                 if (adev->gfx.me.mqd_backup[mqd_idx])
6272                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6273         } else if (amdgpu_in_reset(adev)) {
6274                 /* reset mqd with the backup copy */
6275                 if (adev->gfx.me.mqd_backup[mqd_idx])
6276                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6277                 /* reset the ring */
6278                 ring->wptr = 0;
6279                 adev->wb.wb[ring->wptr_offs] = 0;
6280                 amdgpu_ring_clear_ring(ring);
6281 #ifdef BRING_UP_DEBUG
6282                 mutex_lock(&adev->srbm_mutex);
6283                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6284                 gfx_v10_0_gfx_queue_init_register(ring);
6285                 nv_grbm_select(adev, 0, 0, 0, 0);
6286                 mutex_unlock(&adev->srbm_mutex);
6287 #endif
6288         } else {
6289                 amdgpu_ring_clear_ring(ring);
6290         }
6291
6292         return 0;
6293 }
6294
6295 #ifndef BRING_UP_DEBUG
6296 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6297 {
6298         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6299         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6300         int r, i;
6301
6302         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6303                 return -EINVAL;
6304
6305         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6306                                         adev->gfx.num_gfx_rings);
6307         if (r) {
6308                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6309                 return r;
6310         }
6311
6312         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6313                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6314
6315         return amdgpu_ring_test_helper(kiq_ring);
6316 }
6317 #endif
6318
6319 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6320 {
6321         int r, i;
6322         struct amdgpu_ring *ring;
6323
6324         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6325                 ring = &adev->gfx.gfx_ring[i];
6326
6327                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6328                 if (unlikely(r != 0))
6329                         goto done;
6330
6331                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6332                 if (!r) {
6333                         r = gfx_v10_0_gfx_init_queue(ring);
6334                         amdgpu_bo_kunmap(ring->mqd_obj);
6335                         ring->mqd_ptr = NULL;
6336                 }
6337                 amdgpu_bo_unreserve(ring->mqd_obj);
6338                 if (r)
6339                         goto done;
6340         }
6341 #ifndef BRING_UP_DEBUG
6342         r = gfx_v10_0_kiq_enable_kgq(adev);
6343         if (r)
6344                 goto done;
6345 #endif
6346         r = gfx_v10_0_cp_gfx_start(adev);
6347         if (r)
6348                 goto done;
6349
6350         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6351                 ring = &adev->gfx.gfx_ring[i];
6352                 ring->sched.ready = true;
6353         }
6354 done:
6355         return r;
6356 }
6357
6358 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6359 {
6360         struct amdgpu_device *adev = ring->adev;
6361
6362         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6363                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
6364                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6365                         mqd->cp_hqd_queue_priority =
6366                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6367                 }
6368         }
6369 }
6370
6371 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6372 {
6373         struct amdgpu_device *adev = ring->adev;
6374         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6375         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6376         uint32_t tmp;
6377
6378         mqd->header = 0xC0310800;
6379         mqd->compute_pipelinestat_enable = 0x00000001;
6380         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6381         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6382         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6383         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6384         mqd->compute_misc_reserved = 0x00000003;
6385
6386         eop_base_addr = ring->eop_gpu_addr >> 8;
6387         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6388         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6389
6390         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6391         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6392         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6393                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6394
6395         mqd->cp_hqd_eop_control = tmp;
6396
6397         /* enable doorbell? */
6398         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6399
6400         if (ring->use_doorbell) {
6401                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6402                                     DOORBELL_OFFSET, ring->doorbell_index);
6403                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6404                                     DOORBELL_EN, 1);
6405                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6406                                     DOORBELL_SOURCE, 0);
6407                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6408                                     DOORBELL_HIT, 0);
6409         } else {
6410                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6411                                     DOORBELL_EN, 0);
6412         }
6413
6414         mqd->cp_hqd_pq_doorbell_control = tmp;
6415
6416         /* disable the queue if it's active */
6417         ring->wptr = 0;
6418         mqd->cp_hqd_dequeue_request = 0;
6419         mqd->cp_hqd_pq_rptr = 0;
6420         mqd->cp_hqd_pq_wptr_lo = 0;
6421         mqd->cp_hqd_pq_wptr_hi = 0;
6422
6423         /* set the pointer to the MQD */
6424         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6425         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6426
6427         /* set MQD vmid to 0 */
6428         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6429         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6430         mqd->cp_mqd_control = tmp;
6431
6432         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6433         hqd_gpu_addr = ring->gpu_addr >> 8;
6434         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6435         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6436
6437         /* set up the HQD, this is similar to CP_RB0_CNTL */
6438         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6439         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6440                             (order_base_2(ring->ring_size / 4) - 1));
6441         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6442                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6443 #ifdef __BIG_ENDIAN
6444         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6445 #endif
6446         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6447         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6448         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6449         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6450         mqd->cp_hqd_pq_control = tmp;
6451
6452         /* set the wb address whether it's enabled or not */
6453         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6454         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6455         mqd->cp_hqd_pq_rptr_report_addr_hi =
6456                 upper_32_bits(wb_gpu_addr) & 0xffff;
6457
6458         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6459         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6460         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6461         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6462
6463         tmp = 0;
6464         /* enable the doorbell if requested */
6465         if (ring->use_doorbell) {
6466                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6467                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6468                                 DOORBELL_OFFSET, ring->doorbell_index);
6469
6470                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6471                                     DOORBELL_EN, 1);
6472                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6473                                     DOORBELL_SOURCE, 0);
6474                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6475                                     DOORBELL_HIT, 0);
6476         }
6477
6478         mqd->cp_hqd_pq_doorbell_control = tmp;
6479
6480         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6481         ring->wptr = 0;
6482         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6483
6484         /* set the vmid for the queue */
6485         mqd->cp_hqd_vmid = 0;
6486
6487         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6488         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6489         mqd->cp_hqd_persistent_state = tmp;
6490
6491         /* set MIN_IB_AVAIL_SIZE */
6492         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6493         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6494         mqd->cp_hqd_ib_control = tmp;
6495
6496         /* set static priority for a compute queue/ring */
6497         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6498
6499         /* map_queues packet doesn't need activate the queue,
6500          * so only kiq need set this field.
6501          */
6502         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6503                 mqd->cp_hqd_active = 1;
6504
6505         return 0;
6506 }
6507
6508 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6509 {
6510         struct amdgpu_device *adev = ring->adev;
6511         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6512         int j;
6513
6514         /* inactivate the queue */
6515         if (amdgpu_sriov_vf(adev))
6516                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6517
6518         /* disable wptr polling */
6519         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6520
6521         /* write the EOP addr */
6522         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6523                mqd->cp_hqd_eop_base_addr_lo);
6524         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6525                mqd->cp_hqd_eop_base_addr_hi);
6526
6527         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6528         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6529                mqd->cp_hqd_eop_control);
6530
6531         /* enable doorbell? */
6532         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6533                mqd->cp_hqd_pq_doorbell_control);
6534
6535         /* disable the queue if it's active */
6536         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6537                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6538                 for (j = 0; j < adev->usec_timeout; j++) {
6539                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6540                                 break;
6541                         udelay(1);
6542                 }
6543                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6544                        mqd->cp_hqd_dequeue_request);
6545                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6546                        mqd->cp_hqd_pq_rptr);
6547                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6548                        mqd->cp_hqd_pq_wptr_lo);
6549                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6550                        mqd->cp_hqd_pq_wptr_hi);
6551         }
6552
6553         /* set the pointer to the MQD */
6554         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6555                mqd->cp_mqd_base_addr_lo);
6556         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6557                mqd->cp_mqd_base_addr_hi);
6558
6559         /* set MQD vmid to 0 */
6560         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6561                mqd->cp_mqd_control);
6562
6563         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6564         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6565                mqd->cp_hqd_pq_base_lo);
6566         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6567                mqd->cp_hqd_pq_base_hi);
6568
6569         /* set up the HQD, this is similar to CP_RB0_CNTL */
6570         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6571                mqd->cp_hqd_pq_control);
6572
6573         /* set the wb address whether it's enabled or not */
6574         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6575                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6576         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6577                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6578
6579         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6580         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6581                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6582         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6583                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6584
6585         /* enable the doorbell if requested */
6586         if (ring->use_doorbell) {
6587                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6588                         (adev->doorbell_index.kiq * 2) << 2);
6589                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6590                         (adev->doorbell_index.userqueue_end * 2) << 2);
6591         }
6592
6593         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6594                mqd->cp_hqd_pq_doorbell_control);
6595
6596         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6597         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6598                mqd->cp_hqd_pq_wptr_lo);
6599         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6600                mqd->cp_hqd_pq_wptr_hi);
6601
6602         /* set the vmid for the queue */
6603         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6604
6605         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6606                mqd->cp_hqd_persistent_state);
6607
6608         /* activate the queue */
6609         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6610                mqd->cp_hqd_active);
6611
6612         if (ring->use_doorbell)
6613                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6614
6615         return 0;
6616 }
6617
6618 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6619 {
6620         struct amdgpu_device *adev = ring->adev;
6621         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6622         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6623
6624         gfx_v10_0_kiq_setting(ring);
6625
6626         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6627                 /* reset MQD to a clean status */
6628                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6629                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6630
6631                 /* reset ring buffer */
6632                 ring->wptr = 0;
6633                 amdgpu_ring_clear_ring(ring);
6634
6635                 mutex_lock(&adev->srbm_mutex);
6636                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6637                 gfx_v10_0_kiq_init_register(ring);
6638                 nv_grbm_select(adev, 0, 0, 0, 0);
6639                 mutex_unlock(&adev->srbm_mutex);
6640         } else {
6641                 memset((void *)mqd, 0, sizeof(*mqd));
6642                 mutex_lock(&adev->srbm_mutex);
6643                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6644                 gfx_v10_0_compute_mqd_init(ring);
6645                 gfx_v10_0_kiq_init_register(ring);
6646                 nv_grbm_select(adev, 0, 0, 0, 0);
6647                 mutex_unlock(&adev->srbm_mutex);
6648
6649                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6650                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6651         }
6652
6653         return 0;
6654 }
6655
6656 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6657 {
6658         struct amdgpu_device *adev = ring->adev;
6659         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6660         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6661
6662         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6663                 memset((void *)mqd, 0, sizeof(*mqd));
6664                 mutex_lock(&adev->srbm_mutex);
6665                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6666                 gfx_v10_0_compute_mqd_init(ring);
6667                 nv_grbm_select(adev, 0, 0, 0, 0);
6668                 mutex_unlock(&adev->srbm_mutex);
6669
6670                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6671                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6672         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6673                 /* reset MQD to a clean status */
6674                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6675                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6676
6677                 /* reset ring buffer */
6678                 ring->wptr = 0;
6679                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6680                 amdgpu_ring_clear_ring(ring);
6681         } else {
6682                 amdgpu_ring_clear_ring(ring);
6683         }
6684
6685         return 0;
6686 }
6687
6688 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6689 {
6690         struct amdgpu_ring *ring;
6691         int r;
6692
6693         ring = &adev->gfx.kiq.ring;
6694
6695         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6696         if (unlikely(r != 0))
6697                 return r;
6698
6699         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6700         if (unlikely(r != 0))
6701                 return r;
6702
6703         gfx_v10_0_kiq_init_queue(ring);
6704         amdgpu_bo_kunmap(ring->mqd_obj);
6705         ring->mqd_ptr = NULL;
6706         amdgpu_bo_unreserve(ring->mqd_obj);
6707         ring->sched.ready = true;
6708         return 0;
6709 }
6710
6711 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6712 {
6713         struct amdgpu_ring *ring = NULL;
6714         int r = 0, i;
6715
6716         gfx_v10_0_cp_compute_enable(adev, true);
6717
6718         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6719                 ring = &adev->gfx.compute_ring[i];
6720
6721                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6722                 if (unlikely(r != 0))
6723                         goto done;
6724                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6725                 if (!r) {
6726                         r = gfx_v10_0_kcq_init_queue(ring);
6727                         amdgpu_bo_kunmap(ring->mqd_obj);
6728                         ring->mqd_ptr = NULL;
6729                 }
6730                 amdgpu_bo_unreserve(ring->mqd_obj);
6731                 if (r)
6732                         goto done;
6733         }
6734
6735         r = amdgpu_gfx_enable_kcq(adev);
6736 done:
6737         return r;
6738 }
6739
6740 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6741 {
6742         int r, i;
6743         struct amdgpu_ring *ring;
6744
6745         if (!(adev->flags & AMD_IS_APU))
6746                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6747
6748         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6749                 /* legacy firmware loading */
6750                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6751                 if (r)
6752                         return r;
6753
6754                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6755                 if (r)
6756                         return r;
6757         }
6758
6759         r = gfx_v10_0_kiq_resume(adev);
6760         if (r)
6761                 return r;
6762
6763         r = gfx_v10_0_kcq_resume(adev);
6764         if (r)
6765                 return r;
6766
6767         if (!amdgpu_async_gfx_ring) {
6768                 r = gfx_v10_0_cp_gfx_resume(adev);
6769                 if (r)
6770                         return r;
6771         } else {
6772                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6773                 if (r)
6774                         return r;
6775         }
6776
6777         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6778                 ring = &adev->gfx.gfx_ring[i];
6779                 r = amdgpu_ring_test_helper(ring);
6780                 if (r)
6781                         return r;
6782         }
6783
6784         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6785                 ring = &adev->gfx.compute_ring[i];
6786                 r = amdgpu_ring_test_helper(ring);
6787                 if (r)
6788                         return r;
6789         }
6790
6791         return 0;
6792 }
6793
6794 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6795 {
6796         gfx_v10_0_cp_gfx_enable(adev, enable);
6797         gfx_v10_0_cp_compute_enable(adev, enable);
6798 }
6799
6800 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6801 {
6802         uint32_t data, pattern = 0xDEADBEEF;
6803
6804         /* check if mmVGT_ESGS_RING_SIZE_UMD
6805          * has been remapped to mmVGT_ESGS_RING_SIZE */
6806         switch (adev->asic_type) {
6807         case CHIP_SIENNA_CICHLID:
6808         case CHIP_NAVY_FLOUNDER:
6809                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6810                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6811                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6812
6813                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6814                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
6815                         return true;
6816                 } else {
6817                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6818                         return false;
6819                 }
6820                 break;
6821         default:
6822                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6823                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6824                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6825
6826                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6827                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6828                         return true;
6829                 } else {
6830                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
6831                         return false;
6832                 }
6833                 break;
6834         }
6835 }
6836
6837 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6838 {
6839         uint32_t data;
6840
6841         /* initialize cam_index to 0
6842          * index will auto-inc after each data writting */
6843         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
6844
6845         switch (adev->asic_type) {
6846         case CHIP_SIENNA_CICHLID:
6847         case CHIP_NAVY_FLOUNDER:
6848                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6849                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6850                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6851                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
6852                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6853                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6854                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6855
6856                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6857                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6858                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6859                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
6860                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6861                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6862                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6863
6864                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6865                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6866                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6867                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
6868                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6869                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6870                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6871
6872                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6873                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6874                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6875                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
6876                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6877                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6878                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6879
6880                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6881                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6882                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6883                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
6884                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6885                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6886                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6887
6888                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6889                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6890                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6891                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
6892                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6893                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6894                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6895
6896                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6897                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6898                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6899                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
6900                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6901                 break;
6902         default:
6903                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6904                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6905                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6906                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
6907                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6908                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6909                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6910
6911                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6912                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6913                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6914                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
6915                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6916                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6917                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6918
6919                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6920                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6921                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6922                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
6923                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6924                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6925                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6926
6927                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6928                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6929                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6930                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
6931                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6932                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6933                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6934
6935                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6936                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6937                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6938                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
6939                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6940                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6941                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6942
6943                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6944                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6945                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6946                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
6947                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6948                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6949                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6950
6951                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6952                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6953                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6954                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
6955                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6956                 break;
6957         }
6958
6959         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6960         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6961 }
6962
6963 static int gfx_v10_0_hw_init(void *handle)
6964 {
6965         int r;
6966         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6967
6968         if (!amdgpu_emu_mode)
6969                 gfx_v10_0_init_golden_registers(adev);
6970
6971         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6972                 /**
6973                  * For gfx 10, rlc firmware loading relies on smu firmware is
6974                  * loaded firstly, so in direct type, it has to load smc ucode
6975                  * here before rlc.
6976                  */
6977                 if (adev->smu.ppt_funcs != NULL) {
6978                         r = smu_load_microcode(&adev->smu);
6979                         if (r)
6980                                 return r;
6981
6982                         r = smu_check_fw_status(&adev->smu);
6983                         if (r) {
6984                                 pr_err("SMC firmware status is not correct\n");
6985                                 return r;
6986                         }
6987                 }
6988         }
6989
6990         /* if GRBM CAM not remapped, set up the remapping */
6991         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
6992                 gfx_v10_0_setup_grbm_cam_remapping(adev);
6993
6994         gfx_v10_0_constants_init(adev);
6995
6996         r = gfx_v10_0_rlc_resume(adev);
6997         if (r)
6998                 return r;
6999
7000         /*
7001          * init golden registers and rlc resume may override some registers,
7002          * reconfig them here
7003          */
7004         gfx_v10_0_tcp_harvest(adev);
7005
7006         r = gfx_v10_0_cp_resume(adev);
7007         if (r)
7008                 return r;
7009
7010         if (adev->asic_type == CHIP_SIENNA_CICHLID)
7011                 gfx_v10_3_program_pbb_mode(adev);
7012
7013         return r;
7014 }
7015
7016 #ifndef BRING_UP_DEBUG
7017 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7018 {
7019         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7020         struct amdgpu_ring *kiq_ring = &kiq->ring;
7021         int i;
7022
7023         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7024                 return -EINVAL;
7025
7026         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7027                                         adev->gfx.num_gfx_rings))
7028                 return -ENOMEM;
7029
7030         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7031                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7032                                            PREEMPT_QUEUES, 0, 0);
7033
7034         return amdgpu_ring_test_helper(kiq_ring);
7035 }
7036 #endif
7037
7038 static int gfx_v10_0_hw_fini(void *handle)
7039 {
7040         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7041         int r;
7042         uint32_t tmp;
7043
7044         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7045         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7046
7047         if (!adev->in_pci_err_recovery) {
7048 #ifndef BRING_UP_DEBUG
7049                 if (amdgpu_async_gfx_ring) {
7050                         r = gfx_v10_0_kiq_disable_kgq(adev);
7051                         if (r)
7052                                 DRM_ERROR("KGQ disable failed\n");
7053                 }
7054 #endif
7055                 if (amdgpu_gfx_disable_kcq(adev))
7056                         DRM_ERROR("KCQ disable failed\n");
7057         }
7058
7059         if (amdgpu_sriov_vf(adev)) {
7060                 gfx_v10_0_cp_gfx_enable(adev, false);
7061                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7062                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7063                 tmp &= 0xffffff00;
7064                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7065
7066                 return 0;
7067         }
7068         gfx_v10_0_cp_enable(adev, false);
7069         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7070
7071         return 0;
7072 }
7073
7074 static int gfx_v10_0_suspend(void *handle)
7075 {
7076         return gfx_v10_0_hw_fini(handle);
7077 }
7078
7079 static int gfx_v10_0_resume(void *handle)
7080 {
7081         return gfx_v10_0_hw_init(handle);
7082 }
7083
7084 static bool gfx_v10_0_is_idle(void *handle)
7085 {
7086         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7087
7088         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7089                                 GRBM_STATUS, GUI_ACTIVE))
7090                 return false;
7091         else
7092                 return true;
7093 }
7094
7095 static int gfx_v10_0_wait_for_idle(void *handle)
7096 {
7097         unsigned i;
7098         u32 tmp;
7099         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7100
7101         for (i = 0; i < adev->usec_timeout; i++) {
7102                 /* read MC_STATUS */
7103                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7104                         GRBM_STATUS__GUI_ACTIVE_MASK;
7105
7106                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7107                         return 0;
7108                 udelay(1);
7109         }
7110         return -ETIMEDOUT;
7111 }
7112
7113 static int gfx_v10_0_soft_reset(void *handle)
7114 {
7115         u32 grbm_soft_reset = 0;
7116         u32 tmp;
7117         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7118
7119         /* GRBM_STATUS */
7120         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7121         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7122                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7123                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7124                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7125                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7126                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7127                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7128                                                 1);
7129                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7130                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7131                                                 1);
7132         }
7133
7134         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7135                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7136                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7137                                                 1);
7138         }
7139
7140         /* GRBM_STATUS2 */
7141         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7142         switch (adev->asic_type) {
7143         case CHIP_SIENNA_CICHLID:
7144         case CHIP_NAVY_FLOUNDER:
7145                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7146                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7147                                                         GRBM_SOFT_RESET,
7148                                                         SOFT_RESET_RLC,
7149                                                         1);
7150                 break;
7151         default:
7152                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7153                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7154                                                         GRBM_SOFT_RESET,
7155                                                         SOFT_RESET_RLC,
7156                                                         1);
7157                 break;
7158         }
7159
7160         if (grbm_soft_reset) {
7161                 /* stop the rlc */
7162                 gfx_v10_0_rlc_stop(adev);
7163
7164                 /* Disable GFX parsing/prefetching */
7165                 gfx_v10_0_cp_gfx_enable(adev, false);
7166
7167                 /* Disable MEC parsing/prefetching */
7168                 gfx_v10_0_cp_compute_enable(adev, false);
7169
7170                 if (grbm_soft_reset) {
7171                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7172                         tmp |= grbm_soft_reset;
7173                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7174                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7175                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7176
7177                         udelay(50);
7178
7179                         tmp &= ~grbm_soft_reset;
7180                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7181                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7182                 }
7183
7184                 /* Wait a little for things to settle down */
7185                 udelay(50);
7186         }
7187         return 0;
7188 }
7189
7190 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7191 {
7192         uint64_t clock;
7193
7194         amdgpu_gfx_off_ctrl(adev, false);
7195         mutex_lock(&adev->gfx.gpu_clock_mutex);
7196         clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7197                 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7198         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7199         amdgpu_gfx_off_ctrl(adev, true);
7200         return clock;
7201 }
7202
7203 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7204                                            uint32_t vmid,
7205                                            uint32_t gds_base, uint32_t gds_size,
7206                                            uint32_t gws_base, uint32_t gws_size,
7207                                            uint32_t oa_base, uint32_t oa_size)
7208 {
7209         struct amdgpu_device *adev = ring->adev;
7210
7211         /* GDS Base */
7212         gfx_v10_0_write_data_to_reg(ring, 0, false,
7213                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7214                                     gds_base);
7215
7216         /* GDS Size */
7217         gfx_v10_0_write_data_to_reg(ring, 0, false,
7218                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7219                                     gds_size);
7220
7221         /* GWS */
7222         gfx_v10_0_write_data_to_reg(ring, 0, false,
7223                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7224                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7225
7226         /* OA */
7227         gfx_v10_0_write_data_to_reg(ring, 0, false,
7228                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7229                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7230 }
7231
7232 static int gfx_v10_0_early_init(void *handle)
7233 {
7234         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7235
7236         switch (adev->asic_type) {
7237         case CHIP_NAVI10:
7238         case CHIP_NAVI14:
7239         case CHIP_NAVI12:
7240                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7241                 break;
7242         case CHIP_SIENNA_CICHLID:
7243         case CHIP_NAVY_FLOUNDER:
7244                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7245                 break;
7246         default:
7247                 break;
7248         }
7249
7250         adev->gfx.num_compute_rings = amdgpu_num_kcq;
7251
7252         gfx_v10_0_set_kiq_pm4_funcs(adev);
7253         gfx_v10_0_set_ring_funcs(adev);
7254         gfx_v10_0_set_irq_funcs(adev);
7255         gfx_v10_0_set_gds_init(adev);
7256         gfx_v10_0_set_rlc_funcs(adev);
7257
7258         return 0;
7259 }
7260
7261 static int gfx_v10_0_late_init(void *handle)
7262 {
7263         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7264         int r;
7265
7266         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7267         if (r)
7268                 return r;
7269
7270         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7271         if (r)
7272                 return r;
7273
7274         return 0;
7275 }
7276
7277 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7278 {
7279         uint32_t rlc_cntl;
7280
7281         /* if RLC is not enabled, do nothing */
7282         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7283         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7284 }
7285
7286 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7287 {
7288         uint32_t data;
7289         unsigned i;
7290
7291         data = RLC_SAFE_MODE__CMD_MASK;
7292         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7293
7294         switch (adev->asic_type) {
7295         case CHIP_SIENNA_CICHLID:
7296         case CHIP_NAVY_FLOUNDER:
7297                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7298
7299                 /* wait for RLC_SAFE_MODE */
7300                 for (i = 0; i < adev->usec_timeout; i++) {
7301                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7302                                            RLC_SAFE_MODE, CMD))
7303                                 break;
7304                         udelay(1);
7305                 }
7306                 break;
7307         default:
7308                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7309
7310                 /* wait for RLC_SAFE_MODE */
7311                 for (i = 0; i < adev->usec_timeout; i++) {
7312                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7313                                            RLC_SAFE_MODE, CMD))
7314                                 break;
7315                         udelay(1);
7316                 }
7317                 break;
7318         }
7319 }
7320
7321 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7322 {
7323         uint32_t data;
7324
7325         data = RLC_SAFE_MODE__CMD_MASK;
7326         switch (adev->asic_type) {
7327         case CHIP_SIENNA_CICHLID:
7328         case CHIP_NAVY_FLOUNDER:
7329                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7330                 break;
7331         default:
7332                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7333                 break;
7334         }
7335 }
7336
7337 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7338                                                       bool enable)
7339 {
7340         uint32_t data, def;
7341
7342         /* It is disabled by HW by default */
7343         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7344                 /* 0 - Disable some blocks' MGCG */
7345                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7346                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7347                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7348                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7349
7350                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7351                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7352                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7353                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7354                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7355                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7356
7357                 if (def != data)
7358                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7359
7360                 /* MGLS is a global flag to control all MGLS in GFX */
7361                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7362                         /* 2 - RLC memory Light sleep */
7363                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7364                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7365                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7366                                 if (def != data)
7367                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7368                         }
7369                         /* 3 - CP memory Light sleep */
7370                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7371                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7372                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7373                                 if (def != data)
7374                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7375                         }
7376                 }
7377         } else {
7378                 /* 1 - MGCG_OVERRIDE */
7379                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7380                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7381                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7382                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7383                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7384                 if (def != data)
7385                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7386
7387                 /* 2 - disable MGLS in CP */
7388                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7389                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7390                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7391                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7392                 }
7393
7394                 /* 3 - disable MGLS in RLC */
7395                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7396                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7397                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7398                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7399                 }
7400
7401         }
7402 }
7403
7404 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7405                                            bool enable)
7406 {
7407         uint32_t data, def;
7408
7409         /* Enable 3D CGCG/CGLS */
7410         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7411                 /* write cmd to clear cgcg/cgls ov */
7412                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7413                 /* unset CGCG override */
7414                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7415                 /* update CGCG and CGLS override bits */
7416                 if (def != data)
7417                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7418                 /* enable 3Dcgcg FSM(0x0000363f) */
7419                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7420                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7421                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7422                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7423                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7424                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7425                 if (def != data)
7426                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7427
7428                 /* set IDLE_POLL_COUNT(0x00900100) */
7429                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7430                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7431                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7432                 if (def != data)
7433                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7434         } else {
7435                 /* Disable CGCG/CGLS */
7436                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7437                 /* disable cgcg, cgls should be disabled */
7438                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7439                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7440                 /* disable cgcg and cgls in FSM */
7441                 if (def != data)
7442                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7443         }
7444 }
7445
7446 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7447                                                       bool enable)
7448 {
7449         uint32_t def, data;
7450
7451         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7452                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7453                 /* unset CGCG override */
7454                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7455                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7456                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7457                 else
7458                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7459                 /* update CGCG and CGLS override bits */
7460                 if (def != data)
7461                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7462
7463                 /* enable cgcg FSM(0x0000363F) */
7464                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7465                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7466                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7467                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7468                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7469                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7470                 if (def != data)
7471                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7472
7473                 /* set IDLE_POLL_COUNT(0x00900100) */
7474                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7475                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7476                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7477                 if (def != data)
7478                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7479         } else {
7480                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7481                 /* reset CGCG/CGLS bits */
7482                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7483                 /* disable cgcg and cgls in FSM */
7484                 if (def != data)
7485                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7486         }
7487 }
7488
7489 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7490                                             bool enable)
7491 {
7492         amdgpu_gfx_rlc_enter_safe_mode(adev);
7493
7494         if (enable) {
7495                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7496                  * ===  MGCG + MGLS ===
7497                  */
7498                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7499                 /* ===  CGCG /CGLS for GFX 3D Only === */
7500                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7501                 /* ===  CGCG + CGLS === */
7502                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7503         } else {
7504                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7505                  * ===  CGCG + CGLS ===
7506                  */
7507                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7508                 /* ===  CGCG /CGLS for GFX 3D Only === */
7509                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7510                 /* ===  MGCG + MGLS === */
7511                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7512         }
7513
7514         if (adev->cg_flags &
7515             (AMD_CG_SUPPORT_GFX_MGCG |
7516              AMD_CG_SUPPORT_GFX_CGLS |
7517              AMD_CG_SUPPORT_GFX_CGCG |
7518              AMD_CG_SUPPORT_GFX_3D_CGCG |
7519              AMD_CG_SUPPORT_GFX_3D_CGLS))
7520                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7521
7522         amdgpu_gfx_rlc_exit_safe_mode(adev);
7523
7524         return 0;
7525 }
7526
7527 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7528 {
7529         u32 reg, data;
7530
7531         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7532         if (amdgpu_sriov_is_pp_one_vf(adev))
7533                 data = RREG32_NO_KIQ(reg);
7534         else
7535                 data = RREG32(reg);
7536
7537         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7538         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7539
7540         if (amdgpu_sriov_is_pp_one_vf(adev))
7541                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7542         else
7543                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7544 }
7545
7546 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7547                                         uint32_t offset,
7548                                         struct soc15_reg_rlcg *entries, int arr_size)
7549 {
7550         int i;
7551         uint32_t reg;
7552
7553         if (!entries)
7554                 return false;
7555
7556         for (i = 0; i < arr_size; i++) {
7557                 const struct soc15_reg_rlcg *entry;
7558
7559                 entry = &entries[i];
7560                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7561                 if (offset == reg)
7562                         return true;
7563         }
7564
7565         return false;
7566 }
7567
7568 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7569 {
7570         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7571 }
7572
7573 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7574         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7575         .set_safe_mode = gfx_v10_0_set_safe_mode,
7576         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7577         .init = gfx_v10_0_rlc_init,
7578         .get_csb_size = gfx_v10_0_get_csb_size,
7579         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7580         .resume = gfx_v10_0_rlc_resume,
7581         .stop = gfx_v10_0_rlc_stop,
7582         .reset = gfx_v10_0_rlc_reset,
7583         .start = gfx_v10_0_rlc_start,
7584         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7585 };
7586
7587 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7588         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7589         .set_safe_mode = gfx_v10_0_set_safe_mode,
7590         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7591         .init = gfx_v10_0_rlc_init,
7592         .get_csb_size = gfx_v10_0_get_csb_size,
7593         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7594         .resume = gfx_v10_0_rlc_resume,
7595         .stop = gfx_v10_0_rlc_stop,
7596         .reset = gfx_v10_0_rlc_reset,
7597         .start = gfx_v10_0_rlc_start,
7598         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7599         .rlcg_wreg = gfx_v10_rlcg_wreg,
7600         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7601 };
7602
7603 static int gfx_v10_0_set_powergating_state(void *handle,
7604                                           enum amd_powergating_state state)
7605 {
7606         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7607         bool enable = (state == AMD_PG_STATE_GATE);
7608
7609         if (amdgpu_sriov_vf(adev))
7610                 return 0;
7611
7612         switch (adev->asic_type) {
7613         case CHIP_NAVI10:
7614         case CHIP_NAVI14:
7615         case CHIP_NAVI12:
7616         case CHIP_SIENNA_CICHLID:
7617         case CHIP_NAVY_FLOUNDER:
7618                 amdgpu_gfx_off_ctrl(adev, enable);
7619                 break;
7620         default:
7621                 break;
7622         }
7623         return 0;
7624 }
7625
7626 static int gfx_v10_0_set_clockgating_state(void *handle,
7627                                           enum amd_clockgating_state state)
7628 {
7629         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7630
7631         if (amdgpu_sriov_vf(adev))
7632                 return 0;
7633
7634         switch (adev->asic_type) {
7635         case CHIP_NAVI10:
7636         case CHIP_NAVI14:
7637         case CHIP_NAVI12:
7638         case CHIP_SIENNA_CICHLID:
7639         case CHIP_NAVY_FLOUNDER:
7640                 gfx_v10_0_update_gfx_clock_gating(adev,
7641                                                  state == AMD_CG_STATE_GATE);
7642                 break;
7643         default:
7644                 break;
7645         }
7646         return 0;
7647 }
7648
7649 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7650 {
7651         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7652         int data;
7653
7654         /* AMD_CG_SUPPORT_GFX_MGCG */
7655         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7656         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7657                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
7658
7659         /* AMD_CG_SUPPORT_GFX_CGCG */
7660         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
7661         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7662                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
7663
7664         /* AMD_CG_SUPPORT_GFX_CGLS */
7665         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7666                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
7667
7668         /* AMD_CG_SUPPORT_GFX_RLC_LS */
7669         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
7670         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7671                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7672
7673         /* AMD_CG_SUPPORT_GFX_CP_LS */
7674         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
7675         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7676                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7677
7678         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
7679         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
7680         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7681                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7682
7683         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
7684         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7685                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7686 }
7687
7688 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7689 {
7690         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7691 }
7692
7693 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
7694 {
7695         struct amdgpu_device *adev = ring->adev;
7696         u64 wptr;
7697
7698         /* XXX check if swapping is necessary on BE */
7699         if (ring->use_doorbell) {
7700                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
7701         } else {
7702                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
7703                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
7704         }
7705
7706         return wptr;
7707 }
7708
7709 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
7710 {
7711         struct amdgpu_device *adev = ring->adev;
7712
7713         if (ring->use_doorbell) {
7714                 /* XXX check if swapping is necessary on BE */
7715                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7716                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7717         } else {
7718                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
7719                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
7720         }
7721 }
7722
7723 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
7724 {
7725         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
7726 }
7727
7728 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
7729 {
7730         u64 wptr;
7731
7732         /* XXX check if swapping is necessary on BE */
7733         if (ring->use_doorbell)
7734                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
7735         else
7736                 BUG();
7737         return wptr;
7738 }
7739
7740 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
7741 {
7742         struct amdgpu_device *adev = ring->adev;
7743
7744         /* XXX check if swapping is necessary on BE */
7745         if (ring->use_doorbell) {
7746                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7747                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7748         } else {
7749                 BUG(); /* only DOORBELL method supported on gfx10 now */
7750         }
7751 }
7752
7753 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
7754 {
7755         struct amdgpu_device *adev = ring->adev;
7756         u32 ref_and_mask, reg_mem_engine;
7757         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
7758
7759         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
7760                 switch (ring->me) {
7761                 case 1:
7762                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
7763                         break;
7764                 case 2:
7765                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
7766                         break;
7767                 default:
7768                         return;
7769                 }
7770                 reg_mem_engine = 0;
7771         } else {
7772                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
7773                 reg_mem_engine = 1; /* pfp */
7774         }
7775
7776         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
7777                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
7778                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
7779                                ref_and_mask, ref_and_mask, 0x20);
7780 }
7781
7782 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
7783                                        struct amdgpu_job *job,
7784                                        struct amdgpu_ib *ib,
7785                                        uint32_t flags)
7786 {
7787         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7788         u32 header, control = 0;
7789
7790         if (ib->flags & AMDGPU_IB_FLAG_CE)
7791                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
7792         else
7793                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
7794
7795         control |= ib->length_dw | (vmid << 24);
7796
7797         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
7798                 control |= INDIRECT_BUFFER_PRE_ENB(1);
7799
7800                 if (flags & AMDGPU_IB_PREEMPTED)
7801                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
7802
7803                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
7804                         gfx_v10_0_ring_emit_de_meta(ring,
7805                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7806         }
7807
7808         amdgpu_ring_write(ring, header);
7809         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7810         amdgpu_ring_write(ring,
7811 #ifdef __BIG_ENDIAN
7812                 (2 << 0) |
7813 #endif
7814                 lower_32_bits(ib->gpu_addr));
7815         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7816         amdgpu_ring_write(ring, control);
7817 }
7818
7819 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
7820                                            struct amdgpu_job *job,
7821                                            struct amdgpu_ib *ib,
7822                                            uint32_t flags)
7823 {
7824         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7825         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
7826
7827         /* Currently, there is a high possibility to get wave ID mismatch
7828          * between ME and GDS, leading to a hw deadlock, because ME generates
7829          * different wave IDs than the GDS expects. This situation happens
7830          * randomly when at least 5 compute pipes use GDS ordered append.
7831          * The wave IDs generated by ME are also wrong after suspend/resume.
7832          * Those are probably bugs somewhere else in the kernel driver.
7833          *
7834          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
7835          * GDS to 0 for this ring (me/pipe).
7836          */
7837         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
7838                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
7839                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
7840                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
7841         }
7842
7843         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
7844         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7845         amdgpu_ring_write(ring,
7846 #ifdef __BIG_ENDIAN
7847                                 (2 << 0) |
7848 #endif
7849                                 lower_32_bits(ib->gpu_addr));
7850         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7851         amdgpu_ring_write(ring, control);
7852 }
7853
7854 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
7855                                      u64 seq, unsigned flags)
7856 {
7857         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
7858         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
7859
7860         /* RELEASE_MEM - flush caches, send int */
7861         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
7862         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
7863                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
7864                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
7865                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
7866                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
7867                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
7868                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
7869         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
7870                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
7871
7872         /*
7873          * the address should be Qword aligned if 64bit write, Dword
7874          * aligned if only send 32bit data low (discard data high)
7875          */
7876         if (write64bit)
7877                 BUG_ON(addr & 0x7);
7878         else
7879                 BUG_ON(addr & 0x3);
7880         amdgpu_ring_write(ring, lower_32_bits(addr));
7881         amdgpu_ring_write(ring, upper_32_bits(addr));
7882         amdgpu_ring_write(ring, lower_32_bits(seq));
7883         amdgpu_ring_write(ring, upper_32_bits(seq));
7884         amdgpu_ring_write(ring, 0);
7885 }
7886
7887 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
7888 {
7889         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
7890         uint32_t seq = ring->fence_drv.sync_seq;
7891         uint64_t addr = ring->fence_drv.gpu_addr;
7892
7893         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
7894                                upper_32_bits(addr), seq, 0xffffffff, 4);
7895 }
7896
7897 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
7898                                          unsigned vmid, uint64_t pd_addr)
7899 {
7900         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
7901
7902         /* compute doesn't have PFP */
7903         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
7904                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
7905                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
7906                 amdgpu_ring_write(ring, 0x0);
7907         }
7908 }
7909
7910 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
7911                                           u64 seq, unsigned int flags)
7912 {
7913         struct amdgpu_device *adev = ring->adev;
7914
7915         /* we only allocate 32bit for each seq wb address */
7916         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
7917
7918         /* write fence seq to the "addr" */
7919         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7920         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7921                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
7922         amdgpu_ring_write(ring, lower_32_bits(addr));
7923         amdgpu_ring_write(ring, upper_32_bits(addr));
7924         amdgpu_ring_write(ring, lower_32_bits(seq));
7925
7926         if (flags & AMDGPU_FENCE_FLAG_INT) {
7927                 /* set register to trigger INT */
7928                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7929                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7930                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
7931                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
7932                 amdgpu_ring_write(ring, 0);
7933                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
7934         }
7935 }
7936
7937 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
7938 {
7939         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
7940         amdgpu_ring_write(ring, 0);
7941 }
7942
7943 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
7944                                          uint32_t flags)
7945 {
7946         uint32_t dw2 = 0;
7947
7948         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
7949                 gfx_v10_0_ring_emit_ce_meta(ring,
7950                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7951
7952         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
7953         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
7954                 /* set load_global_config & load_global_uconfig */
7955                 dw2 |= 0x8001;
7956                 /* set load_cs_sh_regs */
7957                 dw2 |= 0x01000000;
7958                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
7959                 dw2 |= 0x10002;
7960
7961                 /* set load_ce_ram if preamble presented */
7962                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
7963                         dw2 |= 0x10000000;
7964         } else {
7965                 /* still load_ce_ram if this is the first time preamble presented
7966                  * although there is no context switch happens.
7967                  */
7968                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
7969                         dw2 |= 0x10000000;
7970         }
7971
7972         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
7973         amdgpu_ring_write(ring, dw2);
7974         amdgpu_ring_write(ring, 0);
7975 }
7976
7977 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
7978 {
7979         unsigned ret;
7980
7981         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
7982         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
7983         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
7984         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
7985         ret = ring->wptr & ring->buf_mask;
7986         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
7987
7988         return ret;
7989 }
7990
7991 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
7992 {
7993         unsigned cur;
7994         BUG_ON(offset > ring->buf_mask);
7995         BUG_ON(ring->ring[offset] != 0x55aa55aa);
7996
7997         cur = (ring->wptr - 1) & ring->buf_mask;
7998         if (likely(cur > offset))
7999                 ring->ring[offset] = cur - offset;
8000         else
8001                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8002 }
8003
8004 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8005 {
8006         int i, r = 0;
8007         struct amdgpu_device *adev = ring->adev;
8008         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8009         struct amdgpu_ring *kiq_ring = &kiq->ring;
8010         unsigned long flags;
8011
8012         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8013                 return -EINVAL;
8014
8015         spin_lock_irqsave(&kiq->ring_lock, flags);
8016
8017         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8018                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8019                 return -ENOMEM;
8020         }
8021
8022         /* assert preemption condition */
8023         amdgpu_ring_set_preempt_cond_exec(ring, false);
8024
8025         /* assert IB preemption, emit the trailing fence */
8026         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8027                                    ring->trail_fence_gpu_addr,
8028                                    ++ring->trail_seq);
8029         amdgpu_ring_commit(kiq_ring);
8030
8031         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8032
8033         /* poll the trailing fence */
8034         for (i = 0; i < adev->usec_timeout; i++) {
8035                 if (ring->trail_seq ==
8036                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8037                         break;
8038                 udelay(1);
8039         }
8040
8041         if (i >= adev->usec_timeout) {
8042                 r = -EINVAL;
8043                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8044         }
8045
8046         /* deassert preemption condition */
8047         amdgpu_ring_set_preempt_cond_exec(ring, true);
8048         return r;
8049 }
8050
8051 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8052 {
8053         struct amdgpu_device *adev = ring->adev;
8054         struct v10_ce_ib_state ce_payload = {0};
8055         uint64_t csa_addr;
8056         int cnt;
8057
8058         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8059         csa_addr = amdgpu_csa_vaddr(ring->adev);
8060
8061         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8062         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8063                                  WRITE_DATA_DST_SEL(8) |
8064                                  WR_CONFIRM) |
8065                                  WRITE_DATA_CACHE_POLICY(0));
8066         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8067                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8068         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8069                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8070
8071         if (resume)
8072                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8073                                            offsetof(struct v10_gfx_meta_data,
8074                                                     ce_payload),
8075                                            sizeof(ce_payload) >> 2);
8076         else
8077                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8078                                            sizeof(ce_payload) >> 2);
8079 }
8080
8081 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8082 {
8083         struct amdgpu_device *adev = ring->adev;
8084         struct v10_de_ib_state de_payload = {0};
8085         uint64_t csa_addr, gds_addr;
8086         int cnt;
8087
8088         csa_addr = amdgpu_csa_vaddr(ring->adev);
8089         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8090                          PAGE_SIZE);
8091         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8092         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8093
8094         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8095         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8096         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8097                                  WRITE_DATA_DST_SEL(8) |
8098                                  WR_CONFIRM) |
8099                                  WRITE_DATA_CACHE_POLICY(0));
8100         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8101                               offsetof(struct v10_gfx_meta_data, de_payload)));
8102         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8103                               offsetof(struct v10_gfx_meta_data, de_payload)));
8104
8105         if (resume)
8106                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8107                                            offsetof(struct v10_gfx_meta_data,
8108                                                     de_payload),
8109                                            sizeof(de_payload) >> 2);
8110         else
8111                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8112                                            sizeof(de_payload) >> 2);
8113 }
8114
8115 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8116                                     bool secure)
8117 {
8118         uint32_t v = secure ? FRAME_TMZ : 0;
8119
8120         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8121         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8122 }
8123
8124 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8125                                      uint32_t reg_val_offs)
8126 {
8127         struct amdgpu_device *adev = ring->adev;
8128
8129         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8130         amdgpu_ring_write(ring, 0 |     /* src: register*/
8131                                 (5 << 8) |      /* dst: memory */
8132                                 (1 << 20));     /* write confirm */
8133         amdgpu_ring_write(ring, reg);
8134         amdgpu_ring_write(ring, 0);
8135         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8136                                 reg_val_offs * 4));
8137         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8138                                 reg_val_offs * 4));
8139 }
8140
8141 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8142                                    uint32_t val)
8143 {
8144         uint32_t cmd = 0;
8145
8146         switch (ring->funcs->type) {
8147         case AMDGPU_RING_TYPE_GFX:
8148                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8149                 break;
8150         case AMDGPU_RING_TYPE_KIQ:
8151                 cmd = (1 << 16); /* no inc addr */
8152                 break;
8153         default:
8154                 cmd = WR_CONFIRM;
8155                 break;
8156         }
8157         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8158         amdgpu_ring_write(ring, cmd);
8159         amdgpu_ring_write(ring, reg);
8160         amdgpu_ring_write(ring, 0);
8161         amdgpu_ring_write(ring, val);
8162 }
8163
8164 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8165                                         uint32_t val, uint32_t mask)
8166 {
8167         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8168 }
8169
8170 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8171                                                    uint32_t reg0, uint32_t reg1,
8172                                                    uint32_t ref, uint32_t mask)
8173 {
8174         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8175         struct amdgpu_device *adev = ring->adev;
8176         bool fw_version_ok = false;
8177
8178         fw_version_ok = adev->gfx.cp_fw_write_wait;
8179
8180         if (fw_version_ok)
8181                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8182                                        ref, mask, 0x20);
8183         else
8184                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8185                                                            ref, mask);
8186 }
8187
8188 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8189                                          unsigned vmid)
8190 {
8191         struct amdgpu_device *adev = ring->adev;
8192         uint32_t value = 0;
8193
8194         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8195         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8196         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8197         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8198         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8199 }
8200
8201 static void
8202 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8203                                       uint32_t me, uint32_t pipe,
8204                                       enum amdgpu_interrupt_state state)
8205 {
8206         uint32_t cp_int_cntl, cp_int_cntl_reg;
8207
8208         if (!me) {
8209                 switch (pipe) {
8210                 case 0:
8211                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8212                         break;
8213                 case 1:
8214                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8215                         break;
8216                 default:
8217                         DRM_DEBUG("invalid pipe %d\n", pipe);
8218                         return;
8219                 }
8220         } else {
8221                 DRM_DEBUG("invalid me %d\n", me);
8222                 return;
8223         }
8224
8225         switch (state) {
8226         case AMDGPU_IRQ_STATE_DISABLE:
8227                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8228                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8229                                             TIME_STAMP_INT_ENABLE, 0);
8230                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8231                 break;
8232         case AMDGPU_IRQ_STATE_ENABLE:
8233                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8234                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8235                                             TIME_STAMP_INT_ENABLE, 1);
8236                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8237                 break;
8238         default:
8239                 break;
8240         }
8241 }
8242
8243 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8244                                                      int me, int pipe,
8245                                                      enum amdgpu_interrupt_state state)
8246 {
8247         u32 mec_int_cntl, mec_int_cntl_reg;
8248
8249         /*
8250          * amdgpu controls only the first MEC. That's why this function only
8251          * handles the setting of interrupts for this specific MEC. All other
8252          * pipes' interrupts are set by amdkfd.
8253          */
8254
8255         if (me == 1) {
8256                 switch (pipe) {
8257                 case 0:
8258                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8259                         break;
8260                 case 1:
8261                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8262                         break;
8263                 case 2:
8264                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8265                         break;
8266                 case 3:
8267                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8268                         break;
8269                 default:
8270                         DRM_DEBUG("invalid pipe %d\n", pipe);
8271                         return;
8272                 }
8273         } else {
8274                 DRM_DEBUG("invalid me %d\n", me);
8275                 return;
8276         }
8277
8278         switch (state) {
8279         case AMDGPU_IRQ_STATE_DISABLE:
8280                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8281                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8282                                              TIME_STAMP_INT_ENABLE, 0);
8283                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8284                 break;
8285         case AMDGPU_IRQ_STATE_ENABLE:
8286                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8287                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8288                                              TIME_STAMP_INT_ENABLE, 1);
8289                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8290                 break;
8291         default:
8292                 break;
8293         }
8294 }
8295
8296 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8297                                             struct amdgpu_irq_src *src,
8298                                             unsigned type,
8299                                             enum amdgpu_interrupt_state state)
8300 {
8301         switch (type) {
8302         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8303                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8304                 break;
8305         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8306                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8307                 break;
8308         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8309                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8310                 break;
8311         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8312                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8313                 break;
8314         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8315                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8316                 break;
8317         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8318                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8319                 break;
8320         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8321                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8322                 break;
8323         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8324                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8325                 break;
8326         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8327                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8328                 break;
8329         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8330                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8331                 break;
8332         default:
8333                 break;
8334         }
8335         return 0;
8336 }
8337
8338 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8339                              struct amdgpu_irq_src *source,
8340                              struct amdgpu_iv_entry *entry)
8341 {
8342         int i;
8343         u8 me_id, pipe_id, queue_id;
8344         struct amdgpu_ring *ring;
8345
8346         DRM_DEBUG("IH: CP EOP\n");
8347         me_id = (entry->ring_id & 0x0c) >> 2;
8348         pipe_id = (entry->ring_id & 0x03) >> 0;
8349         queue_id = (entry->ring_id & 0x70) >> 4;
8350
8351         switch (me_id) {
8352         case 0:
8353                 if (pipe_id == 0)
8354                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8355                 else
8356                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8357                 break;
8358         case 1:
8359         case 2:
8360                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8361                         ring = &adev->gfx.compute_ring[i];
8362                         /* Per-queue interrupt is supported for MEC starting from VI.
8363                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8364                           */
8365                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8366                                 amdgpu_fence_process(ring);
8367                 }
8368                 break;
8369         }
8370         return 0;
8371 }
8372
8373 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8374                                               struct amdgpu_irq_src *source,
8375                                               unsigned type,
8376                                               enum amdgpu_interrupt_state state)
8377 {
8378         switch (state) {
8379         case AMDGPU_IRQ_STATE_DISABLE:
8380         case AMDGPU_IRQ_STATE_ENABLE:
8381                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8382                                PRIV_REG_INT_ENABLE,
8383                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8384                 break;
8385         default:
8386                 break;
8387         }
8388
8389         return 0;
8390 }
8391
8392 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8393                                                struct amdgpu_irq_src *source,
8394                                                unsigned type,
8395                                                enum amdgpu_interrupt_state state)
8396 {
8397         switch (state) {
8398         case AMDGPU_IRQ_STATE_DISABLE:
8399         case AMDGPU_IRQ_STATE_ENABLE:
8400                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8401                                PRIV_INSTR_INT_ENABLE,
8402                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8403         default:
8404                 break;
8405         }
8406
8407         return 0;
8408 }
8409
8410 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8411                                         struct amdgpu_iv_entry *entry)
8412 {
8413         u8 me_id, pipe_id, queue_id;
8414         struct amdgpu_ring *ring;
8415         int i;
8416
8417         me_id = (entry->ring_id & 0x0c) >> 2;
8418         pipe_id = (entry->ring_id & 0x03) >> 0;
8419         queue_id = (entry->ring_id & 0x70) >> 4;
8420
8421         switch (me_id) {
8422         case 0:
8423                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8424                         ring = &adev->gfx.gfx_ring[i];
8425                         /* we only enabled 1 gfx queue per pipe for now */
8426                         if (ring->me == me_id && ring->pipe == pipe_id)
8427                                 drm_sched_fault(&ring->sched);
8428                 }
8429                 break;
8430         case 1:
8431         case 2:
8432                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8433                         ring = &adev->gfx.compute_ring[i];
8434                         if (ring->me == me_id && ring->pipe == pipe_id &&
8435                             ring->queue == queue_id)
8436                                 drm_sched_fault(&ring->sched);
8437                 }
8438                 break;
8439         default:
8440                 BUG();
8441         }
8442 }
8443
8444 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8445                                   struct amdgpu_irq_src *source,
8446                                   struct amdgpu_iv_entry *entry)
8447 {
8448         DRM_ERROR("Illegal register access in command stream\n");
8449         gfx_v10_0_handle_priv_fault(adev, entry);
8450         return 0;
8451 }
8452
8453 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8454                                    struct amdgpu_irq_src *source,
8455                                    struct amdgpu_iv_entry *entry)
8456 {
8457         DRM_ERROR("Illegal instruction in command stream\n");
8458         gfx_v10_0_handle_priv_fault(adev, entry);
8459         return 0;
8460 }
8461
8462 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8463                                              struct amdgpu_irq_src *src,
8464                                              unsigned int type,
8465                                              enum amdgpu_interrupt_state state)
8466 {
8467         uint32_t tmp, target;
8468         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8469
8470         if (ring->me == 1)
8471                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8472         else
8473                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8474         target += ring->pipe;
8475
8476         switch (type) {
8477         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8478                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8479                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8480                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8481                                             GENERIC2_INT_ENABLE, 0);
8482                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8483
8484                         tmp = RREG32(target);
8485                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8486                                             GENERIC2_INT_ENABLE, 0);
8487                         WREG32(target, tmp);
8488                 } else {
8489                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8490                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8491                                             GENERIC2_INT_ENABLE, 1);
8492                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8493
8494                         tmp = RREG32(target);
8495                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8496                                             GENERIC2_INT_ENABLE, 1);
8497                         WREG32(target, tmp);
8498                 }
8499                 break;
8500         default:
8501                 BUG(); /* kiq only support GENERIC2_INT now */
8502                 break;
8503         }
8504         return 0;
8505 }
8506
8507 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8508                              struct amdgpu_irq_src *source,
8509                              struct amdgpu_iv_entry *entry)
8510 {
8511         u8 me_id, pipe_id, queue_id;
8512         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8513
8514         me_id = (entry->ring_id & 0x0c) >> 2;
8515         pipe_id = (entry->ring_id & 0x03) >> 0;
8516         queue_id = (entry->ring_id & 0x70) >> 4;
8517         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8518                    me_id, pipe_id, queue_id);
8519
8520         amdgpu_fence_process(ring);
8521         return 0;
8522 }
8523
8524 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8525 {
8526         const unsigned int gcr_cntl =
8527                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8528                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8529                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8530                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8531                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8532                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8533                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8534                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8535
8536         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8537         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8538         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8539         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8540         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8541         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8542         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8543         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8544         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8545 }
8546
8547 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8548         .name = "gfx_v10_0",
8549         .early_init = gfx_v10_0_early_init,
8550         .late_init = gfx_v10_0_late_init,
8551         .sw_init = gfx_v10_0_sw_init,
8552         .sw_fini = gfx_v10_0_sw_fini,
8553         .hw_init = gfx_v10_0_hw_init,
8554         .hw_fini = gfx_v10_0_hw_fini,
8555         .suspend = gfx_v10_0_suspend,
8556         .resume = gfx_v10_0_resume,
8557         .is_idle = gfx_v10_0_is_idle,
8558         .wait_for_idle = gfx_v10_0_wait_for_idle,
8559         .soft_reset = gfx_v10_0_soft_reset,
8560         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8561         .set_powergating_state = gfx_v10_0_set_powergating_state,
8562         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8563 };
8564
8565 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8566         .type = AMDGPU_RING_TYPE_GFX,
8567         .align_mask = 0xff,
8568         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8569         .support_64bit_ptrs = true,
8570         .vmhub = AMDGPU_GFXHUB_0,
8571         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8572         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8573         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8574         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8575                 5 + /* COND_EXEC */
8576                 7 + /* PIPELINE_SYNC */
8577                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8578                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8579                 2 + /* VM_FLUSH */
8580                 8 + /* FENCE for VM_FLUSH */
8581                 20 + /* GDS switch */
8582                 4 + /* double SWITCH_BUFFER,
8583                      * the first COND_EXEC jump to the place
8584                      * just prior to this double SWITCH_BUFFER
8585                      */
8586                 5 + /* COND_EXEC */
8587                 7 + /* HDP_flush */
8588                 4 + /* VGT_flush */
8589                 14 + /* CE_META */
8590                 31 + /* DE_META */
8591                 3 + /* CNTX_CTRL */
8592                 5 + /* HDP_INVL */
8593                 8 + 8 + /* FENCE x2 */
8594                 2 + /* SWITCH_BUFFER */
8595                 8, /* gfx_v10_0_emit_mem_sync */
8596         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8597         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8598         .emit_fence = gfx_v10_0_ring_emit_fence,
8599         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8600         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8601         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8602         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8603         .test_ring = gfx_v10_0_ring_test_ring,
8604         .test_ib = gfx_v10_0_ring_test_ib,
8605         .insert_nop = amdgpu_ring_insert_nop,
8606         .pad_ib = amdgpu_ring_generic_pad_ib,
8607         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8608         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8609         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8610         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8611         .preempt_ib = gfx_v10_0_ring_preempt_ib,
8612         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8613         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8614         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8615         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8616         .soft_recovery = gfx_v10_0_ring_soft_recovery,
8617         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8618 };
8619
8620 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8621         .type = AMDGPU_RING_TYPE_COMPUTE,
8622         .align_mask = 0xff,
8623         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8624         .support_64bit_ptrs = true,
8625         .vmhub = AMDGPU_GFXHUB_0,
8626         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8627         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8628         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8629         .emit_frame_size =
8630                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8631                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8632                 5 + /* hdp invalidate */
8633                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8634                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8635                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8636                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8637                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8638                 8, /* gfx_v10_0_emit_mem_sync */
8639         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8640         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8641         .emit_fence = gfx_v10_0_ring_emit_fence,
8642         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8643         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8644         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8645         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8646         .test_ring = gfx_v10_0_ring_test_ring,
8647         .test_ib = gfx_v10_0_ring_test_ib,
8648         .insert_nop = amdgpu_ring_insert_nop,
8649         .pad_ib = amdgpu_ring_generic_pad_ib,
8650         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8651         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8652         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8653         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8654 };
8655
8656 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8657         .type = AMDGPU_RING_TYPE_KIQ,
8658         .align_mask = 0xff,
8659         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8660         .support_64bit_ptrs = true,
8661         .vmhub = AMDGPU_GFXHUB_0,
8662         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8663         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8664         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8665         .emit_frame_size =
8666                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8667                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8668                 5 + /*hdp invalidate */
8669                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8670                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8671                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8672                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8673                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8674         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8675         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8676         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8677         .test_ring = gfx_v10_0_ring_test_ring,
8678         .test_ib = gfx_v10_0_ring_test_ib,
8679         .insert_nop = amdgpu_ring_insert_nop,
8680         .pad_ib = amdgpu_ring_generic_pad_ib,
8681         .emit_rreg = gfx_v10_0_ring_emit_rreg,
8682         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8683         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8684         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8685 };
8686
8687 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8688 {
8689         int i;
8690
8691         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
8692
8693         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
8694                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
8695
8696         for (i = 0; i < adev->gfx.num_compute_rings; i++)
8697                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
8698 }
8699
8700 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
8701         .set = gfx_v10_0_set_eop_interrupt_state,
8702         .process = gfx_v10_0_eop_irq,
8703 };
8704
8705 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
8706         .set = gfx_v10_0_set_priv_reg_fault_state,
8707         .process = gfx_v10_0_priv_reg_irq,
8708 };
8709
8710 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
8711         .set = gfx_v10_0_set_priv_inst_fault_state,
8712         .process = gfx_v10_0_priv_inst_irq,
8713 };
8714
8715 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
8716         .set = gfx_v10_0_kiq_set_interrupt_state,
8717         .process = gfx_v10_0_kiq_irq,
8718 };
8719
8720 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
8721 {
8722         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
8723         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
8724
8725         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
8726         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
8727
8728         adev->gfx.priv_reg_irq.num_types = 1;
8729         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
8730
8731         adev->gfx.priv_inst_irq.num_types = 1;
8732         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
8733 }
8734
8735 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
8736 {
8737         switch (adev->asic_type) {
8738         case CHIP_NAVI10:
8739         case CHIP_NAVI14:
8740         case CHIP_SIENNA_CICHLID:
8741         case CHIP_NAVY_FLOUNDER:
8742                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
8743                 break;
8744         case CHIP_NAVI12:
8745                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
8746                 break;
8747         default:
8748                 break;
8749         }
8750 }
8751
8752 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
8753 {
8754         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
8755                             adev->gfx.config.max_sh_per_se *
8756                             adev->gfx.config.max_shader_engines;
8757
8758         adev->gds.gds_size = 0x10000;
8759         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
8760         adev->gds.gws_size = 64;
8761         adev->gds.oa_size = 16;
8762 }
8763
8764 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
8765                                                           u32 bitmap)
8766 {
8767         u32 data;
8768
8769         if (!bitmap)
8770                 return;
8771
8772         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8773         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8774
8775         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
8776 }
8777
8778 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
8779 {
8780         u32 data, wgp_bitmask;
8781         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
8782         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
8783
8784         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8785         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8786
8787         wgp_bitmask =
8788                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
8789
8790         return (~data) & wgp_bitmask;
8791 }
8792
8793 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
8794 {
8795         u32 wgp_idx, wgp_active_bitmap;
8796         u32 cu_bitmap_per_wgp, cu_active_bitmap;
8797
8798         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
8799         cu_active_bitmap = 0;
8800
8801         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
8802                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
8803                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
8804                 if (wgp_active_bitmap & (1 << wgp_idx))
8805                         cu_active_bitmap |= cu_bitmap_per_wgp;
8806         }
8807
8808         return cu_active_bitmap;
8809 }
8810
8811 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
8812                                  struct amdgpu_cu_info *cu_info)
8813 {
8814         int i, j, k, counter, active_cu_number = 0;
8815         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
8816         unsigned disable_masks[4 * 2];
8817
8818         if (!adev || !cu_info)
8819                 return -EINVAL;
8820
8821         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
8822
8823         mutex_lock(&adev->grbm_idx_mutex);
8824         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
8825                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
8826                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
8827                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
8828                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
8829                                 continue;
8830                         mask = 1;
8831                         ao_bitmap = 0;
8832                         counter = 0;
8833                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
8834                         if (i < 4 && j < 2)
8835                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
8836                                         adev, disable_masks[i * 2 + j]);
8837                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
8838                         cu_info->bitmap[i][j] = bitmap;
8839
8840                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
8841                                 if (bitmap & mask) {
8842                                         if (counter < adev->gfx.config.max_cu_per_sh)
8843                                                 ao_bitmap |= mask;
8844                                         counter++;
8845                                 }
8846                                 mask <<= 1;
8847                         }
8848                         active_cu_number += counter;
8849                         if (i < 2 && j < 2)
8850                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
8851                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
8852                 }
8853         }
8854         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
8855         mutex_unlock(&adev->grbm_idx_mutex);
8856
8857         cu_info->number = active_cu_number;
8858         cu_info->ao_cu_mask = ao_cu_mask;
8859         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
8860
8861         return 0;
8862 }
8863
8864 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
8865 {
8866         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
8867
8868         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
8869         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
8870         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
8871
8872         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
8873         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
8874         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
8875
8876         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
8877                                                 adev->gfx.config.max_shader_engines);
8878         disabled_sa = efuse_setting | vbios_setting;
8879         disabled_sa &= max_sa_mask;
8880
8881         return disabled_sa;
8882 }
8883
8884 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
8885 {
8886         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
8887         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
8888
8889         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
8890
8891         max_sa_per_se = adev->gfx.config.max_sh_per_se;
8892         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
8893         max_shader_engines = adev->gfx.config.max_shader_engines;
8894
8895         for (se_index = 0; max_shader_engines > se_index; se_index++) {
8896                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
8897                 disabled_sa_per_se &= max_sa_per_se_mask;
8898                 if (disabled_sa_per_se == max_sa_per_se_mask) {
8899                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
8900                         break;
8901                 }
8902         }
8903 }
8904
8905 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
8906 {
8907         .type = AMD_IP_BLOCK_TYPE_GFX,
8908         .major = 10,
8909         .minor = 0,
8910         .rev = 0,
8911         .funcs = &gfx_v10_0_ip_funcs,
8912 };