2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include <linux/firmware.h>
32 #include <linux/crc32.h>
36 #include "i915_pvinfo.h"
38 #define FIRMWARE_VERSION (0x0)
40 struct gvt_firmware_header {
42 u32 crc32; /* protect the data after this field */
45 u64 cfg_space_offset; /* offset in the file */
47 u64 mmio_offset; /* offset in the file */
48 unsigned char data[1];
51 #define RD(offset) (readl(mmio + offset.reg))
52 #define WR(v, offset) (writel(v, mmio + offset.reg))
54 static void bdw_forcewake_get(void __iomem *mmio)
56 WR(_MASKED_BIT_DISABLE(0xffff), FORCEWAKE_MT);
60 if (wait_for((RD(FORCEWAKE_ACK_HSW) & FORCEWAKE_KERNEL) == 0, 50))
61 gvt_err("fail to wait forcewake idle\n");
63 WR(_MASKED_BIT_ENABLE(FORCEWAKE_KERNEL), FORCEWAKE_MT);
65 if (wait_for((RD(FORCEWAKE_ACK_HSW) & FORCEWAKE_KERNEL), 50))
66 gvt_err("fail to wait forcewake ack\n");
68 if (wait_for((RD(GEN6_GT_THREAD_STATUS_REG) &
69 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 50))
70 gvt_err("fail to wait c0 wake up\n");
76 #define dev_to_drm_minor(d) dev_get_drvdata((d))
79 gvt_firmware_read(struct file *filp, struct kobject *kobj,
80 struct bin_attribute *attr, char *buf,
81 loff_t offset, size_t count)
83 memcpy(buf, attr->private + offset, count);
87 static struct bin_attribute firmware_attr = {
88 .attr = {.name = "gvt_firmware", .mode = (S_IRUSR)},
89 .read = gvt_firmware_read,
94 static int expose_firmware_sysfs(struct intel_gvt *gvt,
97 struct intel_gvt_device_info *info = &gvt->device_info;
98 struct pci_dev *pdev = gvt->dev_priv->drm.pdev;
99 struct intel_gvt_mmio_info *e;
100 struct gvt_firmware_header *h;
107 size = sizeof(*h) + info->mmio_size + info->cfg_space_size - 1;
108 firmware = vmalloc(size);
114 h->magic = VGT_MAGIC;
115 h->version = FIRMWARE_VERSION;
116 h->cfg_space_size = info->cfg_space_size;
117 h->cfg_space_offset = offsetof(struct gvt_firmware_header, data);
118 h->mmio_size = info->mmio_size;
119 h->mmio_offset = h->cfg_space_offset + h->cfg_space_size;
121 p = firmware + h->cfg_space_offset;
123 for (i = 0; i < h->cfg_space_size; i += 4)
124 pci_read_config_dword(pdev, i, p + i);
126 memcpy(gvt->firmware.cfg_space, p, info->cfg_space_size);
128 p = firmware + h->mmio_offset;
130 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) {
133 for (j = 0; j < e->length; j += 4)
134 *(u32 *)(p + e->offset + j) =
135 readl(mmio + e->offset + j);
138 memcpy(gvt->firmware.mmio, p, info->mmio_size);
140 firmware_attr.size = size;
141 firmware_attr.private = firmware;
143 ret = device_create_bin_file(&pdev->dev, &firmware_attr);
151 static void clean_firmware_sysfs(struct intel_gvt *gvt)
153 struct pci_dev *pdev = gvt->dev_priv->drm.pdev;
155 device_remove_bin_file(&pdev->dev, &firmware_attr);
156 vfree(firmware_attr.private);
160 * intel_gvt_free_firmware - free GVT firmware
161 * @gvt: intel gvt device
164 void intel_gvt_free_firmware(struct intel_gvt *gvt)
166 if (!gvt->firmware.firmware_loaded)
167 clean_firmware_sysfs(gvt);
169 kfree(gvt->firmware.cfg_space);
170 kfree(gvt->firmware.mmio);
173 static int verify_firmware(struct intel_gvt *gvt,
174 const struct firmware *fw)
176 struct intel_gvt_device_info *info = &gvt->device_info;
177 struct drm_i915_private *dev_priv = gvt->dev_priv;
178 struct pci_dev *pdev = dev_priv->drm.pdev;
179 struct gvt_firmware_header *h;
180 unsigned long id, crc32_start;
185 h = (struct gvt_firmware_header *)fw->data;
187 crc32_start = offsetof(struct gvt_firmware_header, crc32) + 4;
188 mem = fw->data + crc32_start;
190 #define VERIFY(s, a, b) do { \
191 item = (s); file = (u64)(a); request = (u64)(b); \
193 goto invalid_firmware; \
196 VERIFY("magic number", h->magic, VGT_MAGIC);
197 VERIFY("version", h->version, FIRMWARE_VERSION);
198 VERIFY("crc32", h->crc32, crc32_le(0, mem, fw->size - crc32_start));
199 VERIFY("cfg space size", h->cfg_space_size, info->cfg_space_size);
200 VERIFY("mmio size", h->mmio_size, info->mmio_size);
202 mem = (fw->data + h->cfg_space_offset);
204 id = *(u16 *)(mem + PCI_VENDOR_ID);
205 VERIFY("vender id", id, pdev->vendor);
207 id = *(u16 *)(mem + PCI_DEVICE_ID);
208 VERIFY("device id", id, pdev->device);
210 id = *(u8 *)(mem + PCI_REVISION_ID);
211 VERIFY("revision id", id, pdev->revision);
217 gvt_dbg_core("Invalid firmware: %s [file] 0x%llx [request] 0x%llx\n",
218 item, file, request);
222 #define GVT_FIRMWARE_PATH "i915/gvt"
225 * intel_gvt_load_firmware - load GVT firmware
226 * @gvt: intel gvt device
229 int intel_gvt_load_firmware(struct intel_gvt *gvt)
231 struct intel_gvt_device_info *info = &gvt->device_info;
232 struct drm_i915_private *dev_priv = gvt->dev_priv;
233 struct pci_dev *pdev = dev_priv->drm.pdev;
234 struct intel_gvt_firmware *firmware = &gvt->firmware;
235 struct gvt_firmware_header *h;
236 const struct firmware *fw;
242 path = kmalloc(PATH_MAX, GFP_KERNEL);
246 mem = kmalloc(info->cfg_space_size, GFP_KERNEL);
252 firmware->cfg_space = mem;
254 mem = kmalloc(info->mmio_size, GFP_KERNEL);
257 kfree(firmware->cfg_space);
261 firmware->mmio = mem;
263 mmio = pci_iomap(pdev, info->mmio_bar, info->mmio_size);
266 kfree(firmware->cfg_space);
267 kfree(firmware->mmio);
271 if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv))
272 bdw_forcewake_get(mmio);
274 sprintf(path, "%s/vid_0x%04x_did_0x%04x_rid_0x%04x.golden_hw_state",
275 GVT_FIRMWARE_PATH, pdev->vendor, pdev->device,
278 gvt_dbg_core("request hw state firmware %s...\n", path);
280 ret = request_firmware(&fw, path, &dev_priv->drm.pdev->dev);
284 goto expose_firmware;
286 gvt_dbg_core("success.\n");
288 ret = verify_firmware(gvt, fw);
292 gvt_dbg_core("verified.\n");
294 h = (struct gvt_firmware_header *)fw->data;
296 memcpy(firmware->cfg_space, fw->data + h->cfg_space_offset,
298 memcpy(firmware->mmio, fw->data + h->mmio_offset,
301 release_firmware(fw);
302 firmware->firmware_loaded = true;
303 pci_iounmap(pdev, mmio);
307 release_firmware(fw);
309 expose_firmware_sysfs(gvt, mmio);
310 pci_iounmap(pdev, mmio);