drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/power_supply.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34
  35
  36 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  37
  38 static const struct cg_flag_name clocks[] = {
  39         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  40         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  41         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  42         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  43         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  46         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  49         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  50         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  51         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  52         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  55         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  56         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  58         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  61         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  63         {0, NULL},
  64 };
  65
  66 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  67 {
  68         if (adev->pm.dpm_enabled) {
  69                 mutex_lock(&adev->pm.mutex);
  70                 if (power_supply_is_system_supplied() > 0)
  71                         adev->pm.dpm.ac_power = true;
  72                 else
  73                         adev->pm.dpm.ac_power = false;
  74                 if (adev->powerplay.pp_funcs->enable_bapm)
  75                         amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
  76                 mutex_unlock(&adev->pm.mutex);
  77         }
  78 }
  79
  80 static ssize_t amdgpu_get_dpm_state(struct device *dev,
  81                                     struct device_attribute *attr,
  82                                     char *buf)
  83 {
  84         struct drm_device *ddev = dev_get_drvdata(dev);
  85         struct amdgpu_device *adev = ddev->dev_private;
  86         enum amd_pm_state_type pm;
  87
  88         if (adev->powerplay.pp_funcs->get_current_power_state)
  89                 pm = amdgpu_dpm_get_current_power_state(adev);
  90         else
  91                 pm = adev->pm.dpm.user_state;
  92
  93         return snprintf(buf, PAGE_SIZE, "%s\n",
  94                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
  95                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
  96 }
  97
  98 static ssize_t amdgpu_set_dpm_state(struct device *dev,
  99                                     struct device_attribute *attr,
 100                                     const char *buf,
 101                                     size_t count)
 102 {
 103         struct drm_device *ddev = dev_get_drvdata(dev);
 104         struct amdgpu_device *adev = ddev->dev_private;
 105         enum amd_pm_state_type  state;
 106
 107         if (strncmp("battery", buf, strlen("battery")) == 0)
 108                 state = POWER_STATE_TYPE_BATTERY;
 109         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 110                 state = POWER_STATE_TYPE_BALANCED;
 111         else if (strncmp("performance", buf, strlen("performance")) == 0)
 112                 state = POWER_STATE_TYPE_PERFORMANCE;
 113         else {
 114                 count = -EINVAL;
 115                 goto fail;
 116         }
 117
 118         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 119                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 120         } else {
 121                 mutex_lock(&adev->pm.mutex);
 122                 adev->pm.dpm.user_state = state;
 123                 mutex_unlock(&adev->pm.mutex);
 124
 125                 /* Can't set dpm state when the card is off */
 126                 if (!(adev->flags & AMD_IS_PX) ||
 127                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 128                         amdgpu_pm_compute_clocks(adev);
 129         }
 130 fail:
 131         return count;
 132 }
 133
 134 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 135                                                 struct device_attribute *attr,
 136                                                                 char *buf)
 137 {
 138         struct drm_device *ddev = dev_get_drvdata(dev);
 139         struct amdgpu_device *adev = ddev->dev_private;
 140         enum amd_dpm_forced_level level = 0xff;
 141
 142         if  ((adev->flags & AMD_IS_PX) &&
 143              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 144                 return snprintf(buf, PAGE_SIZE, "off\n");
 145
 146         if (adev->powerplay.pp_funcs->get_performance_level)
 147                 level = amdgpu_dpm_get_performance_level(adev);
 148         else
 149                 level = adev->pm.dpm.forced_level;
 150
 151         return snprintf(buf, PAGE_SIZE, "%s\n",
 152                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 153                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 154                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 155                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 156                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 157                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 158                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 159                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 160                         "unknown");
 161 }
 162
 163 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 164                                                        struct device_attribute *attr,
 165                                                        const char *buf,
 166                                                        size_t count)
 167 {
 168         struct drm_device *ddev = dev_get_drvdata(dev);
 169         struct amdgpu_device *adev = ddev->dev_private;
 170         enum amd_dpm_forced_level level;
 171         enum amd_dpm_forced_level current_level = 0xff;
 172         int ret = 0;
 173
 174         /* Can't force performance level when the card is off */
 175         if  ((adev->flags & AMD_IS_PX) &&
 176              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 177                 return -EINVAL;
 178
 179         if (adev->powerplay.pp_funcs->get_performance_level)
 180                 current_level = amdgpu_dpm_get_performance_level(adev);
 181
 182         if (strncmp("low", buf, strlen("low")) == 0) {
 183                 level = AMD_DPM_FORCED_LEVEL_LOW;
 184         } else if (strncmp("high", buf, strlen("high")) == 0) {
 185                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 186         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 187                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 188         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 189                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 190         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 191                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 192         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 193                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 194         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 195                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 196         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 197                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 198         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 199                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 200         }  else {
 201                 count = -EINVAL;
 202                 goto fail;
 203         }
 204
 205         if (current_level == level)
 206                 return count;
 207
 208         if (adev->powerplay.pp_funcs->force_performance_level) {
 209                 mutex_lock(&adev->pm.mutex);
 210                 if (adev->pm.dpm.thermal_active) {
 211                         count = -EINVAL;
 212                         mutex_unlock(&adev->pm.mutex);
 213                         goto fail;
 214                 }
 215                 ret = amdgpu_dpm_force_performance_level(adev, level);
 216                 if (ret)
 217                         count = -EINVAL;
 218                 else
 219                         adev->pm.dpm.forced_level = level;
 220                 mutex_unlock(&adev->pm.mutex);
 221         }
 222
 223 fail:
 224         return count;
 225 }
 226
 227 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 228                 struct device_attribute *attr,
 229                 char *buf)
 230 {
 231         struct drm_device *ddev = dev_get_drvdata(dev);
 232         struct amdgpu_device *adev = ddev->dev_private;
 233         struct pp_states_info data;
 234         int i, buf_len;
 235
 236         if (adev->powerplay.pp_funcs->get_pp_num_states)
 237                 amdgpu_dpm_get_pp_num_states(adev, &data);
 238
 239         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 240         for (i = 0; i < data.nums; i++)
 241                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 242                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 243                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 244                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 245                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 246
 247         return buf_len;
 248 }
 249
 250 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 251                 struct device_attribute *attr,
 252                 char *buf)
 253 {
 254         struct drm_device *ddev = dev_get_drvdata(dev);
 255         struct amdgpu_device *adev = ddev->dev_private;
 256         struct pp_states_info data;
 257         enum amd_pm_state_type pm = 0;
 258         int i = 0;
 259
 260         if (adev->powerplay.pp_funcs->get_current_power_state
 261                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 262                 pm = amdgpu_dpm_get_current_power_state(adev);
 263                 amdgpu_dpm_get_pp_num_states(adev, &data);
 264
 265                 for (i = 0; i < data.nums; i++) {
 266                         if (pm == data.states[i])
 267                                 break;
 268                 }
 269
 270                 if (i == data.nums)
 271                         i = -EINVAL;
 272         }
 273
 274         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 275 }
 276
 277 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 278                 struct device_attribute *attr,
 279                 char *buf)
 280 {
 281         struct drm_device *ddev = dev_get_drvdata(dev);
 282         struct amdgpu_device *adev = ddev->dev_private;
 283
 284         if (adev->pp_force_state_enabled)
 285                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 286         else
 287                 return snprintf(buf, PAGE_SIZE, "\n");
 288 }
 289
 290 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 291                 struct device_attribute *attr,
 292                 const char *buf,
 293                 size_t count)
 294 {
 295         struct drm_device *ddev = dev_get_drvdata(dev);
 296         struct amdgpu_device *adev = ddev->dev_private;
 297         enum amd_pm_state_type state = 0;
 298         unsigned long idx;
 299         int ret;
 300
 301         if (strlen(buf) == 1)
 302                 adev->pp_force_state_enabled = false;
 303         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 304                         adev->powerplay.pp_funcs->get_pp_num_states) {
 305                 struct pp_states_info data;
 306
 307                 ret = kstrtoul(buf, 0, &idx);
 308                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 309                         count = -EINVAL;
 310                         goto fail;
 311                 }
 312
 313                 amdgpu_dpm_get_pp_num_states(adev, &data);
 314                 state = data.states[idx];
 315                 /* only set user selected power states */
 316                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 317                     state != POWER_STATE_TYPE_DEFAULT) {
 318                         amdgpu_dpm_dispatch_task(adev,
 319                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 320                         adev->pp_force_state_enabled = true;
 321                 }
 322         }
 323 fail:
 324         return count;
 325 }
 326
 327 static ssize_t amdgpu_get_pp_table(struct device *dev,
 328                 struct device_attribute *attr,
 329                 char *buf)
 330 {
 331         struct drm_device *ddev = dev_get_drvdata(dev);
 332         struct amdgpu_device *adev = ddev->dev_private;
 333         char *table = NULL;
 334         int size;
 335
 336         if (adev->powerplay.pp_funcs->get_pp_table)
 337                 size = amdgpu_dpm_get_pp_table(adev, &table);
 338         else
 339                 return 0;
 340
 341         if (size >= PAGE_SIZE)
 342                 size = PAGE_SIZE - 1;
 343
 344         memcpy(buf, table, size);
 345
 346         return size;
 347 }
 348
 349 static ssize_t amdgpu_set_pp_table(struct device *dev,
 350                 struct device_attribute *attr,
 351                 const char *buf,
 352                 size_t count)
 353 {
 354         struct drm_device *ddev = dev_get_drvdata(dev);
 355         struct amdgpu_device *adev = ddev->dev_private;
 356
 357         if (adev->powerplay.pp_funcs->set_pp_table)
 358                 amdgpu_dpm_set_pp_table(adev, buf, count);
 359
 360         return count;
 361 }
 362
 363 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 364                 struct device_attribute *attr,
 365                 const char *buf,
 366                 size_t count)
 367 {
 368         struct drm_device *ddev = dev_get_drvdata(dev);
 369         struct amdgpu_device *adev = ddev->dev_private;
 370         int ret;
 371         uint32_t parameter_size = 0;
 372         long parameter[64];
 373         char buf_cpy[128];
 374         char *tmp_str;
 375         char *sub_str;
 376         const char delimiter[3] = {' ', '\n', '\0'};
 377         uint32_t type;
 378
 379         if (count > 127)
 380                 return -EINVAL;
 381
 382         if (*buf == 's')
 383                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 384         else if (*buf == 'm')
 385                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 386         else if(*buf == 'r')
 387                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 388         else if (*buf == 'c')
 389                 type = PP_OD_COMMIT_DPM_TABLE;
 390         else
 391                 return -EINVAL;
 392
 393         memcpy(buf_cpy, buf, count+1);
 394
 395         tmp_str = buf_cpy;
 396
 397         while (isspace(*++tmp_str));
 398
 399         while (tmp_str[0]) {
 400                 sub_str = strsep(&tmp_str, delimiter);
 401                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 402                 if (ret)
 403                         return -EINVAL;
 404                 parameter_size++;
 405
 406                 while (isspace(*tmp_str))
 407                         tmp_str++;
 408         }
 409
 410         if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 411                 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 412                                                 parameter, parameter_size);
 413
 414         if (ret)
 415                 return -EINVAL;
 416
 417         if (type == PP_OD_COMMIT_DPM_TABLE) {
 418                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
 419                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 420                         return count;
 421                 } else {
 422                         return -EINVAL;
 423                 }
 424         }
 425
 426         return count;
 427 }
 428
 429 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 430                 struct device_attribute *attr,
 431                 char *buf)
 432 {
 433         struct drm_device *ddev = dev_get_drvdata(dev);
 434         struct amdgpu_device *adev = ddev->dev_private;
 435         uint32_t size = 0;
 436
 437         if (adev->powerplay.pp_funcs->print_clock_levels) {
 438                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 439                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 440                 return size;
 441         } else {
 442                 return snprintf(buf, PAGE_SIZE, "\n");
 443         }
 444
 445 }
 446
 447 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 448                 struct device_attribute *attr,
 449                 char *buf)
 450 {
 451         struct drm_device *ddev = dev_get_drvdata(dev);
 452         struct amdgpu_device *adev = ddev->dev_private;
 453
 454         if (adev->powerplay.pp_funcs->print_clock_levels)
 455                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 456         else
 457                 return snprintf(buf, PAGE_SIZE, "\n");
 458 }
 459
 460 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 461                 struct device_attribute *attr,
 462                 const char *buf,
 463                 size_t count)
 464 {
 465         struct drm_device *ddev = dev_get_drvdata(dev);
 466         struct amdgpu_device *adev = ddev->dev_private;
 467         int ret;
 468         long level;
 469         uint32_t i, mask = 0;
 470         char sub_str[2];
 471
 472         for (i = 0; i < strlen(buf); i++) {
 473                 if (*(buf + i) == '\n')
 474                         continue;
 475                 sub_str[0] = *(buf + i);
 476                 sub_str[1] = '\0';
 477                 ret = kstrtol(sub_str, 0, &level);
 478
 479                 if (ret) {
 480                         count = -EINVAL;
 481                         goto fail;
 482                 }
 483                 mask |= 1 << level;
 484         }
 485
 486         if (adev->powerplay.pp_funcs->force_clock_level)
 487                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 488
 489 fail:
 490         return count;
 491 }
 492
 493 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 494                 struct device_attribute *attr,
 495                 char *buf)
 496 {
 497         struct drm_device *ddev = dev_get_drvdata(dev);
 498         struct amdgpu_device *adev = ddev->dev_private;
 499
 500         if (adev->powerplay.pp_funcs->print_clock_levels)
 501                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 502         else
 503                 return snprintf(buf, PAGE_SIZE, "\n");
 504 }
 505
 506 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 507                 struct device_attribute *attr,
 508                 const char *buf,
 509                 size_t count)
 510 {
 511         struct drm_device *ddev = dev_get_drvdata(dev);
 512         struct amdgpu_device *adev = ddev->dev_private;
 513         int ret;
 514         long level;
 515         uint32_t i, mask = 0;
 516         char sub_str[2];
 517
 518         for (i = 0; i < strlen(buf); i++) {
 519                 if (*(buf + i) == '\n')
 520                         continue;
 521                 sub_str[0] = *(buf + i);
 522                 sub_str[1] = '\0';
 523                 ret = kstrtol(sub_str, 0, &level);
 524
 525                 if (ret) {
 526                         count = -EINVAL;
 527                         goto fail;
 528                 }
 529                 mask |= 1 << level;
 530         }
 531         if (adev->powerplay.pp_funcs->force_clock_level)
 532                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 533
 534 fail:
 535         return count;
 536 }
 537
 538 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 539                 struct device_attribute *attr,
 540                 char *buf)
 541 {
 542         struct drm_device *ddev = dev_get_drvdata(dev);
 543         struct amdgpu_device *adev = ddev->dev_private;
 544
 545         if (adev->powerplay.pp_funcs->print_clock_levels)
 546                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 547         else
 548                 return snprintf(buf, PAGE_SIZE, "\n");
 549 }
 550
 551 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 552                 struct device_attribute *attr,
 553                 const char *buf,
 554                 size_t count)
 555 {
 556         struct drm_device *ddev = dev_get_drvdata(dev);
 557         struct amdgpu_device *adev = ddev->dev_private;
 558         int ret;
 559         long level;
 560         uint32_t i, mask = 0;
 561         char sub_str[2];
 562
 563         for (i = 0; i < strlen(buf); i++) {
 564                 if (*(buf + i) == '\n')
 565                         continue;
 566                 sub_str[0] = *(buf + i);
 567                 sub_str[1] = '\0';
 568                 ret = kstrtol(sub_str, 0, &level);
 569
 570                 if (ret) {
 571                         count = -EINVAL;
 572                         goto fail;
 573                 }
 574                 mask |= 1 << level;
 575         }
 576         if (adev->powerplay.pp_funcs->force_clock_level)
 577                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 578
 579 fail:
 580         return count;
 581 }
 582
 583 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
 584                 struct device_attribute *attr,
 585                 char *buf)
 586 {
 587         struct drm_device *ddev = dev_get_drvdata(dev);
 588         struct amdgpu_device *adev = ddev->dev_private;
 589         uint32_t value = 0;
 590
 591         if (adev->powerplay.pp_funcs->get_sclk_od)
 592                 value = amdgpu_dpm_get_sclk_od(adev);
 593
 594         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 595 }
 596
 597 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
 598                 struct device_attribute *attr,
 599                 const char *buf,
 600                 size_t count)
 601 {
 602         struct drm_device *ddev = dev_get_drvdata(dev);
 603         struct amdgpu_device *adev = ddev->dev_private;
 604         int ret;
 605         long int value;
 606
 607         ret = kstrtol(buf, 0, &value);
 608
 609         if (ret) {
 610                 count = -EINVAL;
 611                 goto fail;
 612         }
 613         if (adev->powerplay.pp_funcs->set_sclk_od)
 614                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
 615
 616         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 617                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 618         } else {
 619                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 620                 amdgpu_pm_compute_clocks(adev);
 621         }
 622
 623 fail:
 624         return count;
 625 }
 626
 627 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
 628                 struct device_attribute *attr,
 629                 char *buf)
 630 {
 631         struct drm_device *ddev = dev_get_drvdata(dev);
 632         struct amdgpu_device *adev = ddev->dev_private;
 633         uint32_t value = 0;
 634
 635         if (adev->powerplay.pp_funcs->get_mclk_od)
 636                 value = amdgpu_dpm_get_mclk_od(adev);
 637
 638         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 639 }
 640
 641 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
 642                 struct device_attribute *attr,
 643                 const char *buf,
 644                 size_t count)
 645 {
 646         struct drm_device *ddev = dev_get_drvdata(dev);
 647         struct amdgpu_device *adev = ddev->dev_private;
 648         int ret;
 649         long int value;
 650
 651         ret = kstrtol(buf, 0, &value);
 652
 653         if (ret) {
 654                 count = -EINVAL;
 655                 goto fail;
 656         }
 657         if (adev->powerplay.pp_funcs->set_mclk_od)
 658                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
 659
 660         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 661                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 662         } else {
 663                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 664                 amdgpu_pm_compute_clocks(adev);
 665         }
 666
 667 fail:
 668         return count;
 669 }
 670
 671 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
 672                 struct device_attribute *attr,
 673                 char *buf)
 674 {
 675         struct drm_device *ddev = dev_get_drvdata(dev);
 676         struct amdgpu_device *adev = ddev->dev_private;
 677
 678         if (adev->powerplay.pp_funcs->get_power_profile_mode)
 679                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
 680
 681         return snprintf(buf, PAGE_SIZE, "\n");
 682 }
 683
 684
 685 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
 686                 struct device_attribute *attr,
 687                 const char *buf,
 688                 size_t count)
 689 {
 690         int ret = 0xff;
 691         struct drm_device *ddev = dev_get_drvdata(dev);
 692         struct amdgpu_device *adev = ddev->dev_private;
 693         uint32_t parameter_size = 0;
 694         long parameter[64];
 695         char *sub_str, buf_cpy[128];
 696         char *tmp_str;
 697         uint32_t i = 0;
 698         char tmp[2];
 699         long int profile_mode = 0;
 700         const char delimiter[3] = {' ', '\n', '\0'};
 701
 702         tmp[0] = *(buf);
 703         tmp[1] = '\0';
 704         ret = kstrtol(tmp, 0, &profile_mode);
 705         if (ret)
 706                 goto fail;
 707
 708         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
 709                 if (count < 2 || count > 127)
 710                         return -EINVAL;
 711                 while (isspace(*++buf))
 712                         i++;
 713                 memcpy(buf_cpy, buf, count-i);
 714                 tmp_str = buf_cpy;
 715                 while (tmp_str[0]) {
 716                         sub_str = strsep(&tmp_str, delimiter);
 717                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 718                         if (ret) {
 719                                 count = -EINVAL;
 720                                 goto fail;
 721                         }
 722                         parameter_size++;
 723                         while (isspace(*tmp_str))
 724                                 tmp_str++;
 725                 }
 726         }
 727         parameter[parameter_size] = profile_mode;
 728         if (adev->powerplay.pp_funcs->set_power_profile_mode)
 729                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
 730
 731         if (!ret)
 732                 return count;
 733 fail:
 734         return -EINVAL;
 735 }
 736
 737 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 738 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 739                    amdgpu_get_dpm_forced_performance_level,
 740                    amdgpu_set_dpm_forced_performance_level);
 741 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
 742 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
 743 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
 744                 amdgpu_get_pp_force_state,
 745                 amdgpu_set_pp_force_state);
 746 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
 747                 amdgpu_get_pp_table,
 748                 amdgpu_set_pp_table);
 749 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 750                 amdgpu_get_pp_dpm_sclk,
 751                 amdgpu_set_pp_dpm_sclk);
 752 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
 753                 amdgpu_get_pp_dpm_mclk,
 754                 amdgpu_set_pp_dpm_mclk);
 755 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
 756                 amdgpu_get_pp_dpm_pcie,
 757                 amdgpu_set_pp_dpm_pcie);
 758 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
 759                 amdgpu_get_pp_sclk_od,
 760                 amdgpu_set_pp_sclk_od);
 761 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
 762                 amdgpu_get_pp_mclk_od,
 763                 amdgpu_set_pp_mclk_od);
 764 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
 765                 amdgpu_get_pp_power_profile_mode,
 766                 amdgpu_set_pp_power_profile_mode);
 767 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
 768                 amdgpu_get_pp_od_clk_voltage,
 769                 amdgpu_set_pp_od_clk_voltage);
 770
 771 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 772                                       struct device_attribute *attr,
 773                                       char *buf)
 774 {
 775         struct amdgpu_device *adev = dev_get_drvdata(dev);
 776         struct drm_device *ddev = adev->ddev;
 777         int r, temp, size = sizeof(temp);
 778
 779         /* Can't get temperature when the card is off */
 780         if  ((adev->flags & AMD_IS_PX) &&
 781              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 782                 return -EINVAL;
 783
 784         /* sanity check PP is enabled */
 785         if (!(adev->powerplay.pp_funcs &&
 786               adev->powerplay.pp_funcs->read_sensor))
 787                 return -EINVAL;
 788
 789         /* get the temperature */
 790         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
 791                                    (void *)&temp, &size);
 792         if (r)
 793                 return r;
 794
 795         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 796 }
 797
 798 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
 799                                              struct device_attribute *attr,
 800                                              char *buf)
 801 {
 802         struct amdgpu_device *adev = dev_get_drvdata(dev);
 803         int hyst = to_sensor_dev_attr(attr)->index;
 804         int temp;
 805
 806         if (hyst)
 807                 temp = adev->pm.dpm.thermal.min_temp;
 808         else
 809                 temp = adev->pm.dpm.thermal.max_temp;
 810
 811         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 812 }
 813
 814 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
 815                                             struct device_attribute *attr,
 816                                             char *buf)
 817 {
 818         struct amdgpu_device *adev = dev_get_drvdata(dev);
 819         u32 pwm_mode = 0;
 820
 821         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
 822                 return -EINVAL;
 823
 824         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
 825
 826         return sprintf(buf, "%i\n", pwm_mode);
 827 }
 828
 829 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
 830                                             struct device_attribute *attr,
 831                                             const char *buf,
 832                                             size_t count)
 833 {
 834         struct amdgpu_device *adev = dev_get_drvdata(dev);
 835         int err;
 836         int value;
 837
 838         /* Can't adjust fan when the card is off */
 839         if  ((adev->flags & AMD_IS_PX) &&
 840              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 841                 return -EINVAL;
 842
 843         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
 844                 return -EINVAL;
 845
 846         err = kstrtoint(buf, 10, &value);
 847         if (err)
 848                 return err;
 849
 850         amdgpu_dpm_set_fan_control_mode(adev, value);
 851
 852         return count;
 853 }
 854
 855 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
 856                                          struct device_attribute *attr,
 857                                          char *buf)
 858 {
 859         return sprintf(buf, "%i\n", 0);
 860 }
 861
 862 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
 863                                          struct device_attribute *attr,
 864                                          char *buf)
 865 {
 866         return sprintf(buf, "%i\n", 255);
 867 }
 868
 869 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
 870                                      struct device_attribute *attr,
 871                                      const char *buf, size_t count)
 872 {
 873         struct amdgpu_device *adev = dev_get_drvdata(dev);
 874         int err;
 875         u32 value;
 876
 877         /* Can't adjust fan when the card is off */
 878         if  ((adev->flags & AMD_IS_PX) &&
 879              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 880                 return -EINVAL;
 881
 882         err = kstrtou32(buf, 10, &value);
 883         if (err)
 884                 return err;
 885
 886         value = (value * 100) / 255;
 887
 888         if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
 889                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
 890                 if (err)
 891                         return err;
 892         }
 893
 894         return count;
 895 }
 896
 897 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
 898                                      struct device_attribute *attr,
 899                                      char *buf)
 900 {
 901         struct amdgpu_device *adev = dev_get_drvdata(dev);
 902         int err;
 903         u32 speed = 0;
 904
 905         /* Can't adjust fan when the card is off */
 906         if  ((adev->flags & AMD_IS_PX) &&
 907              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 908                 return -EINVAL;
 909
 910         if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
 911                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
 912                 if (err)
 913                         return err;
 914         }
 915
 916         speed = (speed * 255) / 100;
 917
 918         return sprintf(buf, "%i\n", speed);
 919 }
 920
 921 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
 922                                            struct device_attribute *attr,
 923                                            char *buf)
 924 {
 925         struct amdgpu_device *adev = dev_get_drvdata(dev);
 926         int err;
 927         u32 speed = 0;
 928
 929         /* Can't adjust fan when the card is off */
 930         if  ((adev->flags & AMD_IS_PX) &&
 931              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 932                 return -EINVAL;
 933
 934         if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
 935                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
 936                 if (err)
 937                         return err;
 938         }
 939
 940         return sprintf(buf, "%i\n", speed);
 941 }
 942
 943 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
 944                                         struct device_attribute *attr,
 945                                         char *buf)
 946 {
 947         struct amdgpu_device *adev = dev_get_drvdata(dev);
 948         struct drm_device *ddev = adev->ddev;
 949         u32 vddgfx;
 950         int r, size = sizeof(vddgfx);
 951
 952         /* Can't get voltage when the card is off */
 953         if  ((adev->flags & AMD_IS_PX) &&
 954              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 955                 return -EINVAL;
 956
 957         /* sanity check PP is enabled */
 958         if (!(adev->powerplay.pp_funcs &&
 959               adev->powerplay.pp_funcs->read_sensor))
 960               return -EINVAL;
 961
 962         /* get the voltage */
 963         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
 964                                    (void *)&vddgfx, &size);
 965         if (r)
 966                 return r;
 967
 968         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
 969 }
 970
 971 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
 972                                               struct device_attribute *attr,
 973                                               char *buf)
 974 {
 975         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
 976 }
 977
 978 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
 979                                        struct device_attribute *attr,
 980                                        char *buf)
 981 {
 982         struct amdgpu_device *adev = dev_get_drvdata(dev);
 983         struct drm_device *ddev = adev->ddev;
 984         u32 vddnb;
 985         int r, size = sizeof(vddnb);
 986
 987         /* only APUs have vddnb */
 988         if  (adev->flags & AMD_IS_APU)
 989                 return -EINVAL;
 990
 991         /* Can't get voltage when the card is off */
 992         if  ((adev->flags & AMD_IS_PX) &&
 993              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 994                 return -EINVAL;
 995
 996         /* sanity check PP is enabled */
 997         if (!(adev->powerplay.pp_funcs &&
 998               adev->powerplay.pp_funcs->read_sensor))
 999               return -EINVAL;
1000
1001         /* get the voltage */
1002         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1003                                    (void *)&vddnb, &size);
1004         if (r)
1005                 return r;
1006
1007         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1008 }
1009
1010 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1011                                               struct device_attribute *attr,
1012                                               char *buf)
1013 {
1014         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1015 }
1016
1017 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1018                                            struct device_attribute *attr,
1019                                            char *buf)
1020 {
1021         struct amdgpu_device *adev = dev_get_drvdata(dev);
1022         struct drm_device *ddev = adev->ddev;
1023         u32 query = 0;
1024         int r, size = sizeof(u32);
1025         unsigned uw;
1026
1027         /* Can't get power when the card is off */
1028         if  ((adev->flags & AMD_IS_PX) &&
1029              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1030                 return -EINVAL;
1031
1032         /* sanity check PP is enabled */
1033         if (!(adev->powerplay.pp_funcs &&
1034               adev->powerplay.pp_funcs->read_sensor))
1035               return -EINVAL;
1036
1037         /* get the voltage */
1038         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1039                                    (void *)&query, &size);
1040         if (r)
1041                 return r;
1042
1043         /* convert to microwatts */
1044         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1045
1046         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1047 }
1048
1049 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1050                                          struct device_attribute *attr,
1051                                          char *buf)
1052 {
1053         return sprintf(buf, "%i\n", 0);
1054 }
1055
1056 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1057                                          struct device_attribute *attr,
1058                                          char *buf)
1059 {
1060         struct amdgpu_device *adev = dev_get_drvdata(dev);
1061         uint32_t limit = 0;
1062
1063         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1064                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
1065                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1066         } else {
1067                 return snprintf(buf, PAGE_SIZE, "\n");
1068         }
1069 }
1070
1071 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
1072                                          struct device_attribute *attr,
1073                                          char *buf)
1074 {
1075         struct amdgpu_device *adev = dev_get_drvdata(dev);
1076         uint32_t limit = 0;
1077
1078         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1079                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
1080                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1081         } else {
1082                 return snprintf(buf, PAGE_SIZE, "\n");
1083         }
1084 }
1085
1086
1087 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
1088                 struct device_attribute *attr,
1089                 const char *buf,
1090                 size_t count)
1091 {
1092         struct amdgpu_device *adev = dev_get_drvdata(dev);
1093         int err;
1094         u32 value;
1095
1096         err = kstrtou32(buf, 10, &value);
1097         if (err)
1098                 return err;
1099
1100         value = value / 1000000; /* convert to Watt */
1101         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
1102                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
1103                 if (err)
1104                         return err;
1105         } else {
1106                 return -EINVAL;
1107         }
1108
1109         return count;
1110 }
1111
1112
1113 /**
1114  * DOC: hwmon
1115  *
1116  * The amdgpu driver exposes the following sensor interfaces:
1117  * - GPU temperature (via the on-die sensor)
1118  * - GPU voltage
1119  * - Northbridge voltage (APUs only)
1120  * - GPU power
1121  * - GPU fan
1122  *
1123  * hwmon interfaces for GPU temperature:
1124  * - temp1_input: the on die GPU temperature in millidegrees Celsius
1125  * - temp1_crit: temperature critical max value in millidegrees Celsius
1126  * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1127  *
1128  * hwmon interfaces for GPU voltage:
1129  * - in0_input: the voltage on the GPU in millivolts
1130  * - in1_input: the voltage on the Northbridge in millivolts
1131  *
1132  * hwmon interfaces for GPU power:
1133  * - power1_average: average power used by the GPU in microWatts
1134  * - power1_cap_min: minimum cap supported in microWatts
1135  * - power1_cap_max: maximum cap supported in microWatts
1136  * - power1_cap: selected power cap in microWatts
1137  *
1138  * hwmon interfaces for GPU fan:
1139  * - pwm1: pulse width modulation fan level (0-255)
1140  * - pwm1_enable: pulse width modulation fan control method
1141  *                0: no fan speed control
1142  *                1: manual fan speed control using pwm interface
1143  *                2: automatic fan speed control
1144  * - pwm1_min: pulse width modulation fan control minimum level (0)
1145  * - pwm1_max: pulse width modulation fan control maximum level (255)
1146  * - fan1_input: fan speed in RPM
1147  *
1148  * You can use hwmon tools like sensors to view this information on your system.
1149  *
1150  */
1151
1152 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
1153 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
1154 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
1155 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
1156 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
1157 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
1158 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
1159 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
1160 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
1161 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
1162 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
1163 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
1164 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
1165 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
1166 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
1167 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
1168
1169 static struct attribute *hwmon_attributes[] = {
1170         &sensor_dev_attr_temp1_input.dev_attr.attr,
1171         &sensor_dev_attr_temp1_crit.dev_attr.attr,
1172         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
1173         &sensor_dev_attr_pwm1.dev_attr.attr,
1174         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1175         &sensor_dev_attr_pwm1_min.dev_attr.attr,
1176         &sensor_dev_attr_pwm1_max.dev_attr.attr,
1177         &sensor_dev_attr_fan1_input.dev_attr.attr,
1178         &sensor_dev_attr_in0_input.dev_attr.attr,
1179         &sensor_dev_attr_in0_label.dev_attr.attr,
1180         &sensor_dev_attr_in1_input.dev_attr.attr,
1181         &sensor_dev_attr_in1_label.dev_attr.attr,
1182         &sensor_dev_attr_power1_average.dev_attr.attr,
1183         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
1184         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
1185         &sensor_dev_attr_power1_cap.dev_attr.attr,
1186         NULL
1187 };
1188
1189 static umode_t hwmon_attributes_visible(struct kobject *kobj,
1190                                         struct attribute *attr, int index)
1191 {
1192         struct device *dev = kobj_to_dev(kobj);
1193         struct amdgpu_device *adev = dev_get_drvdata(dev);
1194         umode_t effective_mode = attr->mode;
1195
1196         /* handle non-powerplay limitations */
1197         if (!adev->powerplay.pp_handle) {
1198                 /* Skip fan attributes if fan is not present */
1199                 if (adev->pm.no_fan &&
1200                     (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1201                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1202                      attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1203                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1204                         return 0;
1205                 /* requires powerplay */
1206                 if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr)
1207                         return 0;
1208         }
1209
1210         /* Skip limit attributes if DPM is not enabled */
1211         if (!adev->pm.dpm_enabled &&
1212             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
1213              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
1214              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1215              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1216              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1217              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1218                 return 0;
1219
1220         /* mask fan attributes if we have no bindings for this asic to expose */
1221         if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
1222              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
1223             (!adev->powerplay.pp_funcs->get_fan_control_mode &&
1224              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
1225                 effective_mode &= ~S_IRUGO;
1226
1227         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1228              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
1229             (!adev->powerplay.pp_funcs->set_fan_control_mode &&
1230              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
1231                 effective_mode &= ~S_IWUSR;
1232
1233         if ((adev->flags & AMD_IS_APU) &&
1234             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
1235              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
1236              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
1237                 return 0;
1238
1239         /* hide max/min values if we can't both query and manage the fan */
1240         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1241              !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
1242             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1243              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1244                 return 0;
1245
1246         /* only APUs have vddnb */
1247         if (!(adev->flags & AMD_IS_APU) &&
1248             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
1249              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
1250                 return 0;
1251
1252         return effective_mode;
1253 }
1254
1255 static const struct attribute_group hwmon_attrgroup = {
1256         .attrs = hwmon_attributes,
1257         .is_visible = hwmon_attributes_visible,
1258 };
1259
1260 static const struct attribute_group *hwmon_groups[] = {
1261         &hwmon_attrgroup,
1262         NULL
1263 };
1264
1265 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
1266 {
1267         struct amdgpu_device *adev =
1268                 container_of(work, struct amdgpu_device,
1269                              pm.dpm.thermal.work);
1270         /* switch to the thermal state */
1271         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
1272         int temp, size = sizeof(temp);
1273
1274         if (!adev->pm.dpm_enabled)
1275                 return;
1276
1277         if (adev->powerplay.pp_funcs &&
1278             adev->powerplay.pp_funcs->read_sensor &&
1279             !amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1280                                     (void *)&temp, &size)) {
1281                 if (temp < adev->pm.dpm.thermal.min_temp)
1282                         /* switch back the user state */
1283                         dpm_state = adev->pm.dpm.user_state;
1284         } else {
1285                 if (adev->pm.dpm.thermal.high_to_low)
1286                         /* switch back the user state */
1287                         dpm_state = adev->pm.dpm.user_state;
1288         }
1289         mutex_lock(&adev->pm.mutex);
1290         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
1291                 adev->pm.dpm.thermal_active = true;
1292         else
1293                 adev->pm.dpm.thermal_active = false;
1294         adev->pm.dpm.state = dpm_state;
1295         mutex_unlock(&adev->pm.mutex);
1296
1297         amdgpu_pm_compute_clocks(adev);
1298 }
1299
1300 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
1301                                                      enum amd_pm_state_type dpm_state)
1302 {
1303         int i;
1304         struct amdgpu_ps *ps;
1305         u32 ui_class;
1306         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
1307                 true : false;
1308
1309         /* check if the vblank period is too short to adjust the mclk */
1310         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
1311                 if (amdgpu_dpm_vblank_too_short(adev))
1312                         single_display = false;
1313         }
1314
1315         /* certain older asics have a separare 3D performance state,
1316          * so try that first if the user selected performance
1317          */
1318         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
1319                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
1320         /* balanced states don't exist at the moment */
1321         if (dpm_state == POWER_STATE_TYPE_BALANCED)
1322                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1323
1324 restart_search:
1325         /* Pick the best power state based on current conditions */
1326         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
1327                 ps = &adev->pm.dpm.ps[i];
1328                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
1329                 switch (dpm_state) {
1330                 /* user states */
1331                 case POWER_STATE_TYPE_BATTERY:
1332                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
1333                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1334                                         if (single_display)
1335                                                 return ps;
1336                                 } else
1337                                         return ps;
1338                         }
1339                         break;
1340                 case POWER_STATE_TYPE_BALANCED:
1341                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
1342                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1343                                         if (single_display)
1344                                                 return ps;
1345                                 } else
1346                                         return ps;
1347                         }
1348                         break;
1349                 case POWER_STATE_TYPE_PERFORMANCE:
1350                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
1351                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1352                                         if (single_display)
1353                                                 return ps;
1354                                 } else
1355                                         return ps;
1356                         }
1357                         break;
1358                 /* internal states */
1359                 case POWER_STATE_TYPE_INTERNAL_UVD:
1360                         if (adev->pm.dpm.uvd_ps)
1361                                 return adev->pm.dpm.uvd_ps;
1362                         else
1363                                 break;
1364                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1365                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
1366                                 return ps;
1367                         break;
1368                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1369                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
1370                                 return ps;
1371                         break;
1372                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1373                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
1374                                 return ps;
1375                         break;
1376                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1377                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1378                                 return ps;
1379                         break;
1380                 case POWER_STATE_TYPE_INTERNAL_BOOT:
1381                         return adev->pm.dpm.boot_ps;
1382                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1383                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1384                                 return ps;
1385                         break;
1386                 case POWER_STATE_TYPE_INTERNAL_ACPI:
1387                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1388                                 return ps;
1389                         break;
1390                 case POWER_STATE_TYPE_INTERNAL_ULV:
1391                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1392                                 return ps;
1393                         break;
1394                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1395                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1396                                 return ps;
1397                         break;
1398                 default:
1399                         break;
1400                 }
1401         }
1402         /* use a fallback state if we didn't match */
1403         switch (dpm_state) {
1404         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1405                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1406                 goto restart_search;
1407         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1408         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1409         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1410                 if (adev->pm.dpm.uvd_ps) {
1411                         return adev->pm.dpm.uvd_ps;
1412                 } else {
1413                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1414                         goto restart_search;
1415                 }
1416         case POWER_STATE_TYPE_INTERNAL_THERMAL:
1417                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1418                 goto restart_search;
1419         case POWER_STATE_TYPE_INTERNAL_ACPI:
1420                 dpm_state = POWER_STATE_TYPE_BATTERY;
1421                 goto restart_search;
1422         case POWER_STATE_TYPE_BATTERY:
1423         case POWER_STATE_TYPE_BALANCED:
1424         case POWER_STATE_TYPE_INTERNAL_3DPERF:
1425                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1426                 goto restart_search;
1427         default:
1428                 break;
1429         }
1430
1431         return NULL;
1432 }
1433
1434 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
1435 {
1436         struct amdgpu_ps *ps;
1437         enum amd_pm_state_type dpm_state;
1438         int ret;
1439         bool equal = false;
1440
1441         /* if dpm init failed */
1442         if (!adev->pm.dpm_enabled)
1443                 return;
1444
1445         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1446                 /* add other state override checks here */
1447                 if ((!adev->pm.dpm.thermal_active) &&
1448                     (!adev->pm.dpm.uvd_active))
1449                         adev->pm.dpm.state = adev->pm.dpm.user_state;
1450         }
1451         dpm_state = adev->pm.dpm.state;
1452
1453         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1454         if (ps)
1455                 adev->pm.dpm.requested_ps = ps;
1456         else
1457                 return;
1458
1459         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
1460                 printk("switching from power state:\n");
1461                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1462                 printk("switching to power state:\n");
1463                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1464         }
1465
1466         /* update whether vce is active */
1467         ps->vce_active = adev->pm.dpm.vce_active;
1468         if (adev->powerplay.pp_funcs->display_configuration_changed)
1469                 amdgpu_dpm_display_configuration_changed(adev);
1470
1471         ret = amdgpu_dpm_pre_set_power_state(adev);
1472         if (ret)
1473                 return;
1474
1475         if (adev->powerplay.pp_funcs->check_state_equal) {
1476                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
1477                         equal = false;
1478         }
1479
1480         if (equal)
1481                 return;
1482
1483         amdgpu_dpm_set_power_state(adev);
1484         amdgpu_dpm_post_set_power_state(adev);
1485
1486         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1487         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1488
1489         if (adev->powerplay.pp_funcs->force_performance_level) {
1490                 if (adev->pm.dpm.thermal_active) {
1491                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
1492                         /* force low perf level for thermal */
1493                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
1494                         /* save the user's level */
1495                         adev->pm.dpm.forced_level = level;
1496                 } else {
1497                         /* otherwise, user selected level */
1498                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1499                 }
1500         }
1501 }
1502
1503 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1504 {
1505         if (adev->powerplay.pp_funcs->powergate_uvd) {
1506                 /* enable/disable UVD */
1507                 mutex_lock(&adev->pm.mutex);
1508                 amdgpu_dpm_powergate_uvd(adev, !enable);
1509                 mutex_unlock(&adev->pm.mutex);
1510         } else {
1511                 if (enable) {
1512                         mutex_lock(&adev->pm.mutex);
1513                         adev->pm.dpm.uvd_active = true;
1514                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1515                         mutex_unlock(&adev->pm.mutex);
1516                 } else {
1517                         mutex_lock(&adev->pm.mutex);
1518                         adev->pm.dpm.uvd_active = false;
1519                         mutex_unlock(&adev->pm.mutex);
1520                 }
1521                 amdgpu_pm_compute_clocks(adev);
1522         }
1523 }
1524
1525 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1526 {
1527         if (adev->powerplay.pp_funcs->powergate_vce) {
1528                 /* enable/disable VCE */
1529                 mutex_lock(&adev->pm.mutex);
1530                 amdgpu_dpm_powergate_vce(adev, !enable);
1531                 mutex_unlock(&adev->pm.mutex);
1532         } else {
1533                 if (enable) {
1534                         mutex_lock(&adev->pm.mutex);
1535                         adev->pm.dpm.vce_active = true;
1536                         /* XXX select vce level based on ring/task */
1537                         adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1538                         mutex_unlock(&adev->pm.mutex);
1539                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1540                                                                AMD_CG_STATE_UNGATE);
1541                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1542                                                                AMD_PG_STATE_UNGATE);
1543                         amdgpu_pm_compute_clocks(adev);
1544                 } else {
1545                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1546                                                                AMD_PG_STATE_GATE);
1547                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1548                                                                AMD_CG_STATE_GATE);
1549                         mutex_lock(&adev->pm.mutex);
1550                         adev->pm.dpm.vce_active = false;
1551                         mutex_unlock(&adev->pm.mutex);
1552                         amdgpu_pm_compute_clocks(adev);
1553                 }
1554
1555         }
1556 }
1557
1558 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1559 {
1560         int i;
1561
1562         if (adev->powerplay.pp_funcs->print_power_state == NULL)
1563                 return;
1564
1565         for (i = 0; i < adev->pm.dpm.num_ps; i++)
1566                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1567
1568 }
1569
1570 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1571 {
1572         int ret;
1573
1574         if (adev->pm.sysfs_initialized)
1575                 return 0;
1576
1577         if (adev->pm.dpm_enabled == 0)
1578                 return 0;
1579
1580         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1581                                                                    DRIVER_NAME, adev,
1582                                                                    hwmon_groups);
1583         if (IS_ERR(adev->pm.int_hwmon_dev)) {
1584                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1585                 dev_err(adev->dev,
1586                         "Unable to register hwmon device: %d\n", ret);
1587                 return ret;
1588         }
1589
1590         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1591         if (ret) {
1592                 DRM_ERROR("failed to create device file for dpm state\n");
1593                 return ret;
1594         }
1595         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1596         if (ret) {
1597                 DRM_ERROR("failed to create device file for dpm state\n");
1598                 return ret;
1599         }
1600
1601
1602         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1603         if (ret) {
1604                 DRM_ERROR("failed to create device file pp_num_states\n");
1605                 return ret;
1606         }
1607         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1608         if (ret) {
1609                 DRM_ERROR("failed to create device file pp_cur_state\n");
1610                 return ret;
1611         }
1612         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1613         if (ret) {
1614                 DRM_ERROR("failed to create device file pp_force_state\n");
1615                 return ret;
1616         }
1617         ret = device_create_file(adev->dev, &dev_attr_pp_table);
1618         if (ret) {
1619                 DRM_ERROR("failed to create device file pp_table\n");
1620                 return ret;
1621         }
1622
1623         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1624         if (ret) {
1625                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1626                 return ret;
1627         }
1628         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1629         if (ret) {
1630                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1631                 return ret;
1632         }
1633         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1634         if (ret) {
1635                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1636                 return ret;
1637         }
1638         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1639         if (ret) {
1640                 DRM_ERROR("failed to create device file pp_sclk_od\n");
1641                 return ret;
1642         }
1643         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1644         if (ret) {
1645                 DRM_ERROR("failed to create device file pp_mclk_od\n");
1646                 return ret;
1647         }
1648         ret = device_create_file(adev->dev,
1649                         &dev_attr_pp_power_profile_mode);
1650         if (ret) {
1651                 DRM_ERROR("failed to create device file "
1652                                 "pp_power_profile_mode\n");
1653                 return ret;
1654         }
1655         ret = device_create_file(adev->dev,
1656                         &dev_attr_pp_od_clk_voltage);
1657         if (ret) {
1658                 DRM_ERROR("failed to create device file "
1659                                 "pp_od_clk_voltage\n");
1660                 return ret;
1661         }
1662         ret = amdgpu_debugfs_pm_init(adev);
1663         if (ret) {
1664                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1665                 return ret;
1666         }
1667
1668         adev->pm.sysfs_initialized = true;
1669
1670         return 0;
1671 }
1672
1673 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1674 {
1675         if (adev->pm.dpm_enabled == 0)
1676                 return;
1677
1678         if (adev->pm.int_hwmon_dev)
1679                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1680         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1681         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1682
1683         device_remove_file(adev->dev, &dev_attr_pp_num_states);
1684         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1685         device_remove_file(adev->dev, &dev_attr_pp_force_state);
1686         device_remove_file(adev->dev, &dev_attr_pp_table);
1687
1688         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1689         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1690         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1691         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1692         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
1693         device_remove_file(adev->dev,
1694                         &dev_attr_pp_power_profile_mode);
1695         device_remove_file(adev->dev,
1696                         &dev_attr_pp_od_clk_voltage);
1697 }
1698
1699 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1700 {
1701         int i = 0;
1702
1703         if (!adev->pm.dpm_enabled)
1704                 return;
1705
1706         if (adev->mode_info.num_crtc)
1707                 amdgpu_display_bandwidth_update(adev);
1708
1709         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1710                 struct amdgpu_ring *ring = adev->rings[i];
1711                 if (ring && ring->ready)
1712                         amdgpu_fence_wait_empty(ring);
1713         }
1714
1715         if (!amdgpu_device_has_dc_support(adev)) {
1716                 mutex_lock(&adev->pm.mutex);
1717                 amdgpu_dpm_get_active_displays(adev);
1718                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtcs;
1719                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
1720                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
1721                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
1722                 if (adev->pm.pm_display_cfg.vrefresh > 120)
1723                         adev->pm.pm_display_cfg.min_vblank_time = 0;
1724                 if (adev->powerplay.pp_funcs->display_configuration_change)
1725                         adev->powerplay.pp_funcs->display_configuration_change(
1726                                                         adev->powerplay.pp_handle,
1727                                                         &adev->pm.pm_display_cfg);
1728                 mutex_unlock(&adev->pm.mutex);
1729         }
1730
1731         if (adev->powerplay.pp_funcs->dispatch_tasks) {
1732                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
1733         } else {
1734                 mutex_lock(&adev->pm.mutex);
1735                 /* update battery/ac status */
1736                 if (power_supply_is_system_supplied() > 0)
1737                         adev->pm.dpm.ac_power = true;
1738                 else
1739                         adev->pm.dpm.ac_power = false;
1740
1741                 amdgpu_dpm_change_power_state_locked(adev);
1742
1743                 mutex_unlock(&adev->pm.mutex);
1744         }
1745 }
1746
1747 /*
1748  * Debugfs info
1749  */
1750 #if defined(CONFIG_DEBUG_FS)
1751
1752 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
1753 {
1754         uint32_t value;
1755         uint32_t query = 0;
1756         int size;
1757
1758         /* sanity check PP is enabled */
1759         if (!(adev->powerplay.pp_funcs &&
1760               adev->powerplay.pp_funcs->read_sensor))
1761               return -EINVAL;
1762
1763         /* GPU Clocks */
1764         size = sizeof(value);
1765         seq_printf(m, "GFX Clocks and Power:\n");
1766         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
1767                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
1768         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
1769                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
1770         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
1771                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
1772         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
1773                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
1774         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
1775                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
1776         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
1777                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
1778         size = sizeof(uint32_t);
1779         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
1780                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
1781         size = sizeof(value);
1782         seq_printf(m, "\n");
1783
1784         /* GPU Temp */
1785         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
1786                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
1787
1788         /* GPU Load */
1789         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
1790                 seq_printf(m, "GPU Load: %u %%\n", value);
1791         seq_printf(m, "\n");
1792
1793         /* UVD clocks */
1794         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
1795                 if (!value) {
1796                         seq_printf(m, "UVD: Disabled\n");
1797                 } else {
1798                         seq_printf(m, "UVD: Enabled\n");
1799                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
1800                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
1801                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
1802                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
1803                 }
1804         }
1805         seq_printf(m, "\n");
1806
1807         /* VCE clocks */
1808         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
1809                 if (!value) {
1810                         seq_printf(m, "VCE: Disabled\n");
1811                 } else {
1812                         seq_printf(m, "VCE: Enabled\n");
1813                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
1814                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
1815                 }
1816         }
1817
1818         return 0;
1819 }
1820
1821 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
1822 {
1823         int i;
1824
1825         for (i = 0; clocks[i].flag; i++)
1826                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
1827                            (flags & clocks[i].flag) ? "On" : "Off");
1828 }
1829
1830 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1831 {
1832         struct drm_info_node *node = (struct drm_info_node *) m->private;
1833         struct drm_device *dev = node->minor->dev;
1834         struct amdgpu_device *adev = dev->dev_private;
1835         struct drm_device *ddev = adev->ddev;
1836         u32 flags = 0;
1837
1838         amdgpu_device_ip_get_clockgating_state(adev, &flags);
1839         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
1840         amdgpu_parse_cg_state(m, flags);
1841         seq_printf(m, "\n");
1842
1843         if (!adev->pm.dpm_enabled) {
1844                 seq_printf(m, "dpm not enabled\n");
1845                 return 0;
1846         }
1847         if  ((adev->flags & AMD_IS_PX) &&
1848              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1849                 seq_printf(m, "PX asic powered off\n");
1850         } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
1851                 mutex_lock(&adev->pm.mutex);
1852                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
1853                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
1854                 else
1855                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1856                 mutex_unlock(&adev->pm.mutex);
1857         } else {
1858                 return amdgpu_debugfs_pm_info_pp(m, adev);
1859         }
1860
1861         return 0;
1862 }
1863
1864 static const struct drm_info_list amdgpu_pm_info_list[] = {
1865         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
1866 };
1867 #endif
1868
1869 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
1870 {
1871 #if defined(CONFIG_DEBUG_FS)
1872         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
1873 #else
1874         return 0;
1875 #endif
1876 }