drivers/gpu/drm/i915/intel_hdcp.c

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright (C) 2017 Google, Inc.
   4  *
   5  * Authors:
   6  * Sean Paul <[email protected]>
   7  */
   8
   9 #include <drm/drmP.h>
  10 #include <drm/drm_hdcp.h>
  11 #include <linux/i2c.h>
  12 #include <linux/random.h>
  13
  14 #include "intel_drv.h"
  15 #include "i915_reg.h"
  16
  17 #define KEY_LOAD_TRIES  5
  18
  19 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
  20                                     const struct intel_hdcp_shim *shim)
  21 {
  22         int ret, read_ret;
  23         bool ksv_ready;
  24
  25         /* Poll for ksv list ready (spec says max time allowed is 5s) */
  26         ret = __wait_for(read_ret = shim->read_ksv_ready(intel_dig_port,
  27                                                          &ksv_ready),
  28                          read_ret || ksv_ready, 5 * 1000 * 1000, 1000,
  29                          100 * 1000);
  30         if (ret)
  31                 return ret;
  32         if (read_ret)
  33                 return read_ret;
  34         if (!ksv_ready)
  35                 return -ETIMEDOUT;
  36
  37         return 0;
  38 }
  39
  40 static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv)
  41 {
  42         I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);
  43         I915_WRITE(HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS |
  44                    HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE);
  45 }
  46
  47 static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
  48 {
  49         int ret;
  50         u32 val;
  51
  52         val = I915_READ(HDCP_KEY_STATUS);
  53         if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS))
  54                 return 0;
  55
  56         /*
  57          * On HSW and BDW HW loads the HDCP1.4 Key when Display comes
  58          * out of reset. So if Key is not already loaded, its an error state.
  59          */
  60         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
  61                 if (!(I915_READ(HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE))
  62                         return -ENXIO;
  63
  64         /*
  65          * Initiate loading the HDCP key from fuses.
  66          *
  67          * BXT+ platforms, HDCP key needs to be loaded by SW. Only SKL and KBL
  68          * differ in the key load trigger process from other platforms.
  69          */
  70         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
  71                 mutex_lock(&dev_priv->pcu_lock);
  72                 ret = sandybridge_pcode_write(dev_priv,
  73                                               SKL_PCODE_LOAD_HDCP_KEYS, 1);
  74                 mutex_unlock(&dev_priv->pcu_lock);
  75                 if (ret) {
  76                         DRM_ERROR("Failed to initiate HDCP key load (%d)\n",
  77                                   ret);
  78                         return ret;
  79                 }
  80         } else {
  81                 I915_WRITE(HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER);
  82         }
  83
  84         /* Wait for the keys to load (500us) */
  85         ret = __intel_wait_for_register(dev_priv, HDCP_KEY_STATUS,
  86                                         HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE,
  87                                         10, 1, &val);
  88         if (ret)
  89                 return ret;
  90         else if (!(val & HDCP_KEY_LOAD_STATUS))
  91                 return -ENXIO;
  92
  93         /* Send Aksv over to PCH display for use in authentication */
  94         I915_WRITE(HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER);
  95
  96         return 0;
  97 }
  98
  99 /* Returns updated SHA-1 index */
 100 static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text)
 101 {
 102         I915_WRITE(HDCP_SHA_TEXT, sha_text);
 103         if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
 104                                     HDCP_SHA1_READY, HDCP_SHA1_READY, 1)) {
 105                 DRM_ERROR("Timed out waiting for SHA1 ready\n");
 106                 return -ETIMEDOUT;
 107         }
 108         return 0;
 109 }
 110
 111 static
 112 u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port)
 113 {
 114         enum port port = intel_dig_port->base.port;
 115         switch (port) {
 116         case PORT_A:
 117                 return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
 118         case PORT_B:
 119                 return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0;
 120         case PORT_C:
 121                 return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0;
 122         case PORT_D:
 123                 return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0;
 124         case PORT_E:
 125                 return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
 126         default:
 127                 break;
 128         }
 129         DRM_ERROR("Unknown port %d\n", port);
 130         return -EINVAL;
 131 }
 132
 133 static
 134 bool intel_hdcp_is_ksv_valid(u8 *ksv)
 135 {
 136         int i, ones = 0;
 137         /* KSV has 20 1's and 20 0's */
 138         for (i = 0; i < DRM_HDCP_KSV_LEN; i++)
 139                 ones += hweight8(ksv[i]);
 140         if (ones != 20)
 141                 return false;
 142         return true;
 143 }
 144
 145 /* Implements Part 2 of the HDCP authorization procedure */
 146 static
 147 int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
 148                                const struct intel_hdcp_shim *shim)
 149 {
 150         struct drm_i915_private *dev_priv;
 151         u32 vprime, sha_text, sha_leftovers, rep_ctl;
 152         u8 bstatus[2], num_downstream, *ksv_fifo;
 153         int ret, i, j, sha_idx;
 154
 155         dev_priv = intel_dig_port->base.base.dev->dev_private;
 156
 157         ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
 158         if (ret) {
 159                 DRM_ERROR("KSV list failed to become ready (%d)\n", ret);
 160                 return ret;
 161         }
 162
 163         ret = shim->read_bstatus(intel_dig_port, bstatus);
 164         if (ret)
 165                 return ret;
 166
 167         if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
 168             DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
 169                 DRM_ERROR("Max Topology Limit Exceeded\n");
 170                 return -EPERM;
 171         }
 172
 173         /*
 174          * When repeater reports 0 device count, HDCP1.4 spec allows disabling
 175          * the HDCP encryption. That implies that repeater can't have its own
 176          * display. As there is no consumption of encrypted content in the
 177          * repeater with 0 downstream devices, we are failing the
 178          * authentication.
 179          */
 180         num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
 181         if (num_downstream == 0)
 182                 return -EINVAL;
 183
 184         ksv_fifo = kzalloc(num_downstream * DRM_HDCP_KSV_LEN, GFP_KERNEL);
 185         if (!ksv_fifo)
 186                 return -ENOMEM;
 187
 188         ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
 189         if (ret)
 190                 return ret;
 191
 192         /* Process V' values from the receiver */
 193         for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) {
 194                 ret = shim->read_v_prime_part(intel_dig_port, i, &vprime);
 195                 if (ret)
 196                         return ret;
 197                 I915_WRITE(HDCP_SHA_V_PRIME(i), vprime);
 198         }
 199
 200         /*
 201          * We need to write the concatenation of all device KSVs, BINFO (DP) ||
 202          * BSTATUS (HDMI), and M0 (which is added via HDCP_REP_CTL). This byte
 203          * stream is written via the HDCP_SHA_TEXT register in 32-bit
 204          * increments. Every 64 bytes, we need to write HDCP_REP_CTL again. This
 205          * index will keep track of our progress through the 64 bytes as well as
 206          * helping us work the 40-bit KSVs through our 32-bit register.
 207          *
 208          * NOTE: data passed via HDCP_SHA_TEXT should be big-endian
 209          */
 210         sha_idx = 0;
 211         sha_text = 0;
 212         sha_leftovers = 0;
 213         rep_ctl = intel_hdcp_get_repeater_ctl(intel_dig_port);
 214         I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
 215         for (i = 0; i < num_downstream; i++) {
 216                 unsigned int sha_empty;
 217                 u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN];
 218
 219                 /* Fill up the empty slots in sha_text and write it out */
 220                 sha_empty = sizeof(sha_text) - sha_leftovers;
 221                 for (j = 0; j < sha_empty; j++)
 222                         sha_text |= ksv[j] << ((sizeof(sha_text) - j - 1) * 8);
 223
 224                 ret = intel_write_sha_text(dev_priv, sha_text);
 225                 if (ret < 0)
 226                         return ret;
 227
 228                 /* Programming guide writes this every 64 bytes */
 229                 sha_idx += sizeof(sha_text);
 230                 if (!(sha_idx % 64))
 231                         I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
 232
 233                 /* Store the leftover bytes from the ksv in sha_text */
 234                 sha_leftovers = DRM_HDCP_KSV_LEN - sha_empty;
 235                 sha_text = 0;
 236                 for (j = 0; j < sha_leftovers; j++)
 237                         sha_text |= ksv[sha_empty + j] <<
 238                                         ((sizeof(sha_text) - j - 1) * 8);
 239
 240                 /*
 241                  * If we still have room in sha_text for more data, continue.
 242                  * Otherwise, write it out immediately.
 243                  */
 244                 if (sizeof(sha_text) > sha_leftovers)
 245                         continue;
 246
 247                 ret = intel_write_sha_text(dev_priv, sha_text);
 248                 if (ret < 0)
 249                         return ret;
 250                 sha_leftovers = 0;
 251                 sha_text = 0;
 252                 sha_idx += sizeof(sha_text);
 253         }
 254
 255         /*
 256          * We need to write BINFO/BSTATUS, and M0 now. Depending on how many
 257          * bytes are leftover from the last ksv, we might be able to fit them
 258          * all in sha_text (first 2 cases), or we might need to split them up
 259          * into 2 writes (last 2 cases).
 260          */
 261         if (sha_leftovers == 0) {
 262                 /* Write 16 bits of text, 16 bits of M0 */
 263                 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_16);
 264                 ret = intel_write_sha_text(dev_priv,
 265                                            bstatus[0] << 8 | bstatus[1]);
 266                 if (ret < 0)
 267                         return ret;
 268                 sha_idx += sizeof(sha_text);
 269
 270                 /* Write 32 bits of M0 */
 271                 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0);
 272                 ret = intel_write_sha_text(dev_priv, 0);
 273                 if (ret < 0)
 274                         return ret;
 275                 sha_idx += sizeof(sha_text);
 276
 277                 /* Write 16 bits of M0 */
 278                 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_16);
 279                 ret = intel_write_sha_text(dev_priv, 0);
 280                 if (ret < 0)
 281                         return ret;
 282                 sha_idx += sizeof(sha_text);
 283
 284         } else if (sha_leftovers == 1) {
 285                 /* Write 24 bits of text, 8 bits of M0 */
 286                 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_24);
 287                 sha_text |= bstatus[0] << 16 | bstatus[1] << 8;
 288                 /* Only 24-bits of data, must be in the LSB */
 289                 sha_text = (sha_text & 0xffffff00) >> 8;
 290                 ret = intel_write_sha_text(dev_priv, sha_text);
 291                 if (ret < 0)
 292                         return ret;
 293                 sha_idx += sizeof(sha_text);
 294
 295                 /* Write 32 bits of M0 */
 296                 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0);
 297                 ret = intel_write_sha_text(dev_priv, 0);
 298                 if (ret < 0)
 299                         return ret;
 300                 sha_idx += sizeof(sha_text);
 301
 302                 /* Write 24 bits of M0 */
 303                 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_8);
 304                 ret = intel_write_sha_text(dev_priv, 0);
 305                 if (ret < 0)
 306                         return ret;
 307                 sha_idx += sizeof(sha_text);
 308
 309         } else if (sha_leftovers == 2) {
 310                 /* Write 32 bits of text */
 311                 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
 312                 sha_text |= bstatus[0] << 24 | bstatus[1] << 16;
 313                 ret = intel_write_sha_text(dev_priv, sha_text);
 314                 if (ret < 0)
 315                         return ret;
 316                 sha_idx += sizeof(sha_text);
 317
 318                 /* Write 64 bits of M0 */
 319                 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0);
 320                 for (i = 0; i < 2; i++) {
 321                         ret = intel_write_sha_text(dev_priv, 0);
 322                         if (ret < 0)
 323                                 return ret;
 324                         sha_idx += sizeof(sha_text);
 325                 }
 326         } else if (sha_leftovers == 3) {
 327                 /* Write 32 bits of text */
 328                 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
 329                 sha_text |= bstatus[0] << 24;
 330                 ret = intel_write_sha_text(dev_priv, sha_text);
 331                 if (ret < 0)
 332                         return ret;
 333                 sha_idx += sizeof(sha_text);
 334
 335                 /* Write 8 bits of text, 24 bits of M0 */
 336                 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_8);
 337                 ret = intel_write_sha_text(dev_priv, bstatus[1]);
 338                 if (ret < 0)
 339                         return ret;
 340                 sha_idx += sizeof(sha_text);
 341
 342                 /* Write 32 bits of M0 */
 343                 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0);
 344                 ret = intel_write_sha_text(dev_priv, 0);
 345                 if (ret < 0)
 346                         return ret;
 347                 sha_idx += sizeof(sha_text);
 348
 349                 /* Write 8 bits of M0 */
 350                 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_24);
 351                 ret = intel_write_sha_text(dev_priv, 0);
 352                 if (ret < 0)
 353                         return ret;
 354                 sha_idx += sizeof(sha_text);
 355         } else {
 356                 DRM_ERROR("Invalid number of leftovers %d\n", sha_leftovers);
 357                 return -EINVAL;
 358         }
 359
 360         I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
 361         /* Fill up to 64-4 bytes with zeros (leave the last write for length) */
 362         while ((sha_idx % 64) < (64 - sizeof(sha_text))) {
 363                 ret = intel_write_sha_text(dev_priv, 0);
 364                 if (ret < 0)
 365                         return ret;
 366                 sha_idx += sizeof(sha_text);
 367         }
 368
 369         /*
 370          * Last write gets the length of the concatenation in bits. That is:
 371          *  - 5 bytes per device
 372          *  - 10 bytes for BINFO/BSTATUS(2), M0(8)
 373          */
 374         sha_text = (num_downstream * 5 + 10) * 8;
 375         ret = intel_write_sha_text(dev_priv, sha_text);
 376         if (ret < 0)
 377                 return ret;
 378
 379         /* Tell the HW we're done with the hash and wait for it to ACK */
 380         I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_COMPLETE_HASH);
 381         if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
 382                                     HDCP_SHA1_COMPLETE,
 383                                     HDCP_SHA1_COMPLETE, 1)) {
 384                 DRM_ERROR("Timed out waiting for SHA1 complete\n");
 385                 return -ETIMEDOUT;
 386         }
 387         if (!(I915_READ(HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) {
 388                 DRM_ERROR("SHA-1 mismatch, HDCP failed\n");
 389                 return -ENXIO;
 390         }
 391
 392         DRM_DEBUG_KMS("HDCP is enabled (%d downstream devices)\n",
 393                       num_downstream);
 394         return 0;
 395 }
 396
 397 /* Implements Part 1 of the HDCP authorization procedure */
 398 static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
 399                            const struct intel_hdcp_shim *shim)
 400 {
 401         struct drm_i915_private *dev_priv;
 402         enum port port;
 403         unsigned long r0_prime_gen_start;
 404         int ret, i, tries = 2;
 405         union {
 406                 u32 reg[2];
 407                 u8 shim[DRM_HDCP_AN_LEN];
 408         } an;
 409         union {
 410                 u32 reg[2];
 411                 u8 shim[DRM_HDCP_KSV_LEN];
 412         } bksv;
 413         union {
 414                 u32 reg;
 415                 u8 shim[DRM_HDCP_RI_LEN];
 416         } ri;
 417         bool repeater_present, hdcp_capable;
 418
 419         dev_priv = intel_dig_port->base.base.dev->dev_private;
 420
 421         port = intel_dig_port->base.port;
 422
 423         /*
 424          * Detects whether the display is HDCP capable. Although we check for
 425          * valid Bksv below, the HDCP over DP spec requires that we check
 426          * whether the display supports HDCP before we write An. For HDMI
 427          * displays, this is not necessary.
 428          */
 429         if (shim->hdcp_capable) {
 430                 ret = shim->hdcp_capable(intel_dig_port, &hdcp_capable);
 431                 if (ret)
 432                         return ret;
 433                 if (!hdcp_capable) {
 434                         DRM_ERROR("Panel is not HDCP capable\n");
 435                         return -EINVAL;
 436                 }
 437         }
 438
 439         /* Initialize An with 2 random values and acquire it */
 440         for (i = 0; i < 2; i++)
 441                 I915_WRITE(PORT_HDCP_ANINIT(port), get_random_u32());
 442         I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_CAPTURE_AN);
 443
 444         /* Wait for An to be acquired */
 445         if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port),
 446                                     HDCP_STATUS_AN_READY,
 447                                     HDCP_STATUS_AN_READY, 1)) {
 448                 DRM_ERROR("Timed out waiting for An\n");
 449                 return -ETIMEDOUT;
 450         }
 451
 452         an.reg[0] = I915_READ(PORT_HDCP_ANLO(port));
 453         an.reg[1] = I915_READ(PORT_HDCP_ANHI(port));
 454         ret = shim->write_an_aksv(intel_dig_port, an.shim);
 455         if (ret)
 456                 return ret;
 457
 458         r0_prime_gen_start = jiffies;
 459
 460         memset(&bksv, 0, sizeof(bksv));
 461
 462         /* HDCP spec states that we must retry the bksv if it is invalid */
 463         for (i = 0; i < tries; i++) {
 464                 ret = shim->read_bksv(intel_dig_port, bksv.shim);
 465                 if (ret)
 466                         return ret;
 467                 if (intel_hdcp_is_ksv_valid(bksv.shim))
 468                         break;
 469         }
 470         if (i == tries) {
 471                 DRM_ERROR("HDCP failed, Bksv is invalid\n");
 472                 return -ENODEV;
 473         }
 474
 475         I915_WRITE(PORT_HDCP_BKSVLO(port), bksv.reg[0]);
 476         I915_WRITE(PORT_HDCP_BKSVHI(port), bksv.reg[1]);
 477
 478         ret = shim->repeater_present(intel_dig_port, &repeater_present);
 479         if (ret)
 480                 return ret;
 481         if (repeater_present)
 482                 I915_WRITE(HDCP_REP_CTL,
 483                            intel_hdcp_get_repeater_ctl(intel_dig_port));
 484
 485         ret = shim->toggle_signalling(intel_dig_port, true);
 486         if (ret)
 487                 return ret;
 488
 489         I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_AUTH_AND_ENC);
 490
 491         /* Wait for R0 ready */
 492         if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
 493                      (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) {
 494                 DRM_ERROR("Timed out waiting for R0 ready\n");
 495                 return -ETIMEDOUT;
 496         }
 497
 498         /*
 499          * Wait for R0' to become available. The spec says 100ms from Aksv, but
 500          * some monitors can take longer than this. We'll set the timeout at
 501          * 300ms just to be sure.
 502          *
 503          * On DP, there's an R0_READY bit available but no such bit
 504          * exists on HDMI. Since the upper-bound is the same, we'll just do
 505          * the stupid thing instead of polling on one and not the other.
 506          */
 507         wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300);
 508
 509         ri.reg = 0;
 510         ret = shim->read_ri_prime(intel_dig_port, ri.shim);
 511         if (ret)
 512                 return ret;
 513         I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
 514
 515         /* Wait for Ri prime match */
 516         if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
 517                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
 518                 DRM_ERROR("Timed out waiting for Ri prime match (%x)\n",
 519                           I915_READ(PORT_HDCP_STATUS(port)));
 520                 return -ETIMEDOUT;
 521         }
 522
 523         /* Wait for encryption confirmation */
 524         if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port),
 525                                     HDCP_STATUS_ENC, HDCP_STATUS_ENC, 20)) {
 526                 DRM_ERROR("Timed out waiting for encryption\n");
 527                 return -ETIMEDOUT;
 528         }
 529
 530         /*
 531          * XXX: If we have MST-connected devices, we need to enable encryption
 532          * on those as well.
 533          */
 534
 535         if (repeater_present)
 536                 return intel_hdcp_auth_downstream(intel_dig_port, shim);
 537
 538         DRM_DEBUG_KMS("HDCP is enabled (no repeater present)\n");
 539         return 0;
 540 }
 541
 542 static
 543 struct intel_digital_port *conn_to_dig_port(struct intel_connector *connector)
 544 {
 545         return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
 546 }
 547
 548 static int _intel_hdcp_disable(struct intel_connector *connector)
 549 {
 550         struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
 551         struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
 552         enum port port = intel_dig_port->base.port;
 553         int ret;
 554
 555         DRM_DEBUG_KMS("[%s:%d] HDCP is being disabled...\n",
 556                       connector->base.name, connector->base.base.id);
 557
 558         I915_WRITE(PORT_HDCP_CONF(port), 0);
 559         if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port), ~0, 0,
 560                                     20)) {
 561                 DRM_ERROR("Failed to disable HDCP, timeout clearing status\n");
 562                 return -ETIMEDOUT;
 563         }
 564
 565         ret = connector->hdcp_shim->toggle_signalling(intel_dig_port, false);
 566         if (ret) {
 567                 DRM_ERROR("Failed to disable HDCP signalling\n");
 568                 return ret;
 569         }
 570
 571         DRM_DEBUG_KMS("HDCP is disabled\n");
 572         return 0;
 573 }
 574
 575 static int _intel_hdcp_enable(struct intel_connector *connector)
 576 {
 577         struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
 578         int i, ret, tries = 3;
 579
 580         DRM_DEBUG_KMS("[%s:%d] HDCP is being enabled...\n",
 581                       connector->base.name, connector->base.base.id);
 582
 583         if (!(I915_READ(SKL_FUSE_STATUS) & SKL_FUSE_PG_DIST_STATUS(1))) {
 584                 DRM_ERROR("PG1 is disabled, cannot load keys\n");
 585                 return -ENXIO;
 586         }
 587
 588         for (i = 0; i < KEY_LOAD_TRIES; i++) {
 589                 ret = intel_hdcp_load_keys(dev_priv);
 590                 if (!ret)
 591                         break;
 592                 intel_hdcp_clear_keys(dev_priv);
 593         }
 594         if (ret) {
 595                 DRM_ERROR("Could not load HDCP keys, (%d)\n", ret);
 596                 return ret;
 597         }
 598
 599         /* Incase of authentication failures, HDCP spec expects reauth. */
 600         for (i = 0; i < tries; i++) {
 601                 ret = intel_hdcp_auth(conn_to_dig_port(connector),
 602                                       connector->hdcp_shim);
 603                 if (!ret)
 604                         return 0;
 605
 606                 DRM_DEBUG_KMS("HDCP Auth failure (%d)\n", ret);
 607
 608                 /* Ensuring HDCP encryption and signalling are stopped. */
 609                 _intel_hdcp_disable(connector);
 610         }
 611
 612         DRM_ERROR("HDCP authentication failed (%d tries/%d)\n", tries, ret);
 613         return ret;
 614 }
 615
 616 static void intel_hdcp_check_work(struct work_struct *work)
 617 {
 618         struct intel_connector *connector = container_of(to_delayed_work(work),
 619                                                          struct intel_connector,
 620                                                          hdcp_check_work);
 621         if (!intel_hdcp_check_link(connector))
 622                 schedule_delayed_work(&connector->hdcp_check_work,
 623                                       DRM_HDCP_CHECK_PERIOD_MS);
 624 }
 625
 626 static void intel_hdcp_prop_work(struct work_struct *work)
 627 {
 628         struct intel_connector *connector = container_of(work,
 629                                                          struct intel_connector,
 630                                                          hdcp_prop_work);
 631         struct drm_device *dev = connector->base.dev;
 632         struct drm_connector_state *state;
 633
 634         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 635         mutex_lock(&connector->hdcp_mutex);
 636
 637         /*
 638          * This worker is only used to flip between ENABLED/DESIRED. Either of
 639          * those to UNDESIRED is handled by core. If hdcp_value == UNDESIRED,
 640          * we're running just after hdcp has been disabled, so just exit
 641          */
 642         if (connector->hdcp_value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
 643                 state = connector->base.state;
 644                 state->content_protection = connector->hdcp_value;
 645         }
 646
 647         mutex_unlock(&connector->hdcp_mutex);
 648         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 649 }
 650
 651 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
 652 {
 653         /* PORT E doesn't have HDCP, and PORT F is disabled */
 654         return ((INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
 655                 !IS_CHERRYVIEW(dev_priv) && port < PORT_E);
 656 }
 657
 658 int intel_hdcp_init(struct intel_connector *connector,
 659                     const struct intel_hdcp_shim *hdcp_shim)
 660 {
 661         int ret;
 662
 663         ret = drm_connector_attach_content_protection_property(
 664                         &connector->base);
 665         if (ret)
 666                 return ret;
 667
 668         connector->hdcp_shim = hdcp_shim;
 669         mutex_init(&connector->hdcp_mutex);
 670         INIT_DELAYED_WORK(&connector->hdcp_check_work, intel_hdcp_check_work);
 671         INIT_WORK(&connector->hdcp_prop_work, intel_hdcp_prop_work);
 672         return 0;
 673 }
 674
 675 int intel_hdcp_enable(struct intel_connector *connector)
 676 {
 677         int ret;
 678
 679         if (!connector->hdcp_shim)
 680                 return -ENOENT;
 681
 682         mutex_lock(&connector->hdcp_mutex);
 683
 684         ret = _intel_hdcp_enable(connector);
 685         if (ret)
 686                 goto out;
 687
 688         connector->hdcp_value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
 689         schedule_work(&connector->hdcp_prop_work);
 690         schedule_delayed_work(&connector->hdcp_check_work,
 691                               DRM_HDCP_CHECK_PERIOD_MS);
 692 out:
 693         mutex_unlock(&connector->hdcp_mutex);
 694         return ret;
 695 }
 696
 697 int intel_hdcp_disable(struct intel_connector *connector)
 698 {
 699         int ret = 0;
 700
 701         if (!connector->hdcp_shim)
 702                 return -ENOENT;
 703
 704         mutex_lock(&connector->hdcp_mutex);
 705
 706         if (connector->hdcp_value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
 707                 connector->hdcp_value = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
 708                 ret = _intel_hdcp_disable(connector);
 709         }
 710
 711         mutex_unlock(&connector->hdcp_mutex);
 712         cancel_delayed_work_sync(&connector->hdcp_check_work);
 713         return ret;
 714 }
 715
 716 void intel_hdcp_atomic_check(struct drm_connector *connector,
 717                              struct drm_connector_state *old_state,
 718                              struct drm_connector_state *new_state)
 719 {
 720         uint64_t old_cp = old_state->content_protection;
 721         uint64_t new_cp = new_state->content_protection;
 722         struct drm_crtc_state *crtc_state;
 723
 724         if (!new_state->crtc) {
 725                 /*
 726                  * If the connector is being disabled with CP enabled, mark it
 727                  * desired so it's re-enabled when the connector is brought back
 728                  */
 729                 if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)
 730                         new_state->content_protection =
 731                                 DRM_MODE_CONTENT_PROTECTION_DESIRED;
 732                 return;
 733         }
 734
 735         /*
 736          * Nothing to do if the state didn't change, or HDCP was activated since
 737          * the last commit
 738          */
 739         if (old_cp == new_cp ||
 740             (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
 741              new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED))
 742                 return;
 743
 744         crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
 745                                                    new_state->crtc);
 746         crtc_state->mode_changed = true;
 747 }
 748
 749 /* Implements Part 3 of the HDCP authorization procedure */
 750 int intel_hdcp_check_link(struct intel_connector *connector)
 751 {
 752         struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
 753         struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
 754         enum port port = intel_dig_port->base.port;
 755         int ret = 0;
 756
 757         if (!connector->hdcp_shim)
 758                 return -ENOENT;
 759
 760         mutex_lock(&connector->hdcp_mutex);
 761
 762         if (connector->hdcp_value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
 763                 goto out;
 764
 765         if (!(I915_READ(PORT_HDCP_STATUS(port)) & HDCP_STATUS_ENC)) {
 766                 DRM_ERROR("%s:%d HDCP check failed: link is not encrypted,%x\n",
 767                           connector->base.name, connector->base.base.id,
 768                           I915_READ(PORT_HDCP_STATUS(port)));
 769                 ret = -ENXIO;
 770                 connector->hdcp_value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
 771                 schedule_work(&connector->hdcp_prop_work);
 772                 goto out;
 773         }
 774
 775         if (connector->hdcp_shim->check_link(intel_dig_port)) {
 776                 if (connector->hdcp_value !=
 777                     DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
 778                         connector->hdcp_value =
 779                                 DRM_MODE_CONTENT_PROTECTION_ENABLED;
 780                         schedule_work(&connector->hdcp_prop_work);
 781                 }
 782                 goto out;
 783         }
 784
 785         DRM_DEBUG_KMS("[%s:%d] HDCP link failed, retrying authentication\n",
 786                       connector->base.name, connector->base.base.id);
 787
 788         ret = _intel_hdcp_disable(connector);
 789         if (ret) {
 790                 DRM_ERROR("Failed to disable hdcp (%d)\n", ret);
 791                 connector->hdcp_value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
 792                 schedule_work(&connector->hdcp_prop_work);
 793                 goto out;
 794         }
 795
 796         ret = _intel_hdcp_enable(connector);
 797         if (ret) {
 798                 DRM_ERROR("Failed to enable hdcp (%d)\n", ret);
 799                 connector->hdcp_value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
 800                 schedule_work(&connector->hdcp_prop_work);
 801                 goto out;
 802         }
 803
 804 out:
 805         mutex_unlock(&connector->hdcp_mutex);
 806         return ret;
 807 }