drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <[email protected]>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31
  32 struct ddi_buf_trans {
  33         u32 trans1;     /* balance leg enable, de-emph level */
  34         u32 trans2;     /* vref sel, vswing */
  35         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  36 };
  37
  38 static const u8 index_to_dp_signal_levels[] = {
  39         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  40         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  41         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  42         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  43         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  44         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  45         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  46         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  47         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  48         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  49 };
  50
  51 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  52  * them for both DP and FDI transports, allowing those ports to
  53  * automatically adapt to HDMI connections as well
  54  */
  55 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  56         { 0x00FFFFFF, 0x0006000E, 0x0 },
  57         { 0x00D75FFF, 0x0005000A, 0x0 },
  58         { 0x00C30FFF, 0x00040006, 0x0 },
  59         { 0x80AAAFFF, 0x000B0000, 0x0 },
  60         { 0x00FFFFFF, 0x0005000A, 0x0 },
  61         { 0x00D75FFF, 0x000C0004, 0x0 },
  62         { 0x80C30FFF, 0x000B0000, 0x0 },
  63         { 0x00FFFFFF, 0x00040006, 0x0 },
  64         { 0x80D75FFF, 0x000B0000, 0x0 },
  65 };
  66
  67 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  68         { 0x00FFFFFF, 0x0007000E, 0x0 },
  69         { 0x00D75FFF, 0x000F000A, 0x0 },
  70         { 0x00C30FFF, 0x00060006, 0x0 },
  71         { 0x00AAAFFF, 0x001E0000, 0x0 },
  72         { 0x00FFFFFF, 0x000F000A, 0x0 },
  73         { 0x00D75FFF, 0x00160004, 0x0 },
  74         { 0x00C30FFF, 0x001E0000, 0x0 },
  75         { 0x00FFFFFF, 0x00060006, 0x0 },
  76         { 0x00D75FFF, 0x001E0000, 0x0 },
  77 };
  78
  79 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  80                                         /* Idx  NT mV d T mV d  db      */
  81         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  82         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  83         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  84         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  85         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  86         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  87         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  88         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  89         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  90         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  91         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  92         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  93 };
  94
  95 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  96         { 0x00FFFFFF, 0x00000012, 0x0 },
  97         { 0x00EBAFFF, 0x00020011, 0x0 },
  98         { 0x00C71FFF, 0x0006000F, 0x0 },
  99         { 0x00AAAFFF, 0x000E000A, 0x0 },
 100         { 0x00FFFFFF, 0x00020011, 0x0 },
 101         { 0x00DB6FFF, 0x0005000F, 0x0 },
 102         { 0x00BEEFFF, 0x000A000C, 0x0 },
 103         { 0x00FFFFFF, 0x0005000F, 0x0 },
 104         { 0x00DB6FFF, 0x000A000C, 0x0 },
 105 };
 106
 107 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 108         { 0x00FFFFFF, 0x0007000E, 0x0 },
 109         { 0x00D75FFF, 0x000E000A, 0x0 },
 110         { 0x00BEFFFF, 0x00140006, 0x0 },
 111         { 0x80B2CFFF, 0x001B0002, 0x0 },
 112         { 0x00FFFFFF, 0x000E000A, 0x0 },
 113         { 0x00DB6FFF, 0x00160005, 0x0 },
 114         { 0x80C71FFF, 0x001A0002, 0x0 },
 115         { 0x00F7DFFF, 0x00180004, 0x0 },
 116         { 0x80D75FFF, 0x001B0002, 0x0 },
 117 };
 118
 119 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 120         { 0x00FFFFFF, 0x0001000E, 0x0 },
 121         { 0x00D75FFF, 0x0004000A, 0x0 },
 122         { 0x00C30FFF, 0x00070006, 0x0 },
 123         { 0x00AAAFFF, 0x000C0000, 0x0 },
 124         { 0x00FFFFFF, 0x0004000A, 0x0 },
 125         { 0x00D75FFF, 0x00090004, 0x0 },
 126         { 0x00C30FFF, 0x000C0000, 0x0 },
 127         { 0x00FFFFFF, 0x00070006, 0x0 },
 128         { 0x00D75FFF, 0x000C0000, 0x0 },
 129 };
 130
 131 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 132                                         /* Idx  NT mV d T mV df db      */
 133         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 134         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 135         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 136         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 137         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 138         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 139         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 140         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 141         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 142         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 143 };
 144
 145 /* Skylake H and S */
 146 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 147         { 0x00002016, 0x000000A0, 0x0 },
 148         { 0x00005012, 0x0000009B, 0x0 },
 149         { 0x00007011, 0x00000088, 0x0 },
 150         { 0x80009010, 0x000000C0, 0x1 },
 151         { 0x00002016, 0x0000009B, 0x0 },
 152         { 0x00005012, 0x00000088, 0x0 },
 153         { 0x80007011, 0x000000C0, 0x1 },
 154         { 0x00002016, 0x000000DF, 0x0 },
 155         { 0x80005012, 0x000000C0, 0x1 },
 156 };
 157
 158 /* Skylake U */
 159 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 160         { 0x0000201B, 0x000000A2, 0x0 },
 161         { 0x00005012, 0x00000088, 0x0 },
 162         { 0x80007011, 0x000000CD, 0x1 },
 163         { 0x80009010, 0x000000C0, 0x1 },
 164         { 0x0000201B, 0x0000009D, 0x0 },
 165         { 0x80005012, 0x000000C0, 0x1 },
 166         { 0x80007011, 0x000000C0, 0x1 },
 167         { 0x00002016, 0x00000088, 0x0 },
 168         { 0x80005012, 0x000000C0, 0x1 },
 169 };
 170
 171 /* Skylake Y */
 172 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 173         { 0x00000018, 0x000000A2, 0x0 },
 174         { 0x00005012, 0x00000088, 0x0 },
 175         { 0x80007011, 0x000000CD, 0x3 },
 176         { 0x80009010, 0x000000C0, 0x3 },
 177         { 0x00000018, 0x0000009D, 0x0 },
 178         { 0x80005012, 0x000000C0, 0x3 },
 179         { 0x80007011, 0x000000C0, 0x3 },
 180         { 0x00000018, 0x00000088, 0x0 },
 181         { 0x80005012, 0x000000C0, 0x3 },
 182 };
 183
 184 /* Kabylake H and S */
 185 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 186         { 0x00002016, 0x000000A0, 0x0 },
 187         { 0x00005012, 0x0000009B, 0x0 },
 188         { 0x00007011, 0x00000088, 0x0 },
 189         { 0x80009010, 0x000000C0, 0x1 },
 190         { 0x00002016, 0x0000009B, 0x0 },
 191         { 0x00005012, 0x00000088, 0x0 },
 192         { 0x80007011, 0x000000C0, 0x1 },
 193         { 0x00002016, 0x00000097, 0x0 },
 194         { 0x80005012, 0x000000C0, 0x1 },
 195 };
 196
 197 /* Kabylake U */
 198 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 199         { 0x0000201B, 0x000000A1, 0x0 },
 200         { 0x00005012, 0x00000088, 0x0 },
 201         { 0x80007011, 0x000000CD, 0x3 },
 202         { 0x80009010, 0x000000C0, 0x3 },
 203         { 0x0000201B, 0x0000009D, 0x0 },
 204         { 0x80005012, 0x000000C0, 0x3 },
 205         { 0x80007011, 0x000000C0, 0x3 },
 206         { 0x00002016, 0x0000004F, 0x0 },
 207         { 0x80005012, 0x000000C0, 0x3 },
 208 };
 209
 210 /* Kabylake Y */
 211 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 212         { 0x00001017, 0x000000A1, 0x0 },
 213         { 0x00005012, 0x00000088, 0x0 },
 214         { 0x80007011, 0x000000CD, 0x3 },
 215         { 0x8000800F, 0x000000C0, 0x3 },
 216         { 0x00001017, 0x0000009D, 0x0 },
 217         { 0x80005012, 0x000000C0, 0x3 },
 218         { 0x80007011, 0x000000C0, 0x3 },
 219         { 0x00001017, 0x0000004C, 0x0 },
 220         { 0x80005012, 0x000000C0, 0x3 },
 221 };
 222
 223 /*
 224  * Skylake/Kabylake H and S
 225  * eDP 1.4 low vswing translation parameters
 226  */
 227 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 228         { 0x00000018, 0x000000A8, 0x0 },
 229         { 0x00004013, 0x000000A9, 0x0 },
 230         { 0x00007011, 0x000000A2, 0x0 },
 231         { 0x00009010, 0x0000009C, 0x0 },
 232         { 0x00000018, 0x000000A9, 0x0 },
 233         { 0x00006013, 0x000000A2, 0x0 },
 234         { 0x00007011, 0x000000A6, 0x0 },
 235         { 0x00000018, 0x000000AB, 0x0 },
 236         { 0x00007013, 0x0000009F, 0x0 },
 237         { 0x00000018, 0x000000DF, 0x0 },
 238 };
 239
 240 /*
 241  * Skylake/Kabylake U
 242  * eDP 1.4 low vswing translation parameters
 243  */
 244 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 245         { 0x00000018, 0x000000A8, 0x0 },
 246         { 0x00004013, 0x000000A9, 0x0 },
 247         { 0x00007011, 0x000000A2, 0x0 },
 248         { 0x00009010, 0x0000009C, 0x0 },
 249         { 0x00000018, 0x000000A9, 0x0 },
 250         { 0x00006013, 0x000000A2, 0x0 },
 251         { 0x00007011, 0x000000A6, 0x0 },
 252         { 0x00002016, 0x000000AB, 0x0 },
 253         { 0x00005013, 0x0000009F, 0x0 },
 254         { 0x00000018, 0x000000DF, 0x0 },
 255 };
 256
 257 /*
 258  * Skylake/Kabylake Y
 259  * eDP 1.4 low vswing translation parameters
 260  */
 261 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 262         { 0x00000018, 0x000000A8, 0x0 },
 263         { 0x00004013, 0x000000AB, 0x0 },
 264         { 0x00007011, 0x000000A4, 0x0 },
 265         { 0x00009010, 0x000000DF, 0x0 },
 266         { 0x00000018, 0x000000AA, 0x0 },
 267         { 0x00006013, 0x000000A4, 0x0 },
 268         { 0x00007011, 0x0000009D, 0x0 },
 269         { 0x00000018, 0x000000A0, 0x0 },
 270         { 0x00006012, 0x000000DF, 0x0 },
 271         { 0x00000018, 0x0000008A, 0x0 },
 272 };
 273
 274 /* Skylake/Kabylake U, H and S */
 275 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 276         { 0x00000018, 0x000000AC, 0x0 },
 277         { 0x00005012, 0x0000009D, 0x0 },
 278         { 0x00007011, 0x00000088, 0x0 },
 279         { 0x00000018, 0x000000A1, 0x0 },
 280         { 0x00000018, 0x00000098, 0x0 },
 281         { 0x00004013, 0x00000088, 0x0 },
 282         { 0x80006012, 0x000000CD, 0x1 },
 283         { 0x00000018, 0x000000DF, 0x0 },
 284         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 285         { 0x80003015, 0x000000C0, 0x1 },
 286         { 0x80000018, 0x000000C0, 0x1 },
 287 };
 288
 289 /* Skylake/Kabylake Y */
 290 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 291         { 0x00000018, 0x000000A1, 0x0 },
 292         { 0x00005012, 0x000000DF, 0x0 },
 293         { 0x80007011, 0x000000CB, 0x3 },
 294         { 0x00000018, 0x000000A4, 0x0 },
 295         { 0x00000018, 0x0000009D, 0x0 },
 296         { 0x00004013, 0x00000080, 0x0 },
 297         { 0x80006013, 0x000000C0, 0x3 },
 298         { 0x00000018, 0x0000008A, 0x0 },
 299         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 300         { 0x80003015, 0x000000C0, 0x3 },
 301         { 0x80000018, 0x000000C0, 0x3 },
 302 };
 303
 304 struct bxt_ddi_buf_trans {
 305         u8 margin;      /* swing value */
 306         u8 scale;       /* scale value */
 307         u8 enable;      /* scale enable */
 308         u8 deemphasis;
 309 };
 310
 311 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 312                                         /* Idx  NT mV diff      db  */
 313         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 314         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 315         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 316         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 317         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 318         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 319         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 320         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 321         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 322         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 323 };
 324
 325 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 326                                         /* Idx  NT mV diff      db  */
 327         { 26, 0, 0, 128, },     /* 0:   200             0   */
 328         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 329         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 330         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 331         { 32, 0, 0, 128, },     /* 4:   250             0   */
 332         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 333         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 334         { 43, 0, 0, 128, },     /* 7:   300             0   */
 335         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 336         { 48, 0, 0, 128, },     /* 9:   300             0   */
 337 };
 338
 339 /* BSpec has 2 recommended values - entries 0 and 8.
 340  * Using the entry with higher vswing.
 341  */
 342 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 343                                         /* Idx  NT mV diff      db  */
 344         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 345         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 346         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 347         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 348         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 349         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 350         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 351         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 352         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 353         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 354 };
 355
 356 struct cnl_ddi_buf_trans {
 357         u8 dw2_swing_sel;
 358         u8 dw7_n_scalar;
 359         u8 dw4_cursor_coeff;
 360         u8 dw4_post_cursor_2;
 361         u8 dw4_post_cursor_1;
 362 };
 363
 364 /* Voltage Swing Programming for VccIO 0.85V for DP */
 365 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 366                                                 /* NT mV Trans mV db    */
 367         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 368         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 369         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 370         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 371         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 372         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 373         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 374         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 375         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 376         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 377 };
 378
 379 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 380 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 381                                                 /* NT mV Trans mV db    */
 382         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 383         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 384         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 385         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 386         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 387         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 388         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 389 };
 390
 391 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 392 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 393                                                 /* NT mV Trans mV db    */
 394         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 395         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 396         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 397         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 398         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 399         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 400         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 401         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 402         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 403 };
 404
 405 /* Voltage Swing Programming for VccIO 0.95V for DP */
 406 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 407                                                 /* NT mV Trans mV db    */
 408         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 409         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 410         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 411         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 412         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 413         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 414         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 415         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 416         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 417         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 418 };
 419
 420 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 421 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 422                                                 /* NT mV Trans mV db    */
 423         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 424         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 425         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 426         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 427         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 428         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 429         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 430         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 431         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 432         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 433         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 434 };
 435
 436 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 437 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 438                                                 /* NT mV Trans mV db    */
 439         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 440         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 441         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 442         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 443         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 444         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 445         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 446         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 447         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 448         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 449 };
 450
 451 /* Voltage Swing Programming for VccIO 1.05V for DP */
 452 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 453                                                 /* NT mV Trans mV db    */
 454         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 455         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 456         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 457         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 458         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 459         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 460         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 461         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 462         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 463         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 464 };
 465
 466 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 467 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 468                                                 /* NT mV Trans mV db    */
 469         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 470         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 471         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 472         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 473         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 474         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 475         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 476         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 477         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 478         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 479         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 480 };
 481
 482 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 483 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 484                                                 /* NT mV Trans mV db    */
 485         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 486         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 487         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 488         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 489         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 490         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 491         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 492         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 493         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 494 };
 495
 496 static const struct ddi_buf_trans *
 497 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 498 {
 499         if (dev_priv->vbt.edp.low_vswing) {
 500                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 501                 return bdw_ddi_translations_edp;
 502         } else {
 503                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 504                 return bdw_ddi_translations_dp;
 505         }
 506 }
 507
 508 static const struct ddi_buf_trans *
 509 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 510 {
 511         if (IS_SKL_ULX(dev_priv)) {
 512                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 513                 return skl_y_ddi_translations_dp;
 514         } else if (IS_SKL_ULT(dev_priv)) {
 515                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 516                 return skl_u_ddi_translations_dp;
 517         } else {
 518                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 519                 return skl_ddi_translations_dp;
 520         }
 521 }
 522
 523 static const struct ddi_buf_trans *
 524 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 525 {
 526         if (IS_KBL_ULX(dev_priv)) {
 527                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 528                 return kbl_y_ddi_translations_dp;
 529         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 530                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 531                 return kbl_u_ddi_translations_dp;
 532         } else {
 533                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 534                 return kbl_ddi_translations_dp;
 535         }
 536 }
 537
 538 static const struct ddi_buf_trans *
 539 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 540 {
 541         if (dev_priv->vbt.edp.low_vswing) {
 542                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 543                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 544                         return skl_y_ddi_translations_edp;
 545                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 546                            IS_CFL_ULT(dev_priv)) {
 547                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 548                         return skl_u_ddi_translations_edp;
 549                 } else {
 550                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 551                         return skl_ddi_translations_edp;
 552                 }
 553         }
 554
 555         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 556                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 557         else
 558                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 559 }
 560
 561 static const struct ddi_buf_trans *
 562 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 563 {
 564         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 565                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 566                 return skl_y_ddi_translations_hdmi;
 567         } else {
 568                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 569                 return skl_ddi_translations_hdmi;
 570         }
 571 }
 572
 573 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 574 {
 575         /* Only DDIA and DDIE can select the 10th register with DP */
 576         if (port == PORT_A || port == PORT_E)
 577                 return min(n_entries, 10);
 578         else
 579                 return min(n_entries, 9);
 580 }
 581
 582 static const struct ddi_buf_trans *
 583 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 584                            enum port port, int *n_entries)
 585 {
 586         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 587                 const struct ddi_buf_trans *ddi_translations =
 588                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 589                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 590                 return ddi_translations;
 591         } else if (IS_SKYLAKE(dev_priv)) {
 592                 const struct ddi_buf_trans *ddi_translations =
 593                         skl_get_buf_trans_dp(dev_priv, n_entries);
 594                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 595                 return ddi_translations;
 596         } else if (IS_BROADWELL(dev_priv)) {
 597                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 598                 return  bdw_ddi_translations_dp;
 599         } else if (IS_HASWELL(dev_priv)) {
 600                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 601                 return hsw_ddi_translations_dp;
 602         }
 603
 604         *n_entries = 0;
 605         return NULL;
 606 }
 607
 608 static const struct ddi_buf_trans *
 609 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 610                             enum port port, int *n_entries)
 611 {
 612         if (IS_GEN9_BC(dev_priv)) {
 613                 const struct ddi_buf_trans *ddi_translations =
 614                         skl_get_buf_trans_edp(dev_priv, n_entries);
 615                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 616                 return ddi_translations;
 617         } else if (IS_BROADWELL(dev_priv)) {
 618                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 619         } else if (IS_HASWELL(dev_priv)) {
 620                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 621                 return hsw_ddi_translations_dp;
 622         }
 623
 624         *n_entries = 0;
 625         return NULL;
 626 }
 627
 628 static const struct ddi_buf_trans *
 629 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 630                             int *n_entries)
 631 {
 632         if (IS_BROADWELL(dev_priv)) {
 633                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 634                 return bdw_ddi_translations_fdi;
 635         } else if (IS_HASWELL(dev_priv)) {
 636                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 637                 return hsw_ddi_translations_fdi;
 638         }
 639
 640         *n_entries = 0;
 641         return NULL;
 642 }
 643
 644 static const struct ddi_buf_trans *
 645 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 646                              int *n_entries)
 647 {
 648         if (IS_GEN9_BC(dev_priv)) {
 649                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 650         } else if (IS_BROADWELL(dev_priv)) {
 651                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 652                 return bdw_ddi_translations_hdmi;
 653         } else if (IS_HASWELL(dev_priv)) {
 654                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 655                 return hsw_ddi_translations_hdmi;
 656         }
 657
 658         *n_entries = 0;
 659         return NULL;
 660 }
 661
 662 static const struct bxt_ddi_buf_trans *
 663 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 664 {
 665         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 666         return bxt_ddi_translations_dp;
 667 }
 668
 669 static const struct bxt_ddi_buf_trans *
 670 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 671 {
 672         if (dev_priv->vbt.edp.low_vswing) {
 673                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 674                 return bxt_ddi_translations_edp;
 675         }
 676
 677         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 678 }
 679
 680 static const struct bxt_ddi_buf_trans *
 681 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 682 {
 683         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 684         return bxt_ddi_translations_hdmi;
 685 }
 686
 687 static const struct cnl_ddi_buf_trans *
 688 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 689 {
 690         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 691
 692         if (voltage == VOLTAGE_INFO_0_85V) {
 693                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 694                 return cnl_ddi_translations_hdmi_0_85V;
 695         } else if (voltage == VOLTAGE_INFO_0_95V) {
 696                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 697                 return cnl_ddi_translations_hdmi_0_95V;
 698         } else if (voltage == VOLTAGE_INFO_1_05V) {
 699                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 700                 return cnl_ddi_translations_hdmi_1_05V;
 701         } else {
 702                 *n_entries = 1; /* shut up gcc */
 703                 MISSING_CASE(voltage);
 704         }
 705         return NULL;
 706 }
 707
 708 static const struct cnl_ddi_buf_trans *
 709 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 710 {
 711         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 712
 713         if (voltage == VOLTAGE_INFO_0_85V) {
 714                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 715                 return cnl_ddi_translations_dp_0_85V;
 716         } else if (voltage == VOLTAGE_INFO_0_95V) {
 717                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 718                 return cnl_ddi_translations_dp_0_95V;
 719         } else if (voltage == VOLTAGE_INFO_1_05V) {
 720                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 721                 return cnl_ddi_translations_dp_1_05V;
 722         } else {
 723                 *n_entries = 1; /* shut up gcc */
 724                 MISSING_CASE(voltage);
 725         }
 726         return NULL;
 727 }
 728
 729 static const struct cnl_ddi_buf_trans *
 730 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 731 {
 732         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 733
 734         if (dev_priv->vbt.edp.low_vswing) {
 735                 if (voltage == VOLTAGE_INFO_0_85V) {
 736                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 737                         return cnl_ddi_translations_edp_0_85V;
 738                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 739                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 740                         return cnl_ddi_translations_edp_0_95V;
 741                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 742                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 743                         return cnl_ddi_translations_edp_1_05V;
 744                 } else {
 745                         *n_entries = 1; /* shut up gcc */
 746                         MISSING_CASE(voltage);
 747                 }
 748                 return NULL;
 749         } else {
 750                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 751         }
 752 }
 753
 754 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 755 {
 756         int n_entries, level, default_entry;
 757
 758         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 759
 760         if (IS_CANNONLAKE(dev_priv)) {
 761                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 762                 default_entry = n_entries - 1;
 763         } else if (IS_GEN9_LP(dev_priv)) {
 764                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 765                 default_entry = n_entries - 1;
 766         } else if (IS_GEN9_BC(dev_priv)) {
 767                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 768                 default_entry = 8;
 769         } else if (IS_BROADWELL(dev_priv)) {
 770                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 771                 default_entry = 7;
 772         } else if (IS_HASWELL(dev_priv)) {
 773                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 774                 default_entry = 6;
 775         } else {
 776                 WARN(1, "ddi translation table missing\n");
 777                 return 0;
 778         }
 779
 780         /* Choose a good default if VBT is badly populated */
 781         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 782                 level = default_entry;
 783
 784         if (WARN_ON_ONCE(n_entries == 0))
 785                 return 0;
 786         if (WARN_ON_ONCE(level >= n_entries))
 787                 level = n_entries - 1;
 788
 789         return level;
 790 }
 791
 792 /*
 793  * Starting with Haswell, DDI port buffers must be programmed with correct
 794  * values in advance. This function programs the correct values for
 795  * DP/eDP/FDI use cases.
 796  */
 797 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 798                                          const struct intel_crtc_state *crtc_state)
 799 {
 800         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 801         u32 iboost_bit = 0;
 802         int i, n_entries;
 803         enum port port = encoder->port;
 804         const struct ddi_buf_trans *ddi_translations;
 805
 806         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 807                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 808                                                                &n_entries);
 809         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 810                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 811                                                                &n_entries);
 812         else
 813                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 814                                                               &n_entries);
 815
 816         /* If we're boosting the current, set bit 31 of trans1 */
 817         if (IS_GEN9_BC(dev_priv) &&
 818             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 819                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 820
 821         for (i = 0; i < n_entries; i++) {
 822                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 823                            ddi_translations[i].trans1 | iboost_bit);
 824                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 825                            ddi_translations[i].trans2);
 826         }
 827 }
 828
 829 /*
 830  * Starting with Haswell, DDI port buffers must be programmed with correct
 831  * values in advance. This function programs the correct values for
 832  * HDMI/DVI use cases.
 833  */
 834 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 835                                            int level)
 836 {
 837         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 838         u32 iboost_bit = 0;
 839         int n_entries;
 840         enum port port = encoder->port;
 841         const struct ddi_buf_trans *ddi_translations;
 842
 843         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 844
 845         if (WARN_ON_ONCE(!ddi_translations))
 846                 return;
 847         if (WARN_ON_ONCE(level >= n_entries))
 848                 level = n_entries - 1;
 849
 850         /* If we're boosting the current, set bit 31 of trans1 */
 851         if (IS_GEN9_BC(dev_priv) &&
 852             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
 853                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 854
 855         /* Entry 9 is for HDMI: */
 856         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
 857                    ddi_translations[level].trans1 | iboost_bit);
 858         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
 859                    ddi_translations[level].trans2);
 860 }
 861
 862 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 863                                     enum port port)
 864 {
 865         i915_reg_t reg = DDI_BUF_CTL(port);
 866         int i;
 867
 868         for (i = 0; i < 16; i++) {
 869                 udelay(1);
 870                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 871                         return;
 872         }
 873         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 874 }
 875
 876 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 877 {
 878         switch (pll->id) {
 879         case DPLL_ID_WRPLL1:
 880                 return PORT_CLK_SEL_WRPLL1;
 881         case DPLL_ID_WRPLL2:
 882                 return PORT_CLK_SEL_WRPLL2;
 883         case DPLL_ID_SPLL:
 884                 return PORT_CLK_SEL_SPLL;
 885         case DPLL_ID_LCPLL_810:
 886                 return PORT_CLK_SEL_LCPLL_810;
 887         case DPLL_ID_LCPLL_1350:
 888                 return PORT_CLK_SEL_LCPLL_1350;
 889         case DPLL_ID_LCPLL_2700:
 890                 return PORT_CLK_SEL_LCPLL_2700;
 891         default:
 892                 MISSING_CASE(pll->id);
 893                 return PORT_CLK_SEL_NONE;
 894         }
 895 }
 896
 897 /* Starting with Haswell, different DDI ports can work in FDI mode for
 898  * connection to the PCH-located connectors. For this, it is necessary to train
 899  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 900  *
 901  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 902  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 903  * DDI A (which is used for eDP)
 904  */
 905
 906 void hsw_fdi_link_train(struct intel_crtc *crtc,
 907                         const struct intel_crtc_state *crtc_state)
 908 {
 909         struct drm_device *dev = crtc->base.dev;
 910         struct drm_i915_private *dev_priv = to_i915(dev);
 911         struct intel_encoder *encoder;
 912         u32 temp, i, rx_ctl_val, ddi_pll_sel;
 913
 914         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
 915                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
 916                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
 917         }
 918
 919         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 920          * mode set "sequence for CRT port" document:
 921          * - TP1 to TP2 time with the default value
 922          * - FDI delay to 90h
 923          *
 924          * WaFDIAutoLinkSetTimingOverrride:hsw
 925          */
 926         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
 927                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 928                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 929
 930         /* Enable the PCH Receiver FDI PLL */
 931         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 932                      FDI_RX_PLL_ENABLE |
 933                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
 934         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 935         POSTING_READ(FDI_RX_CTL(PIPE_A));
 936         udelay(220);
 937
 938         /* Switch from Rawclk to PCDclk */
 939         rx_ctl_val |= FDI_PCDCLK;
 940         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 941
 942         /* Configure Port Clock Select */
 943         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
 944         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
 945         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
 946
 947         /* Start the training iterating through available voltages and emphasis,
 948          * testing each value twice. */
 949         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
 950                 /* Configure DP_TP_CTL with auto-training */
 951                 I915_WRITE(DP_TP_CTL(PORT_E),
 952                                         DP_TP_CTL_FDI_AUTOTRAIN |
 953                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 954                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 955                                         DP_TP_CTL_ENABLE);
 956
 957                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 958                  * DDI E does not support port reversal, the functionality is
 959                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 960                  * port reversal bit */
 961                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 962                            DDI_BUF_CTL_ENABLE |
 963                            ((crtc_state->fdi_lanes - 1) << 1) |
 964                            DDI_BUF_TRANS_SELECT(i / 2));
 965                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 966
 967                 udelay(600);
 968
 969                 /* Program PCH FDI Receiver TU */
 970                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
 971
 972                 /* Enable PCH FDI Receiver with auto-training */
 973                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 974                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 975                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 976
 977                 /* Wait for FDI receiver lane calibration */
 978                 udelay(30);
 979
 980                 /* Unset FDI_RX_MISC pwrdn lanes */
 981                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 982                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 983                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 984                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 985
 986                 /* Wait for FDI auto training time */
 987                 udelay(5);
 988
 989                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 990                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 991                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 992                         break;
 993                 }
 994
 995                 /*
 996                  * Leave things enabled even if we failed to train FDI.
 997                  * Results in less fireworks from the state checker.
 998                  */
 999                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1000                         DRM_ERROR("FDI link training failed!\n");
1001                         break;
1002                 }
1003
1004                 rx_ctl_val &= ~FDI_RX_ENABLE;
1005                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1006                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1007
1008                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1009                 temp &= ~DDI_BUF_CTL_ENABLE;
1010                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1011                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1012
1013                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1014                 temp = I915_READ(DP_TP_CTL(PORT_E));
1015                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1016                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1017                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1018                 POSTING_READ(DP_TP_CTL(PORT_E));
1019
1020                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1021
1022                 /* Reset FDI_RX_MISC pwrdn lanes */
1023                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1024                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1025                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1026                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1027                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1028         }
1029
1030         /* Enable normal pixel sending for FDI */
1031         I915_WRITE(DP_TP_CTL(PORT_E),
1032                    DP_TP_CTL_FDI_AUTOTRAIN |
1033                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1034                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1035                    DP_TP_CTL_ENABLE);
1036 }
1037
1038 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1039 {
1040         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1041         struct intel_digital_port *intel_dig_port =
1042                 enc_to_dig_port(&encoder->base);
1043
1044         intel_dp->DP = intel_dig_port->saved_port_bits |
1045                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1046         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1047 }
1048
1049 static struct intel_encoder *
1050 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1051 {
1052         struct drm_device *dev = crtc->base.dev;
1053         struct intel_encoder *encoder, *ret = NULL;
1054         int num_encoders = 0;
1055
1056         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1057                 ret = encoder;
1058                 num_encoders++;
1059         }
1060
1061         if (num_encoders != 1)
1062                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1063                      pipe_name(crtc->pipe));
1064
1065         BUG_ON(ret == NULL);
1066         return ret;
1067 }
1068
1069 /* Finds the only possible encoder associated with the given CRTC. */
1070 struct intel_encoder *
1071 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
1072 {
1073         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1074         struct intel_encoder *ret = NULL;
1075         struct drm_atomic_state *state;
1076         struct drm_connector *connector;
1077         struct drm_connector_state *connector_state;
1078         int num_encoders = 0;
1079         int i;
1080
1081         state = crtc_state->base.state;
1082
1083         for_each_new_connector_in_state(state, connector, connector_state, i) {
1084                 if (connector_state->crtc != crtc_state->base.crtc)
1085                         continue;
1086
1087                 ret = to_intel_encoder(connector_state->best_encoder);
1088                 num_encoders++;
1089         }
1090
1091         WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
1092              pipe_name(crtc->pipe));
1093
1094         BUG_ON(ret == NULL);
1095         return ret;
1096 }
1097
1098 #define LC_FREQ 2700
1099
1100 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1101                                    i915_reg_t reg)
1102 {
1103         int refclk = LC_FREQ;
1104         int n, p, r;
1105         u32 wrpll;
1106
1107         wrpll = I915_READ(reg);
1108         switch (wrpll & WRPLL_PLL_REF_MASK) {
1109         case WRPLL_PLL_SSC:
1110         case WRPLL_PLL_NON_SSC:
1111                 /*
1112                  * We could calculate spread here, but our checking
1113                  * code only cares about 5% accuracy, and spread is a max of
1114                  * 0.5% downspread.
1115                  */
1116                 refclk = 135;
1117                 break;
1118         case WRPLL_PLL_LCPLL:
1119                 refclk = LC_FREQ;
1120                 break;
1121         default:
1122                 WARN(1, "bad wrpll refclk\n");
1123                 return 0;
1124         }
1125
1126         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1127         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1128         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1129
1130         /* Convert to KHz, p & r have a fixed point portion */
1131         return (refclk * n * 100) / (p * r);
1132 }
1133
1134 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1135                                enum intel_dpll_id pll_id)
1136 {
1137         i915_reg_t cfgcr1_reg, cfgcr2_reg;
1138         uint32_t cfgcr1_val, cfgcr2_val;
1139         uint32_t p0, p1, p2, dco_freq;
1140
1141         cfgcr1_reg = DPLL_CFGCR1(pll_id);
1142         cfgcr2_reg = DPLL_CFGCR2(pll_id);
1143
1144         cfgcr1_val = I915_READ(cfgcr1_reg);
1145         cfgcr2_val = I915_READ(cfgcr2_reg);
1146
1147         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1148         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1149
1150         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
1151                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1152         else
1153                 p1 = 1;
1154
1155
1156         switch (p0) {
1157         case DPLL_CFGCR2_PDIV_1:
1158                 p0 = 1;
1159                 break;
1160         case DPLL_CFGCR2_PDIV_2:
1161                 p0 = 2;
1162                 break;
1163         case DPLL_CFGCR2_PDIV_3:
1164                 p0 = 3;
1165                 break;
1166         case DPLL_CFGCR2_PDIV_7:
1167                 p0 = 7;
1168                 break;
1169         }
1170
1171         switch (p2) {
1172         case DPLL_CFGCR2_KDIV_5:
1173                 p2 = 5;
1174                 break;
1175         case DPLL_CFGCR2_KDIV_2:
1176                 p2 = 2;
1177                 break;
1178         case DPLL_CFGCR2_KDIV_3:
1179                 p2 = 3;
1180                 break;
1181         case DPLL_CFGCR2_KDIV_1:
1182                 p2 = 1;
1183                 break;
1184         }
1185
1186         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1187
1188         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1189                 1000) / 0x8000;
1190
1191         return dco_freq / (p0 * p1 * p2 * 5);
1192 }
1193
1194 static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1195                                enum intel_dpll_id pll_id)
1196 {
1197         uint32_t cfgcr0, cfgcr1;
1198         uint32_t p0, p1, p2, dco_freq, ref_clock;
1199
1200         cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1201         cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1202
1203         p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1204         p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1205
1206         if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1207                 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1208                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1209         else
1210                 p1 = 1;
1211
1212
1213         switch (p0) {
1214         case DPLL_CFGCR1_PDIV_2:
1215                 p0 = 2;
1216                 break;
1217         case DPLL_CFGCR1_PDIV_3:
1218                 p0 = 3;
1219                 break;
1220         case DPLL_CFGCR1_PDIV_5:
1221                 p0 = 5;
1222                 break;
1223         case DPLL_CFGCR1_PDIV_7:
1224                 p0 = 7;
1225                 break;
1226         }
1227
1228         switch (p2) {
1229         case DPLL_CFGCR1_KDIV_1:
1230                 p2 = 1;
1231                 break;
1232         case DPLL_CFGCR1_KDIV_2:
1233                 p2 = 2;
1234                 break;
1235         case DPLL_CFGCR1_KDIV_4:
1236                 p2 = 4;
1237                 break;
1238         }
1239
1240         ref_clock = dev_priv->cdclk.hw.ref;
1241
1242         dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1243
1244         dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1245                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1246
1247         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1248                 return 0;
1249
1250         return dco_freq / (p0 * p1 * p2 * 5);
1251 }
1252
1253 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1254 {
1255         int dotclock;
1256
1257         if (pipe_config->has_pch_encoder)
1258                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1259                                                     &pipe_config->fdi_m_n);
1260         else if (intel_crtc_has_dp_encoder(pipe_config))
1261                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1262                                                     &pipe_config->dp_m_n);
1263         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1264                 dotclock = pipe_config->port_clock * 2 / 3;
1265         else
1266                 dotclock = pipe_config->port_clock;
1267
1268         if (pipe_config->ycbcr420)
1269                 dotclock *= 2;
1270
1271         if (pipe_config->pixel_multiplier)
1272                 dotclock /= pipe_config->pixel_multiplier;
1273
1274         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1275 }
1276
1277 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1278                               struct intel_crtc_state *pipe_config)
1279 {
1280         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1281         int link_clock = 0;
1282         uint32_t cfgcr0;
1283         enum intel_dpll_id pll_id;
1284
1285         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1286
1287         cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1288
1289         if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1290                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1291         } else {
1292                 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1293
1294                 switch (link_clock) {
1295                 case DPLL_CFGCR0_LINK_RATE_810:
1296                         link_clock = 81000;
1297                         break;
1298                 case DPLL_CFGCR0_LINK_RATE_1080:
1299                         link_clock = 108000;
1300                         break;
1301                 case DPLL_CFGCR0_LINK_RATE_1350:
1302                         link_clock = 135000;
1303                         break;
1304                 case DPLL_CFGCR0_LINK_RATE_1620:
1305                         link_clock = 162000;
1306                         break;
1307                 case DPLL_CFGCR0_LINK_RATE_2160:
1308                         link_clock = 216000;
1309                         break;
1310                 case DPLL_CFGCR0_LINK_RATE_2700:
1311                         link_clock = 270000;
1312                         break;
1313                 case DPLL_CFGCR0_LINK_RATE_3240:
1314                         link_clock = 324000;
1315                         break;
1316                 case DPLL_CFGCR0_LINK_RATE_4050:
1317                         link_clock = 405000;
1318                         break;
1319                 default:
1320                         WARN(1, "Unsupported link rate\n");
1321                         break;
1322                 }
1323                 link_clock *= 2;
1324         }
1325
1326         pipe_config->port_clock = link_clock;
1327
1328         ddi_dotclock_get(pipe_config);
1329 }
1330
1331 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1332                                 struct intel_crtc_state *pipe_config)
1333 {
1334         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1335         int link_clock = 0;
1336         uint32_t dpll_ctl1;
1337         enum intel_dpll_id pll_id;
1338
1339         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1340
1341         dpll_ctl1 = I915_READ(DPLL_CTRL1);
1342
1343         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1344                 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
1345         } else {
1346                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1347                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
1348
1349                 switch (link_clock) {
1350                 case DPLL_CTRL1_LINK_RATE_810:
1351                         link_clock = 81000;
1352                         break;
1353                 case DPLL_CTRL1_LINK_RATE_1080:
1354                         link_clock = 108000;
1355                         break;
1356                 case DPLL_CTRL1_LINK_RATE_1350:
1357                         link_clock = 135000;
1358                         break;
1359                 case DPLL_CTRL1_LINK_RATE_1620:
1360                         link_clock = 162000;
1361                         break;
1362                 case DPLL_CTRL1_LINK_RATE_2160:
1363                         link_clock = 216000;
1364                         break;
1365                 case DPLL_CTRL1_LINK_RATE_2700:
1366                         link_clock = 270000;
1367                         break;
1368                 default:
1369                         WARN(1, "Unsupported link rate\n");
1370                         break;
1371                 }
1372                 link_clock *= 2;
1373         }
1374
1375         pipe_config->port_clock = link_clock;
1376
1377         ddi_dotclock_get(pipe_config);
1378 }
1379
1380 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1381                               struct intel_crtc_state *pipe_config)
1382 {
1383         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1384         int link_clock = 0;
1385         u32 val, pll;
1386
1387         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1388         switch (val & PORT_CLK_SEL_MASK) {
1389         case PORT_CLK_SEL_LCPLL_810:
1390                 link_clock = 81000;
1391                 break;
1392         case PORT_CLK_SEL_LCPLL_1350:
1393                 link_clock = 135000;
1394                 break;
1395         case PORT_CLK_SEL_LCPLL_2700:
1396                 link_clock = 270000;
1397                 break;
1398         case PORT_CLK_SEL_WRPLL1:
1399                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1400                 break;
1401         case PORT_CLK_SEL_WRPLL2:
1402                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1403                 break;
1404         case PORT_CLK_SEL_SPLL:
1405                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1406                 if (pll == SPLL_PLL_FREQ_810MHz)
1407                         link_clock = 81000;
1408                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1409                         link_clock = 135000;
1410                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1411                         link_clock = 270000;
1412                 else {
1413                         WARN(1, "bad spll freq\n");
1414                         return;
1415                 }
1416                 break;
1417         default:
1418                 WARN(1, "bad port clock sel\n");
1419                 return;
1420         }
1421
1422         pipe_config->port_clock = link_clock * 2;
1423
1424         ddi_dotclock_get(pipe_config);
1425 }
1426
1427 static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
1428 {
1429         struct intel_dpll_hw_state *state;
1430         struct dpll clock;
1431
1432         /* For DDI ports we always use a shared PLL. */
1433         if (WARN_ON(!crtc_state->shared_dpll))
1434                 return 0;
1435
1436         state = &crtc_state->dpll_hw_state;
1437
1438         clock.m1 = 2;
1439         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1440         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1441                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1442         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1443         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1444         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1445
1446         return chv_calc_dpll_params(100000, &clock);
1447 }
1448
1449 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1450                               struct intel_crtc_state *pipe_config)
1451 {
1452         pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
1453
1454         ddi_dotclock_get(pipe_config);
1455 }
1456
1457 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1458                                 struct intel_crtc_state *pipe_config)
1459 {
1460         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1461
1462         if (INTEL_GEN(dev_priv) <= 8)
1463                 hsw_ddi_clock_get(encoder, pipe_config);
1464         else if (IS_GEN9_BC(dev_priv))
1465                 skl_ddi_clock_get(encoder, pipe_config);
1466         else if (IS_GEN9_LP(dev_priv))
1467                 bxt_ddi_clock_get(encoder, pipe_config);
1468         else if (IS_CANNONLAKE(dev_priv))
1469                 cnl_ddi_clock_get(encoder, pipe_config);
1470 }
1471
1472 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1473 {
1474         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1475         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1476         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1477         u32 temp;
1478
1479         if (!intel_crtc_has_dp_encoder(crtc_state))
1480                 return;
1481
1482         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1483
1484         temp = TRANS_MSA_SYNC_CLK;
1485         switch (crtc_state->pipe_bpp) {
1486         case 18:
1487                 temp |= TRANS_MSA_6_BPC;
1488                 break;
1489         case 24:
1490                 temp |= TRANS_MSA_8_BPC;
1491                 break;
1492         case 30:
1493                 temp |= TRANS_MSA_10_BPC;
1494                 break;
1495         case 36:
1496                 temp |= TRANS_MSA_12_BPC;
1497                 break;
1498         default:
1499                 MISSING_CASE(crtc_state->pipe_bpp);
1500                 break;
1501         }
1502
1503         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1504 }
1505
1506 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1507                                     bool state)
1508 {
1509         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1510         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1511         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1512         uint32_t temp;
1513
1514         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1515         if (state == true)
1516                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1517         else
1518                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1519         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1520 }
1521
1522 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1523 {
1524         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1525         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1526         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1527         enum pipe pipe = crtc->pipe;
1528         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1529         enum port port = encoder->port;
1530         uint32_t temp;
1531
1532         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1533         temp = TRANS_DDI_FUNC_ENABLE;
1534         temp |= TRANS_DDI_SELECT_PORT(port);
1535
1536         switch (crtc_state->pipe_bpp) {
1537         case 18:
1538                 temp |= TRANS_DDI_BPC_6;
1539                 break;
1540         case 24:
1541                 temp |= TRANS_DDI_BPC_8;
1542                 break;
1543         case 30:
1544                 temp |= TRANS_DDI_BPC_10;
1545                 break;
1546         case 36:
1547                 temp |= TRANS_DDI_BPC_12;
1548                 break;
1549         default:
1550                 BUG();
1551         }
1552
1553         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1554                 temp |= TRANS_DDI_PVSYNC;
1555         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1556                 temp |= TRANS_DDI_PHSYNC;
1557
1558         if (cpu_transcoder == TRANSCODER_EDP) {
1559                 switch (pipe) {
1560                 case PIPE_A:
1561                         /* On Haswell, can only use the always-on power well for
1562                          * eDP when not using the panel fitter, and when not
1563                          * using motion blur mitigation (which we don't
1564                          * support). */
1565                         if (IS_HASWELL(dev_priv) &&
1566                             (crtc_state->pch_pfit.enabled ||
1567                              crtc_state->pch_pfit.force_thru))
1568                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1569                         else
1570                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1571                         break;
1572                 case PIPE_B:
1573                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1574                         break;
1575                 case PIPE_C:
1576                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1577                         break;
1578                 default:
1579                         BUG();
1580                         break;
1581                 }
1582         }
1583
1584         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1585                 if (crtc_state->has_hdmi_sink)
1586                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1587                 else
1588                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1589
1590                 if (crtc_state->hdmi_scrambling)
1591                         temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1592                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1593                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1594         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1595                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1596                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1597         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1598                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1599                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1600         } else {
1601                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1602                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1603         }
1604
1605         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1606 }
1607
1608 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1609                                        enum transcoder cpu_transcoder)
1610 {
1611         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1612         uint32_t val = I915_READ(reg);
1613
1614         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1615         val |= TRANS_DDI_PORT_NONE;
1616         I915_WRITE(reg, val);
1617 }
1618
1619 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1620                                      bool enable)
1621 {
1622         struct drm_device *dev = intel_encoder->base.dev;
1623         struct drm_i915_private *dev_priv = to_i915(dev);
1624         enum pipe pipe = 0;
1625         int ret = 0;
1626         uint32_t tmp;
1627
1628         if (WARN_ON(!intel_display_power_get_if_enabled(dev_priv,
1629                                                 intel_encoder->power_domain)))
1630                 return -ENXIO;
1631
1632         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1633                 ret = -EIO;
1634                 goto out;
1635         }
1636
1637         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1638         if (enable)
1639                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1640         else
1641                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1642         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1643 out:
1644         intel_display_power_put(dev_priv, intel_encoder->power_domain);
1645         return ret;
1646 }
1647
1648 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1649 {
1650         struct drm_device *dev = intel_connector->base.dev;
1651         struct drm_i915_private *dev_priv = to_i915(dev);
1652         struct intel_encoder *encoder = intel_connector->encoder;
1653         int type = intel_connector->base.connector_type;
1654         enum port port = encoder->port;
1655         enum pipe pipe = 0;
1656         enum transcoder cpu_transcoder;
1657         uint32_t tmp;
1658         bool ret;
1659
1660         if (!intel_display_power_get_if_enabled(dev_priv,
1661                                                 encoder->power_domain))
1662                 return false;
1663
1664         if (!encoder->get_hw_state(encoder, &pipe)) {
1665                 ret = false;
1666                 goto out;
1667         }
1668
1669         if (port == PORT_A)
1670                 cpu_transcoder = TRANSCODER_EDP;
1671         else
1672                 cpu_transcoder = (enum transcoder) pipe;
1673
1674         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1675
1676         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1677         case TRANS_DDI_MODE_SELECT_HDMI:
1678         case TRANS_DDI_MODE_SELECT_DVI:
1679                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1680                 break;
1681
1682         case TRANS_DDI_MODE_SELECT_DP_SST:
1683                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1684                       type == DRM_MODE_CONNECTOR_DisplayPort;
1685                 break;
1686
1687         case TRANS_DDI_MODE_SELECT_DP_MST:
1688                 /* if the transcoder is in MST state then
1689                  * connector isn't connected */
1690                 ret = false;
1691                 break;
1692
1693         case TRANS_DDI_MODE_SELECT_FDI:
1694                 ret = type == DRM_MODE_CONNECTOR_VGA;
1695                 break;
1696
1697         default:
1698                 ret = false;
1699                 break;
1700         }
1701
1702 out:
1703         intel_display_power_put(dev_priv, encoder->power_domain);
1704
1705         return ret;
1706 }
1707
1708 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1709                             enum pipe *pipe)
1710 {
1711         struct drm_device *dev = encoder->base.dev;
1712         struct drm_i915_private *dev_priv = to_i915(dev);
1713         enum port port = encoder->port;
1714         enum pipe p;
1715         u32 tmp;
1716         bool ret;
1717
1718         if (!intel_display_power_get_if_enabled(dev_priv,
1719                                                 encoder->power_domain))
1720                 return false;
1721
1722         ret = false;
1723
1724         tmp = I915_READ(DDI_BUF_CTL(port));
1725
1726         if (!(tmp & DDI_BUF_CTL_ENABLE))
1727                 goto out;
1728
1729         if (port == PORT_A) {
1730                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1731
1732                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1733                 case TRANS_DDI_EDP_INPUT_A_ON:
1734                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1735                         *pipe = PIPE_A;
1736                         break;
1737                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1738                         *pipe = PIPE_B;
1739                         break;
1740                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1741                         *pipe = PIPE_C;
1742                         break;
1743                 }
1744
1745                 ret = true;
1746
1747                 goto out;
1748         }
1749
1750         for_each_pipe(dev_priv, p) {
1751                 enum transcoder cpu_transcoder = (enum transcoder) p;
1752
1753                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1754
1755                 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1756                         if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1757                             TRANS_DDI_MODE_SELECT_DP_MST)
1758                                 goto out;
1759
1760                         *pipe = p;
1761                         ret = true;
1762
1763                         goto out;
1764                 }
1765         }
1766
1767         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1768
1769 out:
1770         if (ret && IS_GEN9_LP(dev_priv)) {
1771                 tmp = I915_READ(BXT_PHY_CTL(port));
1772                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
1773                             BXT_PHY_LANE_POWERDOWN_ACK |
1774                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1775                         DRM_ERROR("Port %c enabled but PHY powered down? "
1776                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
1777         }
1778
1779         intel_display_power_put(dev_priv, encoder->power_domain);
1780
1781         return ret;
1782 }
1783
1784 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1785 {
1786         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1787         enum pipe pipe;
1788
1789         if (intel_ddi_get_hw_state(encoder, &pipe))
1790                 return BIT_ULL(dig_port->ddi_io_power_domain);
1791
1792         return 0;
1793 }
1794
1795 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
1796 {
1797         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1798         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1799         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1800         enum port port = encoder->port;
1801         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1802
1803         if (cpu_transcoder != TRANSCODER_EDP)
1804                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1805                            TRANS_CLK_SEL_PORT(port));
1806 }
1807
1808 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
1809 {
1810         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1811         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1812
1813         if (cpu_transcoder != TRANSCODER_EDP)
1814                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1815                            TRANS_CLK_SEL_DISABLED);
1816 }
1817
1818 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1819                                 enum port port, uint8_t iboost)
1820 {
1821         u32 tmp;
1822
1823         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1824         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1825         if (iboost)
1826                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1827         else
1828                 tmp |= BALANCE_LEG_DISABLE(port);
1829         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1830 }
1831
1832 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
1833                                int level, enum intel_output_type type)
1834 {
1835         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1836         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1837         enum port port = encoder->port;
1838         uint8_t iboost;
1839
1840         if (type == INTEL_OUTPUT_HDMI)
1841                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1842         else
1843                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1844
1845         if (iboost == 0) {
1846                 const struct ddi_buf_trans *ddi_translations;
1847                 int n_entries;
1848
1849                 if (type == INTEL_OUTPUT_HDMI)
1850                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1851                 else if (type == INTEL_OUTPUT_EDP)
1852                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
1853                 else
1854                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
1855
1856                 if (WARN_ON_ONCE(!ddi_translations))
1857                         return;
1858                 if (WARN_ON_ONCE(level >= n_entries))
1859                         level = n_entries - 1;
1860
1861                 iboost = ddi_translations[level].i_boost;
1862         }
1863
1864         /* Make sure that the requested I_boost is valid */
1865         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1866                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1867                 return;
1868         }
1869
1870         _skl_ddi_set_iboost(dev_priv, port, iboost);
1871
1872         if (port == PORT_A && intel_dig_port->max_lanes == 4)
1873                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1874 }
1875
1876 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
1877                                     int level, enum intel_output_type type)
1878 {
1879         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1880         const struct bxt_ddi_buf_trans *ddi_translations;
1881         enum port port = encoder->port;
1882         int n_entries;
1883
1884         if (type == INTEL_OUTPUT_HDMI)
1885                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
1886         else if (type == INTEL_OUTPUT_EDP)
1887                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
1888         else
1889                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
1890
1891         if (WARN_ON_ONCE(!ddi_translations))
1892                 return;
1893         if (WARN_ON_ONCE(level >= n_entries))
1894                 level = n_entries - 1;
1895
1896         bxt_ddi_phy_set_signal_level(dev_priv, port,
1897                                      ddi_translations[level].margin,
1898                                      ddi_translations[level].scale,
1899                                      ddi_translations[level].enable,
1900                                      ddi_translations[level].deemphasis);
1901 }
1902
1903 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1904 {
1905         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1906         enum port port = encoder->port;
1907         int n_entries;
1908
1909         if (IS_CANNONLAKE(dev_priv)) {
1910                 if (encoder->type == INTEL_OUTPUT_EDP)
1911                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
1912                 else
1913                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
1914         } else if (IS_GEN9_LP(dev_priv)) {
1915                 if (encoder->type == INTEL_OUTPUT_EDP)
1916                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
1917                 else
1918                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
1919         } else {
1920                 if (encoder->type == INTEL_OUTPUT_EDP)
1921                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
1922                 else
1923                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
1924         }
1925
1926         if (WARN_ON(n_entries < 1))
1927                 n_entries = 1;
1928         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1929                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1930
1931         return index_to_dp_signal_levels[n_entries - 1] &
1932                 DP_TRAIN_VOLTAGE_SWING_MASK;
1933 }
1934
1935 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
1936                                    int level, enum intel_output_type type)
1937 {
1938         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1939         const struct cnl_ddi_buf_trans *ddi_translations;
1940         enum port port = encoder->port;
1941         int n_entries, ln;
1942         u32 val;
1943
1944         if (type == INTEL_OUTPUT_HDMI)
1945                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
1946         else if (type == INTEL_OUTPUT_EDP)
1947                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
1948         else
1949                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
1950
1951         if (WARN_ON_ONCE(!ddi_translations))
1952                 return;
1953         if (WARN_ON_ONCE(level >= n_entries))
1954                 level = n_entries - 1;
1955
1956         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1957         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1958         val &= ~SCALING_MODE_SEL_MASK;
1959         val |= SCALING_MODE_SEL(2);
1960         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1961
1962         /* Program PORT_TX_DW2 */
1963         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1964         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1965                  RCOMP_SCALAR_MASK);
1966         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1967         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1968         /* Rcomp scalar is fixed as 0x98 for every table entry */
1969         val |= RCOMP_SCALAR(0x98);
1970         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
1971
1972         /* Program PORT_TX_DW4 */
1973         /* We cannot write to GRP. It would overrite individual loadgen */
1974         for (ln = 0; ln < 4; ln++) {
1975                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1976                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1977                          CURSOR_COEFF_MASK);
1978                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1979                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1980                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1981                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
1982         }
1983
1984         /* Program PORT_TX_DW5 */
1985         /* All DW5 values are fixed for every table entry */
1986         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1987         val &= ~RTERM_SELECT_MASK;
1988         val |= RTERM_SELECT(6);
1989         val |= TAP3_DISABLE;
1990         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1991
1992         /* Program PORT_TX_DW7 */
1993         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1994         val &= ~N_SCALAR_MASK;
1995         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1996         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
1997 }
1998
1999 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2000                                     int level, enum intel_output_type type)
2001 {
2002         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2003         enum port port = encoder->port;
2004         int width, rate, ln;
2005         u32 val;
2006
2007         if (type == INTEL_OUTPUT_HDMI) {
2008                 width = 4;
2009                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2010         } else {
2011                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2012
2013                 width = intel_dp->lane_count;
2014                 rate = intel_dp->link_rate;
2015         }
2016
2017         /*
2018          * 1. If port type is eDP or DP,
2019          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2020          * else clear to 0b.
2021          */
2022         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2023         if (type != INTEL_OUTPUT_HDMI)
2024                 val |= COMMON_KEEPER_EN;
2025         else
2026                 val &= ~COMMON_KEEPER_EN;
2027         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2028
2029         /* 2. Program loadgen select */
2030         /*
2031          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2032          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2033          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2034          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2035          */
2036         for (ln = 0; ln <= 3; ln++) {
2037                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2038                 val &= ~LOADGEN_SELECT;
2039
2040                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2041                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2042                         val |= LOADGEN_SELECT;
2043                 }
2044                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2045         }
2046
2047         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2048         val = I915_READ(CNL_PORT_CL1CM_DW5);
2049         val |= SUS_CLOCK_CONFIG;
2050         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2051
2052         /* 4. Clear training enable to change swing values */
2053         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2054         val &= ~TX_TRAINING_EN;
2055         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2056
2057         /* 5. Program swing and de-emphasis */
2058         cnl_ddi_vswing_program(encoder, level, type);
2059
2060         /* 6. Set training enable to trigger update */
2061         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2062         val |= TX_TRAINING_EN;
2063         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2064 }
2065
2066 static uint32_t translate_signal_level(int signal_levels)
2067 {
2068         int i;
2069
2070         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2071                 if (index_to_dp_signal_levels[i] == signal_levels)
2072                         return i;
2073         }
2074
2075         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2076              signal_levels);
2077
2078         return 0;
2079 }
2080
2081 static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2082 {
2083         uint8_t train_set = intel_dp->train_set[0];
2084         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2085                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2086
2087         return translate_signal_level(signal_levels);
2088 }
2089
2090 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2091 {
2092         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2093         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2094         struct intel_encoder *encoder = &dport->base;
2095         int level = intel_ddi_dp_level(intel_dp);
2096
2097         if (IS_CANNONLAKE(dev_priv))
2098                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2099         else
2100                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2101
2102         return 0;
2103 }
2104
2105 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2106 {
2107         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2108         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2109         struct intel_encoder *encoder = &dport->base;
2110         int level = intel_ddi_dp_level(intel_dp);
2111
2112         if (IS_GEN9_BC(dev_priv))
2113                 skl_ddi_set_iboost(encoder, level, encoder->type);
2114
2115         return DDI_BUF_TRANS_SELECT(level);
2116 }
2117
2118 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2119                                  const struct intel_shared_dpll *pll)
2120 {
2121         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2122         enum port port = encoder->port;
2123         uint32_t val;
2124
2125         if (WARN_ON(!pll))
2126                 return;
2127
2128         mutex_lock(&dev_priv->dpll_lock);
2129
2130         if (IS_CANNONLAKE(dev_priv)) {
2131                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2132                 val = I915_READ(DPCLKA_CFGCR0);
2133                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2134                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
2135                 I915_WRITE(DPCLKA_CFGCR0, val);
2136
2137                 /*
2138                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2139                  * This step and the step before must be done with separate
2140                  * register writes.
2141                  */
2142                 val = I915_READ(DPCLKA_CFGCR0);
2143                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2144                 I915_WRITE(DPCLKA_CFGCR0, val);
2145         } else if (IS_GEN9_BC(dev_priv)) {
2146                 /* DDI -> PLL mapping  */
2147                 val = I915_READ(DPLL_CTRL2);
2148
2149                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2150                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2151                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
2152                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2153
2154                 I915_WRITE(DPLL_CTRL2, val);
2155
2156         } else if (INTEL_GEN(dev_priv) < 9) {
2157                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2158         }
2159
2160         mutex_unlock(&dev_priv->dpll_lock);
2161 }
2162
2163 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2164 {
2165         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2166         enum port port = encoder->port;
2167
2168         if (IS_CANNONLAKE(dev_priv))
2169                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2170                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2171         else if (IS_GEN9_BC(dev_priv))
2172                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2173                            DPLL_CTRL2_DDI_CLK_OFF(port));
2174         else if (INTEL_GEN(dev_priv) < 9)
2175                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2176 }
2177
2178 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2179                                     const struct intel_crtc_state *crtc_state,
2180                                     const struct drm_connector_state *conn_state)
2181 {
2182         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2183         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2184         enum port port = encoder->port;
2185         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2186         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2187         int level = intel_ddi_dp_level(intel_dp);
2188
2189         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
2190
2191         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2192                                  crtc_state->lane_count, is_mst);
2193
2194         intel_edp_panel_on(intel_dp);
2195
2196         intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2197
2198         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2199
2200         if (IS_CANNONLAKE(dev_priv))
2201                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2202         else if (IS_GEN9_LP(dev_priv))
2203                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2204         else
2205                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2206
2207         intel_ddi_init_dp_buf_reg(encoder);
2208         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2209         intel_dp_start_link_train(intel_dp);
2210         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2211                 intel_dp_stop_link_train(intel_dp);
2212 }
2213
2214 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2215                                       const struct intel_crtc_state *crtc_state,
2216                                       const struct drm_connector_state *conn_state)
2217 {
2218         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2219         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2220         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2221         enum port port = encoder->port;
2222         int level = intel_ddi_hdmi_level(dev_priv, port);
2223         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2224
2225         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2226         intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2227
2228         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2229
2230         if (IS_CANNONLAKE(dev_priv))
2231                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2232         else if (IS_GEN9_LP(dev_priv))
2233                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2234         else
2235                 intel_prepare_hdmi_ddi_buffers(encoder, level);
2236
2237         if (IS_GEN9_BC(dev_priv))
2238                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
2239
2240         intel_dig_port->set_infoframes(&encoder->base,
2241                                        crtc_state->has_infoframe,
2242                                        crtc_state, conn_state);
2243 }
2244
2245 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
2246                                  const struct intel_crtc_state *crtc_state,
2247                                  const struct drm_connector_state *conn_state)
2248 {
2249         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2250         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2251         enum pipe pipe = crtc->pipe;
2252
2253         /*
2254          * When called from DP MST code:
2255          * - conn_state will be NULL
2256          * - encoder will be the main encoder (ie. mst->primary)
2257          * - the main connector associated with this port
2258          *   won't be active or linked to a crtc
2259          * - crtc_state will be the state of the first stream to
2260          *   be activated on this port, and it may not be the same
2261          *   stream that will be deactivated last, but each stream
2262          *   should have a state that is identical when it comes to
2263          *   the DP link parameteres
2264          */
2265
2266         WARN_ON(crtc_state->has_pch_encoder);
2267
2268         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2269
2270         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2271                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
2272         else
2273                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
2274 }
2275
2276 static void intel_disable_ddi_buf(struct intel_encoder *encoder)
2277 {
2278         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2279         enum port port = encoder->port;
2280         bool wait = false;
2281         u32 val;
2282
2283         val = I915_READ(DDI_BUF_CTL(port));
2284         if (val & DDI_BUF_CTL_ENABLE) {
2285                 val &= ~DDI_BUF_CTL_ENABLE;
2286                 I915_WRITE(DDI_BUF_CTL(port), val);
2287                 wait = true;
2288         }
2289
2290         val = I915_READ(DP_TP_CTL(port));
2291         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2292         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2293         I915_WRITE(DP_TP_CTL(port), val);
2294
2295         if (wait)
2296                 intel_wait_ddi_buf_idle(dev_priv, port);
2297 }
2298
2299 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
2300                                       const struct intel_crtc_state *old_crtc_state,
2301                                       const struct drm_connector_state *old_conn_state)
2302 {
2303         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2304         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2305         struct intel_dp *intel_dp = &dig_port->dp;
2306
2307         /*
2308          * Power down sink before disabling the port, otherwise we end
2309          * up getting interrupts from the sink on detecting link loss.
2310          */
2311         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2312
2313         intel_disable_ddi_buf(encoder);
2314
2315         intel_edp_panel_vdd_on(intel_dp);
2316         intel_edp_panel_off(intel_dp);
2317
2318         intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2319
2320         intel_ddi_clk_disable(encoder);
2321 }
2322
2323 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
2324                                         const struct intel_crtc_state *old_crtc_state,
2325                                         const struct drm_connector_state *old_conn_state)
2326 {
2327         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2328         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2329         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2330
2331         intel_disable_ddi_buf(encoder);
2332
2333         dig_port->set_infoframes(&encoder->base, false,
2334                                  old_crtc_state, old_conn_state);
2335
2336         intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2337
2338         intel_ddi_clk_disable(encoder);
2339
2340         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2341 }
2342
2343 static void intel_ddi_post_disable(struct intel_encoder *encoder,
2344                                    const struct intel_crtc_state *old_crtc_state,
2345                                    const struct drm_connector_state *old_conn_state)
2346 {
2347         /*
2348          * When called from DP MST code:
2349          * - old_conn_state will be NULL
2350          * - encoder will be the main encoder (ie. mst->primary)
2351          * - the main connector associated with this port
2352          *   won't be active or linked to a crtc
2353          * - old_crtc_state will be the state of the last stream to
2354          *   be deactivated on this port, and it may not be the same
2355          *   stream that was activated last, but each stream
2356          *   should have a state that is identical when it comes to
2357          *   the DP link parameteres
2358          */
2359
2360         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2361                 intel_ddi_post_disable_hdmi(encoder,
2362                                             old_crtc_state, old_conn_state);
2363         else
2364                 intel_ddi_post_disable_dp(encoder,
2365                                           old_crtc_state, old_conn_state);
2366 }
2367
2368 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
2369                                 const struct intel_crtc_state *old_crtc_state,
2370                                 const struct drm_connector_state *old_conn_state)
2371 {
2372         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2373         uint32_t val;
2374
2375         /*
2376          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2377          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2378          * step 13 is the correct place for it. Step 18 is where it was
2379          * originally before the BUN.
2380          */
2381         val = I915_READ(FDI_RX_CTL(PIPE_A));
2382         val &= ~FDI_RX_ENABLE;
2383         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2384
2385         intel_disable_ddi_buf(encoder);
2386         intel_ddi_clk_disable(encoder);
2387
2388         val = I915_READ(FDI_RX_MISC(PIPE_A));
2389         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2390         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2391         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2392
2393         val = I915_READ(FDI_RX_CTL(PIPE_A));
2394         val &= ~FDI_PCDCLK;
2395         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2396
2397         val = I915_READ(FDI_RX_CTL(PIPE_A));
2398         val &= ~FDI_RX_PLL_ENABLE;
2399         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2400 }
2401
2402 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
2403                                 const struct intel_crtc_state *crtc_state,
2404                                 const struct drm_connector_state *conn_state)
2405 {
2406         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2407         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2408         enum port port = encoder->port;
2409
2410         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
2411                 intel_dp_stop_link_train(intel_dp);
2412
2413         intel_edp_backlight_on(crtc_state, conn_state);
2414         intel_psr_enable(intel_dp, crtc_state);
2415         intel_edp_drrs_enable(intel_dp, crtc_state);
2416
2417         if (crtc_state->has_audio)
2418                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2419 }
2420
2421 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
2422                                   const struct intel_crtc_state *crtc_state,
2423                                   const struct drm_connector_state *conn_state)
2424 {
2425         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2426         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2427         enum port port = encoder->port;
2428
2429         intel_hdmi_handle_sink_scrambling(encoder,
2430                                           conn_state->connector,
2431                                           crtc_state->hdmi_high_tmds_clock_ratio,
2432                                           crtc_state->hdmi_scrambling);
2433
2434         /* Display WA #1143: skl,kbl,cfl */
2435         if (IS_GEN9_BC(dev_priv)) {
2436                 /*
2437                  * For some reason these chicken bits have been
2438                  * stuffed into a transcoder register, event though
2439                  * the bits affect a specific DDI port rather than
2440                  * a specific transcoder.
2441                  */
2442                 static const enum transcoder port_to_transcoder[] = {
2443                         [PORT_A] = TRANSCODER_EDP,
2444                         [PORT_B] = TRANSCODER_A,
2445                         [PORT_C] = TRANSCODER_B,
2446                         [PORT_D] = TRANSCODER_C,
2447                         [PORT_E] = TRANSCODER_A,
2448                 };
2449                 enum transcoder transcoder = port_to_transcoder[port];
2450                 u32 val;
2451
2452                 val = I915_READ(CHICKEN_TRANS(transcoder));
2453
2454                 if (port == PORT_E)
2455                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
2456                                 DDIE_TRAINING_OVERRIDE_VALUE;
2457                 else
2458                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
2459                                 DDI_TRAINING_OVERRIDE_VALUE;
2460
2461                 I915_WRITE(CHICKEN_TRANS(transcoder), val);
2462                 POSTING_READ(CHICKEN_TRANS(transcoder));
2463
2464                 udelay(1);
2465
2466                 if (port == PORT_E)
2467                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
2468                                  DDIE_TRAINING_OVERRIDE_VALUE);
2469                 else
2470                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
2471                                  DDI_TRAINING_OVERRIDE_VALUE);
2472
2473                 I915_WRITE(CHICKEN_TRANS(transcoder), val);
2474         }
2475
2476         /* In HDMI/DVI mode, the port width, and swing/emphasis values
2477          * are ignored so nothing special needs to be done besides
2478          * enabling the port.
2479          */
2480         I915_WRITE(DDI_BUF_CTL(port),
2481                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
2482
2483         if (crtc_state->has_audio)
2484                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2485 }
2486
2487 static void intel_enable_ddi(struct intel_encoder *encoder,
2488                              const struct intel_crtc_state *crtc_state,
2489                              const struct drm_connector_state *conn_state)
2490 {
2491         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2492                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
2493         else
2494                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
2495
2496         /* Enable hdcp if it's desired */
2497         if (conn_state->content_protection ==
2498             DRM_MODE_CONTENT_PROTECTION_DESIRED)
2499                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
2500 }
2501
2502 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
2503                                  const struct intel_crtc_state *old_crtc_state,
2504                                  const struct drm_connector_state *old_conn_state)
2505 {
2506         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2507
2508         intel_dp->link_trained = false;
2509
2510         if (old_crtc_state->has_audio)
2511                 intel_audio_codec_disable(encoder,
2512                                           old_crtc_state, old_conn_state);
2513
2514         intel_edp_drrs_disable(intel_dp, old_crtc_state);
2515         intel_psr_disable(intel_dp, old_crtc_state);
2516         intel_edp_backlight_off(old_conn_state);
2517 }
2518
2519 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
2520                                    const struct intel_crtc_state *old_crtc_state,
2521                                    const struct drm_connector_state *old_conn_state)
2522 {
2523         if (old_crtc_state->has_audio)
2524                 intel_audio_codec_disable(encoder,
2525                                           old_crtc_state, old_conn_state);
2526
2527         intel_hdmi_handle_sink_scrambling(encoder,
2528                                           old_conn_state->connector,
2529                                           false, false);
2530 }
2531
2532 static void intel_disable_ddi(struct intel_encoder *encoder,
2533                               const struct intel_crtc_state *old_crtc_state,
2534                               const struct drm_connector_state *old_conn_state)
2535 {
2536         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
2537
2538         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2539                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
2540         else
2541                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
2542 }
2543
2544 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
2545                                    const struct intel_crtc_state *pipe_config,
2546                                    const struct drm_connector_state *conn_state)
2547 {
2548         uint8_t mask = pipe_config->lane_lat_optim_mask;
2549
2550         bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
2551 }
2552
2553 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2554 {
2555         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2556         struct drm_i915_private *dev_priv =
2557                 to_i915(intel_dig_port->base.base.dev);
2558         enum port port = intel_dig_port->base.port;
2559         uint32_t val;
2560         bool wait = false;
2561
2562         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2563                 val = I915_READ(DDI_BUF_CTL(port));
2564                 if (val & DDI_BUF_CTL_ENABLE) {
2565                         val &= ~DDI_BUF_CTL_ENABLE;
2566                         I915_WRITE(DDI_BUF_CTL(port), val);
2567                         wait = true;
2568                 }
2569
2570                 val = I915_READ(DP_TP_CTL(port));
2571                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2572                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2573                 I915_WRITE(DP_TP_CTL(port), val);
2574                 POSTING_READ(DP_TP_CTL(port));
2575
2576                 if (wait)
2577                         intel_wait_ddi_buf_idle(dev_priv, port);
2578         }
2579
2580         val = DP_TP_CTL_ENABLE |
2581               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2582         if (intel_dp->link_mst)
2583                 val |= DP_TP_CTL_MODE_MST;
2584         else {
2585                 val |= DP_TP_CTL_MODE_SST;
2586                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2587                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2588         }
2589         I915_WRITE(DP_TP_CTL(port), val);
2590         POSTING_READ(DP_TP_CTL(port));
2591
2592         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2593         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2594         POSTING_READ(DDI_BUF_CTL(port));
2595
2596         udelay(600);
2597 }
2598
2599 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
2600                                        enum transcoder cpu_transcoder)
2601 {
2602         if (cpu_transcoder == TRANSCODER_EDP)
2603                 return false;
2604
2605         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
2606                 return false;
2607
2608         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
2609                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
2610 }
2611
2612 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
2613                                          struct intel_crtc_state *crtc_state)
2614 {
2615         if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
2616                 crtc_state->min_voltage_level = 2;
2617 }
2618
2619 void intel_ddi_get_config(struct intel_encoder *encoder,
2620                           struct intel_crtc_state *pipe_config)
2621 {
2622         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2623         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2624         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2625         struct intel_digital_port *intel_dig_port;
2626         u32 temp, flags = 0;
2627
2628         /* XXX: DSI transcoder paranoia */
2629         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2630                 return;
2631
2632         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2633         if (temp & TRANS_DDI_PHSYNC)
2634                 flags |= DRM_MODE_FLAG_PHSYNC;
2635         else
2636                 flags |= DRM_MODE_FLAG_NHSYNC;
2637         if (temp & TRANS_DDI_PVSYNC)
2638                 flags |= DRM_MODE_FLAG_PVSYNC;
2639         else
2640                 flags |= DRM_MODE_FLAG_NVSYNC;
2641
2642         pipe_config->base.adjusted_mode.flags |= flags;
2643
2644         switch (temp & TRANS_DDI_BPC_MASK) {
2645         case TRANS_DDI_BPC_6:
2646                 pipe_config->pipe_bpp = 18;
2647                 break;
2648         case TRANS_DDI_BPC_8:
2649                 pipe_config->pipe_bpp = 24;
2650                 break;
2651         case TRANS_DDI_BPC_10:
2652                 pipe_config->pipe_bpp = 30;
2653                 break;
2654         case TRANS_DDI_BPC_12:
2655                 pipe_config->pipe_bpp = 36;
2656                 break;
2657         default:
2658                 break;
2659         }
2660
2661         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2662         case TRANS_DDI_MODE_SELECT_HDMI:
2663                 pipe_config->has_hdmi_sink = true;
2664                 intel_dig_port = enc_to_dig_port(&encoder->base);
2665
2666                 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
2667                         pipe_config->has_infoframe = true;
2668
2669                 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
2670                         TRANS_DDI_HDMI_SCRAMBLING_MASK)
2671                         pipe_config->hdmi_scrambling = true;
2672                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
2673                         pipe_config->hdmi_high_tmds_clock_ratio = true;
2674                 /* fall through */
2675         case TRANS_DDI_MODE_SELECT_DVI:
2676                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
2677                 pipe_config->lane_count = 4;
2678                 break;
2679         case TRANS_DDI_MODE_SELECT_FDI:
2680                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
2681                 break;
2682         case TRANS_DDI_MODE_SELECT_DP_SST:
2683                 if (encoder->type == INTEL_OUTPUT_EDP)
2684                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2685                 else
2686                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2687                 pipe_config->lane_count =
2688                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2689                 intel_dp_get_m_n(intel_crtc, pipe_config);
2690                 break;
2691         case TRANS_DDI_MODE_SELECT_DP_MST:
2692                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
2693                 pipe_config->lane_count =
2694                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2695                 intel_dp_get_m_n(intel_crtc, pipe_config);
2696                 break;
2697         default:
2698                 break;
2699         }
2700
2701         pipe_config->has_audio =
2702                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
2703
2704         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2705             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2706                 /*
2707                  * This is a big fat ugly hack.
2708                  *
2709                  * Some machines in UEFI boot mode provide us a VBT that has 18
2710                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2711                  * unknown we fail to light up. Yet the same BIOS boots up with
2712                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2713                  * max, not what it tells us to use.
2714                  *
2715                  * Note: This will still be broken if the eDP panel is not lit
2716                  * up by the BIOS, and thus we can't get the mode at module
2717                  * load.
2718                  */
2719                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2720                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2721                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2722         }
2723
2724         intel_ddi_clock_get(encoder, pipe_config);
2725
2726         if (IS_GEN9_LP(dev_priv))
2727                 pipe_config->lane_lat_optim_mask =
2728                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
2729
2730         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
2731 }
2732
2733 static enum intel_output_type
2734 intel_ddi_compute_output_type(struct intel_encoder *encoder,
2735                               struct intel_crtc_state *crtc_state,
2736                               struct drm_connector_state *conn_state)
2737 {
2738         switch (conn_state->connector->connector_type) {
2739         case DRM_MODE_CONNECTOR_HDMIA:
2740                 return INTEL_OUTPUT_HDMI;
2741         case DRM_MODE_CONNECTOR_eDP:
2742                 return INTEL_OUTPUT_EDP;
2743         case DRM_MODE_CONNECTOR_DisplayPort:
2744                 return INTEL_OUTPUT_DP;
2745         default:
2746                 MISSING_CASE(conn_state->connector->connector_type);
2747                 return INTEL_OUTPUT_UNUSED;
2748         }
2749 }
2750
2751 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2752                                      struct intel_crtc_state *pipe_config,
2753                                      struct drm_connector_state *conn_state)
2754 {
2755         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2756         enum port port = encoder->port;
2757         int ret;
2758
2759         if (port == PORT_A)
2760                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2761
2762         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
2763                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
2764         else
2765                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
2766
2767         if (IS_GEN9_LP(dev_priv) && ret)
2768                 pipe_config->lane_lat_optim_mask =
2769                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
2770
2771         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
2772
2773         return ret;
2774
2775 }
2776
2777 static const struct drm_encoder_funcs intel_ddi_funcs = {
2778         .reset = intel_dp_encoder_reset,
2779         .destroy = intel_dp_encoder_destroy,
2780 };
2781
2782 static struct intel_connector *
2783 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2784 {
2785         struct intel_connector *connector;
2786         enum port port = intel_dig_port->base.port;
2787
2788         connector = intel_connector_alloc();
2789         if (!connector)
2790                 return NULL;
2791
2792         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2793         if (!intel_dp_init_connector(intel_dig_port, connector)) {
2794                 kfree(connector);
2795                 return NULL;
2796         }
2797
2798         return connector;
2799 }
2800
2801 static int modeset_pipe(struct drm_crtc *crtc,
2802                         struct drm_modeset_acquire_ctx *ctx)
2803 {
2804         struct drm_atomic_state *state;
2805         struct drm_crtc_state *crtc_state;
2806         int ret;
2807
2808         state = drm_atomic_state_alloc(crtc->dev);
2809         if (!state)
2810                 return -ENOMEM;
2811
2812         state->acquire_ctx = ctx;
2813
2814         crtc_state = drm_atomic_get_crtc_state(state, crtc);
2815         if (IS_ERR(crtc_state)) {
2816                 ret = PTR_ERR(crtc_state);
2817                 goto out;
2818         }
2819
2820         crtc_state->mode_changed = true;
2821
2822         ret = drm_atomic_add_affected_connectors(state, crtc);
2823         if (ret)
2824                 goto out;
2825
2826         ret = drm_atomic_add_affected_planes(state, crtc);
2827         if (ret)
2828                 goto out;
2829
2830         ret = drm_atomic_commit(state);
2831         if (ret)
2832                 goto out;
2833
2834         return 0;
2835
2836  out:
2837         drm_atomic_state_put(state);
2838
2839         return ret;
2840 }
2841
2842 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
2843                                  struct drm_modeset_acquire_ctx *ctx)
2844 {
2845         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2846         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
2847         struct intel_connector *connector = hdmi->attached_connector;
2848         struct i2c_adapter *adapter =
2849                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2850         struct drm_connector_state *conn_state;
2851         struct intel_crtc_state *crtc_state;
2852         struct intel_crtc *crtc;
2853         u8 config;
2854         int ret;
2855
2856         if (!connector || connector->base.status != connector_status_connected)
2857                 return 0;
2858
2859         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
2860                                ctx);
2861         if (ret)
2862                 return ret;
2863
2864         conn_state = connector->base.state;
2865
2866         crtc = to_intel_crtc(conn_state->crtc);
2867         if (!crtc)
2868                 return 0;
2869
2870         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
2871         if (ret)
2872                 return ret;
2873
2874         crtc_state = to_intel_crtc_state(crtc->base.state);
2875
2876         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
2877
2878         if (!crtc_state->base.active)
2879                 return 0;
2880
2881         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
2882             !crtc_state->hdmi_scrambling)
2883                 return 0;
2884
2885         if (conn_state->commit &&
2886             !try_wait_for_completion(&conn_state->commit->hw_done))
2887                 return 0;
2888
2889         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
2890         if (ret < 0) {
2891                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
2892                 return 0;
2893         }
2894
2895         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
2896             crtc_state->hdmi_high_tmds_clock_ratio &&
2897             !!(config & SCDC_SCRAMBLING_ENABLE) ==
2898             crtc_state->hdmi_scrambling)
2899                 return 0;
2900
2901         /*
2902          * HDMI 2.0 says that one should not send scrambled data
2903          * prior to configuring the sink scrambling, and that
2904          * TMDS clock/data transmission should be suspended when
2905          * changing the TMDS clock rate in the sink. So let's
2906          * just do a full modeset here, even though some sinks
2907          * would be perfectly happy if were to just reconfigure
2908          * the SCDC settings on the fly.
2909          */
2910         return modeset_pipe(&crtc->base, ctx);
2911 }
2912
2913 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
2914                               struct intel_connector *connector)
2915 {
2916         struct drm_modeset_acquire_ctx ctx;
2917         bool changed;
2918         int ret;
2919
2920         changed = intel_encoder_hotplug(encoder, connector);
2921
2922         drm_modeset_acquire_init(&ctx, 0);
2923
2924         for (;;) {
2925                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
2926                         ret = intel_hdmi_reset_link(encoder, &ctx);
2927                 else
2928                         ret = intel_dp_retrain_link(encoder, &ctx);
2929
2930                 if (ret == -EDEADLK) {
2931                         drm_modeset_backoff(&ctx);
2932                         continue;
2933                 }
2934
2935                 break;
2936         }
2937
2938         drm_modeset_drop_locks(&ctx);
2939         drm_modeset_acquire_fini(&ctx);
2940         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
2941
2942         return changed;
2943 }
2944
2945 static struct intel_connector *
2946 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2947 {
2948         struct intel_connector *connector;
2949         enum port port = intel_dig_port->base.port;
2950
2951         connector = intel_connector_alloc();
2952         if (!connector)
2953                 return NULL;
2954
2955         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2956         intel_hdmi_init_connector(intel_dig_port, connector);
2957
2958         return connector;
2959 }
2960
2961 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
2962 {
2963         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2964
2965         if (dport->base.port != PORT_A)
2966                 return false;
2967
2968         if (dport->saved_port_bits & DDI_A_4_LANES)
2969                 return false;
2970
2971         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
2972          *                     supported configuration
2973          */
2974         if (IS_GEN9_LP(dev_priv))
2975                 return true;
2976
2977         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
2978          *             one who does also have a full A/E split called
2979          *             DDI_F what makes DDI_E useless. However for this
2980          *             case let's trust VBT info.
2981          */
2982         if (IS_CANNONLAKE(dev_priv) &&
2983             !intel_bios_is_port_present(dev_priv, PORT_E))
2984                 return true;
2985
2986         return false;
2987 }
2988
2989 static int
2990 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
2991 {
2992         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
2993         enum port port = intel_dport->base.port;
2994         int max_lanes = 4;
2995
2996         if (INTEL_GEN(dev_priv) >= 11)
2997                 return max_lanes;
2998
2999         if (port == PORT_A || port == PORT_E) {
3000                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
3001                         max_lanes = port == PORT_A ? 4 : 0;
3002                 else
3003                         /* Both A and E share 2 lanes */
3004                         max_lanes = 2;
3005         }
3006
3007         /*
3008          * Some BIOS might fail to set this bit on port A if eDP
3009          * wasn't lit up at boot.  Force this bit set when needed
3010          * so we use the proper lane count for our calculations.
3011          */
3012         if (intel_ddi_a_force_4_lanes(intel_dport)) {
3013                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
3014                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
3015                 max_lanes = 4;
3016         }
3017
3018         return max_lanes;
3019 }
3020
3021 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
3022 {
3023         struct intel_digital_port *intel_dig_port;
3024         struct intel_encoder *intel_encoder;
3025         struct drm_encoder *encoder;
3026         bool init_hdmi, init_dp, init_lspcon = false;
3027
3028
3029         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3030                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3031         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3032
3033         if (intel_bios_is_lspcon_present(dev_priv, port)) {
3034                 /*
3035                  * Lspcon device needs to be driven with DP connector
3036                  * with special detection sequence. So make sure DP
3037                  * is initialized before lspcon.
3038                  */
3039                 init_dp = true;
3040                 init_lspcon = true;
3041                 init_hdmi = false;
3042                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
3043         }
3044
3045         if (!init_dp && !init_hdmi) {
3046                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
3047                               port_name(port));
3048                 return;
3049         }
3050
3051         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3052         if (!intel_dig_port)
3053                 return;
3054
3055         intel_encoder = &intel_dig_port->base;
3056         encoder = &intel_encoder->base;
3057
3058         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
3059                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
3060
3061         intel_encoder->hotplug = intel_ddi_hotplug;
3062         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
3063         intel_encoder->compute_config = intel_ddi_compute_config;
3064         intel_encoder->enable = intel_enable_ddi;
3065         if (IS_GEN9_LP(dev_priv))
3066                 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
3067         intel_encoder->pre_enable = intel_ddi_pre_enable;
3068         intel_encoder->disable = intel_disable_ddi;
3069         intel_encoder->post_disable = intel_ddi_post_disable;
3070         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
3071         intel_encoder->get_config = intel_ddi_get_config;
3072         intel_encoder->suspend = intel_dp_encoder_suspend;
3073         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
3074         intel_encoder->type = INTEL_OUTPUT_DDI;
3075         intel_encoder->power_domain = intel_port_to_power_domain(port);
3076         intel_encoder->port = port;
3077         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3078         intel_encoder->cloneable = 0;
3079
3080         if (INTEL_GEN(dev_priv) >= 11)
3081                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3082                         DDI_BUF_PORT_REVERSAL;
3083         else
3084                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3085                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
3086         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3087         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
3088
3089         switch (port) {
3090         case PORT_A:
3091                 intel_dig_port->ddi_io_power_domain =
3092                         POWER_DOMAIN_PORT_DDI_A_IO;
3093                 break;
3094         case PORT_B:
3095                 intel_dig_port->ddi_io_power_domain =
3096                         POWER_DOMAIN_PORT_DDI_B_IO;
3097                 break;
3098         case PORT_C:
3099                 intel_dig_port->ddi_io_power_domain =
3100                         POWER_DOMAIN_PORT_DDI_C_IO;
3101                 break;
3102         case PORT_D:
3103                 intel_dig_port->ddi_io_power_domain =
3104                         POWER_DOMAIN_PORT_DDI_D_IO;
3105                 break;
3106         case PORT_E:
3107                 intel_dig_port->ddi_io_power_domain =
3108                         POWER_DOMAIN_PORT_DDI_E_IO;
3109                 break;
3110         case PORT_F:
3111                 intel_dig_port->ddi_io_power_domain =
3112                         POWER_DOMAIN_PORT_DDI_F_IO;
3113                 break;
3114         default:
3115                 MISSING_CASE(port);
3116         }
3117
3118         intel_infoframe_init(intel_dig_port);
3119
3120         if (init_dp) {
3121                 if (!intel_ddi_init_dp_connector(intel_dig_port))
3122                         goto err;
3123
3124                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
3125                 dev_priv->hotplug.irq_port[port] = intel_dig_port;
3126         }
3127
3128         /* In theory we don't need the encoder->type check, but leave it just in
3129          * case we have some really bad VBTs... */
3130         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3131                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3132                         goto err;
3133         }
3134
3135         if (init_lspcon) {
3136                 if (lspcon_init(intel_dig_port))
3137                         /* TODO: handle hdmi info frame part */
3138                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
3139                                 port_name(port));
3140                 else
3141                         /*
3142                          * LSPCON init faied, but DP init was success, so
3143                          * lets try to drive as DP++ port.
3144                          */
3145                         DRM_ERROR("LSPCON init failed on port %c\n",
3146                                 port_name(port));
3147         }
3148
3149         return;
3150
3151 err:
3152         drm_encoder_cleanup(encoder);
3153         kfree(intel_dig_port);
3154 }