drivers/rtc/rtc-ds1685.c

   1 /*
   2  * An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time
   3  * chips.
   4  *
   5  * Copyright (C) 2011-2014 Joshua Kinard <[email protected]>.
   6  * Copyright (C) 2009 Matthias Fuchs <[email protected]>.
   7  *
   8  * References:
   9  *    DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
  10  *    DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
  11  *    DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
  12  *    Application Note 90, Using the Multiplex Bus RTC Extended Features.
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18
  19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  20
  21 #include <linux/bcd.h>
  22 #include <linux/delay.h>
  23 #include <linux/io.h>
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/rtc.h>
  27 #include <linux/workqueue.h>
  28
  29 #include <linux/rtc/ds1685.h>
  30
  31 #ifdef CONFIG_PROC_FS
  32 #include <linux/proc_fs.h>
  33 #endif
  34
  35
  36 /* ----------------------------------------------------------------------- */
  37 /* Standard read/write functions if platform does not provide overrides */
  38
  39 /**
  40  * ds1685_read - read a value from an rtc register.
  41  * @rtc: pointer to the ds1685 rtc structure.
  42  * @reg: the register address to read.
  43  */
  44 static u8
  45 ds1685_read(struct ds1685_priv *rtc, int reg)
  46 {
  47         return readb((u8 __iomem *)rtc->regs +
  48                      (reg * rtc->regstep));
  49 }
  50
  51 /**
  52  * ds1685_write - write a value to an rtc register.
  53  * @rtc: pointer to the ds1685 rtc structure.
  54  * @reg: the register address to write.
  55  * @value: value to write to the register.
  56  */
  57 static void
  58 ds1685_write(struct ds1685_priv *rtc, int reg, u8 value)
  59 {
  60         writeb(value, ((u8 __iomem *)rtc->regs +
  61                        (reg * rtc->regstep)));
  62 }
  63 /* ----------------------------------------------------------------------- */
  64
  65
  66 /* ----------------------------------------------------------------------- */
  67 /* Inlined functions */
  68
  69 /**
  70  * ds1685_rtc_bcd2bin - bcd2bin wrapper in case platform doesn't support BCD.
  71  * @rtc: pointer to the ds1685 rtc structure.
  72  * @val: u8 time value to consider converting.
  73  * @bcd_mask: u8 mask value if BCD mode is used.
  74  * @bin_mask: u8 mask value if BIN mode is used.
  75  *
  76  * Returns the value, converted to BIN if originally in BCD and bcd_mode TRUE.
  77  */
  78 static inline u8
  79 ds1685_rtc_bcd2bin(struct ds1685_priv *rtc, u8 val, u8 bcd_mask, u8 bin_mask)
  80 {
  81         if (rtc->bcd_mode)
  82                 return (bcd2bin(val) & bcd_mask);
  83
  84         return (val & bin_mask);
  85 }
  86
  87 /**
  88  * ds1685_rtc_bin2bcd - bin2bcd wrapper in case platform doesn't support BCD.
  89  * @rtc: pointer to the ds1685 rtc structure.
  90  * @val: u8 time value to consider converting.
  91  * @bin_mask: u8 mask value if BIN mode is used.
  92  * @bcd_mask: u8 mask value if BCD mode is used.
  93  *
  94  * Returns the value, converted to BCD if originally in BIN and bcd_mode TRUE.
  95  */
  96 static inline u8
  97 ds1685_rtc_bin2bcd(struct ds1685_priv *rtc, u8 val, u8 bin_mask, u8 bcd_mask)
  98 {
  99         if (rtc->bcd_mode)
 100                 return (bin2bcd(val) & bcd_mask);
 101
 102         return (val & bin_mask);
 103 }
 104
 105 /**
 106  * s1685_rtc_check_mday - check validity of the day of month.
 107  * @rtc: pointer to the ds1685 rtc structure.
 108  * @mday: day of month.
 109  *
 110  * Returns -EDOM if the day of month is not within 1..31 range.
 111  */
 112 static inline int
 113 ds1685_rtc_check_mday(struct ds1685_priv *rtc, u8 mday)
 114 {
 115         if (rtc->bcd_mode) {
 116                 if (mday < 0x01 || mday > 0x31 || (mday & 0x0f) > 0x09)
 117                         return -EDOM;
 118         } else {
 119                 if (mday < 1 || mday > 31)
 120                         return -EDOM;
 121         }
 122         return 0;
 123 }
 124
 125 /**
 126  * ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0.
 127  * @rtc: pointer to the ds1685 rtc structure.
 128  */
 129 static inline void
 130 ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc)
 131 {
 132         rtc->write(rtc, RTC_CTRL_A,
 133                    (rtc->read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0)));
 134 }
 135
 136 /**
 137  * ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1.
 138  * @rtc: pointer to the ds1685 rtc structure.
 139  */
 140 static inline void
 141 ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc)
 142 {
 143         rtc->write(rtc, RTC_CTRL_A,
 144                    (rtc->read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0));
 145 }
 146
 147 /**
 148  * ds1685_rtc_begin_data_access - prepare the rtc for data access.
 149  * @rtc: pointer to the ds1685 rtc structure.
 150  *
 151  * This takes several steps to prepare the rtc for access to get/set time
 152  * and alarm values from the rtc registers:
 153  *  - Sets the SET bit in Control Register B.
 154  *  - Reads Ext Control Register 4A and checks the INCR bit.
 155  *  - If INCR is active, a short delay is added before Ext Control Register 4A
 156  *    is read again in a loop until INCR is inactive.
 157  *  - Switches the rtc to bank 1.  This allows access to all relevant
 158  *    data for normal rtc operation, as bank 0 contains only the nvram.
 159  */
 160 static inline void
 161 ds1685_rtc_begin_data_access(struct ds1685_priv *rtc)
 162 {
 163         /* Set the SET bit in Ctrl B */
 164         rtc->write(rtc, RTC_CTRL_B,
 165                    (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
 166
 167         /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
 168         while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
 169                 cpu_relax();
 170
 171         /* Switch to Bank 1 */
 172         ds1685_rtc_switch_to_bank1(rtc);
 173 }
 174
 175 /**
 176  * ds1685_rtc_end_data_access - end data access on the rtc.
 177  * @rtc: pointer to the ds1685 rtc structure.
 178  *
 179  * This ends what was started by ds1685_rtc_begin_data_access:
 180  *  - Switches the rtc back to bank 0.
 181  *  - Clears the SET bit in Control Register B.
 182  */
 183 static inline void
 184 ds1685_rtc_end_data_access(struct ds1685_priv *rtc)
 185 {
 186         /* Switch back to Bank 0 */
 187         ds1685_rtc_switch_to_bank1(rtc);
 188
 189         /* Clear the SET bit in Ctrl B */
 190         rtc->write(rtc, RTC_CTRL_B,
 191                    (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
 192 }
 193
 194 /**
 195  * ds1685_rtc_begin_ctrl_access - prepare the rtc for ctrl access.
 196  * @rtc: pointer to the ds1685 rtc structure.
 197  * @flags: irq flags variable for spin_lock_irqsave.
 198  *
 199  * This takes several steps to prepare the rtc for access to read just the
 200  * control registers:
 201  *  - Sets a spinlock on the rtc IRQ.
 202  *  - Switches the rtc to bank 1.  This allows access to the two extended
 203  *    control registers.
 204  *
 205  * Only use this where you are certain another lock will not be held.
 206  */
 207 static inline void
 208 ds1685_rtc_begin_ctrl_access(struct ds1685_priv *rtc, unsigned long *flags)
 209 {
 210         spin_lock_irqsave(&rtc->lock, *flags);
 211         ds1685_rtc_switch_to_bank1(rtc);
 212 }
 213
 214 /**
 215  * ds1685_rtc_end_ctrl_access - end ctrl access on the rtc.
 216  * @rtc: pointer to the ds1685 rtc structure.
 217  * @flags: irq flags variable for spin_unlock_irqrestore.
 218  *
 219  * This ends what was started by ds1685_rtc_begin_ctrl_access:
 220  *  - Switches the rtc back to bank 0.
 221  *  - Unsets the spinlock on the rtc IRQ.
 222  */
 223 static inline void
 224 ds1685_rtc_end_ctrl_access(struct ds1685_priv *rtc, unsigned long flags)
 225 {
 226         ds1685_rtc_switch_to_bank0(rtc);
 227         spin_unlock_irqrestore(&rtc->lock, flags);
 228 }
 229
 230 /**
 231  * ds1685_rtc_get_ssn - retrieve the silicon serial number.
 232  * @rtc: pointer to the ds1685 rtc structure.
 233  * @ssn: u8 array to hold the bits of the silicon serial number.
 234  *
 235  * This number starts at 0x40, and is 8-bytes long, ending at 0x47. The
 236  * first byte is the model number, the next six bytes are the serial number
 237  * digits, and the final byte is a CRC check byte.  Together, they form the
 238  * silicon serial number.
 239  *
 240  * These values are stored in bank1, so ds1685_rtc_switch_to_bank1 must be
 241  * called first before calling this function, else data will be read out of
 242  * the bank0 NVRAM.  Be sure to call ds1685_rtc_switch_to_bank0 when done.
 243  */
 244 static inline void
 245 ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn)
 246 {
 247         ssn[0] = rtc->read(rtc, RTC_BANK1_SSN_MODEL);
 248         ssn[1] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_1);
 249         ssn[2] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_2);
 250         ssn[3] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_3);
 251         ssn[4] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_4);
 252         ssn[5] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_5);
 253         ssn[6] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_6);
 254         ssn[7] = rtc->read(rtc, RTC_BANK1_SSN_CRC);
 255 }
 256 /* ----------------------------------------------------------------------- */
 257
 258
 259 /* ----------------------------------------------------------------------- */
 260 /* Read/Set Time & Alarm functions */
 261
 262 /**
 263  * ds1685_rtc_read_time - reads the time registers.
 264  * @dev: pointer to device structure.
 265  * @tm: pointer to rtc_time structure.
 266  */
 267 static int
 268 ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm)
 269 {
 270         struct ds1685_priv *rtc = dev_get_drvdata(dev);
 271         u8 ctrlb, century;
 272         u8 seconds, minutes, hours, wday, mday, month, years;
 273
 274         /* Fetch the time info from the RTC registers. */
 275         ds1685_rtc_begin_data_access(rtc);
 276         seconds = rtc->read(rtc, RTC_SECS);
 277         minutes = rtc->read(rtc, RTC_MINS);
 278         hours   = rtc->read(rtc, RTC_HRS);
 279         wday    = rtc->read(rtc, RTC_WDAY);
 280         mday    = rtc->read(rtc, RTC_MDAY);
 281         month   = rtc->read(rtc, RTC_MONTH);
 282         years   = rtc->read(rtc, RTC_YEAR);
 283         century = rtc->read(rtc, RTC_CENTURY);
 284         ctrlb   = rtc->read(rtc, RTC_CTRL_B);
 285         ds1685_rtc_end_data_access(rtc);
 286
 287         /* bcd2bin if needed, perform fixups, and store to rtc_time. */
 288         years        = ds1685_rtc_bcd2bin(rtc, years, RTC_YEAR_BCD_MASK,
 289                                           RTC_YEAR_BIN_MASK);
 290         century      = ds1685_rtc_bcd2bin(rtc, century, RTC_CENTURY_MASK,
 291                                           RTC_CENTURY_MASK);
 292         tm->tm_sec   = ds1685_rtc_bcd2bin(rtc, seconds, RTC_SECS_BCD_MASK,
 293                                           RTC_SECS_BIN_MASK);
 294         tm->tm_min   = ds1685_rtc_bcd2bin(rtc, minutes, RTC_MINS_BCD_MASK,
 295                                           RTC_MINS_BIN_MASK);
 296         tm->tm_hour  = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_24_BCD_MASK,
 297                                           RTC_HRS_24_BIN_MASK);
 298         tm->tm_wday  = (ds1685_rtc_bcd2bin(rtc, wday, RTC_WDAY_MASK,
 299                                            RTC_WDAY_MASK) - 1);
 300         tm->tm_mday  = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
 301                                           RTC_MDAY_BIN_MASK);
 302         tm->tm_mon   = (ds1685_rtc_bcd2bin(rtc, month, RTC_MONTH_BCD_MASK,
 303                                            RTC_MONTH_BIN_MASK) - 1);
 304         tm->tm_year  = ((years + (century * 100)) - 1900);
 305         tm->tm_yday  = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
 306         tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */
 307
 308         return 0;
 309 }
 310
 311 /**
 312  * ds1685_rtc_set_time - sets the time registers.
 313  * @dev: pointer to device structure.
 314  * @tm: pointer to rtc_time structure.
 315  */
 316 static int
 317 ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm)
 318 {
 319         struct ds1685_priv *rtc = dev_get_drvdata(dev);
 320         u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century;
 321
 322         /* Fetch the time info from rtc_time. */
 323         seconds = ds1685_rtc_bin2bcd(rtc, tm->tm_sec, RTC_SECS_BIN_MASK,
 324                                      RTC_SECS_BCD_MASK);
 325         minutes = ds1685_rtc_bin2bcd(rtc, tm->tm_min, RTC_MINS_BIN_MASK,
 326                                      RTC_MINS_BCD_MASK);
 327         hours   = ds1685_rtc_bin2bcd(rtc, tm->tm_hour, RTC_HRS_24_BIN_MASK,
 328                                      RTC_HRS_24_BCD_MASK);
 329         wday    = ds1685_rtc_bin2bcd(rtc, (tm->tm_wday + 1), RTC_WDAY_MASK,
 330                                      RTC_WDAY_MASK);
 331         mday    = ds1685_rtc_bin2bcd(rtc, tm->tm_mday, RTC_MDAY_BIN_MASK,
 332                                      RTC_MDAY_BCD_MASK);
 333         month   = ds1685_rtc_bin2bcd(rtc, (tm->tm_mon + 1), RTC_MONTH_BIN_MASK,
 334                                      RTC_MONTH_BCD_MASK);
 335         years   = ds1685_rtc_bin2bcd(rtc, (tm->tm_year % 100),
 336                                      RTC_YEAR_BIN_MASK, RTC_YEAR_BCD_MASK);
 337         century = ds1685_rtc_bin2bcd(rtc, ((tm->tm_year + 1900) / 100),
 338                                      RTC_CENTURY_MASK, RTC_CENTURY_MASK);
 339
 340         /*
 341          * Perform Sanity Checks:
 342          *   - Months: !> 12, Month Day != 0.
 343          *   - Month Day !> Max days in current month.
 344          *   - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7.
 345          */
 346         if ((tm->tm_mon > 11) || (mday == 0))
 347                 return -EDOM;
 348
 349         if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year))
 350                 return -EDOM;
 351
 352         if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) ||
 353             (tm->tm_sec >= 60)  || (wday > 7))
 354                 return -EDOM;
 355
 356         /*
 357          * Set the data mode to use and store the time values in the
 358          * RTC registers.
 359          */
 360         ds1685_rtc_begin_data_access(rtc);
 361         ctrlb = rtc->read(rtc, RTC_CTRL_B);
 362         if (rtc->bcd_mode)
 363                 ctrlb &= ~(RTC_CTRL_B_DM);
 364         else
 365                 ctrlb |= RTC_CTRL_B_DM;
 366         rtc->write(rtc, RTC_CTRL_B, ctrlb);
 367         rtc->write(rtc, RTC_SECS, seconds);
 368         rtc->write(rtc, RTC_MINS, minutes);
 369         rtc->write(rtc, RTC_HRS, hours);
 370         rtc->write(rtc, RTC_WDAY, wday);
 371         rtc->write(rtc, RTC_MDAY, mday);
 372         rtc->write(rtc, RTC_MONTH, month);
 373         rtc->write(rtc, RTC_YEAR, years);
 374         rtc->write(rtc, RTC_CENTURY, century);
 375         ds1685_rtc_end_data_access(rtc);
 376
 377         return 0;
 378 }
 379
 380 /**
 381  * ds1685_rtc_read_alarm - reads the alarm registers.
 382  * @dev: pointer to device structure.
 383  * @alrm: pointer to rtc_wkalrm structure.
 384  *
 385  * There are three primary alarm registers: seconds, minutes, and hours.
 386  * A fourth alarm register for the month date is also available in bank1 for
 387  * kickstart/wakeup features.  The DS1685/DS1687 manual states that a
 388  * "don't care" value ranging from 0xc0 to 0xff may be written into one or
 389  * more of the three alarm bytes to act as a wildcard value.  The fourth
 390  * byte doesn't support a "don't care" value.
 391  */
 392 static int
 393 ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 394 {
 395         struct ds1685_priv *rtc = dev_get_drvdata(dev);
 396         u8 seconds, minutes, hours, mday, ctrlb, ctrlc;
 397         int ret;
 398
 399         /* Fetch the alarm info from the RTC alarm registers. */
 400         ds1685_rtc_begin_data_access(rtc);
 401         seconds = rtc->read(rtc, RTC_SECS_ALARM);
 402         minutes = rtc->read(rtc, RTC_MINS_ALARM);
 403         hours   = rtc->read(rtc, RTC_HRS_ALARM);
 404         mday    = rtc->read(rtc, RTC_MDAY_ALARM);
 405         ctrlb   = rtc->read(rtc, RTC_CTRL_B);
 406         ctrlc   = rtc->read(rtc, RTC_CTRL_C);
 407         ds1685_rtc_end_data_access(rtc);
 408
 409         /* Check the month date for validity. */
 410         ret = ds1685_rtc_check_mday(rtc, mday);
 411         if (ret)
 412                 return ret;
 413
 414         /*
 415          * Check the three alarm bytes.
 416          *
 417          * The Linux RTC system doesn't support the "don't care" capability
 418          * of this RTC chip.  We check for it anyways in case support is
 419          * added in the future and only assign when we care.
 420          */
 421         if (likely(seconds < 0xc0))
 422                 alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds,
 423                                                        RTC_SECS_BCD_MASK,
 424                                                        RTC_SECS_BIN_MASK);
 425
 426         if (likely(minutes < 0xc0))
 427                 alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes,
 428                                                        RTC_MINS_BCD_MASK,
 429                                                        RTC_MINS_BIN_MASK);
 430
 431         if (likely(hours < 0xc0))
 432                 alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours,
 433                                                         RTC_HRS_24_BCD_MASK,
 434                                                         RTC_HRS_24_BIN_MASK);
 435
 436         /* Write the data to rtc_wkalrm. */
 437         alrm->time.tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
 438                                                 RTC_MDAY_BIN_MASK);
 439         alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE);
 440         alrm->pending = !!(ctrlc & RTC_CTRL_C_AF);
 441
 442         return 0;
 443 }
 444
 445 /**
 446  * ds1685_rtc_set_alarm - sets the alarm in registers.
 447  * @dev: pointer to device structure.
 448  * @alrm: pointer to rtc_wkalrm structure.
 449  */
 450 static int
 451 ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 452 {
 453         struct ds1685_priv *rtc = dev_get_drvdata(dev);
 454         u8 ctrlb, seconds, minutes, hours, mday;
 455         int ret;
 456
 457         /* Fetch the alarm info and convert to BCD. */
 458         seconds = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_sec,
 459                                      RTC_SECS_BIN_MASK,
 460                                      RTC_SECS_BCD_MASK);
 461         minutes = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_min,
 462                                      RTC_MINS_BIN_MASK,
 463                                      RTC_MINS_BCD_MASK);
 464         hours   = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_hour,
 465                                      RTC_HRS_24_BIN_MASK,
 466                                      RTC_HRS_24_BCD_MASK);
 467         mday    = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_mday,
 468                                      RTC_MDAY_BIN_MASK,
 469                                      RTC_MDAY_BCD_MASK);
 470
 471         /* Check the month date for validity. */
 472         ret = ds1685_rtc_check_mday(rtc, mday);
 473         if (ret)
 474                 return ret;
 475
 476         /*
 477          * Check the three alarm bytes.
 478          *
 479          * The Linux RTC system doesn't support the "don't care" capability
 480          * of this RTC chip because rtc_valid_tm tries to validate every
 481          * field, and we only support four fields.  We put the support
 482          * here anyways for the future.
 483          */
 484         if (unlikely(seconds >= 0xc0))
 485                 seconds = 0xff;
 486
 487         if (unlikely(minutes >= 0xc0))
 488                 minutes = 0xff;
 489
 490         if (unlikely(hours >= 0xc0))
 491                 hours = 0xff;
 492
 493         alrm->time.tm_mon       = -1;
 494         alrm->time.tm_year      = -1;
 495         alrm->time.tm_wday      = -1;
 496         alrm->time.tm_yday      = -1;
 497         alrm->time.tm_isdst     = -1;
 498
 499         /* Disable the alarm interrupt first. */
 500         ds1685_rtc_begin_data_access(rtc);
 501         ctrlb = rtc->read(rtc, RTC_CTRL_B);
 502         rtc->write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE)));
 503
 504         /* Read ctrlc to clear RTC_CTRL_C_AF. */
 505         rtc->read(rtc, RTC_CTRL_C);
 506
 507         /*
 508          * Set the data mode to use and store the time values in the
 509          * RTC registers.
 510          */
 511         ctrlb = rtc->read(rtc, RTC_CTRL_B);
 512         if (rtc->bcd_mode)
 513                 ctrlb &= ~(RTC_CTRL_B_DM);
 514         else
 515                 ctrlb |= RTC_CTRL_B_DM;
 516         rtc->write(rtc, RTC_CTRL_B, ctrlb);
 517         rtc->write(rtc, RTC_SECS_ALARM, seconds);
 518         rtc->write(rtc, RTC_MINS_ALARM, minutes);
 519         rtc->write(rtc, RTC_HRS_ALARM, hours);
 520         rtc->write(rtc, RTC_MDAY_ALARM, mday);
 521
 522         /* Re-enable the alarm if needed. */
 523         if (alrm->enabled) {
 524                 ctrlb = rtc->read(rtc, RTC_CTRL_B);
 525                 ctrlb |= RTC_CTRL_B_AIE;
 526                 rtc->write(rtc, RTC_CTRL_B, ctrlb);
 527         }
 528
 529         /* Done! */
 530         ds1685_rtc_end_data_access(rtc);
 531
 532         return 0;
 533 }
 534 /* ----------------------------------------------------------------------- */
 535
 536
 537 /* ----------------------------------------------------------------------- */
 538 /* /dev/rtcX Interface functions */
 539
 540 /**
 541  * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off.
 542  * @dev: pointer to device structure.
 543  * @enabled: flag indicating whether to enable or disable.
 544  */
 545 static int
 546 ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 547 {
 548         struct ds1685_priv *rtc = dev_get_drvdata(dev);
 549         unsigned long flags = 0;
 550
 551         /* Enable/disable the Alarm IRQ-Enable flag. */
 552         spin_lock_irqsave(&rtc->lock, flags);
 553
 554         /* Flip the requisite interrupt-enable bit. */
 555         if (enabled)
 556                 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) |
 557                                              RTC_CTRL_B_AIE));
 558         else
 559                 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) &
 560                                              ~(RTC_CTRL_B_AIE)));
 561
 562         /* Read Control C to clear all the flag bits. */
 563         rtc->read(rtc, RTC_CTRL_C);
 564         spin_unlock_irqrestore(&rtc->lock, flags);
 565
 566         return 0;
 567 }
 568 /* ----------------------------------------------------------------------- */
 569
 570
 571 /* ----------------------------------------------------------------------- */
 572 /* IRQ handler & workqueue. */
 573
 574 /**
 575  * ds1685_rtc_irq_handler - IRQ handler.
 576  * @irq: IRQ number.
 577  * @dev_id: platform device pointer.
 578  */
 579 static irqreturn_t
 580 ds1685_rtc_irq_handler(int irq, void *dev_id)
 581 {
 582         struct platform_device *pdev = dev_id;
 583         struct ds1685_priv *rtc = platform_get_drvdata(pdev);
 584         u8 ctrlb, ctrlc;
 585         unsigned long events = 0;
 586         u8 num_irqs = 0;
 587
 588         /* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */
 589         if (unlikely(!rtc))
 590                 return IRQ_HANDLED;
 591
 592         /* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */
 593         spin_lock(&rtc->lock);
 594         ctrlb = rtc->read(rtc, RTC_CTRL_B);
 595         ctrlc = rtc->read(rtc, RTC_CTRL_C);
 596
 597         /* Is the IRQF bit set? */
 598         if (likely(ctrlc & RTC_CTRL_C_IRQF)) {
 599                 /*
 600                  * We need to determine if it was one of the standard
 601                  * events: PF, AF, or UF.  If so, we handle them and
 602                  * update the RTC core.
 603                  */
 604                 if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) {
 605                         events = RTC_IRQF;
 606
 607                         /* Check for a periodic interrupt. */
 608                         if ((ctrlb & RTC_CTRL_B_PIE) &&
 609                             (ctrlc & RTC_CTRL_C_PF)) {
 610                                 events |= RTC_PF;
 611                                 num_irqs++;
 612                         }
 613
 614                         /* Check for an alarm interrupt. */
 615                         if ((ctrlb & RTC_CTRL_B_AIE) &&
 616                             (ctrlc & RTC_CTRL_C_AF)) {
 617                                 events |= RTC_AF;
 618                                 num_irqs++;
 619                         }
 620
 621                         /* Check for an update interrupt. */
 622                         if ((ctrlb & RTC_CTRL_B_UIE) &&
 623                             (ctrlc & RTC_CTRL_C_UF)) {
 624                                 events |= RTC_UF;
 625                                 num_irqs++;
 626                         }
 627
 628                         rtc_update_irq(rtc->dev, num_irqs, events);
 629                 } else {
 630                         /*
 631                          * One of the "extended" interrupts was received that
 632                          * is not recognized by the RTC core.  These need to
 633                          * be handled in task context as they can call other
 634                          * functions and the time spent in irq context needs
 635                          * to be minimized.  Schedule them into a workqueue
 636                          * and inform the RTC core that the IRQs were handled.
 637                          */
 638                         spin_unlock(&rtc->lock);
 639                         schedule_work(&rtc->work);
 640                         rtc_update_irq(rtc->dev, 0, 0);
 641                         return IRQ_HANDLED;
 642                 }
 643         }
 644         spin_unlock(&rtc->lock);
 645
 646         return events ? IRQ_HANDLED : IRQ_NONE;
 647 }
 648
 649 /**
 650  * ds1685_rtc_work_queue - work queue handler.
 651  * @work: work_struct containing data to work on in task context.
 652  */
 653 static void
 654 ds1685_rtc_work_queue(struct work_struct *work)
 655 {
 656         struct ds1685_priv *rtc = container_of(work,
 657                                                struct ds1685_priv, work);
 658         struct platform_device *pdev = to_platform_device(&rtc->dev->dev);
 659         struct mutex *rtc_mutex = &rtc->dev->ops_lock;
 660         u8 ctrl4a, ctrl4b;
 661
 662         mutex_lock(rtc_mutex);
 663
 664         ds1685_rtc_switch_to_bank1(rtc);
 665         ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
 666         ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
 667
 668         /*
 669          * Check for a kickstart interrupt. With Vcc applied, this
 670          * typically means that the power button was pressed, so we
 671          * begin the shutdown sequence.
 672          */
 673         if ((ctrl4b & RTC_CTRL_4B_KSE) && (ctrl4a & RTC_CTRL_4A_KF)) {
 674                 /* Briefly disable kickstarts to debounce button presses. */
 675                 rtc->write(rtc, RTC_EXT_CTRL_4B,
 676                            (rtc->read(rtc, RTC_EXT_CTRL_4B) &
 677                             ~(RTC_CTRL_4B_KSE)));
 678
 679                 /* Clear the kickstart flag. */
 680                 rtc->write(rtc, RTC_EXT_CTRL_4A,
 681                            (ctrl4a & ~(RTC_CTRL_4A_KF)));
 682
 683
 684                 /*
 685                  * Sleep 500ms before re-enabling kickstarts.  This allows
 686                  * adequate time to avoid reading signal jitter as additional
 687                  * button presses.
 688                  */
 689                 msleep(500);
 690                 rtc->write(rtc, RTC_EXT_CTRL_4B,
 691                            (rtc->read(rtc, RTC_EXT_CTRL_4B) |
 692                             RTC_CTRL_4B_KSE));
 693
 694                 /* Call the platform pre-poweroff function. Else, shutdown. */
 695                 if (rtc->prepare_poweroff != NULL)
 696                         rtc->prepare_poweroff();
 697                 else
 698                         ds1685_rtc_poweroff(pdev);
 699         }
 700
 701         /*
 702          * Check for a wake-up interrupt.  With Vcc applied, this is
 703          * essentially a second alarm interrupt, except it takes into
 704          * account the 'date' register in bank1 in addition to the
 705          * standard three alarm registers.
 706          */
 707         if ((ctrl4b & RTC_CTRL_4B_WIE) && (ctrl4a & RTC_CTRL_4A_WF)) {
 708                 rtc->write(rtc, RTC_EXT_CTRL_4A,
 709                            (ctrl4a & ~(RTC_CTRL_4A_WF)));
 710
 711                 /* Call the platform wake_alarm function if defined. */
 712                 if (rtc->wake_alarm != NULL)
 713                         rtc->wake_alarm();
 714                 else
 715                         dev_warn(&pdev->dev,
 716                                  "Wake Alarm IRQ just occurred!\n");
 717         }
 718
 719         /*
 720          * Check for a ram-clear interrupt.  This happens if RIE=1 and RF=0
 721          * when RCE=1 in 4B.  This clears all NVRAM bytes in bank0 by setting
 722          * each byte to a logic 1.  This has no effect on any extended
 723          * NV-SRAM that might be present, nor on the time/calendar/alarm
 724          * registers.  After a ram-clear is completed, there is a minimum
 725          * recovery time of ~150ms in which all reads/writes are locked out.
 726          * NOTE: A ram-clear can still occur if RCE=1 and RIE=0.  We cannot
 727          * catch this scenario.
 728          */
 729         if ((ctrl4b & RTC_CTRL_4B_RIE) && (ctrl4a & RTC_CTRL_4A_RF)) {
 730                 rtc->write(rtc, RTC_EXT_CTRL_4A,
 731                            (ctrl4a & ~(RTC_CTRL_4A_RF)));
 732                 msleep(150);
 733
 734                 /* Call the platform post_ram_clear function if defined. */
 735                 if (rtc->post_ram_clear != NULL)
 736                         rtc->post_ram_clear();
 737                 else
 738                         dev_warn(&pdev->dev,
 739                                  "RAM-Clear IRQ just occurred!\n");
 740         }
 741         ds1685_rtc_switch_to_bank0(rtc);
 742
 743         mutex_unlock(rtc_mutex);
 744 }
 745 /* ----------------------------------------------------------------------- */
 746
 747
 748 /* ----------------------------------------------------------------------- */
 749 /* ProcFS interface */
 750
 751 #ifdef CONFIG_PROC_FS
 752 #define NUM_REGS        6       /* Num of control registers. */
 753 #define NUM_BITS        8       /* Num bits per register. */
 754 #define NUM_SPACES      4       /* Num spaces between each bit. */
 755
 756 /*
 757  * Periodic Interrupt Rates.
 758  */
 759 static const char *ds1685_rtc_pirq_rate[16] = {
 760         "none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms",
 761         "0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms",
 762         "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms"
 763 };
 764
 765 /*
 766  * Square-Wave Output Frequencies.
 767  */
 768 static const char *ds1685_rtc_sqw_freq[16] = {
 769         "none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", "1024Hz",
 770         "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", "8Hz", "4Hz", "2Hz"
 771 };
 772
 773 /**
 774  * ds1685_rtc_proc - procfs access function.
 775  * @dev: pointer to device structure.
 776  * @seq: pointer to seq_file structure.
 777  */
 778 static int
 779 ds1685_rtc_proc(struct device *dev, struct seq_file *seq)
 780 {
 781         struct ds1685_priv *rtc = dev_get_drvdata(dev);
 782         u8 ctrla, ctrlb, ctrlc, ctrld, ctrl4a, ctrl4b, ssn[8];
 783         char *model;
 784
 785         /* Read all the relevant data from the control registers. */
 786         ds1685_rtc_switch_to_bank1(rtc);
 787         ds1685_rtc_get_ssn(rtc, ssn);
 788         ctrla = rtc->read(rtc, RTC_CTRL_A);
 789         ctrlb = rtc->read(rtc, RTC_CTRL_B);
 790         ctrlc = rtc->read(rtc, RTC_CTRL_C);
 791         ctrld = rtc->read(rtc, RTC_CTRL_D);
 792         ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
 793         ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
 794         ds1685_rtc_switch_to_bank0(rtc);
 795
 796         /* Determine the RTC model. */
 797         switch (ssn[0]) {
 798         case RTC_MODEL_DS1685:
 799                 model = "DS1685/DS1687\0";
 800                 break;
 801         case RTC_MODEL_DS1689:
 802                 model = "DS1689/DS1693\0";
 803                 break;
 804         case RTC_MODEL_DS17285:
 805                 model = "DS17285/DS17287\0";
 806                 break;
 807         case RTC_MODEL_DS17485:
 808                 model = "DS17485/DS17487\0";
 809                 break;
 810         case RTC_MODEL_DS17885:
 811                 model = "DS17885/DS17887\0";
 812                 break;
 813         default:
 814                 model = "Unknown\0";
 815                 break;
 816         }
 817
 818         /* Print out the information. */
 819         seq_printf(seq,
 820            "Model\t\t: %s\n"
 821            "Oscillator\t: %s\n"
 822            "12/24hr\t\t: %s\n"
 823            "DST\t\t: %s\n"
 824            "Data mode\t: %s\n"
 825            "Battery\t\t: %s\n"
 826            "Aux batt\t: %s\n"
 827            "Update IRQ\t: %s\n"
 828            "Periodic IRQ\t: %s\n"
 829            "Periodic Rate\t: %s\n"
 830            "SQW Freq\t: %s\n"
 831            "Serial #\t: %8phC\n",
 832            model,
 833            ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"),
 834            ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"),
 835            ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"),
 836            ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"),
 837            ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"),
 838            ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"),
 839            ((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"),
 840            ((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"),
 841            (!(ctrl4b & RTC_CTRL_4B_E32K) ?
 842             ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"),
 843            (!((ctrl4b & RTC_CTRL_4B_E32K)) ?
 844             ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"),
 845            ssn);
 846         return 0;
 847 }
 848 #else
 849 #define ds1685_rtc_proc NULL
 850 #endif /* CONFIG_PROC_FS */
 851 /* ----------------------------------------------------------------------- */
 852
 853
 854 /* ----------------------------------------------------------------------- */
 855 /* RTC Class operations */
 856
 857 static const struct rtc_class_ops
 858 ds1685_rtc_ops = {
 859         .proc = ds1685_rtc_proc,
 860         .read_time = ds1685_rtc_read_time,
 861         .set_time = ds1685_rtc_set_time,
 862         .read_alarm = ds1685_rtc_read_alarm,
 863         .set_alarm = ds1685_rtc_set_alarm,
 864         .alarm_irq_enable = ds1685_rtc_alarm_irq_enable,
 865 };
 866 /* ----------------------------------------------------------------------- */
 867
 868 static int ds1685_nvram_read(void *priv, unsigned int pos, void *val,
 869                              size_t size)
 870 {
 871         struct ds1685_priv *rtc = priv;
 872         ssize_t count;
 873         unsigned long flags = 0;
 874         u8 *buf = val;
 875
 876         spin_lock_irqsave(&rtc->lock, flags);
 877         ds1685_rtc_switch_to_bank0(rtc);
 878
 879         /* Read NVRAM in time and bank0 registers. */
 880         for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
 881              count++, size--) {
 882                 if (count < NVRAM_SZ_TIME)
 883                         *buf++ = rtc->read(rtc, (NVRAM_TIME_BASE + pos++));
 884                 else
 885                         *buf++ = rtc->read(rtc, (NVRAM_BANK0_BASE + pos++));
 886         }
 887
 888 #ifndef CONFIG_RTC_DRV_DS1689
 889         if (size > 0) {
 890                 ds1685_rtc_switch_to_bank1(rtc);
 891
 892 #ifndef CONFIG_RTC_DRV_DS1685
 893                 /* Enable burst-mode on DS17x85/DS17x87 */
 894                 rtc->write(rtc, RTC_EXT_CTRL_4A,
 895                            (rtc->read(rtc, RTC_EXT_CTRL_4A) |
 896                             RTC_CTRL_4A_BME));
 897
 898                 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
 899                  * reading with burst-mode */
 900                 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
 901                            (pos - NVRAM_TOTAL_SZ_BANK0));
 902 #endif
 903
 904                 /* Read NVRAM in bank1 registers. */
 905                 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
 906                      count++, size--) {
 907 #ifdef CONFIG_RTC_DRV_DS1685
 908                         /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
 909                          * before each read. */
 910                         rtc->write(rtc, RTC_BANK1_RAM_ADDR,
 911                                    (pos - NVRAM_TOTAL_SZ_BANK0));
 912 #endif
 913                         *buf++ = rtc->read(rtc, RTC_BANK1_RAM_DATA_PORT);
 914                         pos++;
 915                 }
 916
 917 #ifndef CONFIG_RTC_DRV_DS1685
 918                 /* Disable burst-mode on DS17x85/DS17x87 */
 919                 rtc->write(rtc, RTC_EXT_CTRL_4A,
 920                            (rtc->read(rtc, RTC_EXT_CTRL_4A) &
 921                             ~(RTC_CTRL_4A_BME)));
 922 #endif
 923                 ds1685_rtc_switch_to_bank0(rtc);
 924         }
 925 #endif /* !CONFIG_RTC_DRV_DS1689 */
 926         spin_unlock_irqrestore(&rtc->lock, flags);
 927
 928         return 0;
 929 }
 930
 931 static int ds1685_nvram_write(void *priv, unsigned int pos, void *val,
 932                               size_t size)
 933 {
 934         struct ds1685_priv *rtc = priv;
 935         ssize_t count;
 936         unsigned long flags = 0;
 937         u8 *buf = val;
 938
 939         spin_lock_irqsave(&rtc->lock, flags);
 940         ds1685_rtc_switch_to_bank0(rtc);
 941
 942         /* Write NVRAM in time and bank0 registers. */
 943         for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
 944              count++, size--)
 945                 if (count < NVRAM_SZ_TIME)
 946                         rtc->write(rtc, (NVRAM_TIME_BASE + pos++),
 947                                    *buf++);
 948                 else
 949                         rtc->write(rtc, (NVRAM_BANK0_BASE), *buf++);
 950
 951 #ifndef CONFIG_RTC_DRV_DS1689
 952         if (size > 0) {
 953                 ds1685_rtc_switch_to_bank1(rtc);
 954
 955 #ifndef CONFIG_RTC_DRV_DS1685
 956                 /* Enable burst-mode on DS17x85/DS17x87 */
 957                 rtc->write(rtc, RTC_EXT_CTRL_4A,
 958                            (rtc->read(rtc, RTC_EXT_CTRL_4A) |
 959                             RTC_CTRL_4A_BME));
 960
 961                 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
 962                  * writing with burst-mode */
 963                 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
 964                            (pos - NVRAM_TOTAL_SZ_BANK0));
 965 #endif
 966
 967                 /* Write NVRAM in bank1 registers. */
 968                 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
 969                      count++, size--) {
 970 #ifdef CONFIG_RTC_DRV_DS1685
 971                         /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
 972                          * before each read. */
 973                         rtc->write(rtc, RTC_BANK1_RAM_ADDR,
 974                                    (pos - NVRAM_TOTAL_SZ_BANK0));
 975 #endif
 976                         rtc->write(rtc, RTC_BANK1_RAM_DATA_PORT, *buf++);
 977                         pos++;
 978                 }
 979
 980 #ifndef CONFIG_RTC_DRV_DS1685
 981                 /* Disable burst-mode on DS17x85/DS17x87 */
 982                 rtc->write(rtc, RTC_EXT_CTRL_4A,
 983                            (rtc->read(rtc, RTC_EXT_CTRL_4A) &
 984                             ~(RTC_CTRL_4A_BME)));
 985 #endif
 986                 ds1685_rtc_switch_to_bank0(rtc);
 987         }
 988 #endif /* !CONFIG_RTC_DRV_DS1689 */
 989         spin_unlock_irqrestore(&rtc->lock, flags);
 990
 991         return 0;
 992 }
 993
 994 /* ----------------------------------------------------------------------- */
 995 /* SysFS interface */
 996
 997 /**
 998  * ds1685_rtc_sysfs_battery_show - sysfs file for main battery status.
 999  * @dev: pointer to device structure.
1000  * @attr: pointer to device_attribute structure.
1001  * @buf: pointer to char array to hold the output.
1002  */
1003 static ssize_t
1004 ds1685_rtc_sysfs_battery_show(struct device *dev,
1005                               struct device_attribute *attr, char *buf)
1006 {
1007         struct ds1685_priv *rtc = dev_get_drvdata(dev);
1008         u8 ctrld;
1009
1010         ctrld = rtc->read(rtc, RTC_CTRL_D);
1011
1012         return sprintf(buf, "%s\n",
1013                         (ctrld & RTC_CTRL_D_VRT) ? "ok" : "not ok or N/A");
1014 }
1015 static DEVICE_ATTR(battery, S_IRUGO, ds1685_rtc_sysfs_battery_show, NULL);
1016
1017 /**
1018  * ds1685_rtc_sysfs_auxbatt_show - sysfs file for aux battery status.
1019  * @dev: pointer to device structure.
1020  * @attr: pointer to device_attribute structure.
1021  * @buf: pointer to char array to hold the output.
1022  */
1023 static ssize_t
1024 ds1685_rtc_sysfs_auxbatt_show(struct device *dev,
1025                               struct device_attribute *attr, char *buf)
1026 {
1027         struct ds1685_priv *rtc = dev_get_drvdata(dev);
1028         u8 ctrl4a;
1029
1030         ds1685_rtc_switch_to_bank1(rtc);
1031         ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
1032         ds1685_rtc_switch_to_bank0(rtc);
1033
1034         return sprintf(buf, "%s\n",
1035                         (ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "not ok or N/A");
1036 }
1037 static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_rtc_sysfs_auxbatt_show, NULL);
1038
1039 /**
1040  * ds1685_rtc_sysfs_serial_show - sysfs file for silicon serial number.
1041  * @dev: pointer to device structure.
1042  * @attr: pointer to device_attribute structure.
1043  * @buf: pointer to char array to hold the output.
1044  */
1045 static ssize_t
1046 ds1685_rtc_sysfs_serial_show(struct device *dev,
1047                              struct device_attribute *attr, char *buf)
1048 {
1049         struct ds1685_priv *rtc = dev_get_drvdata(dev);
1050         u8 ssn[8];
1051
1052         ds1685_rtc_switch_to_bank1(rtc);
1053         ds1685_rtc_get_ssn(rtc, ssn);
1054         ds1685_rtc_switch_to_bank0(rtc);
1055
1056         return sprintf(buf, "%8phC\n", ssn);
1057 }
1058 static DEVICE_ATTR(serial, S_IRUGO, ds1685_rtc_sysfs_serial_show, NULL);
1059
1060 /**
1061  * struct ds1685_rtc_sysfs_misc_attrs - list for misc RTC features.
1062  */
1063 static struct attribute*
1064 ds1685_rtc_sysfs_misc_attrs[] = {
1065         &dev_attr_battery.attr,
1066         &dev_attr_auxbatt.attr,
1067         &dev_attr_serial.attr,
1068         NULL,
1069 };
1070
1071 /**
1072  * struct ds1685_rtc_sysfs_misc_grp - attr group for misc RTC features.
1073  */
1074 static const struct attribute_group
1075 ds1685_rtc_sysfs_misc_grp = {
1076         .name = "misc",
1077         .attrs = ds1685_rtc_sysfs_misc_attrs,
1078 };
1079
1080 /* ----------------------------------------------------------------------- */
1081 /* Driver Probe/Removal */
1082
1083 /**
1084  * ds1685_rtc_probe - initializes rtc driver.
1085  * @pdev: pointer to platform_device structure.
1086  */
1087 static int
1088 ds1685_rtc_probe(struct platform_device *pdev)
1089 {
1090         struct rtc_device *rtc_dev;
1091         struct resource *res;
1092         struct ds1685_priv *rtc;
1093         struct ds1685_rtc_platform_data *pdata;
1094         u8 ctrla, ctrlb, hours;
1095         unsigned char am_pm;
1096         int ret = 0;
1097         struct nvmem_config nvmem_cfg = {
1098                 .name = "ds1685_nvram",
1099                 .size = NVRAM_TOTAL_SZ,
1100                 .reg_read = ds1685_nvram_read,
1101                 .reg_write = ds1685_nvram_write,
1102         };
1103
1104         /* Get the platform data. */
1105         pdata = (struct ds1685_rtc_platform_data *) pdev->dev.platform_data;
1106         if (!pdata)
1107                 return -ENODEV;
1108
1109         /* Allocate memory for the rtc device. */
1110         rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
1111         if (!rtc)
1112                 return -ENOMEM;
1113
1114         /*
1115          * Allocate/setup any IORESOURCE_MEM resources, if required.  Not all
1116          * platforms put the RTC in an easy-access place.  Like the SGI Octane,
1117          * which attaches the RTC to a "ByteBus", hooked to a SuperIO chip
1118          * that sits behind the IOC3 PCI metadevice.
1119          */
1120         if (pdata->alloc_io_resources) {
1121                 /* Get the platform resources. */
1122                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1123                 if (!res)
1124                         return -ENXIO;
1125                 rtc->size = resource_size(res);
1126
1127                 /* Request a memory region. */
1128                 /* XXX: mmio-only for now. */
1129                 if (!devm_request_mem_region(&pdev->dev, res->start, rtc->size,
1130                                              pdev->name))
1131                         return -EBUSY;
1132
1133                 /*
1134                  * Set the base address for the rtc, and ioremap its
1135                  * registers.
1136                  */
1137                 rtc->baseaddr = res->start;
1138                 rtc->regs = devm_ioremap(&pdev->dev, res->start, rtc->size);
1139                 if (!rtc->regs)
1140                         return -ENOMEM;
1141         }
1142         rtc->alloc_io_resources = pdata->alloc_io_resources;
1143
1144         /* Get the register step size. */
1145         if (pdata->regstep > 0)
1146                 rtc->regstep = pdata->regstep;
1147         else
1148                 rtc->regstep = 1;
1149
1150         /* Platform read function, else default if mmio setup */
1151         if (pdata->plat_read)
1152                 rtc->read = pdata->plat_read;
1153         else
1154                 if (pdata->alloc_io_resources)
1155                         rtc->read = ds1685_read;
1156                 else
1157                         return -ENXIO;
1158
1159         /* Platform write function, else default if mmio setup */
1160         if (pdata->plat_write)
1161                 rtc->write = pdata->plat_write;
1162         else
1163                 if (pdata->alloc_io_resources)
1164                         rtc->write = ds1685_write;
1165                 else
1166                         return -ENXIO;
1167
1168         /* Platform pre-shutdown function, if defined. */
1169         if (pdata->plat_prepare_poweroff)
1170                 rtc->prepare_poweroff = pdata->plat_prepare_poweroff;
1171
1172         /* Platform wake_alarm function, if defined. */
1173         if (pdata->plat_wake_alarm)
1174                 rtc->wake_alarm = pdata->plat_wake_alarm;
1175
1176         /* Platform post_ram_clear function, if defined. */
1177         if (pdata->plat_post_ram_clear)
1178                 rtc->post_ram_clear = pdata->plat_post_ram_clear;
1179
1180         /* Init the spinlock, workqueue, & set the driver data. */
1181         spin_lock_init(&rtc->lock);
1182         INIT_WORK(&rtc->work, ds1685_rtc_work_queue);
1183         platform_set_drvdata(pdev, rtc);
1184
1185         /* Turn the oscillator on if is not already on (DV1 = 1). */
1186         ctrla = rtc->read(rtc, RTC_CTRL_A);
1187         if (!(ctrla & RTC_CTRL_A_DV1))
1188                 ctrla |= RTC_CTRL_A_DV1;
1189
1190         /* Enable the countdown chain (DV2 = 0) */
1191         ctrla &= ~(RTC_CTRL_A_DV2);
1192
1193         /* Clear RS3-RS0 in Control A. */
1194         ctrla &= ~(RTC_CTRL_A_RS_MASK);
1195
1196         /*
1197          * All done with Control A.  Switch to Bank 1 for the remainder of
1198          * the RTC setup so we have access to the extended functions.
1199          */
1200         ctrla |= RTC_CTRL_A_DV0;
1201         rtc->write(rtc, RTC_CTRL_A, ctrla);
1202
1203         /* Default to 32768kHz output. */
1204         rtc->write(rtc, RTC_EXT_CTRL_4B,
1205                    (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_E32K));
1206
1207         /* Set the SET bit in Control B so we can do some housekeeping. */
1208         rtc->write(rtc, RTC_CTRL_B,
1209                    (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
1210
1211         /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
1212         while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
1213                 cpu_relax();
1214
1215         /*
1216          * If the platform supports BCD mode, then set DM=0 in Control B.
1217          * Otherwise, set DM=1 for BIN mode.
1218          */
1219         ctrlb = rtc->read(rtc, RTC_CTRL_B);
1220         if (pdata->bcd_mode)
1221                 ctrlb &= ~(RTC_CTRL_B_DM);
1222         else
1223                 ctrlb |= RTC_CTRL_B_DM;
1224         rtc->bcd_mode = pdata->bcd_mode;
1225
1226         /*
1227          * Disable Daylight Savings Time (DSE = 0).
1228          * The RTC has hardcoded timezone information that is rendered
1229          * obselete.  We'll let the OS deal with DST settings instead.
1230          */
1231         if (ctrlb & RTC_CTRL_B_DSE)
1232                 ctrlb &= ~(RTC_CTRL_B_DSE);
1233
1234         /* Force 24-hour mode (2412 = 1). */
1235         if (!(ctrlb & RTC_CTRL_B_2412)) {
1236                 /* Reinitialize the time hours. */
1237                 hours = rtc->read(rtc, RTC_HRS);
1238                 am_pm = hours & RTC_HRS_AMPM_MASK;
1239                 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
1240                                            RTC_HRS_12_BIN_MASK);
1241                 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
1242
1243                 /* Enable 24-hour mode. */
1244                 ctrlb |= RTC_CTRL_B_2412;
1245
1246                 /* Write back to Control B, including DM & DSE bits. */
1247                 rtc->write(rtc, RTC_CTRL_B, ctrlb);
1248
1249                 /* Write the time hours back. */
1250                 rtc->write(rtc, RTC_HRS,
1251                            ds1685_rtc_bin2bcd(rtc, hours,
1252                                               RTC_HRS_24_BIN_MASK,
1253                                               RTC_HRS_24_BCD_MASK));
1254
1255                 /* Reinitialize the alarm hours. */
1256                 hours = rtc->read(rtc, RTC_HRS_ALARM);
1257                 am_pm = hours & RTC_HRS_AMPM_MASK;
1258                 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
1259                                            RTC_HRS_12_BIN_MASK);
1260                 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
1261
1262                 /* Write the alarm hours back. */
1263                 rtc->write(rtc, RTC_HRS_ALARM,
1264                            ds1685_rtc_bin2bcd(rtc, hours,
1265                                               RTC_HRS_24_BIN_MASK,
1266                                               RTC_HRS_24_BCD_MASK));
1267         } else {
1268                 /* 24-hour mode is already set, so write Control B back. */
1269                 rtc->write(rtc, RTC_CTRL_B, ctrlb);
1270         }
1271
1272         /* Unset the SET bit in Control B so the RTC can update. */
1273         rtc->write(rtc, RTC_CTRL_B,
1274                    (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
1275
1276         /* Check the main battery. */
1277         if (!(rtc->read(rtc, RTC_CTRL_D) & RTC_CTRL_D_VRT))
1278                 dev_warn(&pdev->dev,
1279                          "Main battery is exhausted! RTC may be invalid!\n");
1280
1281         /* Check the auxillary battery.  It is optional. */
1282         if (!(rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_VRT2))
1283                 dev_warn(&pdev->dev,
1284                          "Aux battery is exhausted or not available.\n");
1285
1286         /* Read Ctrl B and clear PIE/AIE/UIE. */
1287         rtc->write(rtc, RTC_CTRL_B,
1288                    (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_PAU_MASK)));
1289
1290         /* Reading Ctrl C auto-clears PF/AF/UF. */
1291         rtc->read(rtc, RTC_CTRL_C);
1292
1293         /* Read Ctrl 4B and clear RIE/WIE/KSE. */
1294         rtc->write(rtc, RTC_EXT_CTRL_4B,
1295                    (rtc->read(rtc, RTC_EXT_CTRL_4B) & ~(RTC_CTRL_4B_RWK_MASK)));
1296
1297         /* Clear RF/WF/KF in Ctrl 4A. */
1298         rtc->write(rtc, RTC_EXT_CTRL_4A,
1299                    (rtc->read(rtc, RTC_EXT_CTRL_4A) & ~(RTC_CTRL_4A_RWK_MASK)));
1300
1301         /*
1302          * Re-enable KSE to handle power button events.  We do not enable
1303          * WIE or RIE by default.
1304          */
1305         rtc->write(rtc, RTC_EXT_CTRL_4B,
1306                    (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_KSE));
1307
1308         rtc_dev = devm_rtc_allocate_device(&pdev->dev);
1309         if (IS_ERR(rtc_dev))
1310                 return PTR_ERR(rtc_dev);
1311
1312         rtc_dev->ops = &ds1685_rtc_ops;
1313
1314         /* Century bit is useless because leap year fails in 1900 and 2100 */
1315         rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
1316         rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
1317
1318         /* Maximum periodic rate is 8192Hz (0.122070ms). */
1319         rtc_dev->max_user_freq = RTC_MAX_USER_FREQ;
1320
1321         /* See if the platform doesn't support UIE. */
1322         if (pdata->uie_unsupported)
1323                 rtc_dev->uie_unsupported = 1;
1324         rtc->uie_unsupported = pdata->uie_unsupported;
1325
1326         rtc->dev = rtc_dev;
1327
1328         /*
1329          * Fetch the IRQ and setup the interrupt handler.
1330          *
1331          * Not all platforms have the IRQF pin tied to something.  If not, the
1332          * RTC will still set the *IE / *F flags and raise IRQF in ctrlc, but
1333          * there won't be an automatic way of notifying the kernel about it,
1334          * unless ctrlc is explicitly polled.
1335          */
1336         if (!pdata->no_irq) {
1337                 ret = platform_get_irq(pdev, 0);
1338                 if (ret > 0) {
1339                         rtc->irq_num = ret;
1340
1341                         /* Request an IRQ. */
1342                         ret = devm_request_irq(&pdev->dev, rtc->irq_num,
1343                                                ds1685_rtc_irq_handler,
1344                                                IRQF_SHARED, pdev->name, pdev);
1345
1346                         /* Check to see if something came back. */
1347                         if (unlikely(ret)) {
1348                                 dev_warn(&pdev->dev,
1349                                          "RTC interrupt not available\n");
1350                                 rtc->irq_num = 0;
1351                         }
1352                 } else
1353                         return ret;
1354         }
1355         rtc->no_irq = pdata->no_irq;
1356
1357         /* Setup complete. */
1358         ds1685_rtc_switch_to_bank0(rtc);
1359
1360         ret = rtc_add_group(rtc_dev, &ds1685_rtc_sysfs_misc_grp);
1361         if (ret)
1362                 return ret;
1363
1364         rtc_dev->nvram_old_abi = true;
1365         nvmem_cfg.priv = rtc;
1366         ret = rtc_nvmem_register(rtc_dev, &nvmem_cfg);
1367         if (ret)
1368                 return ret;
1369
1370         return rtc_register_device(rtc_dev);
1371 }
1372
1373 /**
1374  * ds1685_rtc_remove - removes rtc driver.
1375  * @pdev: pointer to platform_device structure.
1376  */
1377 static int
1378 ds1685_rtc_remove(struct platform_device *pdev)
1379 {
1380         struct ds1685_priv *rtc = platform_get_drvdata(pdev);
1381
1382         /* Read Ctrl B and clear PIE/AIE/UIE. */
1383         rtc->write(rtc, RTC_CTRL_B,
1384                    (rtc->read(rtc, RTC_CTRL_B) &
1385                     ~(RTC_CTRL_B_PAU_MASK)));
1386
1387         /* Reading Ctrl C auto-clears PF/AF/UF. */
1388         rtc->read(rtc, RTC_CTRL_C);
1389
1390         /* Read Ctrl 4B and clear RIE/WIE/KSE. */
1391         rtc->write(rtc, RTC_EXT_CTRL_4B,
1392                    (rtc->read(rtc, RTC_EXT_CTRL_4B) &
1393                     ~(RTC_CTRL_4B_RWK_MASK)));
1394
1395         /* Manually clear RF/WF/KF in Ctrl 4A. */
1396         rtc->write(rtc, RTC_EXT_CTRL_4A,
1397                    (rtc->read(rtc, RTC_EXT_CTRL_4A) &
1398                     ~(RTC_CTRL_4A_RWK_MASK)));
1399
1400         cancel_work_sync(&rtc->work);
1401
1402         return 0;
1403 }
1404
1405 /**
1406  * ds1685_rtc_driver - rtc driver properties.
1407  */
1408 static struct platform_driver ds1685_rtc_driver = {
1409         .driver         = {
1410                 .name   = "rtc-ds1685",
1411         },
1412         .probe          = ds1685_rtc_probe,
1413         .remove         = ds1685_rtc_remove,
1414 };
1415 module_platform_driver(ds1685_rtc_driver);
1416 /* ----------------------------------------------------------------------- */
1417
1418
1419 /* ----------------------------------------------------------------------- */
1420 /* Poweroff function */
1421
1422 /**
1423  * ds1685_rtc_poweroff - uses the RTC chip to power the system off.
1424  * @pdev: pointer to platform_device structure.
1425  */
1426 void __noreturn
1427 ds1685_rtc_poweroff(struct platform_device *pdev)
1428 {
1429         u8 ctrla, ctrl4a, ctrl4b;
1430         struct ds1685_priv *rtc;
1431
1432         /* Check for valid RTC data, else, spin forever. */
1433         if (unlikely(!pdev)) {
1434                 pr_emerg("platform device data not available, spinning forever ...\n");
1435                 while(1);
1436                 unreachable();
1437         } else {
1438                 /* Get the rtc data. */
1439                 rtc = platform_get_drvdata(pdev);
1440
1441                 /*
1442                  * Disable our IRQ.  We're powering down, so we're not
1443                  * going to worry about cleaning up.  Most of that should
1444                  * have been taken care of by the shutdown scripts and this
1445                  * is the final function call.
1446                  */
1447                 if (!rtc->no_irq)
1448                         disable_irq_nosync(rtc->irq_num);
1449
1450                 /* Oscillator must be on and the countdown chain enabled. */
1451                 ctrla = rtc->read(rtc, RTC_CTRL_A);
1452                 ctrla |= RTC_CTRL_A_DV1;
1453                 ctrla &= ~(RTC_CTRL_A_DV2);
1454                 rtc->write(rtc, RTC_CTRL_A, ctrla);
1455
1456                 /*
1457                  * Read Control 4A and check the status of the auxillary
1458                  * battery.  This must be present and working (VRT2 = 1)
1459                  * for wakeup and kickstart functionality to be useful.
1460                  */
1461                 ds1685_rtc_switch_to_bank1(rtc);
1462                 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
1463                 if (ctrl4a & RTC_CTRL_4A_VRT2) {
1464                         /* Clear all of the interrupt flags on Control 4A. */
1465                         ctrl4a &= ~(RTC_CTRL_4A_RWK_MASK);
1466                         rtc->write(rtc, RTC_EXT_CTRL_4A, ctrl4a);
1467
1468                         /*
1469                          * The auxillary battery is present and working.
1470                          * Enable extended functions (ABE=1), enable
1471                          * wake-up (WIE=1), and enable kickstart (KSE=1)
1472                          * in Control 4B.
1473                          */
1474                         ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
1475                         ctrl4b |= (RTC_CTRL_4B_ABE | RTC_CTRL_4B_WIE |
1476                                    RTC_CTRL_4B_KSE);
1477                         rtc->write(rtc, RTC_EXT_CTRL_4B, ctrl4b);
1478                 }
1479
1480                 /* Set PAB to 1 in Control 4A to power the system down. */
1481                 dev_warn(&pdev->dev, "Powerdown.\n");
1482                 msleep(20);
1483                 rtc->write(rtc, RTC_EXT_CTRL_4A,
1484                            (ctrl4a | RTC_CTRL_4A_PAB));
1485
1486                 /* Spin ... we do not switch back to bank0. */
1487                 while(1);
1488                 unreachable();
1489         }
1490 }
1491 EXPORT_SYMBOL(ds1685_rtc_poweroff);
1492 /* ----------------------------------------------------------------------- */
1493
1494
1495 MODULE_AUTHOR("Joshua Kinard <[email protected]>");
1496 MODULE_AUTHOR("Matthias Fuchs <[email protected]>");
1497 MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687-series RTC driver");
1498 MODULE_LICENSE("GPL");
1499 MODULE_ALIAS("platform:rtc-ds1685");