drivers/mtd/nand/raw/s3c2410.c

   1 /*
   2  * Copyright © 2004-2008 Simtec Electronics
   3  *      http://armlinux.simtec.co.uk/
   4  *      Ben Dooks <[email protected]>
   5  *
   6  * Samsung S3C2410/S3C2440/S3C2412 NAND driver
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21 */
  22
  23 #define pr_fmt(fmt) "nand-s3c2410: " fmt
  24
  25 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
  26 #define DEBUG
  27 #endif
  28
  29 #include <linux/module.h>
  30 #include <linux/types.h>
  31 #include <linux/kernel.h>
  32 #include <linux/string.h>
  33 #include <linux/io.h>
  34 #include <linux/ioport.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/delay.h>
  37 #include <linux/err.h>
  38 #include <linux/slab.h>
  39 #include <linux/clk.h>
  40 #include <linux/cpufreq.h>
  41 #include <linux/of.h>
  42 #include <linux/of_device.h>
  43
  44 #include <linux/mtd/mtd.h>
  45 #include <linux/mtd/rawnand.h>
  46 #include <linux/mtd/nand_ecc.h>
  47 #include <linux/mtd/partitions.h>
  48
  49 #include <linux/platform_data/mtd-nand-s3c2410.h>
  50
  51 #define S3C2410_NFREG(x) (x)
  52
  53 #define S3C2410_NFCONF          S3C2410_NFREG(0x00)
  54 #define S3C2410_NFCMD           S3C2410_NFREG(0x04)
  55 #define S3C2410_NFADDR          S3C2410_NFREG(0x08)
  56 #define S3C2410_NFDATA          S3C2410_NFREG(0x0C)
  57 #define S3C2410_NFSTAT          S3C2410_NFREG(0x10)
  58 #define S3C2410_NFECC           S3C2410_NFREG(0x14)
  59 #define S3C2440_NFCONT          S3C2410_NFREG(0x04)
  60 #define S3C2440_NFCMD           S3C2410_NFREG(0x08)
  61 #define S3C2440_NFADDR          S3C2410_NFREG(0x0C)
  62 #define S3C2440_NFDATA          S3C2410_NFREG(0x10)
  63 #define S3C2440_NFSTAT          S3C2410_NFREG(0x20)
  64 #define S3C2440_NFMECC0         S3C2410_NFREG(0x2C)
  65 #define S3C2412_NFSTAT          S3C2410_NFREG(0x28)
  66 #define S3C2412_NFMECC0         S3C2410_NFREG(0x34)
  67 #define S3C2410_NFCONF_EN               (1<<15)
  68 #define S3C2410_NFCONF_INITECC          (1<<12)
  69 #define S3C2410_NFCONF_nFCE             (1<<11)
  70 #define S3C2410_NFCONF_TACLS(x)         ((x)<<8)
  71 #define S3C2410_NFCONF_TWRPH0(x)        ((x)<<4)
  72 #define S3C2410_NFCONF_TWRPH1(x)        ((x)<<0)
  73 #define S3C2410_NFSTAT_BUSY             (1<<0)
  74 #define S3C2440_NFCONF_TACLS(x)         ((x)<<12)
  75 #define S3C2440_NFCONF_TWRPH0(x)        ((x)<<8)
  76 #define S3C2440_NFCONF_TWRPH1(x)        ((x)<<4)
  77 #define S3C2440_NFCONT_INITECC          (1<<4)
  78 #define S3C2440_NFCONT_nFCE             (1<<1)
  79 #define S3C2440_NFCONT_ENABLE           (1<<0)
  80 #define S3C2440_NFSTAT_READY            (1<<0)
  81 #define S3C2412_NFCONF_NANDBOOT         (1<<31)
  82 #define S3C2412_NFCONT_INIT_MAIN_ECC    (1<<5)
  83 #define S3C2412_NFCONT_nFCE0            (1<<1)
  84 #define S3C2412_NFSTAT_READY            (1<<0)
  85
  86 /* new oob placement block for use with hardware ecc generation
  87  */
  88 static int s3c2410_ooblayout_ecc(struct mtd_info *mtd, int section,
  89                                  struct mtd_oob_region *oobregion)
  90 {
  91         if (section)
  92                 return -ERANGE;
  93
  94         oobregion->offset = 0;
  95         oobregion->length = 3;
  96
  97         return 0;
  98 }
  99
 100 static int s3c2410_ooblayout_free(struct mtd_info *mtd, int section,
 101                                   struct mtd_oob_region *oobregion)
 102 {
 103         if (section)
 104                 return -ERANGE;
 105
 106         oobregion->offset = 8;
 107         oobregion->length = 8;
 108
 109         return 0;
 110 }
 111
 112 static const struct mtd_ooblayout_ops s3c2410_ooblayout_ops = {
 113         .ecc = s3c2410_ooblayout_ecc,
 114         .free = s3c2410_ooblayout_free,
 115 };
 116
 117 /* controller and mtd information */
 118
 119 struct s3c2410_nand_info;
 120
 121 /**
 122  * struct s3c2410_nand_mtd - driver MTD structure
 123  * @mtd: The MTD instance to pass to the MTD layer.
 124  * @chip: The NAND chip information.
 125  * @set: The platform information supplied for this set of NAND chips.
 126  * @info: Link back to the hardware information.
 127 */
 128 struct s3c2410_nand_mtd {
 129         struct nand_chip                chip;
 130         struct s3c2410_nand_set         *set;
 131         struct s3c2410_nand_info        *info;
 132 };
 133
 134 enum s3c_cpu_type {
 135         TYPE_S3C2410,
 136         TYPE_S3C2412,
 137         TYPE_S3C2440,
 138 };
 139
 140 enum s3c_nand_clk_state {
 141         CLOCK_DISABLE   = 0,
 142         CLOCK_ENABLE,
 143         CLOCK_SUSPEND,
 144 };
 145
 146 /* overview of the s3c2410 nand state */
 147
 148 /**
 149  * struct s3c2410_nand_info - NAND controller state.
 150  * @mtds: An array of MTD instances on this controoler.
 151  * @platform: The platform data for this board.
 152  * @device: The platform device we bound to.
 153  * @clk: The clock resource for this controller.
 154  * @regs: The area mapped for the hardware registers.
 155  * @sel_reg: Pointer to the register controlling the NAND selection.
 156  * @sel_bit: The bit in @sel_reg to select the NAND chip.
 157  * @mtd_count: The number of MTDs created from this controller.
 158  * @save_sel: The contents of @sel_reg to be saved over suspend.
 159  * @clk_rate: The clock rate from @clk.
 160  * @clk_state: The current clock state.
 161  * @cpu_type: The exact type of this controller.
 162  */
 163 struct s3c2410_nand_info {
 164         /* mtd info */
 165         struct nand_controller          controller;
 166         struct s3c2410_nand_mtd         *mtds;
 167         struct s3c2410_platform_nand    *platform;
 168
 169         /* device info */
 170         struct device                   *device;
 171         struct clk                      *clk;
 172         void __iomem                    *regs;
 173         void __iomem                    *sel_reg;
 174         int                             sel_bit;
 175         int                             mtd_count;
 176         unsigned long                   save_sel;
 177         unsigned long                   clk_rate;
 178         enum s3c_nand_clk_state         clk_state;
 179
 180         enum s3c_cpu_type               cpu_type;
 181
 182 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
 183         struct notifier_block   freq_transition;
 184 #endif
 185 };
 186
 187 struct s3c24XX_nand_devtype_data {
 188         enum s3c_cpu_type type;
 189 };
 190
 191 static const struct s3c24XX_nand_devtype_data s3c2410_nand_devtype_data = {
 192         .type = TYPE_S3C2410,
 193 };
 194
 195 static const struct s3c24XX_nand_devtype_data s3c2412_nand_devtype_data = {
 196         .type = TYPE_S3C2412,
 197 };
 198
 199 static const struct s3c24XX_nand_devtype_data s3c2440_nand_devtype_data = {
 200         .type = TYPE_S3C2440,
 201 };
 202
 203 /* conversion functions */
 204
 205 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
 206 {
 207         return container_of(mtd_to_nand(mtd), struct s3c2410_nand_mtd,
 208                             chip);
 209 }
 210
 211 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
 212 {
 213         return s3c2410_nand_mtd_toours(mtd)->info;
 214 }
 215
 216 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
 217 {
 218         return platform_get_drvdata(dev);
 219 }
 220
 221 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
 222 {
 223         return dev_get_platdata(&dev->dev);
 224 }
 225
 226 static inline int allow_clk_suspend(struct s3c2410_nand_info *info)
 227 {
 228 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
 229         return 1;
 230 #else
 231         return 0;
 232 #endif
 233 }
 234
 235 /**
 236  * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock.
 237  * @info: The controller instance.
 238  * @new_state: State to which clock should be set.
 239  */
 240 static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info,
 241                 enum s3c_nand_clk_state new_state)
 242 {
 243         if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND)
 244                 return;
 245
 246         if (info->clk_state == CLOCK_ENABLE) {
 247                 if (new_state != CLOCK_ENABLE)
 248                         clk_disable_unprepare(info->clk);
 249         } else {
 250                 if (new_state == CLOCK_ENABLE)
 251                         clk_prepare_enable(info->clk);
 252         }
 253
 254         info->clk_state = new_state;
 255 }
 256
 257 /* timing calculations */
 258
 259 #define NS_IN_KHZ 1000000
 260
 261 /**
 262  * s3c_nand_calc_rate - calculate timing data.
 263  * @wanted: The cycle time in nanoseconds.
 264  * @clk: The clock rate in kHz.
 265  * @max: The maximum divider value.
 266  *
 267  * Calculate the timing value from the given parameters.
 268  */
 269 static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
 270 {
 271         int result;
 272
 273         result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ);
 274
 275         pr_debug("result %d from %ld, %d\n", result, clk, wanted);
 276
 277         if (result > max) {
 278                 pr_err("%d ns is too big for current clock rate %ld\n",
 279                         wanted, clk);
 280                 return -1;
 281         }
 282
 283         if (result < 1)
 284                 result = 1;
 285
 286         return result;
 287 }
 288
 289 #define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
 290
 291 /* controller setup */
 292
 293 /**
 294  * s3c2410_nand_setrate - setup controller timing information.
 295  * @info: The controller instance.
 296  *
 297  * Given the information supplied by the platform, calculate and set
 298  * the necessary timing registers in the hardware to generate the
 299  * necessary timing cycles to the hardware.
 300  */
 301 static int s3c2410_nand_setrate(struct s3c2410_nand_info *info)
 302 {
 303         struct s3c2410_platform_nand *plat = info->platform;
 304         int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
 305         int tacls, twrph0, twrph1;
 306         unsigned long clkrate = clk_get_rate(info->clk);
 307         unsigned long uninitialized_var(set), cfg, uninitialized_var(mask);
 308         unsigned long flags;
 309
 310         /* calculate the timing information for the controller */
 311
 312         info->clk_rate = clkrate;
 313         clkrate /= 1000;        /* turn clock into kHz for ease of use */
 314
 315         if (plat != NULL) {
 316                 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
 317                 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
 318                 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
 319         } else {
 320                 /* default timings */
 321                 tacls = tacls_max;
 322                 twrph0 = 8;
 323                 twrph1 = 8;
 324         }
 325
 326         if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
 327                 dev_err(info->device, "cannot get suitable timings\n");
 328                 return -EINVAL;
 329         }
 330
 331         dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
 332                 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate),
 333                                                 twrph1, to_ns(twrph1, clkrate));
 334
 335         switch (info->cpu_type) {
 336         case TYPE_S3C2410:
 337                 mask = (S3C2410_NFCONF_TACLS(3) |
 338                         S3C2410_NFCONF_TWRPH0(7) |
 339                         S3C2410_NFCONF_TWRPH1(7));
 340                 set = S3C2410_NFCONF_EN;
 341                 set |= S3C2410_NFCONF_TACLS(tacls - 1);
 342                 set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
 343                 set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
 344                 break;
 345
 346         case TYPE_S3C2440:
 347         case TYPE_S3C2412:
 348                 mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) |
 349                         S3C2440_NFCONF_TWRPH0(7) |
 350                         S3C2440_NFCONF_TWRPH1(7));
 351
 352                 set = S3C2440_NFCONF_TACLS(tacls - 1);
 353                 set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
 354                 set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
 355                 break;
 356
 357         default:
 358                 BUG();
 359         }
 360
 361         local_irq_save(flags);
 362
 363         cfg = readl(info->regs + S3C2410_NFCONF);
 364         cfg &= ~mask;
 365         cfg |= set;
 366         writel(cfg, info->regs + S3C2410_NFCONF);
 367
 368         local_irq_restore(flags);
 369
 370         dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
 371
 372         return 0;
 373 }
 374
 375 /**
 376  * s3c2410_nand_inithw - basic hardware initialisation
 377  * @info: The hardware state.
 378  *
 379  * Do the basic initialisation of the hardware, using s3c2410_nand_setrate()
 380  * to setup the hardware access speeds and set the controller to be enabled.
 381 */
 382 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info)
 383 {
 384         int ret;
 385
 386         ret = s3c2410_nand_setrate(info);
 387         if (ret < 0)
 388                 return ret;
 389
 390         switch (info->cpu_type) {
 391         case TYPE_S3C2410:
 392         default:
 393                 break;
 394
 395         case TYPE_S3C2440:
 396         case TYPE_S3C2412:
 397                 /* enable the controller and de-assert nFCE */
 398
 399                 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
 400         }
 401
 402         return 0;
 403 }
 404
 405 /**
 406  * s3c2410_nand_select_chip - select the given nand chip
 407  * @this: NAND chip object.
 408  * @chip: The chip number.
 409  *
 410  * This is called by the MTD layer to either select a given chip for the
 411  * @mtd instance, or to indicate that the access has finished and the
 412  * chip can be de-selected.
 413  *
 414  * The routine ensures that the nFCE line is correctly setup, and any
 415  * platform specific selection code is called to route nFCE to the specific
 416  * chip.
 417  */
 418 static void s3c2410_nand_select_chip(struct nand_chip *this, int chip)
 419 {
 420         struct s3c2410_nand_info *info;
 421         struct s3c2410_nand_mtd *nmtd;
 422         unsigned long cur;
 423
 424         nmtd = nand_get_controller_data(this);
 425         info = nmtd->info;
 426
 427         if (chip != -1)
 428                 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
 429
 430         cur = readl(info->sel_reg);
 431
 432         if (chip == -1) {
 433                 cur |= info->sel_bit;
 434         } else {
 435                 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
 436                         dev_err(info->device, "invalid chip %d\n", chip);
 437                         return;
 438                 }
 439
 440                 if (info->platform != NULL) {
 441                         if (info->platform->select_chip != NULL)
 442                                 (info->platform->select_chip) (nmtd->set, chip);
 443                 }
 444
 445                 cur &= ~info->sel_bit;
 446         }
 447
 448         writel(cur, info->sel_reg);
 449
 450         if (chip == -1)
 451                 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
 452 }
 453
 454 /* s3c2410_nand_hwcontrol
 455  *
 456  * Issue command and address cycles to the chip
 457 */
 458
 459 static void s3c2410_nand_hwcontrol(struct nand_chip *chip, int cmd,
 460                                    unsigned int ctrl)
 461 {
 462         struct mtd_info *mtd = nand_to_mtd(chip);
 463         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 464
 465         if (cmd == NAND_CMD_NONE)
 466                 return;
 467
 468         if (ctrl & NAND_CLE)
 469                 writeb(cmd, info->regs + S3C2410_NFCMD);
 470         else
 471                 writeb(cmd, info->regs + S3C2410_NFADDR);
 472 }
 473
 474 /* command and control functions */
 475
 476 static void s3c2440_nand_hwcontrol(struct nand_chip *chip, int cmd,
 477                                    unsigned int ctrl)
 478 {
 479         struct mtd_info *mtd = nand_to_mtd(chip);
 480         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 481
 482         if (cmd == NAND_CMD_NONE)
 483                 return;
 484
 485         if (ctrl & NAND_CLE)
 486                 writeb(cmd, info->regs + S3C2440_NFCMD);
 487         else
 488                 writeb(cmd, info->regs + S3C2440_NFADDR);
 489 }
 490
 491 /* s3c2410_nand_devready()
 492  *
 493  * returns 0 if the nand is busy, 1 if it is ready
 494 */
 495
 496 static int s3c2410_nand_devready(struct nand_chip *chip)
 497 {
 498         struct mtd_info *mtd = nand_to_mtd(chip);
 499         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 500         return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
 501 }
 502
 503 static int s3c2440_nand_devready(struct nand_chip *chip)
 504 {
 505         struct mtd_info *mtd = nand_to_mtd(chip);
 506         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 507         return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
 508 }
 509
 510 static int s3c2412_nand_devready(struct nand_chip *chip)
 511 {
 512         struct mtd_info *mtd = nand_to_mtd(chip);
 513         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 514         return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
 515 }
 516
 517 /* ECC handling functions */
 518
 519 static int s3c2410_nand_correct_data(struct nand_chip *chip, u_char *dat,
 520                                      u_char *read_ecc, u_char *calc_ecc)
 521 {
 522         struct mtd_info *mtd = nand_to_mtd(chip);
 523         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 524         unsigned int diff0, diff1, diff2;
 525         unsigned int bit, byte;
 526
 527         pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
 528
 529         diff0 = read_ecc[0] ^ calc_ecc[0];
 530         diff1 = read_ecc[1] ^ calc_ecc[1];
 531         diff2 = read_ecc[2] ^ calc_ecc[2];
 532
 533         pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n",
 534                  __func__, 3, read_ecc, 3, calc_ecc,
 535                  diff0, diff1, diff2);
 536
 537         if (diff0 == 0 && diff1 == 0 && diff2 == 0)
 538                 return 0;               /* ECC is ok */
 539
 540         /* sometimes people do not think about using the ECC, so check
 541          * to see if we have an 0xff,0xff,0xff read ECC and then ignore
 542          * the error, on the assumption that this is an un-eccd page.
 543          */
 544         if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff
 545             && info->platform->ignore_unset_ecc)
 546                 return 0;
 547
 548         /* Can we correct this ECC (ie, one row and column change).
 549          * Note, this is similar to the 256 error code on smartmedia */
 550
 551         if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
 552             ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
 553             ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
 554                 /* calculate the bit position of the error */
 555
 556                 bit  = ((diff2 >> 3) & 1) |
 557                        ((diff2 >> 4) & 2) |
 558                        ((diff2 >> 5) & 4);
 559
 560                 /* calculate the byte position of the error */
 561
 562                 byte = ((diff2 << 7) & 0x100) |
 563                        ((diff1 << 0) & 0x80)  |
 564                        ((diff1 << 1) & 0x40)  |
 565                        ((diff1 << 2) & 0x20)  |
 566                        ((diff1 << 3) & 0x10)  |
 567                        ((diff0 >> 4) & 0x08)  |
 568                        ((diff0 >> 3) & 0x04)  |
 569                        ((diff0 >> 2) & 0x02)  |
 570                        ((diff0 >> 1) & 0x01);
 571
 572                 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
 573                         bit, byte);
 574
 575                 dat[byte] ^= (1 << bit);
 576                 return 1;
 577         }
 578
 579         /* if there is only one bit difference in the ECC, then
 580          * one of only a row or column parity has changed, which
 581          * means the error is most probably in the ECC itself */
 582
 583         diff0 |= (diff1 << 8);
 584         diff0 |= (diff2 << 16);
 585
 586         /* equal to "(diff0 & ~(1 << __ffs(diff0)))" */
 587         if ((diff0 & (diff0 - 1)) == 0)
 588                 return 1;
 589
 590         return -1;
 591 }
 592
 593 /* ECC functions
 594  *
 595  * These allow the s3c2410 and s3c2440 to use the controller's ECC
 596  * generator block to ECC the data as it passes through]
 597 */
 598
 599 static void s3c2410_nand_enable_hwecc(struct nand_chip *chip, int mode)
 600 {
 601         struct s3c2410_nand_info *info;
 602         unsigned long ctrl;
 603
 604         info = s3c2410_nand_mtd_toinfo(nand_to_mtd(chip));
 605         ctrl = readl(info->regs + S3C2410_NFCONF);
 606         ctrl |= S3C2410_NFCONF_INITECC;
 607         writel(ctrl, info->regs + S3C2410_NFCONF);
 608 }
 609
 610 static void s3c2412_nand_enable_hwecc(struct nand_chip *chip, int mode)
 611 {
 612         struct s3c2410_nand_info *info;
 613         unsigned long ctrl;
 614
 615         info = s3c2410_nand_mtd_toinfo(nand_to_mtd(chip));
 616         ctrl = readl(info->regs + S3C2440_NFCONT);
 617         writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC,
 618                info->regs + S3C2440_NFCONT);
 619 }
 620
 621 static void s3c2440_nand_enable_hwecc(struct nand_chip *chip, int mode)
 622 {
 623         struct s3c2410_nand_info *info;
 624         unsigned long ctrl;
 625
 626         info = s3c2410_nand_mtd_toinfo(nand_to_mtd(chip));
 627         ctrl = readl(info->regs + S3C2440_NFCONT);
 628         writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
 629 }
 630
 631 static int s3c2410_nand_calculate_ecc(struct nand_chip *chip,
 632                                       const u_char *dat, u_char *ecc_code)
 633 {
 634         struct mtd_info *mtd = nand_to_mtd(chip);
 635         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 636
 637         ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
 638         ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
 639         ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
 640
 641         pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
 642
 643         return 0;
 644 }
 645
 646 static int s3c2412_nand_calculate_ecc(struct nand_chip *chip,
 647                                       const u_char *dat, u_char *ecc_code)
 648 {
 649         struct mtd_info *mtd = nand_to_mtd(chip);
 650         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 651         unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
 652
 653         ecc_code[0] = ecc;
 654         ecc_code[1] = ecc >> 8;
 655         ecc_code[2] = ecc >> 16;
 656
 657         pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
 658
 659         return 0;
 660 }
 661
 662 static int s3c2440_nand_calculate_ecc(struct nand_chip *chip,
 663                                       const u_char *dat, u_char *ecc_code)
 664 {
 665         struct mtd_info *mtd = nand_to_mtd(chip);
 666         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 667         unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
 668
 669         ecc_code[0] = ecc;
 670         ecc_code[1] = ecc >> 8;
 671         ecc_code[2] = ecc >> 16;
 672
 673         pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff);
 674
 675         return 0;
 676 }
 677
 678 /* over-ride the standard functions for a little more speed. We can
 679  * use read/write block to move the data buffers to/from the controller
 680 */
 681
 682 static void s3c2410_nand_read_buf(struct nand_chip *this, u_char *buf, int len)
 683 {
 684         readsb(this->legacy.IO_ADDR_R, buf, len);
 685 }
 686
 687 static void s3c2440_nand_read_buf(struct nand_chip *this, u_char *buf, int len)
 688 {
 689         struct mtd_info *mtd = nand_to_mtd(this);
 690         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 691
 692         readsl(info->regs + S3C2440_NFDATA, buf, len >> 2);
 693
 694         /* cleanup if we've got less than a word to do */
 695         if (len & 3) {
 696                 buf += len & ~3;
 697
 698                 for (; len & 3; len--)
 699                         *buf++ = readb(info->regs + S3C2440_NFDATA);
 700         }
 701 }
 702
 703 static void s3c2410_nand_write_buf(struct nand_chip *this, const u_char *buf,
 704                                    int len)
 705 {
 706         writesb(this->legacy.IO_ADDR_W, buf, len);
 707 }
 708
 709 static void s3c2440_nand_write_buf(struct nand_chip *this, const u_char *buf,
 710                                    int len)
 711 {
 712         struct mtd_info *mtd = nand_to_mtd(this);
 713         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 714
 715         writesl(info->regs + S3C2440_NFDATA, buf, len >> 2);
 716
 717         /* cleanup any fractional write */
 718         if (len & 3) {
 719                 buf += len & ~3;
 720
 721                 for (; len & 3; len--, buf++)
 722                         writeb(*buf, info->regs + S3C2440_NFDATA);
 723         }
 724 }
 725
 726 /* cpufreq driver support */
 727
 728 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
 729
 730 static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb,
 731                                           unsigned long val, void *data)
 732 {
 733         struct s3c2410_nand_info *info;
 734         unsigned long newclk;
 735
 736         info = container_of(nb, struct s3c2410_nand_info, freq_transition);
 737         newclk = clk_get_rate(info->clk);
 738
 739         if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) ||
 740             (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) {
 741                 s3c2410_nand_setrate(info);
 742         }
 743
 744         return 0;
 745 }
 746
 747 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
 748 {
 749         info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition;
 750
 751         return cpufreq_register_notifier(&info->freq_transition,
 752                                          CPUFREQ_TRANSITION_NOTIFIER);
 753 }
 754
 755 static inline void
 756 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
 757 {
 758         cpufreq_unregister_notifier(&info->freq_transition,
 759                                     CPUFREQ_TRANSITION_NOTIFIER);
 760 }
 761
 762 #else
 763 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
 764 {
 765         return 0;
 766 }
 767
 768 static inline void
 769 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
 770 {
 771 }
 772 #endif
 773
 774 /* device management functions */
 775
 776 static int s3c24xx_nand_remove(struct platform_device *pdev)
 777 {
 778         struct s3c2410_nand_info *info = to_nand_info(pdev);
 779
 780         if (info == NULL)
 781                 return 0;
 782
 783         s3c2410_nand_cpufreq_deregister(info);
 784
 785         /* Release all our mtds  and their partitions, then go through
 786          * freeing the resources used
 787          */
 788
 789         if (info->mtds != NULL) {
 790                 struct s3c2410_nand_mtd *ptr = info->mtds;
 791                 int mtdno;
 792
 793                 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
 794                         pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
 795                         nand_release(&ptr->chip);
 796                 }
 797         }
 798
 799         /* free the common resources */
 800
 801         if (!IS_ERR(info->clk))
 802                 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
 803
 804         return 0;
 805 }
 806
 807 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
 808                                       struct s3c2410_nand_mtd *mtd,
 809                                       struct s3c2410_nand_set *set)
 810 {
 811         if (set) {
 812                 struct mtd_info *mtdinfo = nand_to_mtd(&mtd->chip);
 813
 814                 mtdinfo->name = set->name;
 815
 816                 return mtd_device_register(mtdinfo, set->partitions,
 817                                            set->nr_partitions);
 818         }
 819
 820         return -ENODEV;
 821 }
 822
 823 static int s3c2410_nand_setup_data_interface(struct nand_chip *chip, int csline,
 824                                         const struct nand_data_interface *conf)
 825 {
 826         struct mtd_info *mtd = nand_to_mtd(chip);
 827         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 828         struct s3c2410_platform_nand *pdata = info->platform;
 829         const struct nand_sdr_timings *timings;
 830         int tacls;
 831
 832         timings = nand_get_sdr_timings(conf);
 833         if (IS_ERR(timings))
 834                 return -ENOTSUPP;
 835
 836         tacls = timings->tCLS_min - timings->tWP_min;
 837         if (tacls < 0)
 838                 tacls = 0;
 839
 840         pdata->tacls  = DIV_ROUND_UP(tacls, 1000);
 841         pdata->twrph0 = DIV_ROUND_UP(timings->tWP_min, 1000);
 842         pdata->twrph1 = DIV_ROUND_UP(timings->tCLH_min, 1000);
 843
 844         return s3c2410_nand_setrate(info);
 845 }
 846
 847 /**
 848  * s3c2410_nand_init_chip - initialise a single instance of an chip
 849  * @info: The base NAND controller the chip is on.
 850  * @nmtd: The new controller MTD instance to fill in.
 851  * @set: The information passed from the board specific platform data.
 852  *
 853  * Initialise the given @nmtd from the information in @info and @set. This
 854  * readies the structure for use with the MTD layer functions by ensuring
 855  * all pointers are setup and the necessary control routines selected.
 856  */
 857 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
 858                                    struct s3c2410_nand_mtd *nmtd,
 859                                    struct s3c2410_nand_set *set)
 860 {
 861         struct device_node *np = info->device->of_node;
 862         struct nand_chip *chip = &nmtd->chip;
 863         void __iomem *regs = info->regs;
 864
 865         nand_set_flash_node(chip, set->of_node);
 866
 867         chip->legacy.write_buf    = s3c2410_nand_write_buf;
 868         chip->legacy.read_buf     = s3c2410_nand_read_buf;
 869         chip->legacy.select_chip  = s3c2410_nand_select_chip;
 870         chip->legacy.chip_delay   = 50;
 871         nand_set_controller_data(chip, nmtd);
 872         chip->options      = set->options;
 873         chip->controller   = &info->controller;
 874
 875         /*
 876          * let's keep behavior unchanged for legacy boards booting via pdata and
 877          * auto-detect timings only when booting with a device tree.
 878          */
 879         if (!np)
 880                 chip->options |= NAND_KEEP_TIMINGS;
 881
 882         switch (info->cpu_type) {
 883         case TYPE_S3C2410:
 884                 chip->legacy.IO_ADDR_W = regs + S3C2410_NFDATA;
 885                 info->sel_reg   = regs + S3C2410_NFCONF;
 886                 info->sel_bit   = S3C2410_NFCONF_nFCE;
 887                 chip->legacy.cmd_ctrl  = s3c2410_nand_hwcontrol;
 888                 chip->legacy.dev_ready = s3c2410_nand_devready;
 889                 break;
 890
 891         case TYPE_S3C2440:
 892                 chip->legacy.IO_ADDR_W = regs + S3C2440_NFDATA;
 893                 info->sel_reg   = regs + S3C2440_NFCONT;
 894                 info->sel_bit   = S3C2440_NFCONT_nFCE;
 895                 chip->legacy.cmd_ctrl  = s3c2440_nand_hwcontrol;
 896                 chip->legacy.dev_ready = s3c2440_nand_devready;
 897                 chip->legacy.read_buf  = s3c2440_nand_read_buf;
 898                 chip->legacy.write_buf  = s3c2440_nand_write_buf;
 899                 break;
 900
 901         case TYPE_S3C2412:
 902                 chip->legacy.IO_ADDR_W = regs + S3C2440_NFDATA;
 903                 info->sel_reg   = regs + S3C2440_NFCONT;
 904                 info->sel_bit   = S3C2412_NFCONT_nFCE0;
 905                 chip->legacy.cmd_ctrl  = s3c2440_nand_hwcontrol;
 906                 chip->legacy.dev_ready = s3c2412_nand_devready;
 907
 908                 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
 909                         dev_info(info->device, "System booted from NAND\n");
 910
 911                 break;
 912         }
 913
 914         chip->legacy.IO_ADDR_R = chip->legacy.IO_ADDR_W;
 915
 916         nmtd->info         = info;
 917         nmtd->set          = set;
 918
 919         chip->ecc.mode = info->platform->ecc_mode;
 920
 921         /*
 922          * If you use u-boot BBT creation code, specifying this flag will
 923          * let the kernel fish out the BBT from the NAND.
 924          */
 925         if (set->flash_bbt)
 926                 chip->bbt_options |= NAND_BBT_USE_FLASH;
 927 }
 928
 929 /**
 930  * s3c2410_nand_attach_chip - Init the ECC engine after NAND scan
 931  * @chip: The NAND chip
 932  *
 933  * This hook is called by the core after the identification of the NAND chip,
 934  * once the relevant per-chip information is up to date.. This call ensure that
 935  * we update the internal state accordingly.
 936  *
 937  * The internal state is currently limited to the ECC state information.
 938 */
 939 static int s3c2410_nand_attach_chip(struct nand_chip *chip)
 940 {
 941         struct mtd_info *mtd = nand_to_mtd(chip);
 942         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 943
 944         switch (chip->ecc.mode) {
 945
 946         case NAND_ECC_NONE:
 947                 dev_info(info->device, "ECC disabled\n");
 948                 break;
 949
 950         case NAND_ECC_SOFT:
 951                 /*
 952                  * This driver expects Hamming based ECC when ecc_mode is set
 953                  * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
 954                  * avoid adding an extra ecc_algo field to
 955                  * s3c2410_platform_nand.
 956                  */
 957                 chip->ecc.algo = NAND_ECC_HAMMING;
 958                 dev_info(info->device, "soft ECC\n");
 959                 break;
 960
 961         case NAND_ECC_HW:
 962                 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
 963                 chip->ecc.correct   = s3c2410_nand_correct_data;
 964                 chip->ecc.strength  = 1;
 965
 966                 switch (info->cpu_type) {
 967                 case TYPE_S3C2410:
 968                         chip->ecc.hwctl     = s3c2410_nand_enable_hwecc;
 969                         chip->ecc.calculate = s3c2410_nand_calculate_ecc;
 970                         break;
 971
 972                 case TYPE_S3C2412:
 973                         chip->ecc.hwctl     = s3c2412_nand_enable_hwecc;
 974                         chip->ecc.calculate = s3c2412_nand_calculate_ecc;
 975                         break;
 976
 977                 case TYPE_S3C2440:
 978                         chip->ecc.hwctl     = s3c2440_nand_enable_hwecc;
 979                         chip->ecc.calculate = s3c2440_nand_calculate_ecc;
 980                         break;
 981                 }
 982
 983                 dev_dbg(info->device, "chip %p => page shift %d\n",
 984                         chip, chip->page_shift);
 985
 986                 /* change the behaviour depending on whether we are using
 987                  * the large or small page nand device */
 988                 if (chip->page_shift > 10) {
 989                         chip->ecc.size      = 256;
 990                         chip->ecc.bytes     = 3;
 991                 } else {
 992                         chip->ecc.size      = 512;
 993                         chip->ecc.bytes     = 3;
 994                         mtd_set_ooblayout(nand_to_mtd(chip),
 995                                           &s3c2410_ooblayout_ops);
 996                 }
 997
 998                 dev_info(info->device, "hardware ECC\n");
 999                 break;
1000
1001         default:
1002                 dev_err(info->device, "invalid ECC mode!\n");
1003                 return -EINVAL;
1004         }
1005
1006         if (chip->bbt_options & NAND_BBT_USE_FLASH)
1007                 chip->options |= NAND_SKIP_BBTSCAN;
1008
1009         return 0;
1010 }
1011
1012 static const struct nand_controller_ops s3c24xx_nand_controller_ops = {
1013         .attach_chip = s3c2410_nand_attach_chip,
1014         .setup_data_interface = s3c2410_nand_setup_data_interface,
1015 };
1016
1017 static const struct of_device_id s3c24xx_nand_dt_ids[] = {
1018         {
1019                 .compatible = "samsung,s3c2410-nand",
1020                 .data = &s3c2410_nand_devtype_data,
1021         }, {
1022                 /* also compatible with s3c6400 */
1023                 .compatible = "samsung,s3c2412-nand",
1024                 .data = &s3c2412_nand_devtype_data,
1025         }, {
1026                 .compatible = "samsung,s3c2440-nand",
1027                 .data = &s3c2440_nand_devtype_data,
1028         },
1029         { /* sentinel */ }
1030 };
1031 MODULE_DEVICE_TABLE(of, s3c24xx_nand_dt_ids);
1032
1033 static int s3c24xx_nand_probe_dt(struct platform_device *pdev)
1034 {
1035         const struct s3c24XX_nand_devtype_data *devtype_data;
1036         struct s3c2410_platform_nand *pdata;
1037         struct s3c2410_nand_info *info = platform_get_drvdata(pdev);
1038         struct device_node *np = pdev->dev.of_node, *child;
1039         struct s3c2410_nand_set *sets;
1040
1041         devtype_data = of_device_get_match_data(&pdev->dev);
1042         if (!devtype_data)
1043                 return -ENODEV;
1044
1045         info->cpu_type = devtype_data->type;
1046
1047         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1048         if (!pdata)
1049                 return -ENOMEM;
1050
1051         pdev->dev.platform_data = pdata;
1052
1053         pdata->nr_sets = of_get_child_count(np);
1054         if (!pdata->nr_sets)
1055                 return 0;
1056
1057         sets = devm_kcalloc(&pdev->dev, pdata->nr_sets, sizeof(*sets),
1058                             GFP_KERNEL);
1059         if (!sets)
1060                 return -ENOMEM;
1061
1062         pdata->sets = sets;
1063
1064         for_each_available_child_of_node(np, child) {
1065                 sets->name = (char *)child->name;
1066                 sets->of_node = child;
1067                 sets->nr_chips = 1;
1068
1069                 of_node_get(child);
1070
1071                 sets++;
1072         }
1073
1074         return 0;
1075 }
1076
1077 static int s3c24xx_nand_probe_pdata(struct platform_device *pdev)
1078 {
1079         struct s3c2410_nand_info *info = platform_get_drvdata(pdev);
1080
1081         info->cpu_type = platform_get_device_id(pdev)->driver_data;
1082
1083         return 0;
1084 }
1085
1086 /* s3c24xx_nand_probe
1087  *
1088  * called by device layer when it finds a device matching
1089  * one our driver can handled. This code checks to see if
1090  * it can allocate all necessary resources then calls the
1091  * nand layer to look for devices
1092 */
1093 static int s3c24xx_nand_probe(struct platform_device *pdev)
1094 {
1095         struct s3c2410_platform_nand *plat;
1096         struct s3c2410_nand_info *info;
1097         struct s3c2410_nand_mtd *nmtd;
1098         struct s3c2410_nand_set *sets;
1099         struct resource *res;
1100         int err = 0;
1101         int size;
1102         int nr_sets;
1103         int setno;
1104
1105         info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1106         if (info == NULL) {
1107                 err = -ENOMEM;
1108                 goto exit_error;
1109         }
1110
1111         platform_set_drvdata(pdev, info);
1112
1113         nand_controller_init(&info->controller);
1114         info->controller.ops = &s3c24xx_nand_controller_ops;
1115
1116         /* get the clock source and enable it */
1117
1118         info->clk = devm_clk_get(&pdev->dev, "nand");
1119         if (IS_ERR(info->clk)) {
1120                 dev_err(&pdev->dev, "failed to get clock\n");
1121                 err = -ENOENT;
1122                 goto exit_error;
1123         }
1124
1125         s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
1126
1127         if (pdev->dev.of_node)
1128                 err = s3c24xx_nand_probe_dt(pdev);
1129         else
1130                 err = s3c24xx_nand_probe_pdata(pdev);
1131
1132         if (err)
1133                 goto exit_error;
1134
1135         plat = to_nand_plat(pdev);
1136
1137         /* allocate and map the resource */
1138
1139         /* currently we assume we have the one resource */
1140         res = pdev->resource;
1141         size = resource_size(res);
1142
1143         info->device    = &pdev->dev;
1144         info->platform  = plat;
1145
1146         info->regs = devm_ioremap_resource(&pdev->dev, res);
1147         if (IS_ERR(info->regs)) {
1148                 err = PTR_ERR(info->regs);
1149                 goto exit_error;
1150         }
1151
1152         dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
1153
1154         if (!plat->sets || plat->nr_sets < 1) {
1155                 err = -EINVAL;
1156                 goto exit_error;
1157         }
1158
1159         sets = plat->sets;
1160         nr_sets = plat->nr_sets;
1161
1162         info->mtd_count = nr_sets;
1163
1164         /* allocate our information */
1165
1166         size = nr_sets * sizeof(*info->mtds);
1167         info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1168         if (info->mtds == NULL) {
1169                 err = -ENOMEM;
1170                 goto exit_error;
1171         }
1172
1173         /* initialise all possible chips */
1174
1175         nmtd = info->mtds;
1176
1177         for (setno = 0; setno < nr_sets; setno++, nmtd++, sets++) {
1178                 struct mtd_info *mtd = nand_to_mtd(&nmtd->chip);
1179
1180                 pr_debug("initialising set %d (%p, info %p)\n",
1181                          setno, nmtd, info);
1182
1183                 mtd->dev.parent = &pdev->dev;
1184                 s3c2410_nand_init_chip(info, nmtd, sets);
1185
1186                 err = nand_scan(&nmtd->chip, sets ? sets->nr_chips : 1);
1187                 if (err)
1188                         goto exit_error;
1189
1190                 s3c2410_nand_add_partition(info, nmtd, sets);
1191         }
1192
1193         /* initialise the hardware */
1194         err = s3c2410_nand_inithw(info);
1195         if (err != 0)
1196                 goto exit_error;
1197
1198         err = s3c2410_nand_cpufreq_register(info);
1199         if (err < 0) {
1200                 dev_err(&pdev->dev, "failed to init cpufreq support\n");
1201                 goto exit_error;
1202         }
1203
1204         if (allow_clk_suspend(info)) {
1205                 dev_info(&pdev->dev, "clock idle support enabled\n");
1206                 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
1207         }
1208
1209         return 0;
1210
1211  exit_error:
1212         s3c24xx_nand_remove(pdev);
1213
1214         if (err == 0)
1215                 err = -EINVAL;
1216         return err;
1217 }
1218
1219 /* PM Support */
1220 #ifdef CONFIG_PM
1221
1222 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
1223 {
1224         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1225
1226         if (info) {
1227                 info->save_sel = readl(info->sel_reg);
1228
1229                 /* For the moment, we must ensure nFCE is high during
1230                  * the time we are suspended. This really should be
1231                  * handled by suspending the MTDs we are using, but
1232                  * that is currently not the case. */
1233
1234                 writel(info->save_sel | info->sel_bit, info->sel_reg);
1235
1236                 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
1237         }
1238
1239         return 0;
1240 }
1241
1242 static int s3c24xx_nand_resume(struct platform_device *dev)
1243 {
1244         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1245         unsigned long sel;
1246
1247         if (info) {
1248                 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
1249                 s3c2410_nand_inithw(info);
1250
1251                 /* Restore the state of the nFCE line. */
1252
1253                 sel = readl(info->sel_reg);
1254                 sel &= ~info->sel_bit;
1255                 sel |= info->save_sel & info->sel_bit;
1256                 writel(sel, info->sel_reg);
1257
1258                 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
1259         }
1260
1261         return 0;
1262 }
1263
1264 #else
1265 #define s3c24xx_nand_suspend NULL
1266 #define s3c24xx_nand_resume NULL
1267 #endif
1268
1269 /* driver device registration */
1270
1271 static const struct platform_device_id s3c24xx_driver_ids[] = {
1272         {
1273                 .name           = "s3c2410-nand",
1274                 .driver_data    = TYPE_S3C2410,
1275         }, {
1276                 .name           = "s3c2440-nand",
1277                 .driver_data    = TYPE_S3C2440,
1278         }, {
1279                 .name           = "s3c2412-nand",
1280                 .driver_data    = TYPE_S3C2412,
1281         }, {
1282                 .name           = "s3c6400-nand",
1283                 .driver_data    = TYPE_S3C2412, /* compatible with 2412 */
1284         },
1285         { }
1286 };
1287
1288 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
1289
1290 static struct platform_driver s3c24xx_nand_driver = {
1291         .probe          = s3c24xx_nand_probe,
1292         .remove         = s3c24xx_nand_remove,
1293         .suspend        = s3c24xx_nand_suspend,
1294         .resume         = s3c24xx_nand_resume,
1295         .id_table       = s3c24xx_driver_ids,
1296         .driver         = {
1297                 .name   = "s3c24xx-nand",
1298                 .of_match_table = s3c24xx_nand_dt_ids,
1299         },
1300 };
1301
1302 module_platform_driver(s3c24xx_nand_driver);
1303
1304 MODULE_LICENSE("GPL");
1305 MODULE_AUTHOR("Ben Dooks <[email protected]>");
1306 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");