drivers/mtd/nand/raw/fsmc_nand.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ST Microelectronics
   4  * Flexible Static Memory Controller (FSMC)
   5  * Driver for NAND portions
   6  *
   7  * Copyright © 2010 ST Microelectronics
   8  * Vipin Kumar <[email protected]>
   9  * Ashish Priyadarshi
  10  *
  11  * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8)
  12  *  Copyright © 2007 STMicroelectronics Pvt. Ltd.
  13  *  Copyright © 2009 Alessandro Rubini
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/completion.h>
  18 #include <linux/dmaengine.h>
  19 #include <linux/dma-direction.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/err.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/resource.h>
  25 #include <linux/sched.h>
  26 #include <linux/types.h>
  27 #include <linux/mtd/mtd.h>
  28 #include <linux/mtd/rawnand.h>
  29 #include <linux/mtd/nand_ecc.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/of.h>
  32 #include <linux/mtd/partitions.h>
  33 #include <linux/io.h>
  34 #include <linux/slab.h>
  35 #include <linux/amba/bus.h>
  36 #include <mtd/mtd-abi.h>
  37
  38 /* fsmc controller registers for NOR flash */
  39 #define CTRL                    0x0
  40         /* ctrl register definitions */
  41         #define BANK_ENABLE             BIT(0)
  42         #define MUXED                   BIT(1)
  43         #define NOR_DEV                 (2 << 2)
  44         #define WIDTH_16                BIT(4)
  45         #define RSTPWRDWN               BIT(6)
  46         #define WPROT                   BIT(7)
  47         #define WRT_ENABLE              BIT(12)
  48         #define WAIT_ENB                BIT(13)
  49
  50 #define CTRL_TIM                0x4
  51         /* ctrl_tim register definitions */
  52
  53 #define FSMC_NOR_BANK_SZ        0x8
  54 #define FSMC_NOR_REG_SIZE       0x40
  55
  56 #define FSMC_NOR_REG(base, bank, reg)   ((base) +                       \
  57                                          (FSMC_NOR_BANK_SZ * (bank)) +  \
  58                                          (reg))
  59
  60 /* fsmc controller registers for NAND flash */
  61 #define FSMC_PC                 0x00
  62         /* pc register definitions */
  63         #define FSMC_RESET              BIT(0)
  64         #define FSMC_WAITON             BIT(1)
  65         #define FSMC_ENABLE             BIT(2)
  66         #define FSMC_DEVTYPE_NAND       BIT(3)
  67         #define FSMC_DEVWID_16          BIT(4)
  68         #define FSMC_ECCEN              BIT(6)
  69         #define FSMC_ECCPLEN_256        BIT(7)
  70         #define FSMC_TCLR_SHIFT         (9)
  71         #define FSMC_TCLR_MASK          (0xF)
  72         #define FSMC_TAR_SHIFT          (13)
  73         #define FSMC_TAR_MASK           (0xF)
  74 #define STS                     0x04
  75         /* sts register definitions */
  76         #define FSMC_CODE_RDY           BIT(15)
  77 #define COMM                    0x08
  78         /* comm register definitions */
  79         #define FSMC_TSET_SHIFT         0
  80         #define FSMC_TSET_MASK          0xFF
  81         #define FSMC_TWAIT_SHIFT        8
  82         #define FSMC_TWAIT_MASK         0xFF
  83         #define FSMC_THOLD_SHIFT        16
  84         #define FSMC_THOLD_MASK         0xFF
  85         #define FSMC_THIZ_SHIFT         24
  86         #define FSMC_THIZ_MASK          0xFF
  87 #define ATTRIB                  0x0C
  88 #define IOATA                   0x10
  89 #define ECC1                    0x14
  90 #define ECC2                    0x18
  91 #define ECC3                    0x1C
  92 #define FSMC_NAND_BANK_SZ       0x20
  93
  94 #define FSMC_BUSY_WAIT_TIMEOUT  (1 * HZ)
  95
  96 struct fsmc_nand_timings {
  97         u8 tclr;
  98         u8 tar;
  99         u8 thiz;
 100         u8 thold;
 101         u8 twait;
 102         u8 tset;
 103 };
 104
 105 enum access_mode {
 106         USE_DMA_ACCESS = 1,
 107         USE_WORD_ACCESS,
 108 };
 109
 110 /**
 111  * struct fsmc_nand_data - structure for FSMC NAND device state
 112  *
 113  * @base:               Inherit from the nand_controller struct
 114  * @pid:                Part ID on the AMBA PrimeCell format
 115  * @nand:               Chip related info for a NAND flash.
 116  *
 117  * @bank:               Bank number for probed device.
 118  * @dev:                Parent device
 119  * @mode:               Access mode
 120  * @clk:                Clock structure for FSMC.
 121  *
 122  * @read_dma_chan:      DMA channel for read access
 123  * @write_dma_chan:     DMA channel for write access to NAND
 124  * @dma_access_complete: Completion structure
 125  *
 126  * @dev_timings:        NAND timings
 127  *
 128  * @data_pa:            NAND Physical port for Data.
 129  * @data_va:            NAND port for Data.
 130  * @cmd_va:             NAND port for Command.
 131  * @addr_va:            NAND port for Address.
 132  * @regs_va:            Registers base address for a given bank.
 133  */
 134 struct fsmc_nand_data {
 135         struct nand_controller  base;
 136         u32                     pid;
 137         struct nand_chip        nand;
 138
 139         unsigned int            bank;
 140         struct device           *dev;
 141         enum access_mode        mode;
 142         struct clk              *clk;
 143
 144         /* DMA related objects */
 145         struct dma_chan         *read_dma_chan;
 146         struct dma_chan         *write_dma_chan;
 147         struct completion       dma_access_complete;
 148
 149         struct fsmc_nand_timings *dev_timings;
 150
 151         dma_addr_t              data_pa;
 152         void __iomem            *data_va;
 153         void __iomem            *cmd_va;
 154         void __iomem            *addr_va;
 155         void __iomem            *regs_va;
 156 };
 157
 158 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
 159                                    struct mtd_oob_region *oobregion)
 160 {
 161         struct nand_chip *chip = mtd_to_nand(mtd);
 162
 163         if (section >= chip->ecc.steps)
 164                 return -ERANGE;
 165
 166         oobregion->offset = (section * 16) + 2;
 167         oobregion->length = 3;
 168
 169         return 0;
 170 }
 171
 172 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
 173                                     struct mtd_oob_region *oobregion)
 174 {
 175         struct nand_chip *chip = mtd_to_nand(mtd);
 176
 177         if (section >= chip->ecc.steps)
 178                 return -ERANGE;
 179
 180         oobregion->offset = (section * 16) + 8;
 181
 182         if (section < chip->ecc.steps - 1)
 183                 oobregion->length = 8;
 184         else
 185                 oobregion->length = mtd->oobsize - oobregion->offset;
 186
 187         return 0;
 188 }
 189
 190 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
 191         .ecc = fsmc_ecc1_ooblayout_ecc,
 192         .free = fsmc_ecc1_ooblayout_free,
 193 };
 194
 195 /*
 196  * ECC placement definitions in oobfree type format.
 197  * There are 13 bytes of ecc for every 512 byte block and it has to be read
 198  * consecutively and immediately after the 512 byte data block for hardware to
 199  * generate the error bit offsets in 512 byte data.
 200  */
 201 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
 202                                    struct mtd_oob_region *oobregion)
 203 {
 204         struct nand_chip *chip = mtd_to_nand(mtd);
 205
 206         if (section >= chip->ecc.steps)
 207                 return -ERANGE;
 208
 209         oobregion->length = chip->ecc.bytes;
 210
 211         if (!section && mtd->writesize <= 512)
 212                 oobregion->offset = 0;
 213         else
 214                 oobregion->offset = (section * 16) + 2;
 215
 216         return 0;
 217 }
 218
 219 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
 220                                     struct mtd_oob_region *oobregion)
 221 {
 222         struct nand_chip *chip = mtd_to_nand(mtd);
 223
 224         if (section >= chip->ecc.steps)
 225                 return -ERANGE;
 226
 227         oobregion->offset = (section * 16) + 15;
 228
 229         if (section < chip->ecc.steps - 1)
 230                 oobregion->length = 3;
 231         else
 232                 oobregion->length = mtd->oobsize - oobregion->offset;
 233
 234         return 0;
 235 }
 236
 237 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
 238         .ecc = fsmc_ecc4_ooblayout_ecc,
 239         .free = fsmc_ecc4_ooblayout_free,
 240 };
 241
 242 static inline struct fsmc_nand_data *nand_to_fsmc(struct nand_chip *chip)
 243 {
 244         return container_of(chip, struct fsmc_nand_data, nand);
 245 }
 246
 247 /*
 248  * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
 249  *
 250  * This routine initializes timing parameters related to NAND memory access in
 251  * FSMC registers
 252  */
 253 static void fsmc_nand_setup(struct fsmc_nand_data *host,
 254                             struct fsmc_nand_timings *tims)
 255 {
 256         u32 value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
 257         u32 tclr, tar, thiz, thold, twait, tset;
 258
 259         tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
 260         tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
 261         thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
 262         thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
 263         twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
 264         tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
 265
 266         if (host->nand.options & NAND_BUSWIDTH_16)
 267                 value |= FSMC_DEVWID_16;
 268
 269         writel_relaxed(value | tclr | tar, host->regs_va + FSMC_PC);
 270         writel_relaxed(thiz | thold | twait | tset, host->regs_va + COMM);
 271         writel_relaxed(thiz | thold | twait | tset, host->regs_va + ATTRIB);
 272 }
 273
 274 static int fsmc_calc_timings(struct fsmc_nand_data *host,
 275                              const struct nand_sdr_timings *sdrt,
 276                              struct fsmc_nand_timings *tims)
 277 {
 278         unsigned long hclk = clk_get_rate(host->clk);
 279         unsigned long hclkn = NSEC_PER_SEC / hclk;
 280         u32 thiz, thold, twait, tset;
 281
 282         if (sdrt->tRC_min < 30000)
 283                 return -EOPNOTSUPP;
 284
 285         tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1;
 286         if (tims->tar > FSMC_TAR_MASK)
 287                 tims->tar = FSMC_TAR_MASK;
 288         tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1;
 289         if (tims->tclr > FSMC_TCLR_MASK)
 290                 tims->tclr = FSMC_TCLR_MASK;
 291
 292         thiz = sdrt->tCS_min - sdrt->tWP_min;
 293         tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn);
 294
 295         thold = sdrt->tDH_min;
 296         if (thold < sdrt->tCH_min)
 297                 thold = sdrt->tCH_min;
 298         if (thold < sdrt->tCLH_min)
 299                 thold = sdrt->tCLH_min;
 300         if (thold < sdrt->tWH_min)
 301                 thold = sdrt->tWH_min;
 302         if (thold < sdrt->tALH_min)
 303                 thold = sdrt->tALH_min;
 304         if (thold < sdrt->tREH_min)
 305                 thold = sdrt->tREH_min;
 306         tims->thold = DIV_ROUND_UP(thold / 1000, hclkn);
 307         if (tims->thold == 0)
 308                 tims->thold = 1;
 309         else if (tims->thold > FSMC_THOLD_MASK)
 310                 tims->thold = FSMC_THOLD_MASK;
 311
 312         twait = max(sdrt->tRP_min, sdrt->tWP_min);
 313         tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1;
 314         if (tims->twait == 0)
 315                 tims->twait = 1;
 316         else if (tims->twait > FSMC_TWAIT_MASK)
 317                 tims->twait = FSMC_TWAIT_MASK;
 318
 319         tset = max(sdrt->tCS_min - sdrt->tWP_min,
 320                    sdrt->tCEA_max - sdrt->tREA_max);
 321         tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1;
 322         if (tims->tset == 0)
 323                 tims->tset = 1;
 324         else if (tims->tset > FSMC_TSET_MASK)
 325                 tims->tset = FSMC_TSET_MASK;
 326
 327         return 0;
 328 }
 329
 330 static int fsmc_setup_data_interface(struct nand_chip *nand, int csline,
 331                                      const struct nand_data_interface *conf)
 332 {
 333         struct fsmc_nand_data *host = nand_to_fsmc(nand);
 334         struct fsmc_nand_timings tims;
 335         const struct nand_sdr_timings *sdrt;
 336         int ret;
 337
 338         sdrt = nand_get_sdr_timings(conf);
 339         if (IS_ERR(sdrt))
 340                 return PTR_ERR(sdrt);
 341
 342         ret = fsmc_calc_timings(host, sdrt, &tims);
 343         if (ret)
 344                 return ret;
 345
 346         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
 347                 return 0;
 348
 349         fsmc_nand_setup(host, &tims);
 350
 351         return 0;
 352 }
 353
 354 /*
 355  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
 356  */
 357 static void fsmc_enable_hwecc(struct nand_chip *chip, int mode)
 358 {
 359         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 360
 361         writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCPLEN_256,
 362                        host->regs_va + FSMC_PC);
 363         writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCEN,
 364                        host->regs_va + FSMC_PC);
 365         writel_relaxed(readl(host->regs_va + FSMC_PC) | FSMC_ECCEN,
 366                        host->regs_va + FSMC_PC);
 367 }
 368
 369 /*
 370  * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
 371  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
 372  * max of 8-bits)
 373  */
 374 static int fsmc_read_hwecc_ecc4(struct nand_chip *chip, const u8 *data,
 375                                 u8 *ecc)
 376 {
 377         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 378         u32 ecc_tmp;
 379         unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
 380
 381         do {
 382                 if (readl_relaxed(host->regs_va + STS) & FSMC_CODE_RDY)
 383                         break;
 384
 385                 cond_resched();
 386         } while (!time_after_eq(jiffies, deadline));
 387
 388         if (time_after_eq(jiffies, deadline)) {
 389                 dev_err(host->dev, "calculate ecc timed out\n");
 390                 return -ETIMEDOUT;
 391         }
 392
 393         ecc_tmp = readl_relaxed(host->regs_va + ECC1);
 394         ecc[0] = ecc_tmp;
 395         ecc[1] = ecc_tmp >> 8;
 396         ecc[2] = ecc_tmp >> 16;
 397         ecc[3] = ecc_tmp >> 24;
 398
 399         ecc_tmp = readl_relaxed(host->regs_va + ECC2);
 400         ecc[4] = ecc_tmp;
 401         ecc[5] = ecc_tmp >> 8;
 402         ecc[6] = ecc_tmp >> 16;
 403         ecc[7] = ecc_tmp >> 24;
 404
 405         ecc_tmp = readl_relaxed(host->regs_va + ECC3);
 406         ecc[8] = ecc_tmp;
 407         ecc[9] = ecc_tmp >> 8;
 408         ecc[10] = ecc_tmp >> 16;
 409         ecc[11] = ecc_tmp >> 24;
 410
 411         ecc_tmp = readl_relaxed(host->regs_va + STS);
 412         ecc[12] = ecc_tmp >> 16;
 413
 414         return 0;
 415 }
 416
 417 /*
 418  * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
 419  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
 420  * max of 1-bit)
 421  */
 422 static int fsmc_read_hwecc_ecc1(struct nand_chip *chip, const u8 *data,
 423                                 u8 *ecc)
 424 {
 425         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 426         u32 ecc_tmp;
 427
 428         ecc_tmp = readl_relaxed(host->regs_va + ECC1);
 429         ecc[0] = ecc_tmp;
 430         ecc[1] = ecc_tmp >> 8;
 431         ecc[2] = ecc_tmp >> 16;
 432
 433         return 0;
 434 }
 435
 436 /* Count the number of 0's in buff upto a max of max_bits */
 437 static int count_written_bits(u8 *buff, int size, int max_bits)
 438 {
 439         int k, written_bits = 0;
 440
 441         for (k = 0; k < size; k++) {
 442                 written_bits += hweight8(~buff[k]);
 443                 if (written_bits > max_bits)
 444                         break;
 445         }
 446
 447         return written_bits;
 448 }
 449
 450 static void dma_complete(void *param)
 451 {
 452         struct fsmc_nand_data *host = param;
 453
 454         complete(&host->dma_access_complete);
 455 }
 456
 457 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
 458                     enum dma_data_direction direction)
 459 {
 460         struct dma_chan *chan;
 461         struct dma_device *dma_dev;
 462         struct dma_async_tx_descriptor *tx;
 463         dma_addr_t dma_dst, dma_src, dma_addr;
 464         dma_cookie_t cookie;
 465         unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 466         int ret;
 467         unsigned long time_left;
 468
 469         if (direction == DMA_TO_DEVICE)
 470                 chan = host->write_dma_chan;
 471         else if (direction == DMA_FROM_DEVICE)
 472                 chan = host->read_dma_chan;
 473         else
 474                 return -EINVAL;
 475
 476         dma_dev = chan->device;
 477         dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
 478
 479         if (direction == DMA_TO_DEVICE) {
 480                 dma_src = dma_addr;
 481                 dma_dst = host->data_pa;
 482         } else {
 483                 dma_src = host->data_pa;
 484                 dma_dst = dma_addr;
 485         }
 486
 487         tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
 488                         len, flags);
 489         if (!tx) {
 490                 dev_err(host->dev, "device_prep_dma_memcpy error\n");
 491                 ret = -EIO;
 492                 goto unmap_dma;
 493         }
 494
 495         tx->callback = dma_complete;
 496         tx->callback_param = host;
 497         cookie = tx->tx_submit(tx);
 498
 499         ret = dma_submit_error(cookie);
 500         if (ret) {
 501                 dev_err(host->dev, "dma_submit_error %d\n", cookie);
 502                 goto unmap_dma;
 503         }
 504
 505         dma_async_issue_pending(chan);
 506
 507         time_left =
 508         wait_for_completion_timeout(&host->dma_access_complete,
 509                                     msecs_to_jiffies(3000));
 510         if (time_left == 0) {
 511                 dmaengine_terminate_all(chan);
 512                 dev_err(host->dev, "wait_for_completion_timeout\n");
 513                 ret = -ETIMEDOUT;
 514                 goto unmap_dma;
 515         }
 516
 517         ret = 0;
 518
 519 unmap_dma:
 520         dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
 521
 522         return ret;
 523 }
 524
 525 /*
 526  * fsmc_write_buf - write buffer to chip
 527  * @host:       FSMC NAND controller
 528  * @buf:        data buffer
 529  * @len:        number of bytes to write
 530  */
 531 static void fsmc_write_buf(struct fsmc_nand_data *host, const u8 *buf,
 532                            int len)
 533 {
 534         int i;
 535
 536         if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
 537             IS_ALIGNED(len, sizeof(u32))) {
 538                 u32 *p = (u32 *)buf;
 539
 540                 len = len >> 2;
 541                 for (i = 0; i < len; i++)
 542                         writel_relaxed(p[i], host->data_va);
 543         } else {
 544                 for (i = 0; i < len; i++)
 545                         writeb_relaxed(buf[i], host->data_va);
 546         }
 547 }
 548
 549 /*
 550  * fsmc_read_buf - read chip data into buffer
 551  * @host:       FSMC NAND controller
 552  * @buf:        buffer to store date
 553  * @len:        number of bytes to read
 554  */
 555 static void fsmc_read_buf(struct fsmc_nand_data *host, u8 *buf, int len)
 556 {
 557         int i;
 558
 559         if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
 560             IS_ALIGNED(len, sizeof(u32))) {
 561                 u32 *p = (u32 *)buf;
 562
 563                 len = len >> 2;
 564                 for (i = 0; i < len; i++)
 565                         p[i] = readl_relaxed(host->data_va);
 566         } else {
 567                 for (i = 0; i < len; i++)
 568                         buf[i] = readb_relaxed(host->data_va);
 569         }
 570 }
 571
 572 /*
 573  * fsmc_read_buf_dma - read chip data into buffer
 574  * @host:       FSMC NAND controller
 575  * @buf:        buffer to store date
 576  * @len:        number of bytes to read
 577  */
 578 static void fsmc_read_buf_dma(struct fsmc_nand_data *host, u8 *buf,
 579                               int len)
 580 {
 581         dma_xfer(host, buf, len, DMA_FROM_DEVICE);
 582 }
 583
 584 /*
 585  * fsmc_write_buf_dma - write buffer to chip
 586  * @host:       FSMC NAND controller
 587  * @buf:        data buffer
 588  * @len:        number of bytes to write
 589  */
 590 static void fsmc_write_buf_dma(struct fsmc_nand_data *host, const u8 *buf,
 591                                int len)
 592 {
 593         dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
 594 }
 595
 596 /* fsmc_select_chip - assert or deassert nCE */
 597 static void fsmc_ce_ctrl(struct fsmc_nand_data *host, bool assert)
 598 {
 599         u32 pc = readl(host->regs_va + FSMC_PC);
 600
 601         if (!assert)
 602                 writel_relaxed(pc & ~FSMC_ENABLE, host->regs_va + FSMC_PC);
 603         else
 604                 writel_relaxed(pc | FSMC_ENABLE, host->regs_va + FSMC_PC);
 605
 606         /*
 607          * nCE line changes must be applied before returning from this
 608          * function.
 609          */
 610         mb();
 611 }
 612
 613 /*
 614  * fsmc_exec_op - hook called by the core to execute NAND operations
 615  *
 616  * This controller is simple enough and thus does not need to use the parser
 617  * provided by the core, instead, handle every situation here.
 618  */
 619 static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op,
 620                         bool check_only)
 621 {
 622         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 623         const struct nand_op_instr *instr = NULL;
 624         int ret = 0;
 625         unsigned int op_id;
 626         int i;
 627
 628         pr_debug("Executing operation [%d instructions]:\n", op->ninstrs);
 629
 630         fsmc_ce_ctrl(host, true);
 631
 632         for (op_id = 0; op_id < op->ninstrs; op_id++) {
 633                 instr = &op->instrs[op_id];
 634
 635                 switch (instr->type) {
 636                 case NAND_OP_CMD_INSTR:
 637                         pr_debug("  ->CMD      [0x%02x]\n",
 638                                  instr->ctx.cmd.opcode);
 639
 640                         writeb_relaxed(instr->ctx.cmd.opcode, host->cmd_va);
 641                         break;
 642
 643                 case NAND_OP_ADDR_INSTR:
 644                         pr_debug("  ->ADDR     [%d cyc]",
 645                                  instr->ctx.addr.naddrs);
 646
 647                         for (i = 0; i < instr->ctx.addr.naddrs; i++)
 648                                 writeb_relaxed(instr->ctx.addr.addrs[i],
 649                                                host->addr_va);
 650                         break;
 651
 652                 case NAND_OP_DATA_IN_INSTR:
 653                         pr_debug("  ->DATA_IN  [%d B%s]\n", instr->ctx.data.len,
 654                                  instr->ctx.data.force_8bit ?
 655                                  ", force 8-bit" : "");
 656
 657                         if (host->mode == USE_DMA_ACCESS)
 658                                 fsmc_read_buf_dma(host, instr->ctx.data.buf.in,
 659                                                   instr->ctx.data.len);
 660                         else
 661                                 fsmc_read_buf(host, instr->ctx.data.buf.in,
 662                                               instr->ctx.data.len);
 663                         break;
 664
 665                 case NAND_OP_DATA_OUT_INSTR:
 666                         pr_debug("  ->DATA_OUT [%d B%s]\n", instr->ctx.data.len,
 667                                  instr->ctx.data.force_8bit ?
 668                                  ", force 8-bit" : "");
 669
 670                         if (host->mode == USE_DMA_ACCESS)
 671                                 fsmc_write_buf_dma(host,
 672                                                    instr->ctx.data.buf.out,
 673                                                    instr->ctx.data.len);
 674                         else
 675                                 fsmc_write_buf(host, instr->ctx.data.buf.out,
 676                                                instr->ctx.data.len);
 677                         break;
 678
 679                 case NAND_OP_WAITRDY_INSTR:
 680                         pr_debug("  ->WAITRDY  [max %d ms]\n",
 681                                  instr->ctx.waitrdy.timeout_ms);
 682
 683                         ret = nand_soft_waitrdy(chip,
 684                                                 instr->ctx.waitrdy.timeout_ms);
 685                         break;
 686                 }
 687         }
 688
 689         fsmc_ce_ctrl(host, false);
 690
 691         return ret;
 692 }
 693
 694 /*
 695  * fsmc_read_page_hwecc
 696  * @chip:       nand chip info structure
 697  * @buf:        buffer to store read data
 698  * @oob_required:       caller expects OOB data read to chip->oob_poi
 699  * @page:       page number to read
 700  *
 701  * This routine is needed for fsmc version 8 as reading from NAND chip has to be
 702  * performed in a strict sequence as follows:
 703  * data(512 byte) -> ecc(13 byte)
 704  * After this read, fsmc hardware generates and reports error data bits(up to a
 705  * max of 8 bits)
 706  */
 707 static int fsmc_read_page_hwecc(struct nand_chip *chip, u8 *buf,
 708                                 int oob_required, int page)
 709 {
 710         struct mtd_info *mtd = nand_to_mtd(chip);
 711         int i, j, s, stat, eccsize = chip->ecc.size;
 712         int eccbytes = chip->ecc.bytes;
 713         int eccsteps = chip->ecc.steps;
 714         u8 *p = buf;
 715         u8 *ecc_calc = chip->ecc.calc_buf;
 716         u8 *ecc_code = chip->ecc.code_buf;
 717         int off, len, ret, group = 0;
 718         /*
 719          * ecc_oob is intentionally taken as u16. In 16bit devices, we
 720          * end up reading 14 bytes (7 words) from oob. The local array is
 721          * to maintain word alignment
 722          */
 723         u16 ecc_oob[7];
 724         u8 *oob = (u8 *)&ecc_oob[0];
 725         unsigned int max_bitflips = 0;
 726
 727         for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
 728                 nand_read_page_op(chip, page, s * eccsize, NULL, 0);
 729                 chip->ecc.hwctl(chip, NAND_ECC_READ);
 730                 ret = nand_read_data_op(chip, p, eccsize, false);
 731                 if (ret)
 732                         return ret;
 733
 734                 for (j = 0; j < eccbytes;) {
 735                         struct mtd_oob_region oobregion;
 736
 737                         ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
 738                         if (ret)
 739                                 return ret;
 740
 741                         off = oobregion.offset;
 742                         len = oobregion.length;
 743
 744                         /*
 745                          * length is intentionally kept a higher multiple of 2
 746                          * to read at least 13 bytes even in case of 16 bit NAND
 747                          * devices
 748                          */
 749                         if (chip->options & NAND_BUSWIDTH_16)
 750                                 len = roundup(len, 2);
 751
 752                         nand_read_oob_op(chip, page, off, oob + j, len);
 753                         j += len;
 754                 }
 755
 756                 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
 757                 chip->ecc.calculate(chip, p, &ecc_calc[i]);
 758
 759                 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
 760                 if (stat < 0) {
 761                         mtd->ecc_stats.failed++;
 762                 } else {
 763                         mtd->ecc_stats.corrected += stat;
 764                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 765                 }
 766         }
 767
 768         return max_bitflips;
 769 }
 770
 771 /*
 772  * fsmc_bch8_correct_data
 773  * @mtd:        mtd info structure
 774  * @dat:        buffer of read data
 775  * @read_ecc:   ecc read from device spare area
 776  * @calc_ecc:   ecc calculated from read data
 777  *
 778  * calc_ecc is a 104 bit information containing maximum of 8 error
 779  * offset information of 13 bits each in 512 bytes of read data.
 780  */
 781 static int fsmc_bch8_correct_data(struct nand_chip *chip, u8 *dat,
 782                                   u8 *read_ecc, u8 *calc_ecc)
 783 {
 784         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 785         u32 err_idx[8];
 786         u32 num_err, i;
 787         u32 ecc1, ecc2, ecc3, ecc4;
 788
 789         num_err = (readl_relaxed(host->regs_va + STS) >> 10) & 0xF;
 790
 791         /* no bit flipping */
 792         if (likely(num_err == 0))
 793                 return 0;
 794
 795         /* too many errors */
 796         if (unlikely(num_err > 8)) {
 797                 /*
 798                  * This is a temporary erase check. A newly erased page read
 799                  * would result in an ecc error because the oob data is also
 800                  * erased to FF and the calculated ecc for an FF data is not
 801                  * FF..FF.
 802                  * This is a workaround to skip performing correction in case
 803                  * data is FF..FF
 804                  *
 805                  * Logic:
 806                  * For every page, each bit written as 0 is counted until these
 807                  * number of bits are greater than 8 (the maximum correction
 808                  * capability of FSMC for each 512 + 13 bytes)
 809                  */
 810
 811                 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
 812                 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
 813
 814                 if ((bits_ecc + bits_data) <= 8) {
 815                         if (bits_data)
 816                                 memset(dat, 0xff, chip->ecc.size);
 817                         return bits_data;
 818                 }
 819
 820                 return -EBADMSG;
 821         }
 822
 823         /*
 824          * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
 825          * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
 826          *
 827          * calc_ecc is a 104 bit information containing maximum of 8 error
 828          * offset information of 13 bits each. calc_ecc is copied into a
 829          * u64 array and error offset indexes are populated in err_idx
 830          * array
 831          */
 832         ecc1 = readl_relaxed(host->regs_va + ECC1);
 833         ecc2 = readl_relaxed(host->regs_va + ECC2);
 834         ecc3 = readl_relaxed(host->regs_va + ECC3);
 835         ecc4 = readl_relaxed(host->regs_va + STS);
 836
 837         err_idx[0] = (ecc1 >> 0) & 0x1FFF;
 838         err_idx[1] = (ecc1 >> 13) & 0x1FFF;
 839         err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
 840         err_idx[3] = (ecc2 >> 7) & 0x1FFF;
 841         err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
 842         err_idx[5] = (ecc3 >> 1) & 0x1FFF;
 843         err_idx[6] = (ecc3 >> 14) & 0x1FFF;
 844         err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
 845
 846         i = 0;
 847         while (num_err--) {
 848                 change_bit(0, (unsigned long *)&err_idx[i]);
 849                 change_bit(1, (unsigned long *)&err_idx[i]);
 850
 851                 if (err_idx[i] < chip->ecc.size * 8) {
 852                         change_bit(err_idx[i], (unsigned long *)dat);
 853                         i++;
 854                 }
 855         }
 856         return i;
 857 }
 858
 859 static bool filter(struct dma_chan *chan, void *slave)
 860 {
 861         chan->private = slave;
 862         return true;
 863 }
 864
 865 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
 866                                      struct fsmc_nand_data *host,
 867                                      struct nand_chip *nand)
 868 {
 869         struct device_node *np = pdev->dev.of_node;
 870         u32 val;
 871         int ret;
 872
 873         nand->options = 0;
 874
 875         if (!of_property_read_u32(np, "bank-width", &val)) {
 876                 if (val == 2) {
 877                         nand->options |= NAND_BUSWIDTH_16;
 878                 } else if (val != 1) {
 879                         dev_err(&pdev->dev, "invalid bank-width %u\n", val);
 880                         return -EINVAL;
 881                 }
 882         }
 883
 884         if (of_get_property(np, "nand-skip-bbtscan", NULL))
 885                 nand->options |= NAND_SKIP_BBTSCAN;
 886
 887         host->dev_timings = devm_kzalloc(&pdev->dev,
 888                                          sizeof(*host->dev_timings),
 889                                          GFP_KERNEL);
 890         if (!host->dev_timings)
 891                 return -ENOMEM;
 892
 893         ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
 894                                         sizeof(*host->dev_timings));
 895         if (ret)
 896                 host->dev_timings = NULL;
 897
 898         /* Set default NAND bank to 0 */
 899         host->bank = 0;
 900         if (!of_property_read_u32(np, "bank", &val)) {
 901                 if (val > 3) {
 902                         dev_err(&pdev->dev, "invalid bank %u\n", val);
 903                         return -EINVAL;
 904                 }
 905                 host->bank = val;
 906         }
 907         return 0;
 908 }
 909
 910 static int fsmc_nand_attach_chip(struct nand_chip *nand)
 911 {
 912         struct mtd_info *mtd = nand_to_mtd(nand);
 913         struct fsmc_nand_data *host = nand_to_fsmc(nand);
 914
 915         if (AMBA_REV_BITS(host->pid) >= 8) {
 916                 switch (mtd->oobsize) {
 917                 case 16:
 918                 case 64:
 919                 case 128:
 920                 case 224:
 921                 case 256:
 922                         break;
 923                 default:
 924                         dev_warn(host->dev,
 925                                  "No oob scheme defined for oobsize %d\n",
 926                                  mtd->oobsize);
 927                         return -EINVAL;
 928                 }
 929
 930                 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
 931
 932                 return 0;
 933         }
 934
 935         switch (nand->ecc.mode) {
 936         case NAND_ECC_HW:
 937                 dev_info(host->dev, "Using 1-bit HW ECC scheme\n");
 938                 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
 939                 nand->ecc.correct = nand_correct_data;
 940                 nand->ecc.bytes = 3;
 941                 nand->ecc.strength = 1;
 942                 nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
 943                 break;
 944
 945         case NAND_ECC_SOFT:
 946                 if (nand->ecc.algo == NAND_ECC_BCH) {
 947                         dev_info(host->dev,
 948                                  "Using 4-bit SW BCH ECC scheme\n");
 949                         break;
 950                 }
 951
 952         case NAND_ECC_ON_DIE:
 953                 break;
 954
 955         default:
 956                 dev_err(host->dev, "Unsupported ECC mode!\n");
 957                 return -ENOTSUPP;
 958         }
 959
 960         /*
 961          * Don't set layout for BCH4 SW ECC. This will be
 962          * generated later in nand_bch_init() later.
 963          */
 964         if (nand->ecc.mode == NAND_ECC_HW) {
 965                 switch (mtd->oobsize) {
 966                 case 16:
 967                 case 64:
 968                 case 128:
 969                         mtd_set_ooblayout(mtd,
 970                                           &fsmc_ecc1_ooblayout_ops);
 971                         break;
 972                 default:
 973                         dev_warn(host->dev,
 974                                  "No oob scheme defined for oobsize %d\n",
 975                                  mtd->oobsize);
 976                         return -EINVAL;
 977                 }
 978         }
 979
 980         return 0;
 981 }
 982
 983 static const struct nand_controller_ops fsmc_nand_controller_ops = {
 984         .attach_chip = fsmc_nand_attach_chip,
 985         .exec_op = fsmc_exec_op,
 986         .setup_data_interface = fsmc_setup_data_interface,
 987 };
 988
 989 /*
 990  * fsmc_nand_probe - Probe function
 991  * @pdev:       platform device structure
 992  */
 993 static int __init fsmc_nand_probe(struct platform_device *pdev)
 994 {
 995         struct fsmc_nand_data *host;
 996         struct mtd_info *mtd;
 997         struct nand_chip *nand;
 998         struct resource *res;
 999         void __iomem *base;
1000         dma_cap_mask_t mask;
1001         int ret = 0;
1002         u32 pid;
1003         int i;
1004
1005         /* Allocate memory for the device structure (and zero it) */
1006         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
1007         if (!host)
1008                 return -ENOMEM;
1009
1010         nand = &host->nand;
1011
1012         ret = fsmc_nand_probe_config_dt(pdev, host, nand);
1013         if (ret)
1014                 return ret;
1015
1016         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
1017         host->data_va = devm_ioremap_resource(&pdev->dev, res);
1018         if (IS_ERR(host->data_va))
1019                 return PTR_ERR(host->data_va);
1020
1021         host->data_pa = (dma_addr_t)res->start;
1022
1023         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
1024         host->addr_va = devm_ioremap_resource(&pdev->dev, res);
1025         if (IS_ERR(host->addr_va))
1026                 return PTR_ERR(host->addr_va);
1027
1028         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
1029         host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
1030         if (IS_ERR(host->cmd_va))
1031                 return PTR_ERR(host->cmd_va);
1032
1033         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
1034         base = devm_ioremap_resource(&pdev->dev, res);
1035         if (IS_ERR(base))
1036                 return PTR_ERR(base);
1037
1038         host->regs_va = base + FSMC_NOR_REG_SIZE +
1039                 (host->bank * FSMC_NAND_BANK_SZ);
1040
1041         host->clk = devm_clk_get(&pdev->dev, NULL);
1042         if (IS_ERR(host->clk)) {
1043                 dev_err(&pdev->dev, "failed to fetch block clock\n");
1044                 return PTR_ERR(host->clk);
1045         }
1046
1047         ret = clk_prepare_enable(host->clk);
1048         if (ret)
1049                 return ret;
1050
1051         /*
1052          * This device ID is actually a common AMBA ID as used on the
1053          * AMBA PrimeCell bus. However it is not a PrimeCell.
1054          */
1055         for (pid = 0, i = 0; i < 4; i++)
1056                 pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) &
1057                         255) << (i * 8);
1058
1059         host->pid = pid;
1060
1061         dev_info(&pdev->dev,
1062                  "FSMC device partno %03x, manufacturer %02x, revision %02x, config %02x\n",
1063                  AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
1064                  AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
1065
1066         host->dev = &pdev->dev;
1067
1068         if (host->mode == USE_DMA_ACCESS)
1069                 init_completion(&host->dma_access_complete);
1070
1071         /* Link all private pointers */
1072         mtd = nand_to_mtd(&host->nand);
1073         nand_set_flash_node(nand, pdev->dev.of_node);
1074
1075         mtd->dev.parent = &pdev->dev;
1076
1077         /*
1078          * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
1079          * can overwrite this value if the DT provides a different value.
1080          */
1081         nand->ecc.mode = NAND_ECC_HW;
1082         nand->ecc.hwctl = fsmc_enable_hwecc;
1083         nand->ecc.size = 512;
1084         nand->badblockbits = 7;
1085
1086         if (host->mode == USE_DMA_ACCESS) {
1087                 dma_cap_zero(mask);
1088                 dma_cap_set(DMA_MEMCPY, mask);
1089                 host->read_dma_chan = dma_request_channel(mask, filter, NULL);
1090                 if (!host->read_dma_chan) {
1091                         dev_err(&pdev->dev, "Unable to get read dma channel\n");
1092                         goto disable_clk;
1093                 }
1094                 host->write_dma_chan = dma_request_channel(mask, filter, NULL);
1095                 if (!host->write_dma_chan) {
1096                         dev_err(&pdev->dev, "Unable to get write dma channel\n");
1097                         goto release_dma_read_chan;
1098                 }
1099         }
1100
1101         if (host->dev_timings) {
1102                 fsmc_nand_setup(host, host->dev_timings);
1103                 nand->options |= NAND_KEEP_TIMINGS;
1104         }
1105
1106         if (AMBA_REV_BITS(host->pid) >= 8) {
1107                 nand->ecc.read_page = fsmc_read_page_hwecc;
1108                 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
1109                 nand->ecc.correct = fsmc_bch8_correct_data;
1110                 nand->ecc.bytes = 13;
1111                 nand->ecc.strength = 8;
1112         }
1113
1114         nand_controller_init(&host->base);
1115         host->base.ops = &fsmc_nand_controller_ops;
1116         nand->controller = &host->base;
1117
1118         /*
1119          * Scan to find existence of the device
1120          */
1121         ret = nand_scan(nand, 1);
1122         if (ret)
1123                 goto release_dma_write_chan;
1124
1125         mtd->name = "nand";
1126         ret = mtd_device_register(mtd, NULL, 0);
1127         if (ret)
1128                 goto cleanup_nand;
1129
1130         platform_set_drvdata(pdev, host);
1131         dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1132
1133         return 0;
1134
1135 cleanup_nand:
1136         nand_cleanup(nand);
1137 release_dma_write_chan:
1138         if (host->mode == USE_DMA_ACCESS)
1139                 dma_release_channel(host->write_dma_chan);
1140 release_dma_read_chan:
1141         if (host->mode == USE_DMA_ACCESS)
1142                 dma_release_channel(host->read_dma_chan);
1143 disable_clk:
1144         clk_disable_unprepare(host->clk);
1145
1146         return ret;
1147 }
1148
1149 /*
1150  * Clean up routine
1151  */
1152 static int fsmc_nand_remove(struct platform_device *pdev)
1153 {
1154         struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1155
1156         if (host) {
1157                 nand_release(&host->nand);
1158
1159                 if (host->mode == USE_DMA_ACCESS) {
1160                         dma_release_channel(host->write_dma_chan);
1161                         dma_release_channel(host->read_dma_chan);
1162                 }
1163                 clk_disable_unprepare(host->clk);
1164         }
1165
1166         return 0;
1167 }
1168
1169 #ifdef CONFIG_PM_SLEEP
1170 static int fsmc_nand_suspend(struct device *dev)
1171 {
1172         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1173
1174         if (host)
1175                 clk_disable_unprepare(host->clk);
1176
1177         return 0;
1178 }
1179
1180 static int fsmc_nand_resume(struct device *dev)
1181 {
1182         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1183
1184         if (host) {
1185                 clk_prepare_enable(host->clk);
1186                 if (host->dev_timings)
1187                         fsmc_nand_setup(host, host->dev_timings);
1188         }
1189
1190         return 0;
1191 }
1192 #endif
1193
1194 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1195
1196 static const struct of_device_id fsmc_nand_id_table[] = {
1197         { .compatible = "st,spear600-fsmc-nand" },
1198         { .compatible = "stericsson,fsmc-nand" },
1199         {}
1200 };
1201 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1202
1203 static struct platform_driver fsmc_nand_driver = {
1204         .remove = fsmc_nand_remove,
1205         .driver = {
1206                 .name = "fsmc-nand",
1207                 .of_match_table = fsmc_nand_id_table,
1208                 .pm = &fsmc_nand_pm_ops,
1209         },
1210 };
1211
1212 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1213
1214 MODULE_LICENSE("GPL v2");
1215 MODULE_AUTHOR("Vipin Kumar <[email protected]>, Ashish Priyadarshi");
1216 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");