drivers/mtd/nand/raw/fsl_ifc_nand.c

   1 /*
   2  * Freescale Integrated Flash Controller NAND driver
   3  *
   4  * Copyright 2011-2012 Freescale Semiconductor, Inc
   5  *
   6  * Author: Dipen Dudhat <[email protected]>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/types.h>
  25 #include <linux/kernel.h>
  26 #include <linux/of_address.h>
  27 #include <linux/slab.h>
  28 #include <linux/mtd/mtd.h>
  29 #include <linux/mtd/rawnand.h>
  30 #include <linux/mtd/partitions.h>
  31 #include <linux/mtd/nand_ecc.h>
  32 #include <linux/fsl_ifc.h>
  33 #include <linux/iopoll.h>
  34
  35 #define ERR_BYTE                0xFF /* Value returned for read
  36                                         bytes when read failed  */
  37 #define IFC_TIMEOUT_MSECS       500  /* Maximum number of mSecs to wait
  38                                         for IFC NAND Machine    */
  39
  40 struct fsl_ifc_ctrl;
  41
  42 /* mtd information per set */
  43 struct fsl_ifc_mtd {
  44         struct nand_chip chip;
  45         struct fsl_ifc_ctrl *ctrl;
  46
  47         struct device *dev;
  48         int bank;               /* Chip select bank number              */
  49         unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
  50         u8 __iomem *vbase;      /* Chip select base virtual address     */
  51 };
  52
  53 /* overview of the fsl ifc controller */
  54 struct fsl_ifc_nand_ctrl {
  55         struct nand_controller controller;
  56         struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
  57
  58         void __iomem *addr;     /* Address of assigned IFC buffer       */
  59         unsigned int page;      /* Last page written to / read from     */
  60         unsigned int read_bytes;/* Number of bytes read during command  */
  61         unsigned int column;    /* Saved column from SEQIN              */
  62         unsigned int index;     /* Pointer to next byte to 'read'       */
  63         unsigned int oob;       /* Non zero if operating on OOB data    */
  64         unsigned int eccread;   /* Non zero for a full-page ECC read    */
  65         unsigned int counter;   /* counter for the initializations      */
  66         unsigned int max_bitflips;  /* Saved during READ0 cmd           */
  67 };
  68
  69 static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
  70
  71 /*
  72  * Generic flash bbt descriptors
  73  */
  74 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
  75 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
  76
  77 static struct nand_bbt_descr bbt_main_descr = {
  78         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  79                    NAND_BBT_2BIT | NAND_BBT_VERSION,
  80         .offs = 2, /* 0 on 8-bit small page */
  81         .len = 4,
  82         .veroffs = 6,
  83         .maxblocks = 4,
  84         .pattern = bbt_pattern,
  85 };
  86
  87 static struct nand_bbt_descr bbt_mirror_descr = {
  88         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  89                    NAND_BBT_2BIT | NAND_BBT_VERSION,
  90         .offs = 2, /* 0 on 8-bit small page */
  91         .len = 4,
  92         .veroffs = 6,
  93         .maxblocks = 4,
  94         .pattern = mirror_pattern,
  95 };
  96
  97 static int fsl_ifc_ooblayout_ecc(struct mtd_info *mtd, int section,
  98                                  struct mtd_oob_region *oobregion)
  99 {
 100         struct nand_chip *chip = mtd_to_nand(mtd);
 101
 102         if (section)
 103                 return -ERANGE;
 104
 105         oobregion->offset = 8;
 106         oobregion->length = chip->ecc.total;
 107
 108         return 0;
 109 }
 110
 111 static int fsl_ifc_ooblayout_free(struct mtd_info *mtd, int section,
 112                                   struct mtd_oob_region *oobregion)
 113 {
 114         struct nand_chip *chip = mtd_to_nand(mtd);
 115
 116         if (section > 1)
 117                 return -ERANGE;
 118
 119         if (mtd->writesize == 512 &&
 120             !(chip->options & NAND_BUSWIDTH_16)) {
 121                 if (!section) {
 122                         oobregion->offset = 0;
 123                         oobregion->length = 5;
 124                 } else {
 125                         oobregion->offset = 6;
 126                         oobregion->length = 2;
 127                 }
 128
 129                 return 0;
 130         }
 131
 132         if (!section) {
 133                 oobregion->offset = 2;
 134                 oobregion->length = 6;
 135         } else {
 136                 oobregion->offset = chip->ecc.total + 8;
 137                 oobregion->length = mtd->oobsize - oobregion->offset;
 138         }
 139
 140         return 0;
 141 }
 142
 143 static const struct mtd_ooblayout_ops fsl_ifc_ooblayout_ops = {
 144         .ecc = fsl_ifc_ooblayout_ecc,
 145         .free = fsl_ifc_ooblayout_free,
 146 };
 147
 148 /*
 149  * Set up the IFC hardware block and page address fields, and the ifc nand
 150  * structure addr field to point to the correct IFC buffer in memory
 151  */
 152 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 153 {
 154         struct nand_chip *chip = mtd_to_nand(mtd);
 155         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 156         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 157         struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 158         int buf_num;
 159
 160         ifc_nand_ctrl->page = page_addr;
 161         /* Program ROW0/COL0 */
 162         ifc_out32(page_addr, &ifc->ifc_nand.row0);
 163         ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
 164
 165         buf_num = page_addr & priv->bufnum_mask;
 166
 167         ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
 168         ifc_nand_ctrl->index = column;
 169
 170         /* for OOB data point to the second half of the buffer */
 171         if (oob)
 172                 ifc_nand_ctrl->index += mtd->writesize;
 173 }
 174
 175 /* returns nonzero if entire page is blank */
 176 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
 177                           u32 eccstat, unsigned int bufnum)
 178 {
 179         return  (eccstat >> ((3 - bufnum % 4) * 8)) & 15;
 180 }
 181
 182 /*
 183  * execute IFC NAND command and wait for it to complete
 184  */
 185 static void fsl_ifc_run_command(struct mtd_info *mtd)
 186 {
 187         struct nand_chip *chip = mtd_to_nand(mtd);
 188         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 189         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 190         struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
 191         struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 192         u32 eccstat;
 193         int i;
 194
 195         /* set the chip select for NAND Transaction */
 196         ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT,
 197                   &ifc->ifc_nand.nand_csel);
 198
 199         dev_vdbg(priv->dev,
 200                         "%s: fir0=%08x fcr0=%08x\n",
 201                         __func__,
 202                         ifc_in32(&ifc->ifc_nand.nand_fir0),
 203                         ifc_in32(&ifc->ifc_nand.nand_fcr0));
 204
 205         ctrl->nand_stat = 0;
 206
 207         /* start read/write seq */
 208         ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
 209
 210         /* wait for command complete flag or timeout */
 211         wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
 212                            msecs_to_jiffies(IFC_TIMEOUT_MSECS));
 213
 214         /* ctrl->nand_stat will be updated from IRQ context */
 215         if (!ctrl->nand_stat)
 216                 dev_err(priv->dev, "Controller is not responding\n");
 217         if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
 218                 dev_err(priv->dev, "NAND Flash Timeout Error\n");
 219         if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
 220                 dev_err(priv->dev, "NAND Flash Write Protect Error\n");
 221
 222         nctrl->max_bitflips = 0;
 223
 224         if (nctrl->eccread) {
 225                 int errors;
 226                 int bufnum = nctrl->page & priv->bufnum_mask;
 227                 int sector_start = bufnum * chip->ecc.steps;
 228                 int sector_end = sector_start + chip->ecc.steps - 1;
 229                 __be32 __iomem *eccstat_regs;
 230
 231                 eccstat_regs = ifc->ifc_nand.nand_eccstat;
 232                 eccstat = ifc_in32(&eccstat_regs[sector_start / 4]);
 233
 234                 for (i = sector_start; i <= sector_end; i++) {
 235                         if (i != sector_start && !(i % 4))
 236                                 eccstat = ifc_in32(&eccstat_regs[i / 4]);
 237
 238                         errors = check_read_ecc(mtd, ctrl, eccstat, i);
 239
 240                         if (errors == 15) {
 241                                 /*
 242                                  * Uncorrectable error.
 243                                  * We'll check for blank pages later.
 244                                  *
 245                                  * We disable ECCER reporting due to...
 246                                  * erratum IFC-A002770 -- so report it now if we
 247                                  * see an uncorrectable error in ECCSTAT.
 248                                  */
 249                                 ctrl->nand_stat |= IFC_NAND_EVTER_STAT_ECCER;
 250                                 continue;
 251                         }
 252
 253                         mtd->ecc_stats.corrected += errors;
 254                         nctrl->max_bitflips = max_t(unsigned int,
 255                                                     nctrl->max_bitflips,
 256                                                     errors);
 257                 }
 258
 259                 nctrl->eccread = 0;
 260         }
 261 }
 262
 263 static void fsl_ifc_do_read(struct nand_chip *chip,
 264                             int oob,
 265                             struct mtd_info *mtd)
 266 {
 267         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 268         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 269         struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 270
 271         /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
 272         if (mtd->writesize > 512) {
 273                 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 274                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 275                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 276                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
 277                           (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
 278                           &ifc->ifc_nand.nand_fir0);
 279                 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
 280
 281                 ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
 282                           (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
 283                           &ifc->ifc_nand.nand_fcr0);
 284         } else {
 285                 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 286                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 287                           (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
 288                           (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
 289                           &ifc->ifc_nand.nand_fir0);
 290                 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
 291
 292                 if (oob)
 293                         ifc_out32(NAND_CMD_READOOB <<
 294                                   IFC_NAND_FCR0_CMD0_SHIFT,
 295                                   &ifc->ifc_nand.nand_fcr0);
 296                 else
 297                         ifc_out32(NAND_CMD_READ0 <<
 298                                   IFC_NAND_FCR0_CMD0_SHIFT,
 299                                   &ifc->ifc_nand.nand_fcr0);
 300         }
 301 }
 302
 303 /* cmdfunc send commands to the IFC NAND Machine */
 304 static void fsl_ifc_cmdfunc(struct nand_chip *chip, unsigned int command,
 305                             int column, int page_addr) {
 306         struct mtd_info *mtd = nand_to_mtd(chip);
 307         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 308         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 309         struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 310
 311         /* clear the read buffer */
 312         ifc_nand_ctrl->read_bytes = 0;
 313         if (command != NAND_CMD_PAGEPROG)
 314                 ifc_nand_ctrl->index = 0;
 315
 316         switch (command) {
 317         /* READ0 read the entire buffer to use hardware ECC. */
 318         case NAND_CMD_READ0:
 319                 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
 320                 set_addr(mtd, 0, page_addr, 0);
 321
 322                 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 323                 ifc_nand_ctrl->index += column;
 324
 325                 if (chip->ecc.mode == NAND_ECC_HW)
 326                         ifc_nand_ctrl->eccread = 1;
 327
 328                 fsl_ifc_do_read(chip, 0, mtd);
 329                 fsl_ifc_run_command(mtd);
 330                 return;
 331
 332         /* READOOB reads only the OOB because no ECC is performed. */
 333         case NAND_CMD_READOOB:
 334                 ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
 335                 set_addr(mtd, column, page_addr, 1);
 336
 337                 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 338
 339                 fsl_ifc_do_read(chip, 1, mtd);
 340                 fsl_ifc_run_command(mtd);
 341
 342                 return;
 343
 344         case NAND_CMD_READID:
 345         case NAND_CMD_PARAM: {
 346                 /*
 347                  * For READID, read 8 bytes that are currently used.
 348                  * For PARAM, read all 3 copies of 256-bytes pages.
 349                  */
 350                 int len = 8;
 351                 int timing = IFC_FIR_OP_RB;
 352                 if (command == NAND_CMD_PARAM) {
 353                         timing = IFC_FIR_OP_RBCD;
 354                         len = 256 * 3;
 355                 }
 356
 357                 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 358                           (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 359                           (timing << IFC_NAND_FIR0_OP2_SHIFT),
 360                           &ifc->ifc_nand.nand_fir0);
 361                 ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT,
 362                           &ifc->ifc_nand.nand_fcr0);
 363                 ifc_out32(column, &ifc->ifc_nand.row3);
 364
 365                 ifc_out32(len, &ifc->ifc_nand.nand_fbcr);
 366                 ifc_nand_ctrl->read_bytes = len;
 367
 368                 set_addr(mtd, 0, 0, 0);
 369                 fsl_ifc_run_command(mtd);
 370                 return;
 371         }
 372
 373         /* ERASE1 stores the block and page address */
 374         case NAND_CMD_ERASE1:
 375                 set_addr(mtd, 0, page_addr, 0);
 376                 return;
 377
 378         /* ERASE2 uses the block and page address from ERASE1 */
 379         case NAND_CMD_ERASE2:
 380                 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 381                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 382                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
 383                           &ifc->ifc_nand.nand_fir0);
 384
 385                 ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
 386                           (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
 387                           &ifc->ifc_nand.nand_fcr0);
 388
 389                 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
 390                 ifc_nand_ctrl->read_bytes = 0;
 391                 fsl_ifc_run_command(mtd);
 392                 return;
 393
 394         /* SEQIN sets up the addr buffer and all registers except the length */
 395         case NAND_CMD_SEQIN: {
 396                 u32 nand_fcr0;
 397                 ifc_nand_ctrl->column = column;
 398                 ifc_nand_ctrl->oob = 0;
 399
 400                 if (mtd->writesize > 512) {
 401                         nand_fcr0 =
 402                                 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
 403                                 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
 404                                 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
 405
 406                         ifc_out32(
 407                                 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 408                                 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 409                                 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 410                                 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
 411                                 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
 412                                 &ifc->ifc_nand.nand_fir0);
 413                         ifc_out32(
 414                                 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
 415                                 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) |
 416                                 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
 417                                 &ifc->ifc_nand.nand_fir1);
 418                 } else {
 419                         nand_fcr0 = ((NAND_CMD_PAGEPROG <<
 420                                         IFC_NAND_FCR0_CMD1_SHIFT) |
 421                                     (NAND_CMD_SEQIN <<
 422                                         IFC_NAND_FCR0_CMD2_SHIFT) |
 423                                     (NAND_CMD_STATUS <<
 424                                         IFC_NAND_FCR0_CMD3_SHIFT));
 425
 426                         ifc_out32(
 427                                 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 428                                 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
 429                                 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 430                                 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
 431                                 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
 432                                 &ifc->ifc_nand.nand_fir0);
 433                         ifc_out32(
 434                                 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
 435                                 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
 436                                 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) |
 437                                 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
 438                                 &ifc->ifc_nand.nand_fir1);
 439
 440                         if (column >= mtd->writesize)
 441                                 nand_fcr0 |=
 442                                 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
 443                         else
 444                                 nand_fcr0 |=
 445                                 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
 446                 }
 447
 448                 if (column >= mtd->writesize) {
 449                         /* OOB area --> READOOB */
 450                         column -= mtd->writesize;
 451                         ifc_nand_ctrl->oob = 1;
 452                 }
 453                 ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
 454                 set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
 455                 return;
 456         }
 457
 458         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 459         case NAND_CMD_PAGEPROG: {
 460                 if (ifc_nand_ctrl->oob) {
 461                         ifc_out32(ifc_nand_ctrl->index -
 462                                   ifc_nand_ctrl->column,
 463                                   &ifc->ifc_nand.nand_fbcr);
 464                 } else {
 465                         ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
 466                 }
 467
 468                 fsl_ifc_run_command(mtd);
 469                 return;
 470         }
 471
 472         case NAND_CMD_STATUS: {
 473                 void __iomem *addr;
 474
 475                 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 476                           (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
 477                           &ifc->ifc_nand.nand_fir0);
 478                 ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
 479                           &ifc->ifc_nand.nand_fcr0);
 480                 ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
 481                 set_addr(mtd, 0, 0, 0);
 482                 ifc_nand_ctrl->read_bytes = 1;
 483
 484                 fsl_ifc_run_command(mtd);
 485
 486                 /*
 487                  * The chip always seems to report that it is
 488                  * write-protected, even when it is not.
 489                  */
 490                 addr = ifc_nand_ctrl->addr;
 491                 if (chip->options & NAND_BUSWIDTH_16)
 492                         ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr);
 493                 else
 494                         ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr);
 495                 return;
 496         }
 497
 498         case NAND_CMD_RESET:
 499                 ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
 500                           &ifc->ifc_nand.nand_fir0);
 501                 ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
 502                           &ifc->ifc_nand.nand_fcr0);
 503                 fsl_ifc_run_command(mtd);
 504                 return;
 505
 506         default:
 507                 dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
 508                                         __func__, command);
 509         }
 510 }
 511
 512 static void fsl_ifc_select_chip(struct nand_chip *chip, int cs)
 513 {
 514         /* The hardware does not seem to support multiple
 515          * chips per bank.
 516          */
 517 }
 518
 519 /*
 520  * Write buf to the IFC NAND Controller Data Buffer
 521  */
 522 static void fsl_ifc_write_buf(struct nand_chip *chip, const u8 *buf, int len)
 523 {
 524         struct mtd_info *mtd = nand_to_mtd(chip);
 525         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 526         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 527
 528         if (len <= 0) {
 529                 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
 530                 return;
 531         }
 532
 533         if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
 534                 dev_err(priv->dev,
 535                         "%s: beyond end of buffer (%d requested, %u available)\n",
 536                         __func__, len, bufsize - ifc_nand_ctrl->index);
 537                 len = bufsize - ifc_nand_ctrl->index;
 538         }
 539
 540         memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len);
 541         ifc_nand_ctrl->index += len;
 542 }
 543
 544 /*
 545  * Read a byte from either the IFC hardware buffer
 546  * read function for 8-bit buswidth
 547  */
 548 static uint8_t fsl_ifc_read_byte(struct nand_chip *chip)
 549 {
 550         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 551         unsigned int offset;
 552
 553         /*
 554          * If there are still bytes in the IFC buffer, then use the
 555          * next byte.
 556          */
 557         if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
 558                 offset = ifc_nand_ctrl->index++;
 559                 return ifc_in8(ifc_nand_ctrl->addr + offset);
 560         }
 561
 562         dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
 563         return ERR_BYTE;
 564 }
 565
 566 /*
 567  * Read two bytes from the IFC hardware buffer
 568  * read function for 16-bit buswith
 569  */
 570 static uint8_t fsl_ifc_read_byte16(struct nand_chip *chip)
 571 {
 572         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 573         uint16_t data;
 574
 575         /*
 576          * If there are still bytes in the IFC buffer, then use the
 577          * next byte.
 578          */
 579         if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
 580                 data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);
 581                 ifc_nand_ctrl->index += 2;
 582                 return (uint8_t) data;
 583         }
 584
 585         dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
 586         return ERR_BYTE;
 587 }
 588
 589 /*
 590  * Read from the IFC Controller Data Buffer
 591  */
 592 static void fsl_ifc_read_buf(struct nand_chip *chip, u8 *buf, int len)
 593 {
 594         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 595         int avail;
 596
 597         if (len < 0) {
 598                 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
 599                 return;
 600         }
 601
 602         avail = min((unsigned int)len,
 603                         ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
 604         memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail);
 605         ifc_nand_ctrl->index += avail;
 606
 607         if (len > avail)
 608                 dev_err(priv->dev,
 609                         "%s: beyond end of buffer (%d requested, %d available)\n",
 610                         __func__, len, avail);
 611 }
 612
 613 /*
 614  * This function is called after Program and Erase Operations to
 615  * check for success or failure.
 616  */
 617 static int fsl_ifc_wait(struct nand_chip *chip)
 618 {
 619         struct mtd_info *mtd = nand_to_mtd(chip);
 620         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 621         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 622         struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 623         u32 nand_fsr;
 624         int status;
 625
 626         /* Use READ_STATUS command, but wait for the device to be ready */
 627         ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 628                   (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
 629                   &ifc->ifc_nand.nand_fir0);
 630         ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
 631                   &ifc->ifc_nand.nand_fcr0);
 632         ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
 633         set_addr(mtd, 0, 0, 0);
 634         ifc_nand_ctrl->read_bytes = 1;
 635
 636         fsl_ifc_run_command(mtd);
 637
 638         nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
 639         status = nand_fsr >> 24;
 640         /*
 641          * The chip always seems to report that it is
 642          * write-protected, even when it is not.
 643          */
 644         return status | NAND_STATUS_WP;
 645 }
 646
 647 /*
 648  * The controller does not check for bitflips in erased pages,
 649  * therefore software must check instead.
 650  */
 651 static int check_erased_page(struct nand_chip *chip, u8 *buf)
 652 {
 653         struct mtd_info *mtd = nand_to_mtd(chip);
 654         u8 *ecc = chip->oob_poi;
 655         const int ecc_size = chip->ecc.bytes;
 656         const int pkt_size = chip->ecc.size;
 657         int i, res, bitflips = 0;
 658         struct mtd_oob_region oobregion = { };
 659
 660         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 661         ecc += oobregion.offset;
 662
 663         for (i = 0; i < chip->ecc.steps; ++i) {
 664                 res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
 665                                                   NULL, 0,
 666                                                   chip->ecc.strength);
 667                 if (res < 0)
 668                         mtd->ecc_stats.failed++;
 669                 else
 670                         mtd->ecc_stats.corrected += res;
 671
 672                 bitflips = max(res, bitflips);
 673                 buf += pkt_size;
 674                 ecc += ecc_size;
 675         }
 676
 677         return bitflips;
 678 }
 679
 680 static int fsl_ifc_read_page(struct nand_chip *chip, uint8_t *buf,
 681                              int oob_required, int page)
 682 {
 683         struct mtd_info *mtd = nand_to_mtd(chip);
 684         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 685         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 686         struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
 687
 688         nand_read_page_op(chip, page, 0, buf, mtd->writesize);
 689         if (oob_required)
 690                 fsl_ifc_read_buf(chip, chip->oob_poi, mtd->oobsize);
 691
 692         if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER) {
 693                 if (!oob_required)
 694                         fsl_ifc_read_buf(chip, chip->oob_poi, mtd->oobsize);
 695
 696                 return check_erased_page(chip, buf);
 697         }
 698
 699         if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
 700                 mtd->ecc_stats.failed++;
 701
 702         return nctrl->max_bitflips;
 703 }
 704
 705 /* ECC will be calculated automatically, and errors will be detected in
 706  * waitfunc.
 707  */
 708 static int fsl_ifc_write_page(struct nand_chip *chip, const uint8_t *buf,
 709                               int oob_required, int page)
 710 {
 711         struct mtd_info *mtd = nand_to_mtd(chip);
 712
 713         nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
 714         fsl_ifc_write_buf(chip, chip->oob_poi, mtd->oobsize);
 715
 716         return nand_prog_page_end_op(chip);
 717 }
 718
 719 static int fsl_ifc_attach_chip(struct nand_chip *chip)
 720 {
 721         struct mtd_info *mtd = nand_to_mtd(chip);
 722         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 723
 724         dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
 725                                                         chip->numchips);
 726         dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
 727                                                         chip->chipsize);
 728         dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
 729                                                         chip->pagemask);
 730         dev_dbg(priv->dev, "%s: nand->legacy.chip_delay = %d\n", __func__,
 731                 chip->legacy.chip_delay);
 732         dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
 733                                                         chip->badblockpos);
 734         dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
 735                                                         chip->chip_shift);
 736         dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
 737                                                         chip->page_shift);
 738         dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
 739                                                         chip->phys_erase_shift);
 740         dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
 741                                                         chip->ecc.mode);
 742         dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
 743                                                         chip->ecc.steps);
 744         dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
 745                                                         chip->ecc.bytes);
 746         dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
 747                                                         chip->ecc.total);
 748         dev_dbg(priv->dev, "%s: mtd->ooblayout = %p\n", __func__,
 749                                                         mtd->ooblayout);
 750         dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
 751         dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
 752         dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
 753                                                         mtd->erasesize);
 754         dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
 755                                                         mtd->writesize);
 756         dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
 757                                                         mtd->oobsize);
 758
 759         return 0;
 760 }
 761
 762 static const struct nand_controller_ops fsl_ifc_controller_ops = {
 763         .attach_chip = fsl_ifc_attach_chip,
 764 };
 765
 766 static int fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
 767 {
 768         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 769         struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
 770         struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
 771         uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
 772         uint32_t cs = priv->bank;
 773
 774         if (ctrl->version < FSL_IFC_VERSION_1_1_0)
 775                 return 0;
 776
 777         if (ctrl->version > FSL_IFC_VERSION_1_1_0) {
 778                 u32 ncfgr, status;
 779                 int ret;
 780
 781                 /* Trigger auto initialization */
 782                 ncfgr = ifc_in32(&ifc_runtime->ifc_nand.ncfgr);
 783                 ifc_out32(ncfgr | IFC_NAND_NCFGR_SRAM_INIT_EN, &ifc_runtime->ifc_nand.ncfgr);
 784
 785                 /* Wait until done */
 786                 ret = readx_poll_timeout(ifc_in32, &ifc_runtime->ifc_nand.ncfgr,
 787                                          status, !(status & IFC_NAND_NCFGR_SRAM_INIT_EN),
 788                                          10, IFC_TIMEOUT_MSECS * 1000);
 789                 if (ret)
 790                         dev_err(priv->dev, "Failed to initialize SRAM!\n");
 791
 792                 return ret;
 793         }
 794
 795         /* Save CSOR and CSOR_ext */
 796         csor = ifc_in32(&ifc_global->csor_cs[cs].csor);
 797         csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext);
 798
 799         /* chage PageSize 8K and SpareSize 1K*/
 800         csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
 801         ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor);
 802         ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext);
 803
 804         /* READID */
 805         ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 806                     (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 807                     (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
 808                     &ifc_runtime->ifc_nand.nand_fir0);
 809         ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
 810                     &ifc_runtime->ifc_nand.nand_fcr0);
 811         ifc_out32(0x0, &ifc_runtime->ifc_nand.row3);
 812
 813         ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr);
 814
 815         /* Program ROW0/COL0 */
 816         ifc_out32(0x0, &ifc_runtime->ifc_nand.row0);
 817         ifc_out32(0x0, &ifc_runtime->ifc_nand.col0);
 818
 819         /* set the chip select for NAND Transaction */
 820         ifc_out32(cs << IFC_NAND_CSEL_SHIFT,
 821                 &ifc_runtime->ifc_nand.nand_csel);
 822
 823         /* start read seq */
 824         ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT,
 825                 &ifc_runtime->ifc_nand.nandseq_strt);
 826
 827         /* wait for command complete flag or timeout */
 828         wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
 829                            msecs_to_jiffies(IFC_TIMEOUT_MSECS));
 830
 831         if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) {
 832                 pr_err("fsl-ifc: Failed to Initialise SRAM\n");
 833                 return -ETIMEDOUT;
 834         }
 835
 836         /* Restore CSOR and CSOR_ext */
 837         ifc_out32(csor, &ifc_global->csor_cs[cs].csor);
 838         ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext);
 839
 840         return 0;
 841 }
 842
 843 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
 844 {
 845         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 846         struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
 847         struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
 848         struct nand_chip *chip = &priv->chip;
 849         struct mtd_info *mtd = nand_to_mtd(&priv->chip);
 850         u32 csor;
 851         int ret;
 852
 853         /* Fill in fsl_ifc_mtd structure */
 854         mtd->dev.parent = priv->dev;
 855         nand_set_flash_node(chip, priv->dev->of_node);
 856
 857         /* fill in nand_chip structure */
 858         /* set up function call table */
 859         if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr))
 860                 & CSPR_PORT_SIZE_16)
 861                 chip->legacy.read_byte = fsl_ifc_read_byte16;
 862         else
 863                 chip->legacy.read_byte = fsl_ifc_read_byte;
 864
 865         chip->legacy.write_buf = fsl_ifc_write_buf;
 866         chip->legacy.read_buf = fsl_ifc_read_buf;
 867         chip->legacy.select_chip = fsl_ifc_select_chip;
 868         chip->legacy.cmdfunc = fsl_ifc_cmdfunc;
 869         chip->legacy.waitfunc = fsl_ifc_wait;
 870         chip->legacy.set_features = nand_get_set_features_notsupp;
 871         chip->legacy.get_features = nand_get_set_features_notsupp;
 872
 873         chip->bbt_td = &bbt_main_descr;
 874         chip->bbt_md = &bbt_mirror_descr;
 875
 876         ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr);
 877
 878         /* set up nand options */
 879         chip->bbt_options = NAND_BBT_USE_FLASH;
 880         chip->options = NAND_NO_SUBPAGE_WRITE;
 881
 882         if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)
 883                 & CSPR_PORT_SIZE_16) {
 884                 chip->legacy.read_byte = fsl_ifc_read_byte16;
 885                 chip->options |= NAND_BUSWIDTH_16;
 886         } else {
 887                 chip->legacy.read_byte = fsl_ifc_read_byte;
 888         }
 889
 890         chip->controller = &ifc_nand_ctrl->controller;
 891         nand_set_controller_data(chip, priv);
 892
 893         chip->ecc.read_page = fsl_ifc_read_page;
 894         chip->ecc.write_page = fsl_ifc_write_page;
 895
 896         csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
 897
 898         switch (csor & CSOR_NAND_PGS_MASK) {
 899         case CSOR_NAND_PGS_512:
 900                 if (!(chip->options & NAND_BUSWIDTH_16)) {
 901                         /* Avoid conflict with bad block marker */
 902                         bbt_main_descr.offs = 0;
 903                         bbt_mirror_descr.offs = 0;
 904                 }
 905
 906                 priv->bufnum_mask = 15;
 907                 break;
 908
 909         case CSOR_NAND_PGS_2K:
 910                 priv->bufnum_mask = 3;
 911                 break;
 912
 913         case CSOR_NAND_PGS_4K:
 914                 priv->bufnum_mask = 1;
 915                 break;
 916
 917         case CSOR_NAND_PGS_8K:
 918                 priv->bufnum_mask = 0;
 919                 break;
 920
 921         default:
 922                 dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
 923                 return -ENODEV;
 924         }
 925
 926         /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
 927         if (csor & CSOR_NAND_ECC_DEC_EN) {
 928                 chip->ecc.mode = NAND_ECC_HW;
 929                 mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
 930
 931                 /* Hardware generates ECC per 512 Bytes */
 932                 chip->ecc.size = 512;
 933                 if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
 934                         chip->ecc.bytes = 8;
 935                         chip->ecc.strength = 4;
 936                 } else {
 937                         chip->ecc.bytes = 16;
 938                         chip->ecc.strength = 8;
 939                 }
 940         } else {
 941                 chip->ecc.mode = NAND_ECC_SOFT;
 942                 chip->ecc.algo = NAND_ECC_HAMMING;
 943         }
 944
 945         ret = fsl_ifc_sram_init(priv);
 946         if (ret)
 947                 return ret;
 948
 949         /*
 950          * As IFC version 2.0.0 has 16KB of internal SRAM as compared to older
 951          * versions which had 8KB. Hence bufnum mask needs to be updated.
 952          */
 953         if (ctrl->version >= FSL_IFC_VERSION_2_0_0)
 954                 priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
 955
 956         return 0;
 957 }
 958
 959 static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
 960 {
 961         struct mtd_info *mtd = nand_to_mtd(&priv->chip);
 962
 963         kfree(mtd->name);
 964
 965         if (priv->vbase)
 966                 iounmap(priv->vbase);
 967
 968         ifc_nand_ctrl->chips[priv->bank] = NULL;
 969
 970         return 0;
 971 }
 972
 973 static int match_bank(struct fsl_ifc_global __iomem *ifc_global, int bank,
 974                       phys_addr_t addr)
 975 {
 976         u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr);
 977
 978         if (!(cspr & CSPR_V))
 979                 return 0;
 980         if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
 981                 return 0;
 982
 983         return (cspr & CSPR_BA) == convert_ifc_address(addr);
 984 }
 985
 986 static DEFINE_MUTEX(fsl_ifc_nand_mutex);
 987
 988 static int fsl_ifc_nand_probe(struct platform_device *dev)
 989 {
 990         struct fsl_ifc_runtime __iomem *ifc;
 991         struct fsl_ifc_mtd *priv;
 992         struct resource res;
 993         static const char *part_probe_types[]
 994                 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
 995         int ret;
 996         int bank;
 997         struct device_node *node = dev->dev.of_node;
 998         struct mtd_info *mtd;
 999
1000         if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs)
1001                 return -ENODEV;
1002         ifc = fsl_ifc_ctrl_dev->rregs;
1003
1004         /* get, allocate and map the memory resource */
1005         ret = of_address_to_resource(node, 0, &res);
1006         if (ret) {
1007                 dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
1008                 return ret;
1009         }
1010
1011         /* find which chip select it is connected to */
1012         for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
1013                 if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start))
1014                         break;
1015         }
1016
1017         if (bank >= fsl_ifc_ctrl_dev->banks) {
1018                 dev_err(&dev->dev, "%s: address did not match any chip selects\n",
1019                         __func__);
1020                 return -ENODEV;
1021         }
1022
1023         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1024         if (!priv)
1025                 return -ENOMEM;
1026
1027         mutex_lock(&fsl_ifc_nand_mutex);
1028         if (!fsl_ifc_ctrl_dev->nand) {
1029                 ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
1030                 if (!ifc_nand_ctrl) {
1031                         mutex_unlock(&fsl_ifc_nand_mutex);
1032                         return -ENOMEM;
1033                 }
1034
1035                 ifc_nand_ctrl->read_bytes = 0;
1036                 ifc_nand_ctrl->index = 0;
1037                 ifc_nand_ctrl->addr = NULL;
1038                 fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
1039
1040                 nand_controller_init(&ifc_nand_ctrl->controller);
1041         } else {
1042                 ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
1043         }
1044         mutex_unlock(&fsl_ifc_nand_mutex);
1045
1046         ifc_nand_ctrl->chips[bank] = priv;
1047         priv->bank = bank;
1048         priv->ctrl = fsl_ifc_ctrl_dev;
1049         priv->dev = &dev->dev;
1050
1051         priv->vbase = ioremap(res.start, resource_size(&res));
1052         if (!priv->vbase) {
1053                 dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
1054                 ret = -ENOMEM;
1055                 goto err;
1056         }
1057
1058         dev_set_drvdata(priv->dev, priv);
1059
1060         ifc_out32(IFC_NAND_EVTER_EN_OPC_EN |
1061                   IFC_NAND_EVTER_EN_FTOER_EN |
1062                   IFC_NAND_EVTER_EN_WPER_EN,
1063                   &ifc->ifc_nand.nand_evter_en);
1064
1065         /* enable NAND Machine Interrupts */
1066         ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN |
1067                   IFC_NAND_EVTER_INTR_FTOERIR_EN |
1068                   IFC_NAND_EVTER_INTR_WPERIR_EN,
1069                   &ifc->ifc_nand.nand_evter_intr_en);
1070
1071         mtd = nand_to_mtd(&priv->chip);
1072         mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
1073         if (!mtd->name) {
1074                 ret = -ENOMEM;
1075                 goto err;
1076         }
1077
1078         ret = fsl_ifc_chip_init(priv);
1079         if (ret)
1080                 goto err;
1081
1082         priv->chip.controller->ops = &fsl_ifc_controller_ops;
1083         ret = nand_scan(&priv->chip, 1);
1084         if (ret)
1085                 goto err;
1086
1087         /* First look for RedBoot table or partitions on the command
1088          * line, these take precedence over device tree information */
1089         ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
1090         if (ret)
1091                 goto cleanup_nand;
1092
1093         dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1094                  (unsigned long long)res.start, priv->bank);
1095
1096         return 0;
1097
1098 cleanup_nand:
1099         nand_cleanup(&priv->chip);
1100 err:
1101         fsl_ifc_chip_remove(priv);
1102
1103         return ret;
1104 }
1105
1106 static int fsl_ifc_nand_remove(struct platform_device *dev)
1107 {
1108         struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1109
1110         nand_release(&priv->chip);
1111         fsl_ifc_chip_remove(priv);
1112
1113         mutex_lock(&fsl_ifc_nand_mutex);
1114         ifc_nand_ctrl->counter--;
1115         if (!ifc_nand_ctrl->counter) {
1116                 fsl_ifc_ctrl_dev->nand = NULL;
1117                 kfree(ifc_nand_ctrl);
1118         }
1119         mutex_unlock(&fsl_ifc_nand_mutex);
1120
1121         return 0;
1122 }
1123
1124 static const struct of_device_id fsl_ifc_nand_match[] = {
1125         {
1126                 .compatible = "fsl,ifc-nand",
1127         },
1128         {}
1129 };
1130 MODULE_DEVICE_TABLE(of, fsl_ifc_nand_match);
1131
1132 static struct platform_driver fsl_ifc_nand_driver = {
1133         .driver = {
1134                 .name   = "fsl,ifc-nand",
1135                 .of_match_table = fsl_ifc_nand_match,
1136         },
1137         .probe       = fsl_ifc_nand_probe,
1138         .remove      = fsl_ifc_nand_remove,
1139 };
1140
1141 module_platform_driver(fsl_ifc_nand_driver);
1142
1143 MODULE_LICENSE("GPL");
1144 MODULE_AUTHOR("Freescale");
1145 MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");