drivers/mtd/nand/raw/davinci_nand.c

   1 /*
   2  * davinci_nand.c - NAND Flash Driver for DaVinci family chips
   3  *
   4  * Copyright © 2006 Texas Instruments.
   5  *
   6  * Port to 2.6.23 Copyright © 2008 by:
   7  *   Sander Huijsen <[email protected]>
   8  *   Troy Kisky <[email protected]>
   9  *   Dirk Behme <[email protected]>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/err.h>
  30 #include <linux/io.h>
  31 #include <linux/mtd/rawnand.h>
  32 #include <linux/mtd/partitions.h>
  33 #include <linux/slab.h>
  34 #include <linux/of_device.h>
  35 #include <linux/of.h>
  36
  37 #include <linux/platform_data/mtd-davinci.h>
  38 #include <linux/platform_data/mtd-davinci-aemif.h>
  39
  40 /*
  41  * This is a device driver for the NAND flash controller found on the
  42  * various DaVinci family chips.  It handles up to four SoC chipselects,
  43  * and some flavors of secondary chipselect (e.g. based on A12) as used
  44  * with multichip packages.
  45  *
  46  * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
  47  * available on chips like the DM355 and OMAP-L137 and needed with the
  48  * more error-prone MLC NAND chips.
  49  *
  50  * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
  51  * outputs in a "wire-AND" configuration, with no per-chip signals.
  52  */
  53 struct davinci_nand_info {
  54         struct nand_chip        chip;
  55
  56         struct platform_device  *pdev;
  57
  58         bool                    is_readmode;
  59
  60         void __iomem            *base;
  61         void __iomem            *vaddr;
  62
  63         void __iomem            *current_cs;
  64
  65         uint32_t                mask_chipsel;
  66         uint32_t                mask_ale;
  67         uint32_t                mask_cle;
  68
  69         uint32_t                core_chipsel;
  70
  71         struct davinci_aemif_timing     *timing;
  72 };
  73
  74 static DEFINE_SPINLOCK(davinci_nand_lock);
  75 static bool ecc4_busy;
  76
  77 static inline struct davinci_nand_info *to_davinci_nand(struct mtd_info *mtd)
  78 {
  79         return container_of(mtd_to_nand(mtd), struct davinci_nand_info, chip);
  80 }
  81
  82 static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
  83                 int offset)
  84 {
  85         return __raw_readl(info->base + offset);
  86 }
  87
  88 static inline void davinci_nand_writel(struct davinci_nand_info *info,
  89                 int offset, unsigned long value)
  90 {
  91         __raw_writel(value, info->base + offset);
  92 }
  93
  94 /*----------------------------------------------------------------------*/
  95
  96 /*
  97  * Access to hardware control lines:  ALE, CLE, secondary chipselect.
  98  */
  99
 100 static void nand_davinci_hwcontrol(struct nand_chip *nand, int cmd,
 101                                    unsigned int ctrl)
 102 {
 103         struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(nand));
 104         void __iomem                    *addr = info->current_cs;
 105
 106         /* Did the control lines change? */
 107         if (ctrl & NAND_CTRL_CHANGE) {
 108                 if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
 109                         addr += info->mask_cle;
 110                 else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
 111                         addr += info->mask_ale;
 112
 113                 nand->legacy.IO_ADDR_W = addr;
 114         }
 115
 116         if (cmd != NAND_CMD_NONE)
 117                 iowrite8(cmd, nand->legacy.IO_ADDR_W);
 118 }
 119
 120 static void nand_davinci_select_chip(struct nand_chip *nand, int chip)
 121 {
 122         struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(nand));
 123
 124         info->current_cs = info->vaddr;
 125
 126         /* maybe kick in a second chipselect */
 127         if (chip > 0)
 128                 info->current_cs += info->mask_chipsel;
 129
 130         info->chip.legacy.IO_ADDR_W = info->current_cs;
 131         info->chip.legacy.IO_ADDR_R = info->chip.legacy.IO_ADDR_W;
 132 }
 133
 134 /*----------------------------------------------------------------------*/
 135
 136 /*
 137  * 1-bit hardware ECC ... context maintained for each core chipselect
 138  */
 139
 140 static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
 141 {
 142         struct davinci_nand_info *info = to_davinci_nand(mtd);
 143
 144         return davinci_nand_readl(info, NANDF1ECC_OFFSET
 145                         + 4 * info->core_chipsel);
 146 }
 147
 148 static void nand_davinci_hwctl_1bit(struct nand_chip *chip, int mode)
 149 {
 150         struct davinci_nand_info *info;
 151         uint32_t nandcfr;
 152         unsigned long flags;
 153
 154         info = to_davinci_nand(nand_to_mtd(chip));
 155
 156         /* Reset ECC hardware */
 157         nand_davinci_readecc_1bit(nand_to_mtd(chip));
 158
 159         spin_lock_irqsave(&davinci_nand_lock, flags);
 160
 161         /* Restart ECC hardware */
 162         nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
 163         nandcfr |= BIT(8 + info->core_chipsel);
 164         davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
 165
 166         spin_unlock_irqrestore(&davinci_nand_lock, flags);
 167 }
 168
 169 /*
 170  * Read hardware ECC value and pack into three bytes
 171  */
 172 static int nand_davinci_calculate_1bit(struct nand_chip *chip,
 173                                        const u_char *dat, u_char *ecc_code)
 174 {
 175         unsigned int ecc_val = nand_davinci_readecc_1bit(nand_to_mtd(chip));
 176         unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
 177
 178         /* invert so that erased block ecc is correct */
 179         ecc24 = ~ecc24;
 180         ecc_code[0] = (u_char)(ecc24);
 181         ecc_code[1] = (u_char)(ecc24 >> 8);
 182         ecc_code[2] = (u_char)(ecc24 >> 16);
 183
 184         return 0;
 185 }
 186
 187 static int nand_davinci_correct_1bit(struct nand_chip *chip, u_char *dat,
 188                                      u_char *read_ecc, u_char *calc_ecc)
 189 {
 190         uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
 191                                           (read_ecc[2] << 16);
 192         uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
 193                                           (calc_ecc[2] << 16);
 194         uint32_t diff = eccCalc ^ eccNand;
 195
 196         if (diff) {
 197                 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
 198                         /* Correctable error */
 199                         if ((diff >> (12 + 3)) < chip->ecc.size) {
 200                                 dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
 201                                 return 1;
 202                         } else {
 203                                 return -EBADMSG;
 204                         }
 205                 } else if (!(diff & (diff - 1))) {
 206                         /* Single bit ECC error in the ECC itself,
 207                          * nothing to fix */
 208                         return 1;
 209                 } else {
 210                         /* Uncorrectable error */
 211                         return -EBADMSG;
 212                 }
 213
 214         }
 215         return 0;
 216 }
 217
 218 /*----------------------------------------------------------------------*/
 219
 220 /*
 221  * 4-bit hardware ECC ... context maintained over entire AEMIF
 222  *
 223  * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
 224  * since that forces use of a problematic "infix OOB" layout.
 225  * Among other things, it trashes manufacturer bad block markers.
 226  * Also, and specific to this hardware, it ECC-protects the "prepad"
 227  * in the OOB ... while having ECC protection for parts of OOB would
 228  * seem useful, the current MTD stack sometimes wants to update the
 229  * OOB without recomputing ECC.
 230  */
 231
 232 static void nand_davinci_hwctl_4bit(struct nand_chip *chip, int mode)
 233 {
 234         struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
 235         unsigned long flags;
 236         u32 val;
 237
 238         /* Reset ECC hardware */
 239         davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
 240
 241         spin_lock_irqsave(&davinci_nand_lock, flags);
 242
 243         /* Start 4-bit ECC calculation for read/write */
 244         val = davinci_nand_readl(info, NANDFCR_OFFSET);
 245         val &= ~(0x03 << 4);
 246         val |= (info->core_chipsel << 4) | BIT(12);
 247         davinci_nand_writel(info, NANDFCR_OFFSET, val);
 248
 249         info->is_readmode = (mode == NAND_ECC_READ);
 250
 251         spin_unlock_irqrestore(&davinci_nand_lock, flags);
 252 }
 253
 254 /* Read raw ECC code after writing to NAND. */
 255 static void
 256 nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4])
 257 {
 258         const u32 mask = 0x03ff03ff;
 259
 260         code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
 261         code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
 262         code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
 263         code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
 264 }
 265
 266 /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
 267 static int nand_davinci_calculate_4bit(struct nand_chip *chip,
 268                                        const u_char *dat, u_char *ecc_code)
 269 {
 270         struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
 271         u32 raw_ecc[4], *p;
 272         unsigned i;
 273
 274         /* After a read, terminate ECC calculation by a dummy read
 275          * of some 4-bit ECC register.  ECC covers everything that
 276          * was read; correct() just uses the hardware state, so
 277          * ecc_code is not needed.
 278          */
 279         if (info->is_readmode) {
 280                 davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
 281                 return 0;
 282         }
 283
 284         /* Pack eight raw 10-bit ecc values into ten bytes, making
 285          * two passes which each convert four values (in upper and
 286          * lower halves of two 32-bit words) into five bytes.  The
 287          * ROM boot loader uses this same packing scheme.
 288          */
 289         nand_davinci_readecc_4bit(info, raw_ecc);
 290         for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
 291                 *ecc_code++ =   p[0]        & 0xff;
 292                 *ecc_code++ = ((p[0] >>  8) & 0x03) | ((p[0] >> 14) & 0xfc);
 293                 *ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] <<  4) & 0xf0);
 294                 *ecc_code++ = ((p[1] >>  4) & 0x3f) | ((p[1] >> 10) & 0xc0);
 295                 *ecc_code++ =  (p[1] >> 18) & 0xff;
 296         }
 297
 298         return 0;
 299 }
 300
 301 /* Correct up to 4 bits in data we just read, using state left in the
 302  * hardware plus the ecc_code computed when it was first written.
 303  */
 304 static int nand_davinci_correct_4bit(struct nand_chip *chip, u_char *data,
 305                                      u_char *ecc_code, u_char *null)
 306 {
 307         int i;
 308         struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
 309         unsigned short ecc10[8];
 310         unsigned short *ecc16;
 311         u32 syndrome[4];
 312         u32 ecc_state;
 313         unsigned num_errors, corrected;
 314         unsigned long timeo;
 315
 316         /* Unpack ten bytes into eight 10 bit values.  We know we're
 317          * little-endian, and use type punning for less shifting/masking.
 318          */
 319         if (WARN_ON(0x01 & (uintptr_t)ecc_code))
 320                 return -EINVAL;
 321         ecc16 = (unsigned short *)ecc_code;
 322
 323         ecc10[0] =  (ecc16[0] >>  0) & 0x3ff;
 324         ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0);
 325         ecc10[2] =  (ecc16[1] >>  4) & 0x3ff;
 326         ecc10[3] = ((ecc16[1] >> 14) & 0x3)  | ((ecc16[2] << 2) & 0x3fc);
 327         ecc10[4] =  (ecc16[2] >>  8)         | ((ecc16[3] << 8) & 0x300);
 328         ecc10[5] =  (ecc16[3] >>  2) & 0x3ff;
 329         ecc10[6] = ((ecc16[3] >> 12) & 0xf)  | ((ecc16[4] << 4) & 0x3f0);
 330         ecc10[7] =  (ecc16[4] >>  6) & 0x3ff;
 331
 332         /* Tell ECC controller about the expected ECC codes. */
 333         for (i = 7; i >= 0; i--)
 334                 davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]);
 335
 336         /* Allow time for syndrome calculation ... then read it.
 337          * A syndrome of all zeroes 0 means no detected errors.
 338          */
 339         davinci_nand_readl(info, NANDFSR_OFFSET);
 340         nand_davinci_readecc_4bit(info, syndrome);
 341         if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3]))
 342                 return 0;
 343
 344         /*
 345          * Clear any previous address calculation by doing a dummy read of an
 346          * error address register.
 347          */
 348         davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);
 349
 350         /* Start address calculation, and wait for it to complete.
 351          * We _could_ start reading more data while this is working,
 352          * to speed up the overall page read.
 353          */
 354         davinci_nand_writel(info, NANDFCR_OFFSET,
 355                         davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));
 356
 357         /*
 358          * ECC_STATE field reads 0x3 (Error correction complete) immediately
 359          * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
 360          * begin trying to poll for the state, you may fall right out of your
 361          * loop without any of the correction calculations having taken place.
 362          * The recommendation from the hardware team is to initially delay as
 363          * long as ECC_STATE reads less than 4. After that, ECC HW has entered
 364          * correction state.
 365          */
 366         timeo = jiffies + usecs_to_jiffies(100);
 367         do {
 368                 ecc_state = (davinci_nand_readl(info,
 369                                 NANDFSR_OFFSET) >> 8) & 0x0f;
 370                 cpu_relax();
 371         } while ((ecc_state < 4) && time_before(jiffies, timeo));
 372
 373         for (;;) {
 374                 u32     fsr = davinci_nand_readl(info, NANDFSR_OFFSET);
 375
 376                 switch ((fsr >> 8) & 0x0f) {
 377                 case 0:         /* no error, should not happen */
 378                         davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
 379                         return 0;
 380                 case 1:         /* five or more errors detected */
 381                         davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
 382                         return -EBADMSG;
 383                 case 2:         /* error addresses computed */
 384                 case 3:
 385                         num_errors = 1 + ((fsr >> 16) & 0x03);
 386                         goto correct;
 387                 default:        /* still working on it */
 388                         cpu_relax();
 389                         continue;
 390                 }
 391         }
 392
 393 correct:
 394         /* correct each error */
 395         for (i = 0, corrected = 0; i < num_errors; i++) {
 396                 int error_address, error_value;
 397
 398                 if (i > 1) {
 399                         error_address = davinci_nand_readl(info,
 400                                                 NAND_ERR_ADD2_OFFSET);
 401                         error_value = davinci_nand_readl(info,
 402                                                 NAND_ERR_ERRVAL2_OFFSET);
 403                 } else {
 404                         error_address = davinci_nand_readl(info,
 405                                                 NAND_ERR_ADD1_OFFSET);
 406                         error_value = davinci_nand_readl(info,
 407                                                 NAND_ERR_ERRVAL1_OFFSET);
 408                 }
 409
 410                 if (i & 1) {
 411                         error_address >>= 16;
 412                         error_value >>= 16;
 413                 }
 414                 error_address &= 0x3ff;
 415                 error_address = (512 + 7) - error_address;
 416
 417                 if (error_address < 512) {
 418                         data[error_address] ^= error_value;
 419                         corrected++;
 420                 }
 421         }
 422
 423         return corrected;
 424 }
 425
 426 /*----------------------------------------------------------------------*/
 427
 428 /*
 429  * NOTE:  NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
 430  * how these chips are normally wired.  This translates to both 8 and 16
 431  * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
 432  *
 433  * For now we assume that configuration, or any other one which ignores
 434  * the two LSBs for NAND access ... so we can issue 32-bit reads/writes
 435  * and have that transparently morphed into multiple NAND operations.
 436  */
 437 static void nand_davinci_read_buf(struct nand_chip *chip, uint8_t *buf,
 438                                   int len)
 439 {
 440         if ((0x03 & ((uintptr_t)buf)) == 0 && (0x03 & len) == 0)
 441                 ioread32_rep(chip->legacy.IO_ADDR_R, buf, len >> 2);
 442         else if ((0x01 & ((uintptr_t)buf)) == 0 && (0x01 & len) == 0)
 443                 ioread16_rep(chip->legacy.IO_ADDR_R, buf, len >> 1);
 444         else
 445                 ioread8_rep(chip->legacy.IO_ADDR_R, buf, len);
 446 }
 447
 448 static void nand_davinci_write_buf(struct nand_chip *chip, const uint8_t *buf,
 449                                    int len)
 450 {
 451         if ((0x03 & ((uintptr_t)buf)) == 0 && (0x03 & len) == 0)
 452                 iowrite32_rep(chip->legacy.IO_ADDR_R, buf, len >> 2);
 453         else if ((0x01 & ((uintptr_t)buf)) == 0 && (0x01 & len) == 0)
 454                 iowrite16_rep(chip->legacy.IO_ADDR_R, buf, len >> 1);
 455         else
 456                 iowrite8_rep(chip->legacy.IO_ADDR_R, buf, len);
 457 }
 458
 459 /*
 460  * Check hardware register for wait status. Returns 1 if device is ready,
 461  * 0 if it is still busy.
 462  */
 463 static int nand_davinci_dev_ready(struct nand_chip *chip)
 464 {
 465         struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
 466
 467         return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
 468 }
 469
 470 /*----------------------------------------------------------------------*/
 471
 472 /* An ECC layout for using 4-bit ECC with small-page flash, storing
 473  * ten ECC bytes plus the manufacturer's bad block marker byte, and
 474  * and not overlapping the default BBT markers.
 475  */
 476 static int hwecc4_ooblayout_small_ecc(struct mtd_info *mtd, int section,
 477                                       struct mtd_oob_region *oobregion)
 478 {
 479         if (section > 2)
 480                 return -ERANGE;
 481
 482         if (!section) {
 483                 oobregion->offset = 0;
 484                 oobregion->length = 5;
 485         } else if (section == 1) {
 486                 oobregion->offset = 6;
 487                 oobregion->length = 2;
 488         } else {
 489                 oobregion->offset = 13;
 490                 oobregion->length = 3;
 491         }
 492
 493         return 0;
 494 }
 495
 496 static int hwecc4_ooblayout_small_free(struct mtd_info *mtd, int section,
 497                                        struct mtd_oob_region *oobregion)
 498 {
 499         if (section > 1)
 500                 return -ERANGE;
 501
 502         if (!section) {
 503                 oobregion->offset = 8;
 504                 oobregion->length = 5;
 505         } else {
 506                 oobregion->offset = 16;
 507                 oobregion->length = mtd->oobsize - 16;
 508         }
 509
 510         return 0;
 511 }
 512
 513 static const struct mtd_ooblayout_ops hwecc4_small_ooblayout_ops = {
 514         .ecc = hwecc4_ooblayout_small_ecc,
 515         .free = hwecc4_ooblayout_small_free,
 516 };
 517
 518 #if defined(CONFIG_OF)
 519 static const struct of_device_id davinci_nand_of_match[] = {
 520         {.compatible = "ti,davinci-nand", },
 521         {.compatible = "ti,keystone-nand", },
 522         {},
 523 };
 524 MODULE_DEVICE_TABLE(of, davinci_nand_of_match);
 525
 526 static struct davinci_nand_pdata
 527         *nand_davinci_get_pdata(struct platform_device *pdev)
 528 {
 529         if (!dev_get_platdata(&pdev->dev) && pdev->dev.of_node) {
 530                 struct davinci_nand_pdata *pdata;
 531                 const char *mode;
 532                 u32 prop;
 533
 534                 pdata =  devm_kzalloc(&pdev->dev,
 535                                 sizeof(struct davinci_nand_pdata),
 536                                 GFP_KERNEL);
 537                 pdev->dev.platform_data = pdata;
 538                 if (!pdata)
 539                         return ERR_PTR(-ENOMEM);
 540                 if (!of_property_read_u32(pdev->dev.of_node,
 541                         "ti,davinci-chipselect", &prop))
 542                         pdata->core_chipsel = prop;
 543                 else
 544                         return ERR_PTR(-EINVAL);
 545
 546                 if (!of_property_read_u32(pdev->dev.of_node,
 547                         "ti,davinci-mask-ale", &prop))
 548                         pdata->mask_ale = prop;
 549                 if (!of_property_read_u32(pdev->dev.of_node,
 550                         "ti,davinci-mask-cle", &prop))
 551                         pdata->mask_cle = prop;
 552                 if (!of_property_read_u32(pdev->dev.of_node,
 553                         "ti,davinci-mask-chipsel", &prop))
 554                         pdata->mask_chipsel = prop;
 555                 if (!of_property_read_string(pdev->dev.of_node,
 556                         "ti,davinci-ecc-mode", &mode)) {
 557                         if (!strncmp("none", mode, 4))
 558                                 pdata->ecc_mode = NAND_ECC_NONE;
 559                         if (!strncmp("soft", mode, 4))
 560                                 pdata->ecc_mode = NAND_ECC_SOFT;
 561                         if (!strncmp("hw", mode, 2))
 562                                 pdata->ecc_mode = NAND_ECC_HW;
 563                 }
 564                 if (!of_property_read_u32(pdev->dev.of_node,
 565                         "ti,davinci-ecc-bits", &prop))
 566                         pdata->ecc_bits = prop;
 567
 568                 if (!of_property_read_u32(pdev->dev.of_node,
 569                         "ti,davinci-nand-buswidth", &prop) && prop == 16)
 570                         pdata->options |= NAND_BUSWIDTH_16;
 571
 572                 if (of_property_read_bool(pdev->dev.of_node,
 573                         "ti,davinci-nand-use-bbt"))
 574                         pdata->bbt_options = NAND_BBT_USE_FLASH;
 575
 576                 /*
 577                  * Since kernel v4.8, this driver has been fixed to enable
 578                  * use of 4-bit hardware ECC with subpages and verified on
 579                  * TI's keystone EVMs (K2L, K2HK and K2E).
 580                  * However, in the interest of not breaking systems using
 581                  * existing UBI partitions, sub-page writes are not being
 582                  * (re)enabled. If you want to use subpage writes on Keystone
 583                  * platforms (i.e. do not have any existing UBI partitions),
 584                  * then use "ti,davinci-nand" as the compatible in your
 585                  * device-tree file.
 586                  */
 587                 if (of_device_is_compatible(pdev->dev.of_node,
 588                                             "ti,keystone-nand")) {
 589                         pdata->options |= NAND_NO_SUBPAGE_WRITE;
 590                 }
 591         }
 592
 593         return dev_get_platdata(&pdev->dev);
 594 }
 595 #else
 596 static struct davinci_nand_pdata
 597         *nand_davinci_get_pdata(struct platform_device *pdev)
 598 {
 599         return dev_get_platdata(&pdev->dev);
 600 }
 601 #endif
 602
 603 static int davinci_nand_attach_chip(struct nand_chip *chip)
 604 {
 605         struct mtd_info *mtd = nand_to_mtd(chip);
 606         struct davinci_nand_info *info = to_davinci_nand(mtd);
 607         struct davinci_nand_pdata *pdata = nand_davinci_get_pdata(info->pdev);
 608         int ret = 0;
 609
 610         if (IS_ERR(pdata))
 611                 return PTR_ERR(pdata);
 612
 613         switch (info->chip.ecc.mode) {
 614         case NAND_ECC_NONE:
 615                 pdata->ecc_bits = 0;
 616                 break;
 617         case NAND_ECC_SOFT:
 618                 pdata->ecc_bits = 0;
 619                 /*
 620                  * This driver expects Hamming based ECC when ecc_mode is set
 621                  * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
 622                  * avoid adding an extra ->ecc_algo field to
 623                  * davinci_nand_pdata.
 624                  */
 625                 info->chip.ecc.algo = NAND_ECC_HAMMING;
 626                 break;
 627         case NAND_ECC_HW:
 628                 if (pdata->ecc_bits == 4) {
 629                         /*
 630                          * No sanity checks:  CPUs must support this,
 631                          * and the chips may not use NAND_BUSWIDTH_16.
 632                          */
 633
 634                         /* No sharing 4-bit hardware between chipselects yet */
 635                         spin_lock_irq(&davinci_nand_lock);
 636                         if (ecc4_busy)
 637                                 ret = -EBUSY;
 638                         else
 639                                 ecc4_busy = true;
 640                         spin_unlock_irq(&davinci_nand_lock);
 641
 642                         if (ret == -EBUSY)
 643                                 return ret;
 644
 645                         info->chip.ecc.calculate = nand_davinci_calculate_4bit;
 646                         info->chip.ecc.correct = nand_davinci_correct_4bit;
 647                         info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
 648                         info->chip.ecc.bytes = 10;
 649                         info->chip.ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
 650                         info->chip.ecc.algo = NAND_ECC_BCH;
 651                 } else {
 652                         /* 1bit ecc hamming */
 653                         info->chip.ecc.calculate = nand_davinci_calculate_1bit;
 654                         info->chip.ecc.correct = nand_davinci_correct_1bit;
 655                         info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
 656                         info->chip.ecc.bytes = 3;
 657                         info->chip.ecc.algo = NAND_ECC_HAMMING;
 658                 }
 659                 info->chip.ecc.size = 512;
 660                 info->chip.ecc.strength = pdata->ecc_bits;
 661                 break;
 662         default:
 663                 return -EINVAL;
 664         }
 665
 666         /*
 667          * Update ECC layout if needed ... for 1-bit HW ECC, the default
 668          * is OK, but it allocates 6 bytes when only 3 are needed (for
 669          * each 512 bytes).  For the 4-bit HW ECC, that default is not
 670          * usable:  10 bytes are needed, not 6.
 671          */
 672         if (pdata->ecc_bits == 4) {
 673                 int chunks = mtd->writesize / 512;
 674
 675                 if (!chunks || mtd->oobsize < 16) {
 676                         dev_dbg(&info->pdev->dev, "too small\n");
 677                         return -EINVAL;
 678                 }
 679
 680                 /* For small page chips, preserve the manufacturer's
 681                  * badblock marking data ... and make sure a flash BBT
 682                  * table marker fits in the free bytes.
 683                  */
 684                 if (chunks == 1) {
 685                         mtd_set_ooblayout(mtd, &hwecc4_small_ooblayout_ops);
 686                 } else if (chunks == 4 || chunks == 8) {
 687                         mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
 688                         info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
 689                 } else {
 690                         return -EIO;
 691                 }
 692         }
 693
 694         return ret;
 695 }
 696
 697 static const struct nand_controller_ops davinci_nand_controller_ops = {
 698         .attach_chip = davinci_nand_attach_chip,
 699 };
 700
 701 static int nand_davinci_probe(struct platform_device *pdev)
 702 {
 703         struct davinci_nand_pdata       *pdata;
 704         struct davinci_nand_info        *info;
 705         struct resource                 *res1;
 706         struct resource                 *res2;
 707         void __iomem                    *vaddr;
 708         void __iomem                    *base;
 709         int                             ret;
 710         uint32_t                        val;
 711         struct mtd_info                 *mtd;
 712
 713         pdata = nand_davinci_get_pdata(pdev);
 714         if (IS_ERR(pdata))
 715                 return PTR_ERR(pdata);
 716
 717         /* insist on board-specific configuration */
 718         if (!pdata)
 719                 return -ENODEV;
 720
 721         /* which external chipselect will we be managing? */
 722         if (pdata->core_chipsel < 0 || pdata->core_chipsel > 3)
 723                 return -ENODEV;
 724
 725         info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
 726         if (!info)
 727                 return -ENOMEM;
 728
 729         platform_set_drvdata(pdev, info);
 730
 731         res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 732         res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 733         if (!res1 || !res2) {
 734                 dev_err(&pdev->dev, "resource missing\n");
 735                 return -EINVAL;
 736         }
 737
 738         vaddr = devm_ioremap_resource(&pdev->dev, res1);
 739         if (IS_ERR(vaddr))
 740                 return PTR_ERR(vaddr);
 741
 742         /*
 743          * This registers range is used to setup NAND settings. In case with
 744          * TI AEMIF driver, the same memory address range is requested already
 745          * by AEMIF, so we cannot request it twice, just ioremap.
 746          * The AEMIF and NAND drivers not use the same registers in this range.
 747          */
 748         base = devm_ioremap(&pdev->dev, res2->start, resource_size(res2));
 749         if (!base) {
 750                 dev_err(&pdev->dev, "ioremap failed for resource %pR\n", res2);
 751                 return -EADDRNOTAVAIL;
 752         }
 753
 754         info->pdev              = pdev;
 755         info->base              = base;
 756         info->vaddr             = vaddr;
 757
 758         mtd                     = nand_to_mtd(&info->chip);
 759         mtd->dev.parent         = &pdev->dev;
 760         nand_set_flash_node(&info->chip, pdev->dev.of_node);
 761
 762         info->chip.legacy.IO_ADDR_R     = vaddr;
 763         info->chip.legacy.IO_ADDR_W     = vaddr;
 764         info->chip.legacy.chip_delay    = 0;
 765         info->chip.legacy.select_chip   = nand_davinci_select_chip;
 766
 767         /* options such as NAND_BBT_USE_FLASH */
 768         info->chip.bbt_options  = pdata->bbt_options;
 769         /* options such as 16-bit widths */
 770         info->chip.options      = pdata->options;
 771         info->chip.bbt_td       = pdata->bbt_td;
 772         info->chip.bbt_md       = pdata->bbt_md;
 773         info->timing            = pdata->timing;
 774
 775         info->current_cs        = info->vaddr;
 776         info->core_chipsel      = pdata->core_chipsel;
 777         info->mask_chipsel      = pdata->mask_chipsel;
 778
 779         /* use nandboot-capable ALE/CLE masks by default */
 780         info->mask_ale          = pdata->mask_ale ? : MASK_ALE;
 781         info->mask_cle          = pdata->mask_cle ? : MASK_CLE;
 782
 783         /* Set address of hardware control function */
 784         info->chip.legacy.cmd_ctrl      = nand_davinci_hwcontrol;
 785         info->chip.legacy.dev_ready     = nand_davinci_dev_ready;
 786
 787         /* Speed up buffer I/O */
 788         info->chip.legacy.read_buf     = nand_davinci_read_buf;
 789         info->chip.legacy.write_buf    = nand_davinci_write_buf;
 790
 791         /* Use board-specific ECC config */
 792         info->chip.ecc.mode     = pdata->ecc_mode;
 793
 794         spin_lock_irq(&davinci_nand_lock);
 795
 796         /* put CSxNAND into NAND mode */
 797         val = davinci_nand_readl(info, NANDFCR_OFFSET);
 798         val |= BIT(info->core_chipsel);
 799         davinci_nand_writel(info, NANDFCR_OFFSET, val);
 800
 801         spin_unlock_irq(&davinci_nand_lock);
 802
 803         /* Scan to find existence of the device(s) */
 804         info->chip.legacy.dummy_controller.ops = &davinci_nand_controller_ops;
 805         ret = nand_scan(&info->chip, pdata->mask_chipsel ? 2 : 1);
 806         if (ret < 0) {
 807                 dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
 808                 return ret;
 809         }
 810
 811         if (pdata->parts)
 812                 ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
 813         else
 814                 ret = mtd_device_register(mtd, NULL, 0);
 815         if (ret < 0)
 816                 goto err_cleanup_nand;
 817
 818         val = davinci_nand_readl(info, NRCSR_OFFSET);
 819         dev_info(&pdev->dev, "controller rev. %d.%d\n",
 820                (val >> 8) & 0xff, val & 0xff);
 821
 822         return 0;
 823
 824 err_cleanup_nand:
 825         nand_cleanup(&info->chip);
 826
 827         return ret;
 828 }
 829
 830 static int nand_davinci_remove(struct platform_device *pdev)
 831 {
 832         struct davinci_nand_info *info = platform_get_drvdata(pdev);
 833
 834         spin_lock_irq(&davinci_nand_lock);
 835         if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
 836                 ecc4_busy = false;
 837         spin_unlock_irq(&davinci_nand_lock);
 838
 839         nand_release(&info->chip);
 840
 841         return 0;
 842 }
 843
 844 static struct platform_driver nand_davinci_driver = {
 845         .probe          = nand_davinci_probe,
 846         .remove         = nand_davinci_remove,
 847         .driver         = {
 848                 .name   = "davinci_nand",
 849                 .of_match_table = of_match_ptr(davinci_nand_of_match),
 850         },
 851 };
 852 MODULE_ALIAS("platform:davinci_nand");
 853
 854 module_platform_driver(nand_davinci_driver);
 855
 856 MODULE_LICENSE("GPL");
 857 MODULE_AUTHOR("Texas Instruments");
 858 MODULE_DESCRIPTION("Davinci NAND flash driver");
 859